1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Authors:
6 * Dave Airlie <airlied@redhat.com>
7 * Gerd Hoffmann <kraxel@redhat.com>
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29#include <linux/dma-mapping.h>
30#include <linux/virtio.h>
31#include <linux/virtio_config.h>
32#include <linux/virtio_ring.h>
33
34#include <drm/drm_edid.h>
35
36#include "virtgpu_drv.h"
37#include "virtgpu_trace.h"
38
39#define MAX_INLINE_CMD_SIZE 96
40#define MAX_INLINE_RESP_SIZE 24
41#define VBUFFER_SIZE (sizeof(struct virtio_gpu_vbuffer) \
42 + MAX_INLINE_CMD_SIZE \
43 + MAX_INLINE_RESP_SIZE)
44
45static void convert_to_hw_box(struct virtio_gpu_box *dst,
46 const struct drm_virtgpu_3d_box *src)
47{
48 dst->x = cpu_to_le32(src->x);
49 dst->y = cpu_to_le32(src->y);
50 dst->z = cpu_to_le32(src->z);
51 dst->w = cpu_to_le32(src->w);
52 dst->h = cpu_to_le32(src->h);
53 dst->d = cpu_to_le32(src->d);
54}
55
56void virtio_gpu_ctrl_ack(struct virtqueue *vq)
57{
58 struct drm_device *dev = vq->vdev->priv;
59 struct virtio_gpu_device *vgdev = dev->dev_private;
60
61 schedule_work(work: &vgdev->ctrlq.dequeue_work);
62}
63
64void virtio_gpu_cursor_ack(struct virtqueue *vq)
65{
66 struct drm_device *dev = vq->vdev->priv;
67 struct virtio_gpu_device *vgdev = dev->dev_private;
68
69 schedule_work(work: &vgdev->cursorq.dequeue_work);
70}
71
72int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev)
73{
74 vgdev->vbufs = kmem_cache_create("virtio-gpu-vbufs",
75 VBUFFER_SIZE,
76 __alignof__(struct virtio_gpu_vbuffer),
77 0, NULL);
78 if (!vgdev->vbufs)
79 return -ENOMEM;
80 return 0;
81}
82
83void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev)
84{
85 kmem_cache_destroy(s: vgdev->vbufs);
86 vgdev->vbufs = NULL;
87}
88
89/* For drm_panic */
90static struct virtio_gpu_vbuffer*
91virtio_gpu_panic_get_vbuf(struct virtio_gpu_device *vgdev, int size)
92{
93 struct virtio_gpu_vbuffer *vbuf;
94
95 vbuf = kmem_cache_zalloc(vgdev->vbufs, GFP_ATOMIC);
96
97 vbuf->buf = (void *)vbuf + sizeof(*vbuf);
98 vbuf->size = size;
99 vbuf->resp_cb = NULL;
100 vbuf->resp_size = sizeof(struct virtio_gpu_ctrl_hdr);
101 vbuf->resp_buf = (void *)vbuf->buf + size;
102 return vbuf;
103}
104
105static struct virtio_gpu_vbuffer*
106virtio_gpu_get_vbuf(struct virtio_gpu_device *vgdev,
107 int size, int resp_size, void *resp_buf,
108 virtio_gpu_resp_cb resp_cb)
109{
110 struct virtio_gpu_vbuffer *vbuf;
111
112 vbuf = kmem_cache_zalloc(vgdev->vbufs, GFP_KERNEL | __GFP_NOFAIL);
113
114 BUG_ON(size > MAX_INLINE_CMD_SIZE ||
115 size < sizeof(struct virtio_gpu_ctrl_hdr));
116 vbuf->buf = (void *)vbuf + sizeof(*vbuf);
117 vbuf->size = size;
118
119 vbuf->resp_cb = resp_cb;
120 vbuf->resp_size = resp_size;
121 if (resp_size <= MAX_INLINE_RESP_SIZE)
122 vbuf->resp_buf = (void *)vbuf->buf + size;
123 else
124 vbuf->resp_buf = resp_buf;
125 BUG_ON(!vbuf->resp_buf);
126 return vbuf;
127}
128
129static struct virtio_gpu_ctrl_hdr *
130virtio_gpu_vbuf_ctrl_hdr(struct virtio_gpu_vbuffer *vbuf)
131{
132 /* this assumes a vbuf contains a command that starts with a
133 * virtio_gpu_ctrl_hdr, which is true for both ctrl and cursor
134 * virtqueues.
135 */
136 return (struct virtio_gpu_ctrl_hdr *)vbuf->buf;
137}
138
139static struct virtio_gpu_update_cursor*
140virtio_gpu_alloc_cursor(struct virtio_gpu_device *vgdev,
141 struct virtio_gpu_vbuffer **vbuffer_p)
142{
143 struct virtio_gpu_vbuffer *vbuf;
144
145 vbuf = virtio_gpu_get_vbuf
146 (vgdev, size: sizeof(struct virtio_gpu_update_cursor),
147 resp_size: 0, NULL, NULL);
148 if (IS_ERR(ptr: vbuf)) {
149 *vbuffer_p = NULL;
150 return ERR_CAST(ptr: vbuf);
151 }
152 *vbuffer_p = vbuf;
153 return (struct virtio_gpu_update_cursor *)vbuf->buf;
154}
155
156/* For drm_panic */
157static void *virtio_gpu_panic_alloc_cmd_resp(struct virtio_gpu_device *vgdev,
158 struct virtio_gpu_vbuffer **vbuffer_p,
159 int cmd_size)
160{
161 struct virtio_gpu_vbuffer *vbuf;
162
163 vbuf = virtio_gpu_panic_get_vbuf(vgdev, size: cmd_size);
164 *vbuffer_p = vbuf;
165 return (struct virtio_gpu_command *)vbuf->buf;
166}
167
168static void *virtio_gpu_alloc_cmd_resp(struct virtio_gpu_device *vgdev,
169 virtio_gpu_resp_cb cb,
170 struct virtio_gpu_vbuffer **vbuffer_p,
171 int cmd_size, int resp_size,
172 void *resp_buf)
173{
174 struct virtio_gpu_vbuffer *vbuf;
175
176 vbuf = virtio_gpu_get_vbuf(vgdev, size: cmd_size,
177 resp_size, resp_buf, resp_cb: cb);
178 *vbuffer_p = vbuf;
179 return (struct virtio_gpu_command *)vbuf->buf;
180}
181
182static void *virtio_gpu_alloc_cmd(struct virtio_gpu_device *vgdev,
183 struct virtio_gpu_vbuffer **vbuffer_p,
184 int size)
185{
186 return virtio_gpu_alloc_cmd_resp(vgdev, NULL, vbuffer_p, cmd_size: size,
187 resp_size: sizeof(struct virtio_gpu_ctrl_hdr),
188 NULL);
189}
190
191static void *virtio_gpu_alloc_cmd_cb(struct virtio_gpu_device *vgdev,
192 struct virtio_gpu_vbuffer **vbuffer_p,
193 int size,
194 virtio_gpu_resp_cb cb)
195{
196 return virtio_gpu_alloc_cmd_resp(vgdev, cb, vbuffer_p, cmd_size: size,
197 resp_size: sizeof(struct virtio_gpu_ctrl_hdr),
198 NULL);
199}
200
201static void free_vbuf(struct virtio_gpu_device *vgdev,
202 struct virtio_gpu_vbuffer *vbuf)
203{
204 if (vbuf->resp_size > MAX_INLINE_RESP_SIZE)
205 kfree(objp: vbuf->resp_buf);
206 kvfree(addr: vbuf->data_buf);
207 kmem_cache_free(s: vgdev->vbufs, objp: vbuf);
208}
209
210static void reclaim_vbufs(struct virtqueue *vq, struct list_head *reclaim_list)
211{
212 struct virtio_gpu_vbuffer *vbuf;
213 unsigned int len;
214 int freed = 0;
215
216 while ((vbuf = virtqueue_get_buf(vq, len: &len))) {
217 list_add_tail(new: &vbuf->list, head: reclaim_list);
218 freed++;
219 }
220 if (freed == 0)
221 DRM_DEBUG("Huh? zero vbufs reclaimed");
222}
223
224void virtio_gpu_dequeue_ctrl_func(struct work_struct *work)
225{
226 struct virtio_gpu_device *vgdev =
227 container_of(work, struct virtio_gpu_device,
228 ctrlq.dequeue_work);
229 struct list_head reclaim_list;
230 struct virtio_gpu_vbuffer *entry, *tmp;
231 struct virtio_gpu_ctrl_hdr *resp;
232 u64 fence_id;
233
234 INIT_LIST_HEAD(list: &reclaim_list);
235 spin_lock(lock: &vgdev->ctrlq.qlock);
236 do {
237 virtqueue_disable_cb(vq: vgdev->ctrlq.vq);
238 reclaim_vbufs(vq: vgdev->ctrlq.vq, reclaim_list: &reclaim_list);
239
240 } while (!virtqueue_enable_cb(vq: vgdev->ctrlq.vq));
241 spin_unlock(lock: &vgdev->ctrlq.qlock);
242
243 list_for_each_entry(entry, &reclaim_list, list) {
244 resp = (struct virtio_gpu_ctrl_hdr *)entry->resp_buf;
245
246 trace_virtio_gpu_cmd_response(vq: vgdev->ctrlq.vq, hdr: resp, seqno: entry->seqno);
247
248 if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA)) {
249 if (le32_to_cpu(resp->type) >= VIRTIO_GPU_RESP_ERR_UNSPEC) {
250 struct virtio_gpu_ctrl_hdr *cmd;
251
252 cmd = virtio_gpu_vbuf_ctrl_hdr(vbuf: entry);
253 DRM_ERROR_RATELIMITED("response 0x%x (command 0x%x)\n",
254 le32_to_cpu(resp->type),
255 le32_to_cpu(cmd->type));
256 } else
257 DRM_DEBUG("response 0x%x\n", le32_to_cpu(resp->type));
258 }
259 if (resp->flags & cpu_to_le32(VIRTIO_GPU_FLAG_FENCE)) {
260 fence_id = le64_to_cpu(resp->fence_id);
261 virtio_gpu_fence_event_process(vdev: vgdev, fence_id);
262 }
263 if (entry->resp_cb)
264 entry->resp_cb(vgdev, entry);
265 }
266 wake_up(&vgdev->ctrlq.ack_queue);
267
268 list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
269 if (entry->objs)
270 virtio_gpu_array_put_free_delayed(vgdev, objs: entry->objs);
271 list_del(entry: &entry->list);
272 free_vbuf(vgdev, vbuf: entry);
273 }
274}
275
276void virtio_gpu_dequeue_cursor_func(struct work_struct *work)
277{
278 struct virtio_gpu_device *vgdev =
279 container_of(work, struct virtio_gpu_device,
280 cursorq.dequeue_work);
281 struct list_head reclaim_list;
282 struct virtio_gpu_vbuffer *entry, *tmp;
283
284 INIT_LIST_HEAD(list: &reclaim_list);
285 spin_lock(lock: &vgdev->cursorq.qlock);
286 do {
287 virtqueue_disable_cb(vq: vgdev->cursorq.vq);
288 reclaim_vbufs(vq: vgdev->cursorq.vq, reclaim_list: &reclaim_list);
289 } while (!virtqueue_enable_cb(vq: vgdev->cursorq.vq));
290 spin_unlock(lock: &vgdev->cursorq.qlock);
291
292 list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
293 struct virtio_gpu_ctrl_hdr *resp =
294 (struct virtio_gpu_ctrl_hdr *)entry->resp_buf;
295
296 trace_virtio_gpu_cmd_response(vq: vgdev->cursorq.vq, hdr: resp, seqno: entry->seqno);
297 list_del(entry: &entry->list);
298 free_vbuf(vgdev, vbuf: entry);
299 }
300 wake_up(&vgdev->cursorq.ack_queue);
301}
302
303/* Create sg_table from a vmalloc'd buffer. */
304static struct sg_table *vmalloc_to_sgt(char *data, uint32_t size, int *sg_ents)
305{
306 int ret, s, i;
307 struct sg_table *sgt;
308 struct scatterlist *sg;
309 struct page *pg;
310
311 if (WARN_ON(!PAGE_ALIGNED(data)))
312 return NULL;
313
314 sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
315 if (!sgt)
316 return NULL;
317
318 *sg_ents = DIV_ROUND_UP(size, PAGE_SIZE);
319 ret = sg_alloc_table(sgt, *sg_ents, GFP_KERNEL);
320 if (ret) {
321 kfree(objp: sgt);
322 return NULL;
323 }
324
325 for_each_sgtable_sg(sgt, sg, i) {
326 pg = vmalloc_to_page(addr: data);
327 if (!pg) {
328 sg_free_table(sgt);
329 kfree(objp: sgt);
330 return NULL;
331 }
332
333 s = min_t(int, PAGE_SIZE, size);
334 sg_set_page(sg, page: pg, len: s, offset: 0);
335
336 size -= s;
337 data += s;
338 }
339
340 return sgt;
341}
342
343/* For drm_panic */
344static int virtio_gpu_panic_queue_ctrl_sgs(struct virtio_gpu_device *vgdev,
345 struct virtio_gpu_vbuffer *vbuf,
346 int elemcnt,
347 struct scatterlist **sgs,
348 int outcnt,
349 int incnt)
350{
351 struct virtqueue *vq = vgdev->ctrlq.vq;
352 int ret;
353
354 if (vgdev->has_indirect)
355 elemcnt = 1;
356
357 if (vq->num_free < elemcnt)
358 return -ENOMEM;
359
360 ret = virtqueue_add_sgs(vq, sgs, out_sgs: outcnt, in_sgs: incnt, data: vbuf, GFP_ATOMIC);
361 WARN_ON(ret);
362
363 vbuf->seqno = ++vgdev->ctrlq.seqno;
364 trace_virtio_gpu_cmd_queue(vq, hdr: virtio_gpu_vbuf_ctrl_hdr(vbuf), seqno: vbuf->seqno);
365
366 atomic_inc(v: &vgdev->pending_commands);
367
368 return 0;
369}
370
371static int virtio_gpu_queue_ctrl_sgs(struct virtio_gpu_device *vgdev,
372 struct virtio_gpu_vbuffer *vbuf,
373 struct virtio_gpu_fence *fence,
374 int elemcnt,
375 struct scatterlist **sgs,
376 int outcnt,
377 int incnt)
378{
379 struct virtqueue *vq = vgdev->ctrlq.vq;
380 int ret, idx;
381
382 if (!drm_dev_enter(dev: vgdev->ddev, idx: &idx)) {
383 if (fence && vbuf->objs)
384 virtio_gpu_array_unlock_resv(objs: vbuf->objs);
385 free_vbuf(vgdev, vbuf);
386 return -ENODEV;
387 }
388
389 if (vgdev->has_indirect)
390 elemcnt = 1;
391
392again:
393 spin_lock(lock: &vgdev->ctrlq.qlock);
394
395 if (vq->num_free < elemcnt) {
396 spin_unlock(lock: &vgdev->ctrlq.qlock);
397 virtio_gpu_notify(vgdev);
398 wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= elemcnt);
399 goto again;
400 }
401
402 /* now that the position of the vbuf in the virtqueue is known, we can
403 * finally set the fence id
404 */
405 if (fence) {
406 virtio_gpu_fence_emit(vgdev, cmd_hdr: virtio_gpu_vbuf_ctrl_hdr(vbuf),
407 fence);
408 if (vbuf->objs) {
409 virtio_gpu_array_add_fence(objs: vbuf->objs, fence: &fence->f);
410 virtio_gpu_array_unlock_resv(objs: vbuf->objs);
411 }
412 }
413
414 ret = virtqueue_add_sgs(vq, sgs, out_sgs: outcnt, in_sgs: incnt, data: vbuf, GFP_ATOMIC);
415 WARN_ON(ret);
416
417 vbuf->seqno = ++vgdev->ctrlq.seqno;
418 trace_virtio_gpu_cmd_queue(vq, hdr: virtio_gpu_vbuf_ctrl_hdr(vbuf), seqno: vbuf->seqno);
419
420 atomic_inc(v: &vgdev->pending_commands);
421
422 spin_unlock(lock: &vgdev->ctrlq.qlock);
423
424 drm_dev_exit(idx);
425 return 0;
426}
427
428/* For drm_panic */
429static int virtio_gpu_panic_queue_ctrl_buffer(struct virtio_gpu_device *vgdev,
430 struct virtio_gpu_vbuffer *vbuf)
431{
432 struct scatterlist *sgs[3], vcmd, vresp;
433 int elemcnt = 0, outcnt = 0, incnt = 0;
434
435 /* set up vcmd */
436 sg_init_one(&vcmd, vbuf->buf, vbuf->size);
437 elemcnt++;
438 sgs[outcnt] = &vcmd;
439 outcnt++;
440
441 /* set up vresp */
442 if (vbuf->resp_size) {
443 sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size);
444 elemcnt++;
445 sgs[outcnt + incnt] = &vresp;
446 incnt++;
447 }
448
449 return virtio_gpu_panic_queue_ctrl_sgs(vgdev, vbuf,
450 elemcnt, sgs,
451 outcnt, incnt);
452}
453
454static int virtio_gpu_queue_fenced_ctrl_buffer(struct virtio_gpu_device *vgdev,
455 struct virtio_gpu_vbuffer *vbuf,
456 struct virtio_gpu_fence *fence)
457{
458 struct scatterlist *sgs[3], vcmd, vout, vresp;
459 struct sg_table *sgt = NULL;
460 int elemcnt = 0, outcnt = 0, incnt = 0, ret;
461
462 /* set up vcmd */
463 sg_init_one(&vcmd, vbuf->buf, vbuf->size);
464 elemcnt++;
465 sgs[outcnt] = &vcmd;
466 outcnt++;
467
468 /* set up vout */
469 if (vbuf->data_size) {
470 if (is_vmalloc_addr(x: vbuf->data_buf)) {
471 int sg_ents;
472
473 sgt = vmalloc_to_sgt(data: vbuf->data_buf, size: vbuf->data_size,
474 sg_ents: &sg_ents);
475 if (!sgt) {
476 if (fence && vbuf->objs)
477 virtio_gpu_array_unlock_resv(objs: vbuf->objs);
478 return -ENOMEM;
479 }
480
481 elemcnt += sg_ents;
482 sgs[outcnt] = sgt->sgl;
483 } else {
484 sg_init_one(&vout, vbuf->data_buf, vbuf->data_size);
485 elemcnt++;
486 sgs[outcnt] = &vout;
487 }
488 outcnt++;
489 }
490
491 /* set up vresp */
492 if (vbuf->resp_size) {
493 sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size);
494 elemcnt++;
495 sgs[outcnt + incnt] = &vresp;
496 incnt++;
497 }
498
499 ret = virtio_gpu_queue_ctrl_sgs(vgdev, vbuf, fence, elemcnt, sgs, outcnt,
500 incnt);
501
502 if (sgt) {
503 sg_free_table(sgt);
504 kfree(objp: sgt);
505 }
506 return ret;
507}
508
509/* For drm_panic */
510void virtio_gpu_panic_notify(struct virtio_gpu_device *vgdev)
511{
512 bool notify;
513
514 if (!atomic_read(v: &vgdev->pending_commands))
515 return;
516
517 atomic_set(v: &vgdev->pending_commands, i: 0);
518 notify = virtqueue_kick_prepare(vq: vgdev->ctrlq.vq);
519
520 if (notify)
521 virtqueue_notify(vq: vgdev->ctrlq.vq);
522}
523
524void virtio_gpu_notify(struct virtio_gpu_device *vgdev)
525{
526 bool notify;
527
528 if (!atomic_read(v: &vgdev->pending_commands))
529 return;
530
531 spin_lock(lock: &vgdev->ctrlq.qlock);
532 atomic_set(v: &vgdev->pending_commands, i: 0);
533 notify = virtqueue_kick_prepare(vq: vgdev->ctrlq.vq);
534 spin_unlock(lock: &vgdev->ctrlq.qlock);
535
536 if (notify)
537 virtqueue_notify(vq: vgdev->ctrlq.vq);
538}
539
540static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev,
541 struct virtio_gpu_vbuffer *vbuf)
542{
543 return virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, NULL);
544}
545
546static void virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev,
547 struct virtio_gpu_vbuffer *vbuf)
548{
549 struct virtqueue *vq = vgdev->cursorq.vq;
550 struct scatterlist *sgs[1], ccmd;
551 int idx, ret, outcnt;
552 bool notify;
553
554 if (!drm_dev_enter(dev: vgdev->ddev, idx: &idx)) {
555 free_vbuf(vgdev, vbuf);
556 return;
557 }
558
559 sg_init_one(&ccmd, vbuf->buf, vbuf->size);
560 sgs[0] = &ccmd;
561 outcnt = 1;
562
563 spin_lock(lock: &vgdev->cursorq.qlock);
564retry:
565 ret = virtqueue_add_sgs(vq, sgs, out_sgs: outcnt, in_sgs: 0, data: vbuf, GFP_ATOMIC);
566 if (ret == -ENOSPC) {
567 spin_unlock(lock: &vgdev->cursorq.qlock);
568 wait_event(vgdev->cursorq.ack_queue, vq->num_free >= outcnt);
569 spin_lock(lock: &vgdev->cursorq.qlock);
570 goto retry;
571 } else {
572 vbuf->seqno = ++vgdev->cursorq.seqno;
573 trace_virtio_gpu_cmd_queue(vq,
574 hdr: virtio_gpu_vbuf_ctrl_hdr(vbuf),
575 seqno: vbuf->seqno);
576
577 notify = virtqueue_kick_prepare(vq);
578 }
579
580 spin_unlock(lock: &vgdev->cursorq.qlock);
581
582 if (notify)
583 virtqueue_notify(vq);
584
585 drm_dev_exit(idx);
586}
587
588/* just create gem objects for userspace and long lived objects,
589 * just use dma_alloced pages for the queue objects?
590 */
591
592/* create a basic resource */
593void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
594 struct virtio_gpu_object *bo,
595 struct virtio_gpu_object_params *params,
596 struct virtio_gpu_object_array *objs,
597 struct virtio_gpu_fence *fence)
598{
599 struct virtio_gpu_resource_create_2d *cmd_p;
600 struct virtio_gpu_vbuffer *vbuf;
601
602 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
603 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
604 vbuf->objs = objs;
605
606 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_2D);
607 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
608 cmd_p->format = cpu_to_le32(params->format);
609 cmd_p->width = cpu_to_le32(params->width);
610 cmd_p->height = cpu_to_le32(params->height);
611
612 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
613 bo->created = true;
614}
615
616static void virtio_gpu_cmd_unref_cb(struct virtio_gpu_device *vgdev,
617 struct virtio_gpu_vbuffer *vbuf)
618{
619 struct virtio_gpu_object *bo;
620
621 bo = vbuf->resp_cb_data;
622 vbuf->resp_cb_data = NULL;
623
624 virtio_gpu_cleanup_object(bo);
625}
626
627void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
628 struct virtio_gpu_object *bo)
629{
630 struct virtio_gpu_resource_unref *cmd_p;
631 struct virtio_gpu_vbuffer *vbuf;
632 int ret;
633
634 cmd_p = virtio_gpu_alloc_cmd_cb(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p),
635 cb: virtio_gpu_cmd_unref_cb);
636 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
637
638 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNREF);
639 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
640
641 vbuf->resp_cb_data = bo;
642 ret = virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
643 if (ret < 0)
644 virtio_gpu_cleanup_object(bo);
645}
646
647void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
648 uint32_t scanout_id, uint32_t resource_id,
649 uint32_t width, uint32_t height,
650 uint32_t x, uint32_t y)
651{
652 struct virtio_gpu_set_scanout *cmd_p;
653 struct virtio_gpu_vbuffer *vbuf;
654
655 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
656 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
657
658 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT);
659 cmd_p->resource_id = cpu_to_le32(resource_id);
660 cmd_p->scanout_id = cpu_to_le32(scanout_id);
661 cmd_p->r.width = cpu_to_le32(width);
662 cmd_p->r.height = cpu_to_le32(height);
663 cmd_p->r.x = cpu_to_le32(x);
664 cmd_p->r.y = cpu_to_le32(y);
665
666 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
667}
668
669/* For drm_panic */
670void virtio_gpu_panic_cmd_resource_flush(struct virtio_gpu_device *vgdev,
671 uint32_t resource_id,
672 uint32_t x, uint32_t y,
673 uint32_t width, uint32_t height)
674{
675 struct virtio_gpu_resource_flush *cmd_p;
676 struct virtio_gpu_vbuffer *vbuf;
677
678 cmd_p = virtio_gpu_panic_alloc_cmd_resp(vgdev, vbuffer_p: &vbuf, cmd_size: sizeof(*cmd_p));
679 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
680 vbuf->objs = NULL;
681
682 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_FLUSH);
683 cmd_p->resource_id = cpu_to_le32(resource_id);
684 cmd_p->r.width = cpu_to_le32(width);
685 cmd_p->r.height = cpu_to_le32(height);
686 cmd_p->r.x = cpu_to_le32(x);
687 cmd_p->r.y = cpu_to_le32(y);
688
689 virtio_gpu_panic_queue_ctrl_buffer(vgdev, vbuf);
690}
691
692void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
693 uint32_t resource_id,
694 uint32_t x, uint32_t y,
695 uint32_t width, uint32_t height,
696 struct virtio_gpu_object_array *objs,
697 struct virtio_gpu_fence *fence)
698{
699 struct virtio_gpu_resource_flush *cmd_p;
700 struct virtio_gpu_vbuffer *vbuf;
701
702 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
703 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
704 vbuf->objs = objs;
705
706 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_FLUSH);
707 cmd_p->resource_id = cpu_to_le32(resource_id);
708 cmd_p->r.width = cpu_to_le32(width);
709 cmd_p->r.height = cpu_to_le32(height);
710 cmd_p->r.x = cpu_to_le32(x);
711 cmd_p->r.y = cpu_to_le32(y);
712
713 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
714}
715
716/* For drm_panic */
717int virtio_gpu_panic_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
718 uint64_t offset,
719 uint32_t width, uint32_t height,
720 uint32_t x, uint32_t y,
721 struct virtio_gpu_object_array *objs)
722{
723 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
724 struct virtio_gpu_transfer_to_host_2d *cmd_p;
725 struct virtio_gpu_vbuffer *vbuf;
726 bool use_dma_api = !virtio_has_dma_quirk(vdev: vgdev->vdev);
727
728 if (virtio_gpu_is_shmem(bo) && use_dma_api)
729 dma_sync_sgtable_for_device(dev: vgdev->vdev->dev.parent,
730 sgt: bo->base.sgt, dir: DMA_TO_DEVICE);
731
732 cmd_p = virtio_gpu_panic_alloc_cmd_resp(vgdev, vbuffer_p: &vbuf, cmd_size: sizeof(*cmd_p));
733 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
734 vbuf->objs = objs;
735
736 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D);
737 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
738 cmd_p->offset = cpu_to_le64(offset);
739 cmd_p->r.width = cpu_to_le32(width);
740 cmd_p->r.height = cpu_to_le32(height);
741 cmd_p->r.x = cpu_to_le32(x);
742 cmd_p->r.y = cpu_to_le32(y);
743
744 return virtio_gpu_panic_queue_ctrl_buffer(vgdev, vbuf);
745}
746
747void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
748 uint64_t offset,
749 uint32_t width, uint32_t height,
750 uint32_t x, uint32_t y,
751 struct virtio_gpu_object_array *objs,
752 struct virtio_gpu_fence *fence)
753{
754 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
755 struct virtio_gpu_transfer_to_host_2d *cmd_p;
756 struct virtio_gpu_vbuffer *vbuf;
757 bool use_dma_api = !virtio_has_dma_quirk(vdev: vgdev->vdev);
758
759 if (virtio_gpu_is_shmem(bo) && use_dma_api)
760 dma_sync_sgtable_for_device(dev: vgdev->vdev->dev.parent,
761 sgt: bo->base.sgt, dir: DMA_TO_DEVICE);
762
763 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
764 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
765 vbuf->objs = objs;
766
767 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D);
768 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
769 cmd_p->offset = cpu_to_le64(offset);
770 cmd_p->r.width = cpu_to_le32(width);
771 cmd_p->r.height = cpu_to_le32(height);
772 cmd_p->r.x = cpu_to_le32(x);
773 cmd_p->r.y = cpu_to_le32(y);
774
775 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
776}
777
778static void
779virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev,
780 uint32_t resource_id,
781 struct virtio_gpu_mem_entry *ents,
782 uint32_t nents,
783 struct virtio_gpu_fence *fence)
784{
785 struct virtio_gpu_resource_attach_backing *cmd_p;
786 struct virtio_gpu_vbuffer *vbuf;
787
788 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
789 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
790
791 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING);
792 cmd_p->resource_id = cpu_to_le32(resource_id);
793 cmd_p->nr_entries = cpu_to_le32(nents);
794
795 vbuf->data_buf = ents;
796 vbuf->data_size = sizeof(*ents) * nents;
797
798 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
799}
800
801static void
802virtio_gpu_cmd_resource_detach_backing(struct virtio_gpu_device *vgdev,
803 uint32_t resource_id,
804 struct virtio_gpu_fence *fence)
805{
806 struct virtio_gpu_resource_detach_backing *cmd_p;
807 struct virtio_gpu_vbuffer *vbuf;
808
809 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
810 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
811
812 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING);
813 cmd_p->resource_id = cpu_to_le32(resource_id);
814
815 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
816}
817
818static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev,
819 struct virtio_gpu_vbuffer *vbuf)
820{
821 struct virtio_gpu_resp_display_info *resp =
822 (struct virtio_gpu_resp_display_info *)vbuf->resp_buf;
823 int i;
824
825 spin_lock(lock: &vgdev->display_info_lock);
826 for (i = 0; i < vgdev->num_scanouts; i++) {
827 vgdev->outputs[i].info = resp->pmodes[i];
828 if (resp->pmodes[i].enabled) {
829 DRM_DEBUG("output %d: %dx%d+%d+%d", i,
830 le32_to_cpu(resp->pmodes[i].r.width),
831 le32_to_cpu(resp->pmodes[i].r.height),
832 le32_to_cpu(resp->pmodes[i].r.x),
833 le32_to_cpu(resp->pmodes[i].r.y));
834 } else {
835 DRM_DEBUG("output %d: disabled", i);
836 }
837 }
838
839 vgdev->display_info_pending = false;
840 spin_unlock(lock: &vgdev->display_info_lock);
841 wake_up(&vgdev->resp_wq);
842
843 if (!drm_helper_hpd_irq_event(dev: vgdev->ddev))
844 drm_kms_helper_hotplug_event(dev: vgdev->ddev);
845}
846
847static void virtio_gpu_cmd_get_capset_info_cb(struct virtio_gpu_device *vgdev,
848 struct virtio_gpu_vbuffer *vbuf)
849{
850 struct virtio_gpu_get_capset_info *cmd =
851 (struct virtio_gpu_get_capset_info *)vbuf->buf;
852 struct virtio_gpu_resp_capset_info *resp =
853 (struct virtio_gpu_resp_capset_info *)vbuf->resp_buf;
854 int i = le32_to_cpu(cmd->capset_index);
855
856 spin_lock(lock: &vgdev->display_info_lock);
857 if (vgdev->capsets) {
858 vgdev->capsets[i].id = le32_to_cpu(resp->capset_id);
859 vgdev->capsets[i].max_version = le32_to_cpu(resp->capset_max_version);
860 vgdev->capsets[i].max_size = le32_to_cpu(resp->capset_max_size);
861 } else {
862 DRM_ERROR("invalid capset memory.");
863 }
864 spin_unlock(lock: &vgdev->display_info_lock);
865 wake_up(&vgdev->resp_wq);
866}
867
868static void virtio_gpu_cmd_capset_cb(struct virtio_gpu_device *vgdev,
869 struct virtio_gpu_vbuffer *vbuf)
870{
871 struct virtio_gpu_get_capset *cmd =
872 (struct virtio_gpu_get_capset *)vbuf->buf;
873 struct virtio_gpu_resp_capset *resp =
874 (struct virtio_gpu_resp_capset *)vbuf->resp_buf;
875 struct virtio_gpu_drv_cap_cache *cache_ent;
876
877 spin_lock(lock: &vgdev->display_info_lock);
878 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
879 if (cache_ent->version == le32_to_cpu(cmd->capset_version) &&
880 cache_ent->id == le32_to_cpu(cmd->capset_id)) {
881 memcpy(to: cache_ent->caps_cache, from: resp->capset_data,
882 len: cache_ent->size);
883 /* Copy must occur before is_valid is signalled. */
884 smp_wmb();
885 atomic_set(v: &cache_ent->is_valid, i: 1);
886 break;
887 }
888 }
889 spin_unlock(lock: &vgdev->display_info_lock);
890 wake_up_all(&vgdev->resp_wq);
891}
892
893static int virtio_get_edid_block(void *data, u8 *buf,
894 unsigned int block, size_t len)
895{
896 struct virtio_gpu_resp_edid *resp = data;
897 size_t start = block * EDID_LENGTH;
898
899 if (start + len > le32_to_cpu(resp->size))
900 return -EINVAL;
901 memcpy(to: buf, from: resp->edid + start, len);
902 return 0;
903}
904
905static void virtio_gpu_cmd_get_edid_cb(struct virtio_gpu_device *vgdev,
906 struct virtio_gpu_vbuffer *vbuf)
907{
908 struct virtio_gpu_cmd_get_edid *cmd =
909 (struct virtio_gpu_cmd_get_edid *)vbuf->buf;
910 struct virtio_gpu_resp_edid *resp =
911 (struct virtio_gpu_resp_edid *)vbuf->resp_buf;
912 uint32_t scanout = le32_to_cpu(cmd->scanout);
913 struct virtio_gpu_output *output;
914 const struct drm_edid *new_edid, *old_edid;
915
916 if (scanout >= vgdev->num_scanouts)
917 return;
918 output = vgdev->outputs + scanout;
919
920 new_edid = drm_edid_read_custom(connector: &output->conn, read_block: virtio_get_edid_block, context: resp);
921 drm_edid_connector_update(connector: &output->conn, edid: new_edid);
922
923 spin_lock(lock: &vgdev->display_info_lock);
924 old_edid = output->drm_edid;
925 output->drm_edid = new_edid;
926 spin_unlock(lock: &vgdev->display_info_lock);
927
928 drm_edid_free(drm_edid: old_edid);
929 wake_up(&vgdev->resp_wq);
930}
931
932int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev)
933{
934 struct virtio_gpu_ctrl_hdr *cmd_p;
935 struct virtio_gpu_vbuffer *vbuf;
936 void *resp_buf;
937
938 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_display_info),
939 GFP_KERNEL);
940 if (!resp_buf)
941 return -ENOMEM;
942
943 cmd_p = virtio_gpu_alloc_cmd_resp
944 (vgdev, cb: &virtio_gpu_cmd_get_display_info_cb, vbuffer_p: &vbuf,
945 cmd_size: sizeof(*cmd_p), resp_size: sizeof(struct virtio_gpu_resp_display_info),
946 resp_buf);
947 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
948
949 vgdev->display_info_pending = true;
950 cmd_p->type = cpu_to_le32(VIRTIO_GPU_CMD_GET_DISPLAY_INFO);
951 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
952 return 0;
953}
954
955int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx)
956{
957 struct virtio_gpu_get_capset_info *cmd_p;
958 struct virtio_gpu_vbuffer *vbuf;
959 void *resp_buf;
960
961 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset_info),
962 GFP_KERNEL);
963 if (!resp_buf)
964 return -ENOMEM;
965
966 cmd_p = virtio_gpu_alloc_cmd_resp
967 (vgdev, cb: &virtio_gpu_cmd_get_capset_info_cb, vbuffer_p: &vbuf,
968 cmd_size: sizeof(*cmd_p), resp_size: sizeof(struct virtio_gpu_resp_capset_info),
969 resp_buf);
970 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
971
972 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET_INFO);
973 cmd_p->capset_index = cpu_to_le32(idx);
974 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
975 return 0;
976}
977
978int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
979 int idx, int version,
980 struct virtio_gpu_drv_cap_cache **cache_p)
981{
982 struct virtio_gpu_get_capset *cmd_p;
983 struct virtio_gpu_vbuffer *vbuf;
984 int max_size;
985 struct virtio_gpu_drv_cap_cache *cache_ent;
986 struct virtio_gpu_drv_cap_cache *search_ent;
987 void *resp_buf;
988
989 *cache_p = NULL;
990
991 if (idx >= vgdev->num_capsets)
992 return -EINVAL;
993
994 if (version > vgdev->capsets[idx].max_version)
995 return -EINVAL;
996
997 cache_ent = kzalloc(sizeof(*cache_ent), GFP_KERNEL);
998 if (!cache_ent)
999 return -ENOMEM;
1000
1001 max_size = vgdev->capsets[idx].max_size;
1002 cache_ent->caps_cache = kmalloc(max_size, GFP_KERNEL);
1003 if (!cache_ent->caps_cache) {
1004 kfree(objp: cache_ent);
1005 return -ENOMEM;
1006 }
1007
1008 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset) + max_size,
1009 GFP_KERNEL);
1010 if (!resp_buf) {
1011 kfree(objp: cache_ent->caps_cache);
1012 kfree(objp: cache_ent);
1013 return -ENOMEM;
1014 }
1015
1016 cache_ent->version = version;
1017 cache_ent->id = vgdev->capsets[idx].id;
1018 atomic_set(v: &cache_ent->is_valid, i: 0);
1019 cache_ent->size = max_size;
1020 spin_lock(lock: &vgdev->display_info_lock);
1021 /* Search while under lock in case it was added by another task. */
1022 list_for_each_entry(search_ent, &vgdev->cap_cache, head) {
1023 if (search_ent->id == vgdev->capsets[idx].id &&
1024 search_ent->version == version) {
1025 *cache_p = search_ent;
1026 break;
1027 }
1028 }
1029 if (!*cache_p)
1030 list_add_tail(new: &cache_ent->head, head: &vgdev->cap_cache);
1031 spin_unlock(lock: &vgdev->display_info_lock);
1032
1033 if (*cache_p) {
1034 /* Entry was found, so free everything that was just created. */
1035 kfree(objp: resp_buf);
1036 kfree(objp: cache_ent->caps_cache);
1037 kfree(objp: cache_ent);
1038 return 0;
1039 }
1040
1041 cmd_p = virtio_gpu_alloc_cmd_resp
1042 (vgdev, cb: &virtio_gpu_cmd_capset_cb, vbuffer_p: &vbuf, cmd_size: sizeof(*cmd_p),
1043 resp_size: sizeof(struct virtio_gpu_resp_capset) + max_size,
1044 resp_buf);
1045 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET);
1046 cmd_p->capset_id = cpu_to_le32(vgdev->capsets[idx].id);
1047 cmd_p->capset_version = cpu_to_le32(version);
1048 *cache_p = cache_ent;
1049 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1050
1051 return 0;
1052}
1053
1054int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev)
1055{
1056 struct virtio_gpu_cmd_get_edid *cmd_p;
1057 struct virtio_gpu_vbuffer *vbuf;
1058 void *resp_buf;
1059 int scanout;
1060
1061 if (WARN_ON(!vgdev->has_edid))
1062 return -EINVAL;
1063
1064 for (scanout = 0; scanout < vgdev->num_scanouts; scanout++) {
1065 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_edid),
1066 GFP_KERNEL);
1067 if (!resp_buf)
1068 return -ENOMEM;
1069
1070 cmd_p = virtio_gpu_alloc_cmd_resp
1071 (vgdev, cb: &virtio_gpu_cmd_get_edid_cb, vbuffer_p: &vbuf,
1072 cmd_size: sizeof(*cmd_p), resp_size: sizeof(struct virtio_gpu_resp_edid),
1073 resp_buf);
1074 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_EDID);
1075 cmd_p->scanout = cpu_to_le32(scanout);
1076 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1077 }
1078
1079 return 0;
1080}
1081
1082void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
1083 uint32_t context_init, uint32_t nlen,
1084 const char *name)
1085{
1086 struct virtio_gpu_ctx_create *cmd_p;
1087 struct virtio_gpu_vbuffer *vbuf;
1088
1089 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1090 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1091
1092 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_CREATE);
1093 cmd_p->hdr.ctx_id = cpu_to_le32(id);
1094 cmd_p->nlen = cpu_to_le32(nlen);
1095 cmd_p->context_init = cpu_to_le32(context_init);
1096 strscpy(cmd_p->debug_name, name, sizeof(cmd_p->debug_name));
1097 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1098}
1099
1100void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
1101 uint32_t id)
1102{
1103 struct virtio_gpu_ctx_destroy *cmd_p;
1104 struct virtio_gpu_vbuffer *vbuf;
1105
1106 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1107 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1108
1109 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DESTROY);
1110 cmd_p->hdr.ctx_id = cpu_to_le32(id);
1111 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1112}
1113
1114void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
1115 uint32_t ctx_id,
1116 struct virtio_gpu_object_array *objs)
1117{
1118 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1119 struct virtio_gpu_ctx_resource *cmd_p;
1120 struct virtio_gpu_vbuffer *vbuf;
1121
1122 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1123 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1124 vbuf->objs = objs;
1125
1126 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE);
1127 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1128 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1129 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1130}
1131
1132void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
1133 uint32_t ctx_id,
1134 struct virtio_gpu_object_array *objs)
1135{
1136 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1137 struct virtio_gpu_ctx_resource *cmd_p;
1138 struct virtio_gpu_vbuffer *vbuf;
1139
1140 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1141 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1142 vbuf->objs = objs;
1143
1144 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE);
1145 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1146 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1147 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1148}
1149
1150void
1151virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
1152 struct virtio_gpu_object *bo,
1153 struct virtio_gpu_object_params *params,
1154 struct virtio_gpu_object_array *objs,
1155 struct virtio_gpu_fence *fence)
1156{
1157 struct virtio_gpu_resource_create_3d *cmd_p;
1158 struct virtio_gpu_vbuffer *vbuf;
1159
1160 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1161 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1162 vbuf->objs = objs;
1163
1164 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_3D);
1165 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1166 cmd_p->format = cpu_to_le32(params->format);
1167 cmd_p->width = cpu_to_le32(params->width);
1168 cmd_p->height = cpu_to_le32(params->height);
1169
1170 cmd_p->target = cpu_to_le32(params->target);
1171 cmd_p->bind = cpu_to_le32(params->bind);
1172 cmd_p->depth = cpu_to_le32(params->depth);
1173 cmd_p->array_size = cpu_to_le32(params->array_size);
1174 cmd_p->last_level = cpu_to_le32(params->last_level);
1175 cmd_p->nr_samples = cpu_to_le32(params->nr_samples);
1176 cmd_p->flags = cpu_to_le32(params->flags);
1177
1178 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1179
1180 bo->created = true;
1181}
1182
1183void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
1184 uint32_t ctx_id,
1185 uint64_t offset, uint32_t level,
1186 uint32_t stride,
1187 uint32_t layer_stride,
1188 struct drm_virtgpu_3d_box *box,
1189 struct virtio_gpu_object_array *objs,
1190 struct virtio_gpu_fence *fence)
1191{
1192 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1193 struct virtio_gpu_transfer_host_3d *cmd_p;
1194 struct virtio_gpu_vbuffer *vbuf;
1195 bool use_dma_api = !virtio_has_dma_quirk(vdev: vgdev->vdev);
1196
1197 if (virtio_gpu_is_shmem(bo) && use_dma_api)
1198 dma_sync_sgtable_for_device(dev: vgdev->vdev->dev.parent,
1199 sgt: bo->base.sgt, dir: DMA_TO_DEVICE);
1200
1201 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1202 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1203
1204 vbuf->objs = objs;
1205
1206 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D);
1207 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1208 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1209 convert_to_hw_box(dst: &cmd_p->box, src: box);
1210 cmd_p->offset = cpu_to_le64(offset);
1211 cmd_p->level = cpu_to_le32(level);
1212 cmd_p->stride = cpu_to_le32(stride);
1213 cmd_p->layer_stride = cpu_to_le32(layer_stride);
1214
1215 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1216}
1217
1218void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
1219 uint32_t ctx_id,
1220 uint64_t offset, uint32_t level,
1221 uint32_t stride,
1222 uint32_t layer_stride,
1223 struct drm_virtgpu_3d_box *box,
1224 struct virtio_gpu_object_array *objs,
1225 struct virtio_gpu_fence *fence)
1226{
1227 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1228 struct virtio_gpu_transfer_host_3d *cmd_p;
1229 struct virtio_gpu_vbuffer *vbuf;
1230
1231 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1232 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1233
1234 vbuf->objs = objs;
1235
1236 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D);
1237 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1238 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1239 convert_to_hw_box(dst: &cmd_p->box, src: box);
1240 cmd_p->offset = cpu_to_le64(offset);
1241 cmd_p->level = cpu_to_le32(level);
1242 cmd_p->stride = cpu_to_le32(stride);
1243 cmd_p->layer_stride = cpu_to_le32(layer_stride);
1244
1245 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1246}
1247
1248void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
1249 void *data, uint32_t data_size,
1250 uint32_t ctx_id,
1251 struct virtio_gpu_object_array *objs,
1252 struct virtio_gpu_fence *fence)
1253{
1254 struct virtio_gpu_cmd_submit *cmd_p;
1255 struct virtio_gpu_vbuffer *vbuf;
1256
1257 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1258 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1259
1260 vbuf->data_buf = data;
1261 vbuf->data_size = data_size;
1262 vbuf->objs = objs;
1263
1264 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SUBMIT_3D);
1265 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1266 cmd_p->size = cpu_to_le32(data_size);
1267
1268 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1269}
1270
1271void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
1272 struct virtio_gpu_object *obj,
1273 struct virtio_gpu_mem_entry *ents,
1274 unsigned int nents)
1275{
1276 if (obj->attached)
1277 return;
1278
1279 virtio_gpu_cmd_resource_attach_backing(vgdev, resource_id: obj->hw_res_handle,
1280 ents, nents, NULL);
1281
1282 obj->attached = true;
1283}
1284
1285void virtio_gpu_object_detach(struct virtio_gpu_device *vgdev,
1286 struct virtio_gpu_object *obj,
1287 struct virtio_gpu_fence *fence)
1288{
1289 if (!obj->attached)
1290 return;
1291
1292 virtio_gpu_cmd_resource_detach_backing(vgdev, resource_id: obj->hw_res_handle,
1293 fence);
1294
1295 obj->attached = false;
1296}
1297
1298void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
1299 struct virtio_gpu_output *output)
1300{
1301 struct virtio_gpu_vbuffer *vbuf;
1302 struct virtio_gpu_update_cursor *cur_p;
1303
1304 output->cursor.pos.scanout_id = cpu_to_le32(output->index);
1305 cur_p = virtio_gpu_alloc_cursor(vgdev, vbuffer_p: &vbuf);
1306 memcpy(to: cur_p, from: &output->cursor, len: sizeof(output->cursor));
1307 virtio_gpu_queue_cursor(vgdev, vbuf);
1308}
1309
1310static void virtio_gpu_cmd_resource_uuid_cb(struct virtio_gpu_device *vgdev,
1311 struct virtio_gpu_vbuffer *vbuf)
1312{
1313 struct virtio_gpu_object *obj =
1314 gem_to_virtio_gpu_obj(vbuf->objs->objs[0]);
1315 struct virtio_gpu_resp_resource_uuid *resp =
1316 (struct virtio_gpu_resp_resource_uuid *)vbuf->resp_buf;
1317 uint32_t resp_type = le32_to_cpu(resp->hdr.type);
1318
1319 spin_lock(lock: &vgdev->resource_export_lock);
1320 WARN_ON(obj->uuid_state != STATE_INITIALIZING);
1321
1322 if (resp_type == VIRTIO_GPU_RESP_OK_RESOURCE_UUID &&
1323 obj->uuid_state == STATE_INITIALIZING) {
1324 import_uuid(dst: &obj->uuid, src: resp->uuid);
1325 obj->uuid_state = STATE_OK;
1326 } else {
1327 obj->uuid_state = STATE_ERR;
1328 }
1329 spin_unlock(lock: &vgdev->resource_export_lock);
1330
1331 wake_up_all(&vgdev->resp_wq);
1332}
1333
1334int
1335virtio_gpu_cmd_resource_assign_uuid(struct virtio_gpu_device *vgdev,
1336 struct virtio_gpu_object_array *objs)
1337{
1338 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1339 struct virtio_gpu_resource_assign_uuid *cmd_p;
1340 struct virtio_gpu_vbuffer *vbuf;
1341 struct virtio_gpu_resp_resource_uuid *resp_buf;
1342
1343 resp_buf = kzalloc(sizeof(*resp_buf), GFP_KERNEL);
1344 if (!resp_buf) {
1345 spin_lock(lock: &vgdev->resource_export_lock);
1346 bo->uuid_state = STATE_ERR;
1347 spin_unlock(lock: &vgdev->resource_export_lock);
1348 virtio_gpu_array_put_free(objs);
1349 return -ENOMEM;
1350 }
1351
1352 cmd_p = virtio_gpu_alloc_cmd_resp
1353 (vgdev, cb: virtio_gpu_cmd_resource_uuid_cb, vbuffer_p: &vbuf, cmd_size: sizeof(*cmd_p),
1354 resp_size: sizeof(struct virtio_gpu_resp_resource_uuid), resp_buf);
1355 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1356
1357 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID);
1358 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1359
1360 vbuf->objs = objs;
1361 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1362 return 0;
1363}
1364
1365static void virtio_gpu_cmd_resource_map_cb(struct virtio_gpu_device *vgdev,
1366 struct virtio_gpu_vbuffer *vbuf)
1367{
1368 struct virtio_gpu_object *bo =
1369 gem_to_virtio_gpu_obj(vbuf->objs->objs[0]);
1370 struct virtio_gpu_resp_map_info *resp =
1371 (struct virtio_gpu_resp_map_info *)vbuf->resp_buf;
1372 struct virtio_gpu_object_vram *vram = to_virtio_gpu_vram(bo);
1373 uint32_t resp_type = le32_to_cpu(resp->hdr.type);
1374
1375 spin_lock(lock: &vgdev->host_visible_lock);
1376
1377 if (resp_type == VIRTIO_GPU_RESP_OK_MAP_INFO) {
1378 vram->map_info = resp->map_info;
1379 vram->map_state = STATE_OK;
1380 } else {
1381 vram->map_state = STATE_ERR;
1382 }
1383
1384 spin_unlock(lock: &vgdev->host_visible_lock);
1385 wake_up_all(&vgdev->resp_wq);
1386}
1387
1388int virtio_gpu_cmd_map(struct virtio_gpu_device *vgdev,
1389 struct virtio_gpu_object_array *objs, uint64_t offset)
1390{
1391 struct virtio_gpu_resource_map_blob *cmd_p;
1392 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1393 struct virtio_gpu_vbuffer *vbuf;
1394 struct virtio_gpu_resp_map_info *resp_buf;
1395
1396 resp_buf = kzalloc(sizeof(*resp_buf), GFP_KERNEL);
1397 if (!resp_buf)
1398 return -ENOMEM;
1399
1400 cmd_p = virtio_gpu_alloc_cmd_resp
1401 (vgdev, cb: virtio_gpu_cmd_resource_map_cb, vbuffer_p: &vbuf, cmd_size: sizeof(*cmd_p),
1402 resp_size: sizeof(struct virtio_gpu_resp_map_info), resp_buf);
1403 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1404
1405 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB);
1406 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1407 cmd_p->offset = cpu_to_le64(offset);
1408 vbuf->objs = objs;
1409
1410 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1411 return 0;
1412}
1413
1414void virtio_gpu_cmd_unmap(struct virtio_gpu_device *vgdev,
1415 struct virtio_gpu_object *bo)
1416{
1417 struct virtio_gpu_resource_unmap_blob *cmd_p;
1418 struct virtio_gpu_vbuffer *vbuf;
1419
1420 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1421 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1422
1423 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB);
1424 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1425
1426 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1427}
1428
1429void
1430virtio_gpu_cmd_resource_create_blob(struct virtio_gpu_device *vgdev,
1431 struct virtio_gpu_object *bo,
1432 struct virtio_gpu_object_params *params,
1433 struct virtio_gpu_mem_entry *ents,
1434 uint32_t nents)
1435{
1436 struct virtio_gpu_resource_create_blob *cmd_p;
1437 struct virtio_gpu_vbuffer *vbuf;
1438
1439 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1440 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1441
1442 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB);
1443 cmd_p->hdr.ctx_id = cpu_to_le32(params->ctx_id);
1444 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1445 cmd_p->blob_mem = cpu_to_le32(params->blob_mem);
1446 cmd_p->blob_flags = cpu_to_le32(params->blob_flags);
1447 cmd_p->blob_id = cpu_to_le64(params->blob_id);
1448 cmd_p->size = cpu_to_le64(params->size);
1449 cmd_p->nr_entries = cpu_to_le32(nents);
1450
1451 vbuf->data_buf = ents;
1452 vbuf->data_size = sizeof(*ents) * nents;
1453
1454 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1455 bo->created = true;
1456
1457 if (nents)
1458 bo->attached = true;
1459}
1460
1461void virtio_gpu_cmd_set_scanout_blob(struct virtio_gpu_device *vgdev,
1462 uint32_t scanout_id,
1463 struct virtio_gpu_object *bo,
1464 struct drm_framebuffer *fb,
1465 uint32_t width, uint32_t height,
1466 uint32_t x, uint32_t y)
1467{
1468 uint32_t i;
1469 struct virtio_gpu_set_scanout_blob *cmd_p;
1470 struct virtio_gpu_vbuffer *vbuf;
1471 uint32_t format = virtio_gpu_translate_format(drm_fourcc: fb->format->format);
1472
1473 cmd_p = virtio_gpu_alloc_cmd(vgdev, vbuffer_p: &vbuf, size: sizeof(*cmd_p));
1474 memset(s: cmd_p, c: 0, n: sizeof(*cmd_p));
1475
1476 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT_BLOB);
1477 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1478 cmd_p->scanout_id = cpu_to_le32(scanout_id);
1479
1480 cmd_p->format = cpu_to_le32(format);
1481 cmd_p->width = cpu_to_le32(fb->width);
1482 cmd_p->height = cpu_to_le32(fb->height);
1483
1484 for (i = 0; i < 4; i++) {
1485 cmd_p->strides[i] = cpu_to_le32(fb->pitches[i]);
1486 cmd_p->offsets[i] = cpu_to_le32(fb->offsets[i]);
1487 }
1488
1489 cmd_p->r.width = cpu_to_le32(width);
1490 cmd_p->r.height = cpu_to_le32(height);
1491 cmd_p->r.x = cpu_to_le32(x);
1492 cmd_p->r.y = cpu_to_le32(y);
1493
1494 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1495}
1496