1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/device.h>
10#include <linux/errno.h>
11#include <linux/types.h>
12#include <linux/pci.h>
13#include <linux/dma-mapping.h>
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16
17#include <linux/pm_domain.h>
18#include <linux/pm_runtime.h>
19
20#include <linux/mei.h>
21
22#include "mei_dev.h"
23#include "client.h"
24#include "hw-me-regs.h"
25#include "hw-me.h"
26
27/* mei_pci_tbl - PCI Device ID Table */
28static const struct pci_device_id mei_me_pci_tbl[] = {
29 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
30 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
31 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
32 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
34 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
39 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
40
41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
50
51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
55
56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
57 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
58 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
69
70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
76
77 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
79
80 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
81
82 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
83
84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
86 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
87
88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
91 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
92
93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
97 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
98
99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
100 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
101
102 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
103 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
104
105 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
106
107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
109
110 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
111
112 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
113
114 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
116 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
117 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
118
119 {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)},
120
121 {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
122 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
123 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
124
125 {MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)},
126
127 {MEI_PCI_DEVICE(MEI_DEV_ID_PTL_H, MEI_ME_PCH15_CFG)},
128 {MEI_PCI_DEVICE(MEI_DEV_ID_PTL_P, MEI_ME_PCH15_CFG)},
129
130 /* required last entry */
131 {0, }
132};
133
134MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
135
136#ifdef CONFIG_PM
137static inline void mei_me_set_pm_domain(struct mei_device *dev);
138static inline void mei_me_unset_pm_domain(struct mei_device *dev);
139#else
140static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
141static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
142#endif /* CONFIG_PM */
143
144static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
145{
146 struct pci_dev *pdev = to_pci_dev(dev->parent);
147
148 return pci_read_config_dword(dev: pdev, where, val);
149}
150
151/**
152 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
153 *
154 * @pdev: PCI device structure
155 * @cfg: per generation config
156 *
157 * Return: true if ME Interface is valid, false otherwise
158 */
159static bool mei_me_quirk_probe(struct pci_dev *pdev,
160 const struct mei_cfg *cfg)
161{
162 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
163 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
164 return false;
165 }
166
167 return true;
168}
169
170/**
171 * mei_me_probe - Device Initialization Routine
172 *
173 * @pdev: PCI device structure
174 * @ent: entry in kcs_pci_tbl
175 *
176 * Return: 0 on success, <0 on failure.
177 */
178static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
179{
180 const struct mei_cfg *cfg;
181 struct mei_device *dev;
182 struct mei_me_hw *hw;
183 unsigned int irqflags;
184 int err;
185
186 cfg = mei_me_get_cfg(idx: ent->driver_data);
187 if (!cfg)
188 return -ENODEV;
189
190 if (!mei_me_quirk_probe(pdev, cfg))
191 return -ENODEV;
192
193 /* enable pci dev */
194 err = pcim_enable_device(pdev);
195 if (err) {
196 dev_err(&pdev->dev, "failed to enable pci device.\n");
197 goto end;
198 }
199 /* set PCI host mastering */
200 pci_set_master(dev: pdev);
201 /* pci request regions and mapping IO device memory for mei driver */
202 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
203 if (err) {
204 dev_err(&pdev->dev, "failed to get pci regions.\n");
205 goto end;
206 }
207
208 err = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(64));
209 if (err) {
210 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
211 goto end;
212 }
213
214 /* allocates and initializes the mei dev structure */
215 dev = mei_me_dev_init(parent: &pdev->dev, cfg, slow_fw: false);
216 if (!dev) {
217 err = -ENOMEM;
218 goto end;
219 }
220 hw = to_me_hw(dev);
221 hw->mem_addr = pcim_iomap_table(pdev)[0];
222 hw->read_fws = mei_me_read_fws;
223
224 pci_enable_msi(dev: pdev);
225
226 hw->irq = pdev->irq;
227
228 /* request and enable interrupt */
229 irqflags = pci_dev_msi_enabled(pci_dev: pdev) ? IRQF_ONESHOT : IRQF_SHARED;
230
231 err = request_threaded_irq(irq: pdev->irq,
232 handler: mei_me_irq_quick_handler,
233 thread_fn: mei_me_irq_thread_handler,
234 flags: irqflags, KBUILD_MODNAME, dev);
235 if (err) {
236 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
237 pdev->irq);
238 goto end;
239 }
240
241 err = mei_register(dev, parent: &pdev->dev);
242 if (err)
243 goto release_irq;
244
245 if (mei_start(dev)) {
246 dev_err(&pdev->dev, "init hw failure.\n");
247 err = -ENODEV;
248 goto deregister;
249 }
250
251 pm_runtime_set_autosuspend_delay(dev: &pdev->dev, MEI_ME_RPM_TIMEOUT);
252 pm_runtime_use_autosuspend(dev: &pdev->dev);
253
254 pci_set_drvdata(pdev, data: dev);
255
256 /*
257 * MEI requires to resume from runtime suspend mode
258 * in order to perform link reset flow upon system suspend.
259 */
260 dev_pm_set_driver_flags(dev: &pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
261
262 /*
263 * ME maps runtime suspend/resume to D0i states,
264 * hence we need to go around native PCI runtime service which
265 * eventually brings the device into D3cold/hot state,
266 * but the mei device cannot wake up from D3 unlike from D0i3.
267 * To get around the PCI device native runtime pm,
268 * ME uses runtime pm domain handlers which take precedence
269 * over the driver's pm handlers.
270 */
271 mei_me_set_pm_domain(dev);
272
273 if (mei_pg_is_enabled(dev)) {
274 pm_runtime_put_noidle(dev: &pdev->dev);
275 if (hw->d0i3_supported)
276 pm_runtime_allow(dev: &pdev->dev);
277 }
278
279 dev_dbg(&pdev->dev, "initialization successful.\n");
280
281 return 0;
282
283deregister:
284 mei_deregister(dev);
285release_irq:
286 mei_cancel_work(dev);
287 mei_disable_interrupts(dev);
288 free_irq(pdev->irq, dev);
289end:
290 dev_err(&pdev->dev, "initialization failed.\n");
291 return err;
292}
293
294/**
295 * mei_me_shutdown - Device Removal Routine
296 *
297 * @pdev: PCI device structure
298 *
299 * mei_me_shutdown is called from the reboot notifier
300 * it's a simplified version of remove so we go down
301 * faster.
302 */
303static void mei_me_shutdown(struct pci_dev *pdev)
304{
305 struct mei_device *dev = pci_get_drvdata(pdev);
306
307 dev_dbg(&pdev->dev, "shutdown\n");
308 mei_stop(dev);
309
310 mei_me_unset_pm_domain(dev);
311
312 mei_disable_interrupts(dev);
313 free_irq(pdev->irq, dev);
314}
315
316/**
317 * mei_me_remove - Device Removal Routine
318 *
319 * @pdev: PCI device structure
320 *
321 * mei_me_remove is called by the PCI subsystem to alert the driver
322 * that it should release a PCI device.
323 */
324static void mei_me_remove(struct pci_dev *pdev)
325{
326 struct mei_device *dev = pci_get_drvdata(pdev);
327
328 if (mei_pg_is_enabled(dev))
329 pm_runtime_get_noresume(dev: &pdev->dev);
330
331 dev_dbg(&pdev->dev, "stop\n");
332 mei_stop(dev);
333
334 mei_me_unset_pm_domain(dev);
335
336 mei_disable_interrupts(dev);
337
338 free_irq(pdev->irq, dev);
339
340 mei_deregister(dev);
341}
342
343#ifdef CONFIG_PM_SLEEP
344static int mei_me_pci_prepare(struct device *device)
345{
346 pm_runtime_resume(dev: device);
347 return 0;
348}
349
350static int mei_me_pci_suspend(struct device *device)
351{
352 struct pci_dev *pdev = to_pci_dev(device);
353 struct mei_device *dev = pci_get_drvdata(pdev);
354
355 dev_dbg(&pdev->dev, "suspend\n");
356
357 mei_stop(dev);
358
359 mei_disable_interrupts(dev);
360
361 free_irq(pdev->irq, dev);
362 pci_disable_msi(dev: pdev);
363
364 return 0;
365}
366
367static int mei_me_pci_resume(struct device *device)
368{
369 struct pci_dev *pdev = to_pci_dev(device);
370 struct mei_device *dev = pci_get_drvdata(pdev);
371 unsigned int irqflags;
372 int err;
373
374 pci_enable_msi(dev: pdev);
375
376 irqflags = pci_dev_msi_enabled(pci_dev: pdev) ? IRQF_ONESHOT : IRQF_SHARED;
377
378 /* request and enable interrupt */
379 err = request_threaded_irq(irq: pdev->irq,
380 handler: mei_me_irq_quick_handler,
381 thread_fn: mei_me_irq_thread_handler,
382 flags: irqflags, KBUILD_MODNAME, dev);
383
384 if (err) {
385 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
386 pdev->irq);
387 return err;
388 }
389
390 err = mei_restart(dev);
391 if (err) {
392 free_irq(pdev->irq, dev);
393 return err;
394 }
395
396 /* Start timer if stopped in suspend */
397 schedule_delayed_work(dwork: &dev->timer_work, HZ);
398
399 return 0;
400}
401
402static void mei_me_pci_complete(struct device *device)
403{
404 pm_runtime_suspend(dev: device);
405}
406#else /* CONFIG_PM_SLEEP */
407
408#define mei_me_pci_prepare NULL
409#define mei_me_pci_complete NULL
410
411#endif /* !CONFIG_PM_SLEEP */
412
413#ifdef CONFIG_PM
414static int mei_me_pm_runtime_idle(struct device *device)
415{
416 struct mei_device *dev = dev_get_drvdata(dev: device);
417
418 dev_dbg(device, "rpm: me: runtime_idle\n");
419
420 if (mei_write_is_idle(dev))
421 pm_runtime_autosuspend(dev: device);
422
423 return -EBUSY;
424}
425
426static int mei_me_pm_runtime_suspend(struct device *device)
427{
428 struct mei_device *dev = dev_get_drvdata(dev: device);
429 int ret;
430
431 dev_dbg(device, "rpm: me: runtime suspend\n");
432
433 mutex_lock(lock: &dev->device_lock);
434
435 if (mei_write_is_idle(dev))
436 ret = mei_me_pg_enter_sync(dev);
437 else
438 ret = -EAGAIN;
439
440 mutex_unlock(lock: &dev->device_lock);
441
442 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
443
444 if (ret && ret != -EAGAIN)
445 schedule_work(work: &dev->reset_work);
446
447 return ret;
448}
449
450static int mei_me_pm_runtime_resume(struct device *device)
451{
452 struct mei_device *dev = dev_get_drvdata(dev: device);
453 int ret;
454
455 dev_dbg(device, "rpm: me: runtime resume\n");
456
457 mutex_lock(lock: &dev->device_lock);
458
459 ret = mei_me_pg_exit_sync(dev);
460
461 mutex_unlock(lock: &dev->device_lock);
462
463 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
464
465 if (ret)
466 schedule_work(work: &dev->reset_work);
467
468 return ret;
469}
470
471/**
472 * mei_me_set_pm_domain - fill and set pm domain structure for device
473 *
474 * @dev: mei_device
475 */
476static inline void mei_me_set_pm_domain(struct mei_device *dev)
477{
478 struct pci_dev *pdev = to_pci_dev(dev->parent);
479
480 if (pdev->dev.bus && pdev->dev.bus->pm) {
481 dev->pg_domain.ops = *pdev->dev.bus->pm;
482
483 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
484 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
485 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
486
487 dev_pm_domain_set(dev: &pdev->dev, pd: &dev->pg_domain);
488 }
489}
490
491/**
492 * mei_me_unset_pm_domain - clean pm domain structure for device
493 *
494 * @dev: mei_device
495 */
496static inline void mei_me_unset_pm_domain(struct mei_device *dev)
497{
498 /* stop using pm callbacks if any */
499 dev_pm_domain_set(dev: dev->parent, NULL);
500}
501
502static const struct dev_pm_ops mei_me_pm_ops = {
503 .prepare = mei_me_pci_prepare,
504 .complete = mei_me_pci_complete,
505 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
506 mei_me_pci_resume)
507 SET_RUNTIME_PM_OPS(
508 mei_me_pm_runtime_suspend,
509 mei_me_pm_runtime_resume,
510 mei_me_pm_runtime_idle)
511};
512
513#define MEI_ME_PM_OPS (&mei_me_pm_ops)
514#else
515#define MEI_ME_PM_OPS NULL
516#endif /* CONFIG_PM */
517/*
518 * PCI driver structure
519 */
520static struct pci_driver mei_me_driver = {
521 .name = KBUILD_MODNAME,
522 .id_table = mei_me_pci_tbl,
523 .probe = mei_me_probe,
524 .remove = mei_me_remove,
525 .shutdown = mei_me_shutdown,
526 .driver.pm = MEI_ME_PM_OPS,
527 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
528};
529
530module_pci_driver(mei_me_driver);
531
532MODULE_AUTHOR("Intel Corporation");
533MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
534MODULE_LICENSE("GPL v2");
535