1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * New driver for Marvell Yukon 2 chipset.
4 * Based on earlier sk98lin, and skge driver.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/crc32.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/netdevice.h>
19#include <linux/dma-mapping.h>
20#include <linux/etherdevice.h>
21#include <linux/ethtool.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24#include <linux/ip.h>
25#include <linux/slab.h>
26#include <net/ip.h>
27#include <linux/tcp.h>
28#include <linux/in.h>
29#include <linux/delay.h>
30#include <linux/workqueue.h>
31#include <linux/if_vlan.h>
32#include <linux/prefetch.h>
33#include <linux/debugfs.h>
34#include <linux/mii.h>
35#include <linux/of_net.h>
36#include <linux/dmi.h>
37#include <linux/skbuff_ref.h>
38
39#include <asm/irq.h>
40
41#include "sky2.h"
42
43#define DRV_NAME "sky2"
44#define DRV_VERSION "1.30"
45
46/*
47 * The Yukon II chipset takes 64 bit command blocks (called list elements)
48 * that are organized into three (receive, transmit, status) different rings
49 * similar to Tigon3.
50 */
51
52#define RX_LE_SIZE 1024
53#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
54#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
55#define RX_DEF_PENDING RX_MAX_PENDING
56
57/* This is the worst case number of transmit list elements for a single skb:
58 * VLAN:GSO + CKSUM + Data + skb_frags * DMA
59 */
60#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
61#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
62#define TX_MAX_PENDING 1024
63#define TX_DEF_PENDING 63
64
65#define TX_WATCHDOG (5 * HZ)
66#define PHY_RETRIES 1000
67
68#define SKY2_EEPROM_MAGIC 0x9955aabb
69
70#define RING_NEXT(x, s) (((x)+1) & ((s)-1))
71
72static const u32 default_msg =
73 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
74 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
75 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
76
77static int debug = -1; /* defaults above */
78module_param(debug, int, 0);
79MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
80
81static int copybreak __read_mostly = 128;
82module_param(copybreak, int, 0);
83MODULE_PARM_DESC(copybreak, "Receive copy threshold");
84
85static int disable_msi = -1;
86module_param(disable_msi, int, 0);
87MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
88
89static int legacy_pme = 0;
90module_param(legacy_pme, int, 0);
91MODULE_PARM_DESC(legacy_pme, "Legacy power management");
92
93static const struct pci_device_id sky2_id_table[] = {
94 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
95 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
96 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
97 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
98 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
99 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
100 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
101 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4373) }, /* 88E8075 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
137 { 0 }
138};
139
140MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142/* Avoid conditionals by using array */
143static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
145static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
146
147static void sky2_set_multicast(struct net_device *dev);
148static irqreturn_t sky2_intr(int irq, void *dev_id);
149
150/* Access to PHY via serial interconnect */
151static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
152{
153 int i;
154
155 gma_write16(hw, port, r: GM_SMI_DATA, v: val);
156 gma_write16(hw, port, r: GM_SMI_CTRL,
157 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
158
159 for (i = 0; i < PHY_RETRIES; i++) {
160 u16 ctrl = gma_read16(hw, port, reg: GM_SMI_CTRL);
161 if (ctrl == 0xffff)
162 goto io_error;
163
164 if (!(ctrl & GM_SMI_CT_BUSY))
165 return 0;
166
167 udelay(usec: 10);
168 }
169
170 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
171 return -ETIMEDOUT;
172
173io_error:
174 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
175 return -EIO;
176}
177
178static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
179{
180 int i;
181
182 gma_write16(hw, port, r: GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
183 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
184
185 for (i = 0; i < PHY_RETRIES; i++) {
186 u16 ctrl = gma_read16(hw, port, reg: GM_SMI_CTRL);
187 if (ctrl == 0xffff)
188 goto io_error;
189
190 if (ctrl & GM_SMI_CT_RD_VAL) {
191 *val = gma_read16(hw, port, reg: GM_SMI_DATA);
192 return 0;
193 }
194
195 udelay(usec: 10);
196 }
197
198 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
199 return -ETIMEDOUT;
200io_error:
201 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
202 return -EIO;
203}
204
205static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
206{
207 u16 v = 0;
208 __gm_phy_read(hw, port, reg, val: &v);
209 return v;
210}
211
212
213static void sky2_power_on(struct sky2_hw *hw)
214{
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, reg: B0_POWER_CTRL,
217 val: PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, reg: B2_Y2_CLK_CTRL, val: Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
223 /* enable bits are inverted */
224 sky2_write8(hw, reg: B2_Y2_CLK_GATE,
225 val: Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, reg: B2_Y2_CLK_GATE, val: 0);
230
231 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
232 u32 reg;
233
234 sky2_pci_write32(hw, reg: PCI_DEV_REG3, val: 0);
235
236 reg = sky2_pci_read32(hw, reg: PCI_DEV_REG4);
237 /* set all bits to 0 except bits 15..12 and 8 */
238 reg &= P_ASPM_CONTROL_MSK;
239 sky2_pci_write32(hw, reg: PCI_DEV_REG4, val: reg);
240
241 reg = sky2_pci_read32(hw, reg: PCI_DEV_REG5);
242 /* set all bits to 0 except bits 28 & 27 */
243 reg &= P_CTL_TIM_VMAIN_AV_MSK;
244 sky2_pci_write32(hw, reg: PCI_DEV_REG5, val: reg);
245
246 sky2_pci_write32(hw, reg: PCI_CFG_REG_1, val: 0);
247
248 sky2_write16(hw, reg: B0_CTST, val: Y2_HW_WOL_ON);
249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, reg: B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, reg: B2_GP_IO, val: reg);
254
255 sky2_read32(hw, reg: B2_GP_IO);
256 }
257
258 /* Turn on "driver loaded" LED */
259 sky2_write16(hw, reg: B0_CTST, val: Y2_LED_STAT_ON);
260}
261
262static void sky2_power_aux(struct sky2_hw *hw)
263{
264 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
265 sky2_write8(hw, reg: B2_Y2_CLK_GATE, val: 0);
266 else
267 /* enable bits are inverted */
268 sky2_write8(hw, reg: B2_Y2_CLK_GATE,
269 val: Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
270 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
271 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
272
273 /* switch power to VAUX if supported and PME from D3cold */
274 if ( (sky2_read32(hw, reg: B0_CTST) & Y2_VAUX_AVAIL) &&
275 pci_pme_capable(dev: hw->pdev, PCI_D3cold))
276 sky2_write8(hw, reg: B0_POWER_CTRL,
277 val: (PC_VAUX_ENA | PC_VCC_ENA |
278 PC_VAUX_ON | PC_VCC_OFF));
279
280 /* turn off "driver loaded LED" */
281 sky2_write16(hw, reg: B0_CTST, val: Y2_LED_STAT_OFF);
282}
283
284static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
285{
286 u16 reg;
287
288 /* disable all GMAC IRQ's */
289 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), val: 0);
290
291 gma_write16(hw, port, r: GM_MC_ADDR_H1, v: 0); /* clear MC hash */
292 gma_write16(hw, port, r: GM_MC_ADDR_H2, v: 0);
293 gma_write16(hw, port, r: GM_MC_ADDR_H3, v: 0);
294 gma_write16(hw, port, r: GM_MC_ADDR_H4, v: 0);
295
296 reg = gma_read16(hw, port, reg: GM_RX_CTRL);
297 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
298 gma_write16(hw, port, r: GM_RX_CTRL, v: reg);
299}
300
301/* flow control to advertise bits */
302static const u16 copper_fc_adv[] = {
303 [FC_NONE] = 0,
304 [FC_TX] = PHY_M_AN_ASP,
305 [FC_RX] = PHY_M_AN_PC,
306 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
307};
308
309/* flow control to advertise bits when using 1000BaseX */
310static const u16 fiber_fc_adv[] = {
311 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
312 [FC_TX] = PHY_M_P_ASYM_MD_X,
313 [FC_RX] = PHY_M_P_SYM_MD_X,
314 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
315};
316
317/* flow control to GMA disable bits */
318static const u16 gm_fc_disable[] = {
319 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
320 [FC_TX] = GM_GPCR_FC_RX_DIS,
321 [FC_RX] = GM_GPCR_FC_TX_DIS,
322 [FC_BOTH] = 0,
323};
324
325
326static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
327{
328 struct sky2_port *sky2 = netdev_priv(dev: hw->dev[port]);
329 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
330
331 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
332 !(hw->flags & SKY2_HW_NEWER_PHY)) {
333 u16 ectrl = gm_phy_read(hw, port, reg: PHY_MARV_EXT_CTRL);
334
335 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
336 PHY_M_EC_MAC_S_MSK);
337 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
338
339 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
340 if (hw->chip_id == CHIP_ID_YUKON_EC)
341 /* set downshift counter to 3x and enable downshift */
342 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
343 else
344 /* set master & slave downshift counter to 1x */
345 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
346
347 gm_phy_write(hw, port, reg: PHY_MARV_EXT_CTRL, val: ectrl);
348 }
349
350 ctrl = gm_phy_read(hw, port, reg: PHY_MARV_PHY_CTRL);
351 if (sky2_is_copper(hw)) {
352 if (!(hw->flags & SKY2_HW_GIGABIT)) {
353 /* enable automatic crossover */
354 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
355
356 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
357 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
358 u16 spec;
359
360 /* Enable Class A driver for FE+ A0 */
361 spec = gm_phy_read(hw, port, reg: PHY_MARV_FE_SPEC_2);
362 spec |= PHY_M_FESC_SEL_CL_A;
363 gm_phy_write(hw, port, reg: PHY_MARV_FE_SPEC_2, val: spec);
364 }
365 } else {
366 /* disable energy detect */
367 ctrl &= ~PHY_M_PC_EN_DET_MSK;
368
369 /* enable automatic crossover */
370 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
371
372 /* downshift on PHY 88E1112 and 88E1149 is changed */
373 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
374 (hw->flags & SKY2_HW_NEWER_PHY)) {
375 /* set downshift counter to 3x and enable downshift */
376 ctrl &= ~PHY_M_PC_DSC_MSK;
377 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
378 }
379 }
380 } else {
381 /* workaround for deviation #4.88 (CRC errors) */
382 /* disable Automatic Crossover */
383
384 ctrl &= ~PHY_M_PC_MDIX_MSK;
385 }
386
387 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL, val: ctrl);
388
389 /* special setup for PHY 88E1112 Fiber */
390 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
391 pg = gm_phy_read(hw, port, reg: PHY_MARV_EXT_ADR);
392
393 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
394 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 2);
395 ctrl = gm_phy_read(hw, port, reg: PHY_MARV_PHY_CTRL);
396 ctrl &= ~PHY_M_MAC_MD_MSK;
397 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
398 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL, val: ctrl);
399
400 if (hw->pmd_type == 'P') {
401 /* select page 1 to access Fiber registers */
402 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 1);
403
404 /* for SFP-module set SIGDET polarity to low */
405 ctrl = gm_phy_read(hw, port, reg: PHY_MARV_PHY_CTRL);
406 ctrl |= PHY_M_FIB_SIGD_POL;
407 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL, val: ctrl);
408 }
409
410 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: pg);
411 }
412
413 ctrl = PHY_CT_RESET;
414 ct1000 = 0;
415 adv = PHY_AN_CSMA;
416 reg = 0;
417
418 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
419 if (sky2_is_copper(hw)) {
420 if (sky2->advertising & ADVERTISED_1000baseT_Full)
421 ct1000 |= PHY_M_1000C_AFD;
422 if (sky2->advertising & ADVERTISED_1000baseT_Half)
423 ct1000 |= PHY_M_1000C_AHD;
424 if (sky2->advertising & ADVERTISED_100baseT_Full)
425 adv |= PHY_M_AN_100_FD;
426 if (sky2->advertising & ADVERTISED_100baseT_Half)
427 adv |= PHY_M_AN_100_HD;
428 if (sky2->advertising & ADVERTISED_10baseT_Full)
429 adv |= PHY_M_AN_10_FD;
430 if (sky2->advertising & ADVERTISED_10baseT_Half)
431 adv |= PHY_M_AN_10_HD;
432
433 } else { /* special defines for FIBER (88E1040S only) */
434 if (sky2->advertising & ADVERTISED_1000baseT_Full)
435 adv |= PHY_M_AN_1000X_AFD;
436 if (sky2->advertising & ADVERTISED_1000baseT_Half)
437 adv |= PHY_M_AN_1000X_AHD;
438 }
439
440 /* Restart Auto-negotiation */
441 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
442 } else {
443 /* forced speed/duplex settings */
444 ct1000 = PHY_M_1000C_MSE;
445
446 /* Disable auto update for duplex flow control and duplex */
447 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
448
449 switch (sky2->speed) {
450 case SPEED_1000:
451 ctrl |= PHY_CT_SP1000;
452 reg |= GM_GPCR_SPEED_1000;
453 break;
454 case SPEED_100:
455 ctrl |= PHY_CT_SP100;
456 reg |= GM_GPCR_SPEED_100;
457 break;
458 }
459
460 if (sky2->duplex == DUPLEX_FULL) {
461 reg |= GM_GPCR_DUP_FULL;
462 ctrl |= PHY_CT_DUP_MD;
463 } else if (sky2->speed < SPEED_1000)
464 sky2->flow_mode = FC_NONE;
465 }
466
467 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
468 if (sky2_is_copper(hw))
469 adv |= copper_fc_adv[sky2->flow_mode];
470 else
471 adv |= fiber_fc_adv[sky2->flow_mode];
472 } else {
473 reg |= GM_GPCR_AU_FCT_DIS;
474 reg |= gm_fc_disable[sky2->flow_mode];
475
476 /* Forward pause packets to GMAC? */
477 if (sky2->flow_mode & FC_RX)
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), val: GMC_PAUSE_ON);
479 else
480 sky2_write8(hw, SK_REG(port, GMAC_CTRL), val: GMC_PAUSE_OFF);
481 }
482
483 gma_write16(hw, port, r: GM_GP_CTRL, v: reg);
484
485 if (hw->flags & SKY2_HW_GIGABIT)
486 gm_phy_write(hw, port, reg: PHY_MARV_1000T_CTRL, val: ct1000);
487
488 gm_phy_write(hw, port, reg: PHY_MARV_AUNE_ADV, val: adv);
489 gm_phy_write(hw, port, reg: PHY_MARV_CTRL, val: ctrl);
490
491 /* Setup Phy LED's */
492 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
493 ledover = 0;
494
495 switch (hw->chip_id) {
496 case CHIP_ID_YUKON_FE:
497 /* on 88E3082 these bits are at 11..9 (shifted left) */
498 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
499
500 ctrl = gm_phy_read(hw, port, reg: PHY_MARV_FE_LED_PAR);
501
502 /* delete ACT LED control bits */
503 ctrl &= ~PHY_M_FELP_LED1_MSK;
504 /* change ACT LED control to blink mode */
505 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
506 gm_phy_write(hw, port, reg: PHY_MARV_FE_LED_PAR, val: ctrl);
507 break;
508
509 case CHIP_ID_YUKON_FE_P:
510 /* Enable Link Partner Next Page */
511 ctrl = gm_phy_read(hw, port, reg: PHY_MARV_PHY_CTRL);
512 ctrl |= PHY_M_PC_ENA_LIP_NP;
513
514 /* disable Energy Detect and enable scrambler */
515 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
516 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL, val: ctrl);
517
518 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
519 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
520 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
521 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
522
523 gm_phy_write(hw, port, reg: PHY_MARV_FE_LED_PAR, val: ctrl);
524 break;
525
526 case CHIP_ID_YUKON_XL:
527 pg = gm_phy_read(hw, port, reg: PHY_MARV_EXT_ADR);
528
529 /* select page 3 to access LED control register */
530 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 3);
531
532 /* set LED Function Control register */
533 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL,
534 val: (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
535 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
536 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
537 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
538
539 /* set Polarity Control register */
540 gm_phy_write(hw, port, reg: PHY_MARV_PHY_STAT,
541 val: (PHY_M_POLC_LS1_P_MIX(4) |
542 PHY_M_POLC_IS0_P_MIX(4) |
543 PHY_M_POLC_LOS_CTRL(2) |
544 PHY_M_POLC_INIT_CTRL(2) |
545 PHY_M_POLC_STA1_CTRL(2) |
546 PHY_M_POLC_STA0_CTRL(2)));
547
548 /* restore page register */
549 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: pg);
550 break;
551
552 case CHIP_ID_YUKON_EC_U:
553 case CHIP_ID_YUKON_EX:
554 case CHIP_ID_YUKON_SUPR:
555 pg = gm_phy_read(hw, port, reg: PHY_MARV_EXT_ADR);
556
557 /* select page 3 to access LED control register */
558 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 3);
559
560 /* set LED Function Control register */
561 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL,
562 val: (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
563 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
564 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
565 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
566
567 /* set Blink Rate in LED Timer Control Register */
568 gm_phy_write(hw, port, reg: PHY_MARV_INT_MASK,
569 val: ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
570 /* restore page register */
571 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: pg);
572 break;
573
574 default:
575 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
576 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
577
578 /* turn off the Rx LED (LED_RX) */
579 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
580 }
581
582 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
583 /* apply fixes in PHY AFE */
584 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 255);
585
586 /* increase differential signal amplitude in 10BASE-T */
587 gm_phy_write(hw, port, reg: 0x18, val: 0xaa99);
588 gm_phy_write(hw, port, reg: 0x17, val: 0x2011);
589
590 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
591 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
592 gm_phy_write(hw, port, reg: 0x18, val: 0xa204);
593 gm_phy_write(hw, port, reg: 0x17, val: 0x2002);
594 }
595
596 /* set page register to 0 */
597 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 0);
598 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
599 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
600 /* apply workaround for integrated resistors calibration */
601 gm_phy_write(hw, port, reg: PHY_MARV_PAGE_ADDR, val: 17);
602 gm_phy_write(hw, port, reg: PHY_MARV_PAGE_DATA, val: 0x3f60);
603 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
604 /* apply fixes in PHY AFE */
605 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 0x00ff);
606
607 /* apply RDAC termination workaround */
608 gm_phy_write(hw, port, reg: 24, val: 0x2800);
609 gm_phy_write(hw, port, reg: 23, val: 0x2001);
610
611 /* set page register back to 0 */
612 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 0);
613 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
614 hw->chip_id < CHIP_ID_YUKON_SUPR) {
615 /* no effect on Yukon-XL */
616 gm_phy_write(hw, port, reg: PHY_MARV_LED_CTRL, val: ledctrl);
617
618 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
619 sky2->speed == SPEED_100) {
620 /* turn on 100 Mbps LED (LED_LINK100) */
621 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
622 }
623
624 if (ledover)
625 gm_phy_write(hw, port, reg: PHY_MARV_LED_OVER, val: ledover);
626
627 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
628 (sky2_read8(hw, reg: B2_MAC_CFG) & 0xf) == 0x7) {
629 int i;
630 /* This a phy register setup workaround copied from vendor driver. */
631 static const struct {
632 u16 reg, val;
633 } eee_afe[] = {
634 { 0x156, 0x58ce },
635 { 0x153, 0x99eb },
636 { 0x141, 0x8064 },
637 /* { 0x155, 0x130b },*/
638 { 0x000, 0x0000 },
639 { 0x151, 0x8433 },
640 { 0x14b, 0x8c44 },
641 { 0x14c, 0x0f90 },
642 { 0x14f, 0x39aa },
643 /* { 0x154, 0x2f39 },*/
644 { 0x14d, 0xba33 },
645 { 0x144, 0x0048 },
646 { 0x152, 0x2010 },
647 /* { 0x158, 0x1223 },*/
648 { 0x140, 0x4444 },
649 { 0x154, 0x2f3b },
650 { 0x158, 0xb203 },
651 { 0x157, 0x2029 },
652 };
653
654 /* Start Workaround for OptimaEEE Rev.Z0 */
655 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 0x00fb);
656
657 gm_phy_write(hw, port, reg: 1, val: 0x4099);
658 gm_phy_write(hw, port, reg: 3, val: 0x1120);
659 gm_phy_write(hw, port, reg: 11, val: 0x113c);
660 gm_phy_write(hw, port, reg: 14, val: 0x8100);
661 gm_phy_write(hw, port, reg: 15, val: 0x112a);
662 gm_phy_write(hw, port, reg: 17, val: 0x1008);
663
664 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 0x00fc);
665 gm_phy_write(hw, port, reg: 1, val: 0x20b0);
666
667 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 0x00ff);
668
669 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
670 /* apply AFE settings */
671 gm_phy_write(hw, port, reg: 17, val: eee_afe[i].val);
672 gm_phy_write(hw, port, reg: 16, val: eee_afe[i].reg | 1u<<13);
673 }
674
675 /* End Workaround for OptimaEEE */
676 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 0);
677
678 /* Enable 10Base-Te (EEE) */
679 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
680 reg = gm_phy_read(hw, port, reg: PHY_MARV_EXT_CTRL);
681 gm_phy_write(hw, port, reg: PHY_MARV_EXT_CTRL,
682 val: reg | PHY_M_10B_TE_ENABLE);
683 }
684 }
685
686 /* Enable phy interrupt on auto-negotiation complete (or link up) */
687 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
688 gm_phy_write(hw, port, reg: PHY_MARV_INT_MASK, val: PHY_M_IS_AN_COMPL);
689 else
690 gm_phy_write(hw, port, reg: PHY_MARV_INT_MASK, val: PHY_M_DEF_MSK);
691}
692
693static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
694static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
695
696static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
697{
698 u32 reg1;
699
700 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_ON);
701 reg1 = sky2_pci_read32(hw, reg: PCI_DEV_REG1);
702 reg1 &= ~phy_power[port];
703
704 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
705 reg1 |= coma_mode[port];
706
707 sky2_pci_write32(hw, reg: PCI_DEV_REG1, val: reg1);
708 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_OFF);
709 sky2_pci_read32(hw, reg: PCI_DEV_REG1);
710
711 if (hw->chip_id == CHIP_ID_YUKON_FE)
712 gm_phy_write(hw, port, reg: PHY_MARV_CTRL, val: PHY_CT_ANE);
713 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
714 sky2_write8(hw, SK_REG(port, GPHY_CTRL), val: GPC_RST_CLR);
715}
716
717static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
718{
719 u32 reg1;
720 u16 ctrl;
721
722 /* release GPHY Control reset */
723 sky2_write8(hw, SK_REG(port, GPHY_CTRL), val: GPC_RST_CLR);
724
725 /* release GMAC reset */
726 sky2_write8(hw, SK_REG(port, GMAC_CTRL), val: GMC_RST_CLR);
727
728 if (hw->flags & SKY2_HW_NEWER_PHY) {
729 /* select page 2 to access MAC control register */
730 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 2);
731
732 ctrl = gm_phy_read(hw, port, reg: PHY_MARV_PHY_CTRL);
733 /* allow GMII Power Down */
734 ctrl &= ~PHY_M_MAC_GMIF_PUP;
735 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL, val: ctrl);
736
737 /* set page register back to 0 */
738 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 0);
739 }
740
741 /* setup General Purpose Control Register */
742 gma_write16(hw, port, r: GM_GP_CTRL,
743 v: GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
744 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
745 GM_GPCR_AU_SPD_DIS);
746
747 if (hw->chip_id != CHIP_ID_YUKON_EC) {
748 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
749 /* select page 2 to access MAC control register */
750 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 2);
751
752 ctrl = gm_phy_read(hw, port, reg: PHY_MARV_PHY_CTRL);
753 /* enable Power Down */
754 ctrl |= PHY_M_PC_POW_D_ENA;
755 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL, val: ctrl);
756
757 /* set page register back to 0 */
758 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 0);
759 }
760
761 /* set IEEE compatible Power Down Mode (dev. #4.99) */
762 gm_phy_write(hw, port, reg: PHY_MARV_CTRL, val: PHY_CT_PDOWN);
763 }
764
765 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_ON);
766 reg1 = sky2_pci_read32(hw, reg: PCI_DEV_REG1);
767 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
768 sky2_pci_write32(hw, reg: PCI_DEV_REG1, val: reg1);
769 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_OFF);
770}
771
772/* configure IPG according to used link speed */
773static void sky2_set_ipg(struct sky2_port *sky2)
774{
775 u16 reg;
776
777 reg = gma_read16(hw: sky2->hw, port: sky2->port, reg: GM_SERIAL_MODE);
778 reg &= ~GM_SMOD_IPG_MSK;
779 if (sky2->speed > SPEED_100)
780 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
781 else
782 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
783 gma_write16(hw: sky2->hw, port: sky2->port, r: GM_SERIAL_MODE, v: reg);
784}
785
786/* Enable Rx/Tx */
787static void sky2_enable_rx_tx(struct sky2_port *sky2)
788{
789 struct sky2_hw *hw = sky2->hw;
790 unsigned port = sky2->port;
791 u16 reg;
792
793 reg = gma_read16(hw, port, reg: GM_GP_CTRL);
794 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
795 gma_write16(hw, port, r: GM_GP_CTRL, v: reg);
796}
797
798/* Force a renegotiation */
799static void sky2_phy_reinit(struct sky2_port *sky2)
800{
801 spin_lock_bh(lock: &sky2->phy_lock);
802 sky2_phy_init(hw: sky2->hw, port: sky2->port);
803 sky2_enable_rx_tx(sky2);
804 spin_unlock_bh(lock: &sky2->phy_lock);
805}
806
807/* Put device in state to listen for Wake On Lan */
808static void sky2_wol_init(struct sky2_port *sky2)
809{
810 struct sky2_hw *hw = sky2->hw;
811 unsigned port = sky2->port;
812 enum flow_control save_mode;
813 u16 ctrl;
814
815 /* Bring hardware out of reset */
816 sky2_write16(hw, reg: B0_CTST, val: CS_RST_CLR);
817 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), val: GMLC_RST_CLR);
818
819 sky2_write8(hw, SK_REG(port, GPHY_CTRL), val: GPC_RST_CLR);
820 sky2_write8(hw, SK_REG(port, GMAC_CTRL), val: GMC_RST_CLR);
821
822 /* Force to 10/100
823 * sky2_reset will re-enable on resume
824 */
825 save_mode = sky2->flow_mode;
826 ctrl = sky2->advertising;
827
828 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
829 sky2->flow_mode = FC_NONE;
830
831 spin_lock_bh(lock: &sky2->phy_lock);
832 sky2_phy_power_up(hw, port);
833 sky2_phy_init(hw, port);
834 spin_unlock_bh(lock: &sky2->phy_lock);
835
836 sky2->flow_mode = save_mode;
837 sky2->advertising = ctrl;
838
839 /* Set GMAC to no flow control and auto update for speed/duplex */
840 gma_write16(hw, port, r: GM_GP_CTRL,
841 v: GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
842 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
843
844 /* Set WOL address */
845 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
846 sky2->netdev->dev_addr, ETH_ALEN);
847
848 /* Turn on appropriate WOL control bits */
849 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), val: WOL_CTL_CLEAR_RESULT);
850 ctrl = 0;
851 if (sky2->wol & WAKE_PHY)
852 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
853 else
854 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
855
856 if (sky2->wol & WAKE_MAGIC)
857 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
858 else
859 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
860
861 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
862 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), val: ctrl);
863
864 /* Disable PiG firmware */
865 sky2_write16(hw, reg: B0_CTST, val: Y2_HW_WOL_OFF);
866
867 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
868 if (legacy_pme) {
869 u32 reg1 = sky2_pci_read32(hw, reg: PCI_DEV_REG1);
870 reg1 |= PCI_Y2_PME_LEGACY;
871 sky2_pci_write32(hw, reg: PCI_DEV_REG1, val: reg1);
872 }
873
874 /* block receiver */
875 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), val: GMF_RST_SET);
876 sky2_read32(hw, reg: B0_CTST);
877}
878
879static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
880{
881 struct net_device *dev = hw->dev[port];
882
883 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
884 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
885 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
886 /* Yukon-Extreme B0 and further Extreme devices */
887 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), val: TX_STFW_ENA);
888 } else if (dev->mtu > ETH_DATA_LEN) {
889 /* set Tx GMAC FIFO Almost Empty Threshold */
890 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
891 val: (ECU_JUMBO_WM << 16) | ECU_AE_THR);
892
893 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), val: TX_STFW_DIS);
894 } else
895 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), val: TX_STFW_ENA);
896}
897
898static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
899{
900 struct sky2_port *sky2 = netdev_priv(dev: hw->dev[port]);
901 u16 reg;
902 u32 rx_reg;
903 int i;
904 const u8 *addr = hw->dev[port]->dev_addr;
905
906 sky2_write8(hw, SK_REG(port, GPHY_CTRL), val: GPC_RST_SET);
907 sky2_write8(hw, SK_REG(port, GPHY_CTRL), val: GPC_RST_CLR);
908
909 sky2_write8(hw, SK_REG(port, GMAC_CTRL), val: GMC_RST_CLR);
910
911 if (hw->chip_id == CHIP_ID_YUKON_XL &&
912 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
913 port == 1) {
914 /* WA DEV_472 -- looks like crossed wires on port 2 */
915 /* clear GMAC 1 Control reset */
916 sky2_write8(hw, SK_REG(0, GMAC_CTRL), val: GMC_RST_CLR);
917 do {
918 sky2_write8(hw, SK_REG(1, GMAC_CTRL), val: GMC_RST_SET);
919 sky2_write8(hw, SK_REG(1, GMAC_CTRL), val: GMC_RST_CLR);
920 } while (gm_phy_read(hw, port: 1, reg: PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
921 gm_phy_read(hw, port: 1, reg: PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
922 gm_phy_read(hw, port: 1, reg: PHY_MARV_INT_MASK) != 0);
923 }
924
925 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
926
927 /* Enable Transmit FIFO Underrun */
928 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
929
930 spin_lock_bh(lock: &sky2->phy_lock);
931 sky2_phy_power_up(hw, port);
932 sky2_phy_init(hw, port);
933 spin_unlock_bh(lock: &sky2->phy_lock);
934
935 /* MIB clear */
936 reg = gma_read16(hw, port, reg: GM_PHY_ADDR);
937 gma_write16(hw, port, r: GM_PHY_ADDR, v: reg | GM_PAR_MIB_CLR);
938
939 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
940 gma_read16(hw, port, reg: i);
941 gma_write16(hw, port, r: GM_PHY_ADDR, v: reg);
942
943 /* transmit control */
944 gma_write16(hw, port, r: GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
945
946 /* receive control reg: unicast + multicast + no FCS */
947 gma_write16(hw, port, r: GM_RX_CTRL,
948 v: GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
949
950 /* transmit flow control */
951 gma_write16(hw, port, r: GM_TX_FLOW_CTRL, v: 0xffff);
952
953 /* transmit parameter */
954 gma_write16(hw, port, r: GM_TX_PARAM,
955 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
956 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
957 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
958 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
959
960 /* serial mode register */
961 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
962 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
963
964 if (hw->dev[port]->mtu > ETH_DATA_LEN)
965 reg |= GM_SMOD_JUMBO_ENA;
966
967 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
968 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
969 reg |= GM_NEW_FLOW_CTRL;
970
971 gma_write16(hw, port, r: GM_SERIAL_MODE, v: reg);
972
973 /* virtual address for data */
974 gma_set_addr(hw, port, reg: GM_SRC_ADDR_2L, addr);
975
976 /* physical address: used for pause frames */
977 gma_set_addr(hw, port, reg: GM_SRC_ADDR_1L, addr);
978
979 /* ignore counter overflows */
980 gma_write16(hw, port, r: GM_TX_IRQ_MSK, v: 0);
981 gma_write16(hw, port, r: GM_RX_IRQ_MSK, v: 0);
982 gma_write16(hw, port, r: GM_TR_IRQ_MSK, v: 0);
983
984 /* Configure Rx MAC FIFO */
985 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), val: GMF_RST_CLR);
986 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
987 if (hw->chip_id == CHIP_ID_YUKON_EX ||
988 hw->chip_id == CHIP_ID_YUKON_FE_P)
989 rx_reg |= GMF_RX_OVER_ON;
990
991 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), val: rx_reg);
992
993 if (hw->chip_id == CHIP_ID_YUKON_XL) {
994 /* Hardware errata - clear flush mask */
995 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), val: 0);
996 } else {
997 /* Flush Rx MAC FIFO on any flow control or error */
998 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), val: GMR_FS_ANY_ERR);
999 }
1000
1001 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1002 reg = RX_GMF_FL_THR_DEF + 1;
1003 /* Another magic mystery workaround from sk98lin */
1004 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1005 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1006 reg = 0x178;
1007 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), val: reg);
1008
1009 /* Configure Tx MAC FIFO */
1010 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), val: GMF_RST_CLR);
1011 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), val: GMF_OPER_ON);
1012
1013 /* On chips without ram buffer, pause is controlled by MAC level */
1014 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1015 /* Pause threshold is scaled by 8 in bytes */
1016 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1017 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1018 reg = 1568 / 8;
1019 else
1020 reg = 1024 / 8;
1021 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), val: reg);
1022 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), val: 768 / 8);
1023
1024 sky2_set_tx_stfwd(hw, port);
1025 }
1026
1027 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1028 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1029 /* disable dynamic watermark */
1030 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1031 reg &= ~TX_DYN_WM_ENA;
1032 sky2_write16(hw, SK_REG(port, TX_GMF_EA), val: reg);
1033 }
1034}
1035
1036/* Assign Ram Buffer allocation to queue */
1037static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1038{
1039 u32 end;
1040
1041 /* convert from K bytes to qwords used for hw register */
1042 start *= 1024/8;
1043 space *= 1024/8;
1044 end = start + space - 1;
1045
1046 sky2_write8(hw, RB_ADDR(q, RB_CTRL), val: RB_RST_CLR);
1047 sky2_write32(hw, RB_ADDR(q, RB_START), val: start);
1048 sky2_write32(hw, RB_ADDR(q, RB_END), val: end);
1049 sky2_write32(hw, RB_ADDR(q, RB_WP), val: start);
1050 sky2_write32(hw, RB_ADDR(q, RB_RP), val: start);
1051
1052 if (q == Q_R1 || q == Q_R2) {
1053 u32 tp = space - space/4;
1054
1055 /* On receive queue's set the thresholds
1056 * give receiver priority when > 3/4 full
1057 * send pause when down to 2K
1058 */
1059 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), val: tp);
1060 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), val: space/2);
1061
1062 tp = space - 8192/8;
1063 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), val: tp);
1064 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), val: space/4);
1065 } else {
1066 /* Enable store & forward on Tx queue's because
1067 * Tx FIFO is only 1K on Yukon
1068 */
1069 sky2_write8(hw, RB_ADDR(q, RB_CTRL), val: RB_ENA_STFWD);
1070 }
1071
1072 sky2_write8(hw, RB_ADDR(q, RB_CTRL), val: RB_ENA_OP_MD);
1073 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1074}
1075
1076/* Setup Bus Memory Interface */
1077static void sky2_qset(struct sky2_hw *hw, u16 q)
1078{
1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), val: BMU_CLR_RESET);
1080 sky2_write32(hw, Q_ADDR(q, Q_CSR), val: BMU_OPER_INIT);
1081 sky2_write32(hw, Q_ADDR(q, Q_CSR), val: BMU_FIFO_OP_ON);
1082 sky2_write32(hw, Q_ADDR(q, Q_WM), val: BMU_WM_DEFAULT);
1083}
1084
1085/* Setup prefetch unit registers. This is the interface between
1086 * hardware and driver list elements
1087 */
1088static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1089 dma_addr_t addr, u32 last)
1090{
1091 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), val: PREF_UNIT_RST_SET);
1092 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), val: PREF_UNIT_RST_CLR);
1093 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1094 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1095 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), val: last);
1096 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), val: PREF_UNIT_OP_ON);
1097
1098 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1099}
1100
1101static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1102{
1103 struct sky2_tx_le *le = sky2->tx_le + *slot;
1104
1105 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1106 le->ctrl = 0;
1107 return le;
1108}
1109
1110static void tx_init(struct sky2_port *sky2)
1111{
1112 struct sky2_tx_le *le;
1113
1114 sky2->tx_prod = sky2->tx_cons = 0;
1115 sky2->tx_tcpsum = 0;
1116 sky2->tx_last_mss = 0;
1117 netdev_reset_queue(dev_queue: sky2->netdev);
1118
1119 le = get_tx_le(sky2, slot: &sky2->tx_prod);
1120 le->addr = 0;
1121 le->opcode = OP_ADDR64 | HW_OWNER;
1122 sky2->tx_last_upper = 0;
1123}
1124
1125/* Update chip's next pointer */
1126static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1127{
1128 /* Make sure write' to descriptors are complete before we tell hardware */
1129 wmb();
1130 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), val: idx);
1131}
1132
1133
1134static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1135{
1136 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1137 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1138 le->ctrl = 0;
1139 return le;
1140}
1141
1142static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1143{
1144 unsigned size;
1145
1146 /* Space needed for frame data + headers rounded up */
1147 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1148
1149 /* Stopping point for hardware truncation */
1150 return (size - 8) / sizeof(u32);
1151}
1152
1153static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1154{
1155 struct rx_ring_info *re;
1156 unsigned size;
1157
1158 /* Space needed for frame data + headers rounded up */
1159 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1160
1161 sky2->rx_nfrags = size >> PAGE_SHIFT;
1162 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1163
1164 /* Compute residue after pages */
1165 size -= sky2->rx_nfrags << PAGE_SHIFT;
1166
1167 /* Optimize to handle small packets and headers */
1168 if (size < copybreak)
1169 size = copybreak;
1170 if (size < ETH_HLEN)
1171 size = ETH_HLEN;
1172
1173 return size;
1174}
1175
1176/* Build description to hardware for one receive segment */
1177static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1178 dma_addr_t map, unsigned len)
1179{
1180 struct sky2_rx_le *le;
1181
1182 if (sizeof(dma_addr_t) > sizeof(u32)) {
1183 le = sky2_next_rx(sky2);
1184 le->addr = cpu_to_le32(upper_32_bits(map));
1185 le->opcode = OP_ADDR64 | HW_OWNER;
1186 }
1187
1188 le = sky2_next_rx(sky2);
1189 le->addr = cpu_to_le32(lower_32_bits(map));
1190 le->length = cpu_to_le16(len);
1191 le->opcode = op | HW_OWNER;
1192}
1193
1194/* Build description to hardware for one possibly fragmented skb */
1195static void sky2_rx_submit(struct sky2_port *sky2,
1196 const struct rx_ring_info *re)
1197{
1198 int i;
1199
1200 sky2_rx_add(sky2, op: OP_PACKET, map: re->data_addr, len: sky2->rx_data_size);
1201
1202 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1203 sky2_rx_add(sky2, op: OP_BUFFER, map: re->frag_addr[i], PAGE_SIZE);
1204}
1205
1206
1207static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1208 unsigned size)
1209{
1210 struct sk_buff *skb = re->skb;
1211 int i;
1212
1213 re->data_addr = dma_map_single(&pdev->dev, skb->data, size,
1214 DMA_FROM_DEVICE);
1215 if (dma_mapping_error(dev: &pdev->dev, dma_addr: re->data_addr))
1216 goto mapping_error;
1217
1218 dma_unmap_len_set(re, data_size, size);
1219
1220 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1221 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1222
1223 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1224 skb_frag_size(frag),
1225 DMA_FROM_DEVICE);
1226
1227 if (dma_mapping_error(dev: &pdev->dev, dma_addr: re->frag_addr[i]))
1228 goto map_page_error;
1229 }
1230 return 0;
1231
1232map_page_error:
1233 while (--i >= 0) {
1234 dma_unmap_page(&pdev->dev, re->frag_addr[i],
1235 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1236 DMA_FROM_DEVICE);
1237 }
1238
1239 dma_unmap_single(&pdev->dev, re->data_addr,
1240 dma_unmap_len(re, data_size), DMA_FROM_DEVICE);
1241
1242mapping_error:
1243 if (net_ratelimit())
1244 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1245 skb->dev->name);
1246 return -EIO;
1247}
1248
1249static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1250{
1251 struct sk_buff *skb = re->skb;
1252 int i;
1253
1254 dma_unmap_single(&pdev->dev, re->data_addr,
1255 dma_unmap_len(re, data_size), DMA_FROM_DEVICE);
1256
1257 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1258 dma_unmap_page(&pdev->dev, re->frag_addr[i],
1259 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1260 DMA_FROM_DEVICE);
1261}
1262
1263/* Tell chip where to start receive checksum.
1264 * Actually has two checksums, but set both same to avoid possible byte
1265 * order problems.
1266 */
1267static void rx_set_checksum(struct sky2_port *sky2)
1268{
1269 struct sky2_rx_le *le = sky2_next_rx(sky2);
1270
1271 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1272 le->ctrl = 0;
1273 le->opcode = OP_TCPSTART | HW_OWNER;
1274
1275 sky2_write32(hw: sky2->hw,
1276 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1277 val: (sky2->netdev->features & NETIF_F_RXCSUM)
1278 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1279}
1280
1281/* Enable/disable receive hash calculation (RSS) */
1282static void rx_set_rss(struct net_device *dev, netdev_features_t features)
1283{
1284 struct sky2_port *sky2 = netdev_priv(dev);
1285 struct sky2_hw *hw = sky2->hw;
1286 int i, nkeys = 4;
1287
1288 /* Supports IPv6 and other modes */
1289 if (hw->flags & SKY2_HW_NEW_LE) {
1290 nkeys = 10;
1291 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), val: HASH_ALL);
1292 }
1293
1294 /* Program RSS initial values */
1295 if (features & NETIF_F_RXHASH) {
1296 u32 rss_key[10];
1297
1298 netdev_rss_key_fill(buffer: rss_key, len: sizeof(rss_key));
1299 for (i = 0; i < nkeys; i++)
1300 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1301 val: rss_key[i]);
1302
1303 /* Need to turn on (undocumented) flag to make hashing work */
1304 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1305 val: RX_STFW_ENA);
1306
1307 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1308 val: BMU_ENA_RX_RSS_HASH);
1309 } else
1310 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1311 val: BMU_DIS_RX_RSS_HASH);
1312}
1313
1314/*
1315 * The RX Stop command will not work for Yukon-2 if the BMU does not
1316 * reach the end of packet and since we can't make sure that we have
1317 * incoming data, we must reset the BMU while it is not doing a DMA
1318 * transfer. Since it is possible that the RX path is still active,
1319 * the RX RAM buffer will be stopped first, so any possible incoming
1320 * data will not trigger a DMA. After the RAM buffer is stopped, the
1321 * BMU is polled until any DMA in progress is ended and only then it
1322 * will be reset.
1323 */
1324static void sky2_rx_stop(struct sky2_port *sky2)
1325{
1326 struct sky2_hw *hw = sky2->hw;
1327 unsigned rxq = rxqaddr[sky2->port];
1328 int i;
1329
1330 /* disable the RAM Buffer receive queue */
1331 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), val: RB_DIS_OP_MD);
1332
1333 for (i = 0; i < 0xffff; i++)
1334 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1335 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1336 goto stopped;
1337
1338 netdev_warn(dev: sky2->netdev, format: "receiver stop failed\n");
1339stopped:
1340 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), val: BMU_RST_SET | BMU_FIFO_RST);
1341
1342 /* reset the Rx prefetch unit */
1343 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), val: PREF_UNIT_RST_SET);
1344}
1345
1346/* Clean out receive buffer area, assumes receiver hardware stopped */
1347static void sky2_rx_clean(struct sky2_port *sky2)
1348{
1349 unsigned i;
1350
1351 if (sky2->rx_le)
1352 memset(s: sky2->rx_le, c: 0, RX_LE_BYTES);
1353
1354 for (i = 0; i < sky2->rx_pending; i++) {
1355 struct rx_ring_info *re = sky2->rx_ring + i;
1356
1357 if (re->skb) {
1358 sky2_rx_unmap_skb(pdev: sky2->hw->pdev, re);
1359 kfree_skb(skb: re->skb);
1360 re->skb = NULL;
1361 }
1362 }
1363}
1364
1365/* Basic MII support */
1366static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1367{
1368 struct mii_ioctl_data *data = if_mii(rq: ifr);
1369 struct sky2_port *sky2 = netdev_priv(dev);
1370 struct sky2_hw *hw = sky2->hw;
1371 int err = -EOPNOTSUPP;
1372
1373 if (!netif_running(dev))
1374 return -ENODEV; /* Phy still in reset */
1375
1376 switch (cmd) {
1377 case SIOCGMIIPHY:
1378 data->phy_id = PHY_ADDR_MARV;
1379
1380 fallthrough;
1381 case SIOCGMIIREG: {
1382 u16 val = 0;
1383
1384 spin_lock_bh(lock: &sky2->phy_lock);
1385 err = __gm_phy_read(hw, port: sky2->port, reg: data->reg_num & 0x1f, val: &val);
1386 spin_unlock_bh(lock: &sky2->phy_lock);
1387
1388 data->val_out = val;
1389 break;
1390 }
1391
1392 case SIOCSMIIREG:
1393 spin_lock_bh(lock: &sky2->phy_lock);
1394 err = gm_phy_write(hw, port: sky2->port, reg: data->reg_num & 0x1f,
1395 val: data->val_in);
1396 spin_unlock_bh(lock: &sky2->phy_lock);
1397 break;
1398 }
1399 return err;
1400}
1401
1402#define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1403
1404static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
1405{
1406 struct sky2_port *sky2 = netdev_priv(dev);
1407 struct sky2_hw *hw = sky2->hw;
1408 u16 port = sky2->port;
1409
1410 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1411 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1412 val: RX_VLAN_STRIP_ON);
1413 else
1414 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1415 val: RX_VLAN_STRIP_OFF);
1416
1417 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
1418 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1419 val: TX_VLAN_TAG_ON);
1420
1421 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1422 } else {
1423 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1424 val: TX_VLAN_TAG_OFF);
1425
1426 /* Can't do transmit offload of vlan without hw vlan */
1427 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1428 }
1429}
1430
1431/* Amount of required worst case padding in rx buffer */
1432static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1433{
1434 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1435}
1436
1437/*
1438 * Allocate an skb for receiving. If the MTU is large enough
1439 * make the skb non-linear with a fragment list of pages.
1440 */
1441static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1442{
1443 struct sk_buff *skb;
1444 int i;
1445
1446 skb = __netdev_alloc_skb(dev: sky2->netdev,
1447 length: sky2->rx_data_size + sky2_rx_pad(hw: sky2->hw),
1448 gfp_mask: gfp);
1449 if (!skb)
1450 goto nomem;
1451
1452 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1453 unsigned char *start;
1454 /*
1455 * Workaround for a bug in FIFO that cause hang
1456 * if the FIFO if the receive buffer is not 64 byte aligned.
1457 * The buffer returned from netdev_alloc_skb is
1458 * aligned except if slab debugging is enabled.
1459 */
1460 start = PTR_ALIGN(skb->data, 8);
1461 skb_reserve(skb, len: start - skb->data);
1462 } else
1463 skb_reserve(skb, NET_IP_ALIGN);
1464
1465 for (i = 0; i < sky2->rx_nfrags; i++) {
1466 struct page *page = alloc_page(gfp);
1467
1468 if (!page)
1469 goto free_partial;
1470 skb_fill_page_desc(skb, i, page, off: 0, PAGE_SIZE);
1471 }
1472
1473 return skb;
1474free_partial:
1475 kfree_skb(skb);
1476nomem:
1477 return NULL;
1478}
1479
1480static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1481{
1482 sky2_put_idx(hw: sky2->hw, q: rxq, idx: sky2->rx_put);
1483}
1484
1485static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1486{
1487 struct sky2_hw *hw = sky2->hw;
1488 unsigned i;
1489
1490 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1491
1492 /* Fill Rx ring */
1493 for (i = 0; i < sky2->rx_pending; i++) {
1494 struct rx_ring_info *re = sky2->rx_ring + i;
1495
1496 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1497 if (!re->skb)
1498 return -ENOMEM;
1499
1500 if (sky2_rx_map_skb(pdev: hw->pdev, re, size: sky2->rx_data_size)) {
1501 dev_kfree_skb(re->skb);
1502 re->skb = NULL;
1503 return -ENOMEM;
1504 }
1505 }
1506 return 0;
1507}
1508
1509/*
1510 * Setup receiver buffer pool.
1511 * Normal case this ends up creating one list element for skb
1512 * in the receive ring. Worst case if using large MTU and each
1513 * allocation falls on a different 64 bit region, that results
1514 * in 6 list elements per ring entry.
1515 * One element is used for checksum enable/disable, and one
1516 * extra to avoid wrap.
1517 */
1518static void sky2_rx_start(struct sky2_port *sky2)
1519{
1520 struct sky2_hw *hw = sky2->hw;
1521 struct rx_ring_info *re;
1522 unsigned rxq = rxqaddr[sky2->port];
1523 unsigned i, thresh;
1524
1525 sky2->rx_put = sky2->rx_next = 0;
1526 sky2_qset(hw, q: rxq);
1527
1528 /* On PCI express lowering the watermark gives better performance */
1529 if (pci_is_pcie(dev: hw->pdev))
1530 sky2_write32(hw, Q_ADDR(rxq, Q_WM), val: BMU_WM_PEX);
1531
1532 /* These chips have no ram buffer?
1533 * MAC Rx RAM Read is controlled by hardware
1534 */
1535 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1536 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1537 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), val: F_M_RX_RAM_DIS);
1538
1539 sky2_prefetch_init(hw, qaddr: rxq, addr: sky2->rx_le_map, RX_LE_SIZE - 1);
1540
1541 if (!(hw->flags & SKY2_HW_NEW_LE))
1542 rx_set_checksum(sky2);
1543
1544 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1545 rx_set_rss(dev: sky2->netdev, features: sky2->netdev->features);
1546
1547 /* submit Rx ring */
1548 for (i = 0; i < sky2->rx_pending; i++) {
1549 re = sky2->rx_ring + i;
1550 sky2_rx_submit(sky2, re);
1551 }
1552
1553 /*
1554 * The receiver hangs if it receives frames larger than the
1555 * packet buffer. As a workaround, truncate oversize frames, but
1556 * the register is limited to 9 bits, so if you do frames > 2052
1557 * you better get the MTU right!
1558 */
1559 thresh = sky2_get_rx_threshold(sky2);
1560 if (thresh > 0x1ff)
1561 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), val: RX_TRUNC_OFF);
1562 else {
1563 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), val: thresh);
1564 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), val: RX_TRUNC_ON);
1565 }
1566
1567 /* Tell chip about available buffers */
1568 sky2_rx_update(sky2, rxq);
1569
1570 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1571 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1572 /*
1573 * Disable flushing of non ASF packets;
1574 * must be done after initializing the BMUs;
1575 * drivers without ASF support should do this too, otherwise
1576 * it may happen that they cannot run on ASF devices;
1577 * remember that the MAC FIFO isn't reset during initialization.
1578 */
1579 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), val: RX_MACSEC_FLUSH_OFF);
1580 }
1581
1582 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1583 /* Enable RX Home Address & Routing Header checksum fix */
1584 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1585 val: RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1586
1587 /* Enable TX Home Address & Routing Header checksum fix */
1588 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1589 val: TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1590 }
1591}
1592
1593static int sky2_alloc_buffers(struct sky2_port *sky2)
1594{
1595 struct sky2_hw *hw = sky2->hw;
1596
1597 /* must be power of 2 */
1598 sky2->tx_le = dma_alloc_coherent(dev: &hw->pdev->dev,
1599 size: sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1600 dma_handle: &sky2->tx_le_map, GFP_KERNEL);
1601 if (!sky2->tx_le)
1602 goto nomem;
1603
1604 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1605 GFP_KERNEL);
1606 if (!sky2->tx_ring)
1607 goto nomem;
1608
1609 sky2->rx_le = dma_alloc_coherent(dev: &hw->pdev->dev, RX_LE_BYTES,
1610 dma_handle: &sky2->rx_le_map, GFP_KERNEL);
1611 if (!sky2->rx_le)
1612 goto nomem;
1613
1614 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1615 GFP_KERNEL);
1616 if (!sky2->rx_ring)
1617 goto nomem;
1618
1619 return sky2_alloc_rx_skbs(sky2);
1620nomem:
1621 return -ENOMEM;
1622}
1623
1624static void sky2_free_buffers(struct sky2_port *sky2)
1625{
1626 struct sky2_hw *hw = sky2->hw;
1627
1628 sky2_rx_clean(sky2);
1629
1630 if (sky2->rx_le) {
1631 dma_free_coherent(dev: &hw->pdev->dev, RX_LE_BYTES, cpu_addr: sky2->rx_le,
1632 dma_handle: sky2->rx_le_map);
1633 sky2->rx_le = NULL;
1634 }
1635 if (sky2->tx_le) {
1636 dma_free_coherent(dev: &hw->pdev->dev,
1637 size: sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1638 cpu_addr: sky2->tx_le, dma_handle: sky2->tx_le_map);
1639 sky2->tx_le = NULL;
1640 }
1641 kfree(objp: sky2->tx_ring);
1642 kfree(objp: sky2->rx_ring);
1643
1644 sky2->tx_ring = NULL;
1645 sky2->rx_ring = NULL;
1646}
1647
1648static void sky2_hw_up(struct sky2_port *sky2)
1649{
1650 struct sky2_hw *hw = sky2->hw;
1651 unsigned port = sky2->port;
1652 u32 ramsize;
1653 int cap;
1654 struct net_device *otherdev = hw->dev[sky2->port^1];
1655
1656 tx_init(sky2);
1657
1658 /*
1659 * On dual port PCI-X card, there is an problem where status
1660 * can be received out of order due to split transactions
1661 */
1662 if (otherdev && netif_running(dev: otherdev) &&
1663 (cap = pci_find_capability(dev: hw->pdev, PCI_CAP_ID_PCIX))) {
1664 u16 cmd;
1665
1666 cmd = sky2_pci_read16(hw, reg: cap + PCI_X_CMD);
1667 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1668 sky2_pci_write16(hw, reg: cap + PCI_X_CMD, val: cmd);
1669 }
1670
1671 sky2_mac_init(hw, port);
1672
1673 /* Register is number of 4K blocks on internal RAM buffer. */
1674 ramsize = sky2_read8(hw, reg: B2_E_0) * 4;
1675 if (ramsize > 0) {
1676 u32 rxspace;
1677
1678 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1679 if (ramsize < 16)
1680 rxspace = ramsize / 2;
1681 else
1682 rxspace = 8 + (2*(ramsize - 16))/3;
1683
1684 sky2_ramset(hw, q: rxqaddr[port], start: 0, space: rxspace);
1685 sky2_ramset(hw, q: txqaddr[port], start: rxspace, space: ramsize - rxspace);
1686
1687 /* Make sure SyncQ is disabled */
1688 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1689 val: RB_RST_SET);
1690 }
1691
1692 sky2_qset(hw, q: txqaddr[port]);
1693
1694 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1695 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1696 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), val: F_TX_CHK_AUTO_OFF);
1697
1698 /* Set almost empty threshold */
1699 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1700 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1701 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), val: ECU_TXFF_LEV);
1702
1703 sky2_prefetch_init(hw, qaddr: txqaddr[port], addr: sky2->tx_le_map,
1704 last: sky2->tx_ring_size - 1);
1705
1706 sky2_vlan_mode(dev: sky2->netdev, features: sky2->netdev->features);
1707 netdev_update_features(dev: sky2->netdev);
1708
1709 sky2_rx_start(sky2);
1710}
1711
1712/* Setup device IRQ and enable napi to process */
1713static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1714{
1715 struct pci_dev *pdev = hw->pdev;
1716 int err;
1717
1718 err = request_irq(irq: pdev->irq, handler: sky2_intr,
1719 flags: (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1720 name, dev: hw);
1721 if (err)
1722 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1723 else {
1724 hw->flags |= SKY2_HW_IRQ_SETUP;
1725
1726 napi_enable(n: &hw->napi);
1727 sky2_write32(hw, reg: B0_IMSK, val: Y2_IS_BASE);
1728 sky2_read32(hw, reg: B0_IMSK);
1729 }
1730
1731 return err;
1732}
1733
1734
1735/* Bring up network interface. */
1736static int sky2_open(struct net_device *dev)
1737{
1738 struct sky2_port *sky2 = netdev_priv(dev);
1739 struct sky2_hw *hw = sky2->hw;
1740 unsigned port = sky2->port;
1741 u32 imask;
1742 int err;
1743
1744 netif_carrier_off(dev);
1745
1746 err = sky2_alloc_buffers(sky2);
1747 if (err)
1748 goto err_out;
1749
1750 /* With single port, IRQ is setup when device is brought up */
1751 if (hw->ports == 1 && (err = sky2_setup_irq(hw, name: dev->name)))
1752 goto err_out;
1753
1754 sky2_hw_up(sky2);
1755
1756 /* Enable interrupts from phy/mac for port */
1757 imask = sky2_read32(hw, reg: B0_IMSK);
1758
1759 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1760 hw->chip_id == CHIP_ID_YUKON_PRM ||
1761 hw->chip_id == CHIP_ID_YUKON_OP_2)
1762 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1763
1764 imask |= portirq_msk[port];
1765 sky2_write32(hw, reg: B0_IMSK, val: imask);
1766 sky2_read32(hw, reg: B0_IMSK);
1767
1768 netif_info(sky2, ifup, dev, "enabling interface\n");
1769
1770 return 0;
1771
1772err_out:
1773 sky2_free_buffers(sky2);
1774 return err;
1775}
1776
1777/* Modular subtraction in ring */
1778static inline int tx_inuse(const struct sky2_port *sky2)
1779{
1780 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1781}
1782
1783/* Number of list elements available for next tx */
1784static inline int tx_avail(const struct sky2_port *sky2)
1785{
1786 return sky2->tx_pending - tx_inuse(sky2);
1787}
1788
1789/* Estimate of number of transmit list elements required */
1790static unsigned tx_le_req(const struct sk_buff *skb)
1791{
1792 unsigned count;
1793
1794 count = (skb_shinfo(skb)->nr_frags + 1)
1795 * (sizeof(dma_addr_t) / sizeof(u32));
1796
1797 if (skb_is_gso(skb))
1798 ++count;
1799 else if (sizeof(dma_addr_t) == sizeof(u32))
1800 ++count; /* possible vlan */
1801
1802 if (skb->ip_summed == CHECKSUM_PARTIAL)
1803 ++count;
1804
1805 return count;
1806}
1807
1808static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1809{
1810 if (re->flags & TX_MAP_SINGLE)
1811 dma_unmap_single(&pdev->dev, dma_unmap_addr(re, mapaddr),
1812 dma_unmap_len(re, maplen), DMA_TO_DEVICE);
1813 else if (re->flags & TX_MAP_PAGE)
1814 dma_unmap_page(&pdev->dev, dma_unmap_addr(re, mapaddr),
1815 dma_unmap_len(re, maplen), DMA_TO_DEVICE);
1816 re->flags = 0;
1817}
1818
1819/*
1820 * Put one packet in ring for transmit.
1821 * A single packet can generate multiple list elements, and
1822 * the number of ring elements will probably be less than the number
1823 * of list elements used.
1824 */
1825static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1826 struct net_device *dev)
1827{
1828 struct sky2_port *sky2 = netdev_priv(dev);
1829 struct sky2_hw *hw = sky2->hw;
1830 struct sky2_tx_le *le = NULL;
1831 struct tx_ring_info *re;
1832 unsigned i, len;
1833 dma_addr_t mapping;
1834 u32 upper;
1835 u16 slot;
1836 u16 mss;
1837 u8 ctrl;
1838
1839 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1840 return NETDEV_TX_BUSY;
1841
1842 len = skb_headlen(skb);
1843 mapping = dma_map_single(&hw->pdev->dev, skb->data, len,
1844 DMA_TO_DEVICE);
1845
1846 if (dma_mapping_error(dev: &hw->pdev->dev, dma_addr: mapping))
1847 goto mapping_error;
1848
1849 slot = sky2->tx_prod;
1850 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1851 "tx queued, slot %u, len %d\n", slot, skb->len);
1852
1853 /* Send high bits if needed */
1854 upper = upper_32_bits(mapping);
1855 if (upper != sky2->tx_last_upper) {
1856 le = get_tx_le(sky2, slot: &slot);
1857 le->addr = cpu_to_le32(upper);
1858 sky2->tx_last_upper = upper;
1859 le->opcode = OP_ADDR64 | HW_OWNER;
1860 }
1861
1862 /* Check for TCP Segmentation Offload */
1863 mss = skb_shinfo(skb)->gso_size;
1864 if (mss != 0) {
1865
1866 if (!(hw->flags & SKY2_HW_NEW_LE))
1867 mss += skb_tcp_all_headers(skb);
1868
1869 if (mss != sky2->tx_last_mss) {
1870 le = get_tx_le(sky2, slot: &slot);
1871 le->addr = cpu_to_le32(mss);
1872
1873 if (hw->flags & SKY2_HW_NEW_LE)
1874 le->opcode = OP_MSS | HW_OWNER;
1875 else
1876 le->opcode = OP_LRGLEN | HW_OWNER;
1877 sky2->tx_last_mss = mss;
1878 }
1879 }
1880
1881 ctrl = 0;
1882
1883 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1884 if (skb_vlan_tag_present(skb)) {
1885 if (!le) {
1886 le = get_tx_le(sky2, slot: &slot);
1887 le->addr = 0;
1888 le->opcode = OP_VLAN|HW_OWNER;
1889 } else
1890 le->opcode |= OP_VLAN;
1891 le->length = cpu_to_be16(skb_vlan_tag_get(skb));
1892 ctrl |= INS_VLAN;
1893 }
1894
1895 /* Handle TCP checksum offload */
1896 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1897 /* On Yukon EX (some versions) encoding change. */
1898 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1899 ctrl |= CALSUM; /* auto checksum */
1900 else {
1901 const unsigned offset = skb_transport_offset(skb);
1902 u32 tcpsum;
1903
1904 tcpsum = offset << 16; /* sum start */
1905 tcpsum |= offset + skb->csum_offset; /* sum write */
1906
1907 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1908 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1909 ctrl |= UDPTCP;
1910
1911 if (tcpsum != sky2->tx_tcpsum) {
1912 sky2->tx_tcpsum = tcpsum;
1913
1914 le = get_tx_le(sky2, slot: &slot);
1915 le->addr = cpu_to_le32(tcpsum);
1916 le->length = 0; /* initial checksum value */
1917 le->ctrl = 1; /* one packet */
1918 le->opcode = OP_TCPLISW | HW_OWNER;
1919 }
1920 }
1921 }
1922
1923 re = sky2->tx_ring + slot;
1924 re->flags = TX_MAP_SINGLE;
1925 dma_unmap_addr_set(re, mapaddr, mapping);
1926 dma_unmap_len_set(re, maplen, len);
1927
1928 le = get_tx_le(sky2, slot: &slot);
1929 le->addr = cpu_to_le32(lower_32_bits(mapping));
1930 le->length = cpu_to_le16(len);
1931 le->ctrl = ctrl;
1932 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1933
1934
1935 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1936 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1937
1938 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1939 skb_frag_size(frag), DMA_TO_DEVICE);
1940
1941 if (dma_mapping_error(dev: &hw->pdev->dev, dma_addr: mapping))
1942 goto mapping_unwind;
1943
1944 upper = upper_32_bits(mapping);
1945 if (upper != sky2->tx_last_upper) {
1946 le = get_tx_le(sky2, slot: &slot);
1947 le->addr = cpu_to_le32(upper);
1948 sky2->tx_last_upper = upper;
1949 le->opcode = OP_ADDR64 | HW_OWNER;
1950 }
1951
1952 re = sky2->tx_ring + slot;
1953 re->flags = TX_MAP_PAGE;
1954 dma_unmap_addr_set(re, mapaddr, mapping);
1955 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1956
1957 le = get_tx_le(sky2, slot: &slot);
1958 le->addr = cpu_to_le32(lower_32_bits(mapping));
1959 le->length = cpu_to_le16(skb_frag_size(frag));
1960 le->ctrl = ctrl;
1961 le->opcode = OP_BUFFER | HW_OWNER;
1962 }
1963
1964 re->skb = skb;
1965 le->ctrl |= EOP;
1966
1967 sky2->tx_prod = slot;
1968
1969 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1970 netif_stop_queue(dev);
1971
1972 netdev_sent_queue(dev, bytes: skb->len);
1973 sky2_put_idx(hw, q: txqaddr[sky2->port], idx: sky2->tx_prod);
1974
1975 return NETDEV_TX_OK;
1976
1977mapping_unwind:
1978 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1979 re = sky2->tx_ring + i;
1980
1981 sky2_tx_unmap(pdev: hw->pdev, re);
1982 }
1983
1984mapping_error:
1985 if (net_ratelimit())
1986 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1987 dev_kfree_skb_any(skb);
1988 return NETDEV_TX_OK;
1989}
1990
1991/*
1992 * Free ring elements from starting at tx_cons until "done"
1993 *
1994 * NB:
1995 * 1. The hardware will tell us about partial completion of multi-part
1996 * buffers so make sure not to free skb to early.
1997 * 2. This may run in parallel start_xmit because the it only
1998 * looks at the tail of the queue of FIFO (tx_cons), not
1999 * the head (tx_prod)
2000 */
2001static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2002{
2003 struct net_device *dev = sky2->netdev;
2004 u16 idx;
2005 unsigned int bytes_compl = 0, pkts_compl = 0;
2006
2007 BUG_ON(done >= sky2->tx_ring_size);
2008
2009 for (idx = sky2->tx_cons; idx != done;
2010 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2011 struct tx_ring_info *re = sky2->tx_ring + idx;
2012 struct sk_buff *skb = re->skb;
2013
2014 sky2_tx_unmap(pdev: sky2->hw->pdev, re);
2015
2016 if (skb) {
2017 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2018 "tx done %u\n", idx);
2019
2020 pkts_compl++;
2021 bytes_compl += skb->len;
2022
2023 re->skb = NULL;
2024 dev_kfree_skb_any(skb);
2025
2026 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2027 }
2028 }
2029
2030 sky2->tx_cons = idx;
2031 smp_mb();
2032
2033 netdev_completed_queue(dev, pkts: pkts_compl, bytes: bytes_compl);
2034
2035 u64_stats_update_begin(syncp: &sky2->tx_stats.syncp);
2036 sky2->tx_stats.packets += pkts_compl;
2037 sky2->tx_stats.bytes += bytes_compl;
2038 u64_stats_update_end(syncp: &sky2->tx_stats.syncp);
2039}
2040
2041static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2042{
2043 /* Disable Force Sync bit and Enable Alloc bit */
2044 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2045 val: TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2046
2047 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2048 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), val: 0L);
2049 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), val: 0L);
2050
2051 /* Reset the PCI FIFO of the async Tx queue */
2052 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2053 val: BMU_RST_SET | BMU_FIFO_RST);
2054
2055 /* Reset the Tx prefetch units */
2056 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2057 val: PREF_UNIT_RST_SET);
2058
2059 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), val: RB_RST_SET);
2060 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), val: GMF_RST_SET);
2061
2062 sky2_read32(hw, reg: B0_CTST);
2063}
2064
2065static void sky2_hw_down(struct sky2_port *sky2)
2066{
2067 struct sky2_hw *hw = sky2->hw;
2068 unsigned port = sky2->port;
2069 u16 ctrl;
2070
2071 /* Force flow control off */
2072 sky2_write8(hw, SK_REG(port, GMAC_CTRL), val: GMC_PAUSE_OFF);
2073
2074 /* Stop transmitter */
2075 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), val: BMU_STOP);
2076 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2077
2078 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2079 val: RB_RST_SET | RB_DIS_OP_MD);
2080
2081 ctrl = gma_read16(hw, port, reg: GM_GP_CTRL);
2082 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2083 gma_write16(hw, port, r: GM_GP_CTRL, v: ctrl);
2084
2085 sky2_write8(hw, SK_REG(port, GPHY_CTRL), val: GPC_RST_SET);
2086
2087 /* Workaround shared GMAC reset */
2088 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2089 port == 0 && hw->dev[1] && netif_running(dev: hw->dev[1])))
2090 sky2_write8(hw, SK_REG(port, GMAC_CTRL), val: GMC_RST_SET);
2091
2092 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), val: GMF_RST_SET);
2093
2094 /* Force any delayed status interrupt and NAPI */
2095 sky2_write32(hw, reg: STAT_LEV_TIMER_CNT, val: 0);
2096 sky2_write32(hw, reg: STAT_TX_TIMER_CNT, val: 0);
2097 sky2_write32(hw, reg: STAT_ISR_TIMER_CNT, val: 0);
2098 sky2_read8(hw, reg: STAT_ISR_TIMER_CTRL);
2099
2100 sky2_rx_stop(sky2);
2101
2102 spin_lock_bh(lock: &sky2->phy_lock);
2103 sky2_phy_power_down(hw, port);
2104 spin_unlock_bh(lock: &sky2->phy_lock);
2105
2106 sky2_tx_reset(hw, port);
2107
2108 /* Free any pending frames stuck in HW queue */
2109 sky2_tx_complete(sky2, done: sky2->tx_prod);
2110}
2111
2112/* Network shutdown */
2113static int sky2_close(struct net_device *dev)
2114{
2115 struct sky2_port *sky2 = netdev_priv(dev);
2116 struct sky2_hw *hw = sky2->hw;
2117
2118 /* Never really got started! */
2119 if (!sky2->tx_le)
2120 return 0;
2121
2122 netif_info(sky2, ifdown, dev, "disabling interface\n");
2123
2124 if (hw->ports == 1) {
2125 sky2_write32(hw, reg: B0_IMSK, val: 0);
2126 sky2_read32(hw, reg: B0_IMSK);
2127
2128 napi_disable(n: &hw->napi);
2129 free_irq(hw->pdev->irq, hw);
2130 hw->flags &= ~SKY2_HW_IRQ_SETUP;
2131 } else {
2132 u32 imask;
2133
2134 /* Disable port IRQ */
2135 imask = sky2_read32(hw, reg: B0_IMSK);
2136 imask &= ~portirq_msk[sky2->port];
2137 sky2_write32(hw, reg: B0_IMSK, val: imask);
2138 sky2_read32(hw, reg: B0_IMSK);
2139
2140 synchronize_irq(irq: hw->pdev->irq);
2141 napi_synchronize(n: &hw->napi);
2142 }
2143
2144 sky2_hw_down(sky2);
2145
2146 sky2_free_buffers(sky2);
2147
2148 return 0;
2149}
2150
2151static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2152{
2153 if (hw->flags & SKY2_HW_FIBRE_PHY)
2154 return SPEED_1000;
2155
2156 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2157 if (aux & PHY_M_PS_SPEED_100)
2158 return SPEED_100;
2159 else
2160 return SPEED_10;
2161 }
2162
2163 switch (aux & PHY_M_PS_SPEED_MSK) {
2164 case PHY_M_PS_SPEED_1000:
2165 return SPEED_1000;
2166 case PHY_M_PS_SPEED_100:
2167 return SPEED_100;
2168 default:
2169 return SPEED_10;
2170 }
2171}
2172
2173static void sky2_link_up(struct sky2_port *sky2)
2174{
2175 struct sky2_hw *hw = sky2->hw;
2176 unsigned port = sky2->port;
2177 static const char *fc_name[] = {
2178 [FC_NONE] = "none",
2179 [FC_TX] = "tx",
2180 [FC_RX] = "rx",
2181 [FC_BOTH] = "both",
2182 };
2183
2184 sky2_set_ipg(sky2);
2185
2186 sky2_enable_rx_tx(sky2);
2187
2188 gm_phy_write(hw, port, reg: PHY_MARV_INT_MASK, val: PHY_M_DEF_MSK);
2189
2190 netif_carrier_on(dev: sky2->netdev);
2191
2192 mod_timer(timer: &hw->watchdog_timer, expires: jiffies + 1);
2193
2194 /* Turn on link LED */
2195 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2196 val: LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2197
2198 netif_info(sky2, link, sky2->netdev,
2199 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2200 sky2->speed,
2201 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2202 fc_name[sky2->flow_status]);
2203}
2204
2205static void sky2_link_down(struct sky2_port *sky2)
2206{
2207 struct sky2_hw *hw = sky2->hw;
2208 unsigned port = sky2->port;
2209 u16 reg;
2210
2211 gm_phy_write(hw, port, reg: PHY_MARV_INT_MASK, val: 0);
2212
2213 reg = gma_read16(hw, port, reg: GM_GP_CTRL);
2214 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2215 gma_write16(hw, port, r: GM_GP_CTRL, v: reg);
2216
2217 netif_carrier_off(dev: sky2->netdev);
2218
2219 /* Turn off link LED */
2220 sky2_write8(hw, SK_REG(port, LNK_LED_REG), val: LINKLED_OFF);
2221
2222 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2223
2224 sky2_phy_init(hw, port);
2225}
2226
2227static enum flow_control sky2_flow(int rx, int tx)
2228{
2229 if (rx)
2230 return tx ? FC_BOTH : FC_RX;
2231 else
2232 return tx ? FC_TX : FC_NONE;
2233}
2234
2235static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2236{
2237 struct sky2_hw *hw = sky2->hw;
2238 unsigned port = sky2->port;
2239 u16 advert, lpa;
2240
2241 advert = gm_phy_read(hw, port, reg: PHY_MARV_AUNE_ADV);
2242 lpa = gm_phy_read(hw, port, reg: PHY_MARV_AUNE_LP);
2243 if (lpa & PHY_M_AN_RF) {
2244 netdev_err(dev: sky2->netdev, format: "remote fault\n");
2245 return -1;
2246 }
2247
2248 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2249 netdev_err(dev: sky2->netdev, format: "speed/duplex mismatch\n");
2250 return -1;
2251 }
2252
2253 sky2->speed = sky2_phy_speed(hw, aux);
2254 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2255
2256 /* Since the pause result bits seem to in different positions on
2257 * different chips. look at registers.
2258 */
2259 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2260 /* Shift for bits in fiber PHY */
2261 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2262 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2263
2264 if (advert & ADVERTISE_1000XPAUSE)
2265 advert |= ADVERTISE_PAUSE_CAP;
2266 if (advert & ADVERTISE_1000XPSE_ASYM)
2267 advert |= ADVERTISE_PAUSE_ASYM;
2268 if (lpa & LPA_1000XPAUSE)
2269 lpa |= LPA_PAUSE_CAP;
2270 if (lpa & LPA_1000XPAUSE_ASYM)
2271 lpa |= LPA_PAUSE_ASYM;
2272 }
2273
2274 sky2->flow_status = FC_NONE;
2275 if (advert & ADVERTISE_PAUSE_CAP) {
2276 if (lpa & LPA_PAUSE_CAP)
2277 sky2->flow_status = FC_BOTH;
2278 else if (advert & ADVERTISE_PAUSE_ASYM)
2279 sky2->flow_status = FC_RX;
2280 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2281 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2282 sky2->flow_status = FC_TX;
2283 }
2284
2285 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2286 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2287 sky2->flow_status = FC_NONE;
2288
2289 if (sky2->flow_status & FC_TX)
2290 sky2_write8(hw, SK_REG(port, GMAC_CTRL), val: GMC_PAUSE_ON);
2291 else
2292 sky2_write8(hw, SK_REG(port, GMAC_CTRL), val: GMC_PAUSE_OFF);
2293
2294 return 0;
2295}
2296
2297/* Interrupt from PHY */
2298static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2299{
2300 struct net_device *dev = hw->dev[port];
2301 struct sky2_port *sky2 = netdev_priv(dev);
2302 u16 istatus, phystat;
2303
2304 if (!netif_running(dev))
2305 return;
2306
2307 spin_lock(lock: &sky2->phy_lock);
2308 istatus = gm_phy_read(hw, port, reg: PHY_MARV_INT_STAT);
2309 phystat = gm_phy_read(hw, port, reg: PHY_MARV_PHY_STAT);
2310
2311 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2312 istatus, phystat);
2313
2314 if (istatus & PHY_M_IS_AN_COMPL) {
2315 if (sky2_autoneg_done(sky2, aux: phystat) == 0 &&
2316 !netif_carrier_ok(dev))
2317 sky2_link_up(sky2);
2318 goto out;
2319 }
2320
2321 if (istatus & PHY_M_IS_LSP_CHANGE)
2322 sky2->speed = sky2_phy_speed(hw, aux: phystat);
2323
2324 if (istatus & PHY_M_IS_DUP_CHANGE)
2325 sky2->duplex =
2326 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2327
2328 if (istatus & PHY_M_IS_LST_CHANGE) {
2329 if (phystat & PHY_M_PS_LINK_UP)
2330 sky2_link_up(sky2);
2331 else
2332 sky2_link_down(sky2);
2333 }
2334out:
2335 spin_unlock(lock: &sky2->phy_lock);
2336}
2337
2338/* Special quick link interrupt (Yukon-2 Optima only) */
2339static void sky2_qlink_intr(struct sky2_hw *hw)
2340{
2341 struct sky2_port *sky2 = netdev_priv(dev: hw->dev[0]);
2342 u32 imask;
2343 u16 phy;
2344
2345 /* disable irq */
2346 imask = sky2_read32(hw, reg: B0_IMSK);
2347 imask &= ~Y2_IS_PHY_QLNK;
2348 sky2_write32(hw, reg: B0_IMSK, val: imask);
2349
2350 /* reset PHY Link Detect */
2351 phy = sky2_pci_read16(hw, reg: PSM_CONFIG_REG4);
2352 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_ON);
2353 sky2_pci_write16(hw, reg: PSM_CONFIG_REG4, val: phy | 1);
2354 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_OFF);
2355
2356 sky2_link_up(sky2);
2357}
2358
2359/* Transmit timeout is only called if we are running, carrier is up
2360 * and tx queue is full (stopped).
2361 */
2362static void sky2_tx_timeout(struct net_device *dev, unsigned int txqueue)
2363{
2364 struct sky2_port *sky2 = netdev_priv(dev);
2365 struct sky2_hw *hw = sky2->hw;
2366
2367 netif_err(sky2, timer, dev, "tx timeout\n");
2368
2369 netdev_printk(KERN_DEBUG, dev, format: "transmit ring %u .. %u report=%u done=%u\n",
2370 sky2->tx_cons, sky2->tx_prod,
2371 sky2_read16(hw, reg: sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2372 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2373
2374 /* can't restart safely under softirq */
2375 schedule_work(work: &hw->restart_work);
2376}
2377
2378static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2379{
2380 struct sky2_port *sky2 = netdev_priv(dev);
2381 struct sky2_hw *hw = sky2->hw;
2382 unsigned port = sky2->port;
2383 int err;
2384 u16 ctl, mode;
2385 u32 imask;
2386
2387 if (!netif_running(dev)) {
2388 WRITE_ONCE(dev->mtu, new_mtu);
2389 netdev_update_features(dev);
2390 return 0;
2391 }
2392
2393 imask = sky2_read32(hw, reg: B0_IMSK);
2394 sky2_write32(hw, reg: B0_IMSK, val: 0);
2395 sky2_read32(hw, reg: B0_IMSK);
2396
2397 netif_trans_update(dev); /* prevent tx timeout */
2398 napi_disable(n: &hw->napi);
2399 netif_tx_disable(dev);
2400
2401 synchronize_irq(irq: hw->pdev->irq);
2402
2403 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2404 sky2_set_tx_stfwd(hw, port);
2405
2406 ctl = gma_read16(hw, port, reg: GM_GP_CTRL);
2407 gma_write16(hw, port, r: GM_GP_CTRL, v: ctl & ~GM_GPCR_RX_ENA);
2408 sky2_rx_stop(sky2);
2409 sky2_rx_clean(sky2);
2410
2411 WRITE_ONCE(dev->mtu, new_mtu);
2412 netdev_update_features(dev);
2413
2414 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2415 if (sky2->speed > SPEED_100)
2416 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2417 else
2418 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2419
2420 if (dev->mtu > ETH_DATA_LEN)
2421 mode |= GM_SMOD_JUMBO_ENA;
2422
2423 gma_write16(hw, port, r: GM_SERIAL_MODE, v: mode);
2424
2425 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), val: RB_ENA_OP_MD);
2426
2427 err = sky2_alloc_rx_skbs(sky2);
2428 if (!err)
2429 sky2_rx_start(sky2);
2430 else
2431 sky2_rx_clean(sky2);
2432 sky2_write32(hw, reg: B0_IMSK, val: imask);
2433
2434 sky2_read32(hw, reg: B0_Y2_SP_LISR);
2435 napi_enable(n: &hw->napi);
2436
2437 if (err)
2438 dev_close(dev);
2439 else {
2440 gma_write16(hw, port, r: GM_GP_CTRL, v: ctl);
2441
2442 netif_wake_queue(dev);
2443 }
2444
2445 return err;
2446}
2447
2448static inline bool needs_copy(const struct rx_ring_info *re,
2449 unsigned length)
2450{
2451#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2452 /* Some architectures need the IP header to be aligned */
2453 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2454 return true;
2455#endif
2456 return length < copybreak;
2457}
2458
2459/* For small just reuse existing skb for next receive */
2460static struct sk_buff *receive_copy(struct sky2_port *sky2,
2461 const struct rx_ring_info *re,
2462 unsigned length)
2463{
2464 struct sk_buff *skb;
2465
2466 skb = netdev_alloc_skb_ip_align(dev: sky2->netdev, length);
2467 if (likely(skb)) {
2468 dma_sync_single_for_cpu(dev: &sky2->hw->pdev->dev, addr: re->data_addr,
2469 size: length, dir: DMA_FROM_DEVICE);
2470 skb_copy_from_linear_data(skb: re->skb, to: skb->data, len: length);
2471 skb->ip_summed = re->skb->ip_summed;
2472 skb->csum = re->skb->csum;
2473 skb_copy_hash(to: skb, from: re->skb);
2474 __vlan_hwaccel_copy_tag(dst: skb, src: re->skb);
2475
2476 dma_sync_single_for_device(dev: &sky2->hw->pdev->dev,
2477 addr: re->data_addr, size: length,
2478 dir: DMA_FROM_DEVICE);
2479 __vlan_hwaccel_clear_tag(skb: re->skb);
2480 skb_clear_hash(skb: re->skb);
2481 re->skb->ip_summed = CHECKSUM_NONE;
2482 skb_put(skb, len: length);
2483 }
2484 return skb;
2485}
2486
2487/* Adjust length of skb with fragments to match received data */
2488static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2489 unsigned int length)
2490{
2491 int i, num_frags;
2492 unsigned int size;
2493
2494 /* put header into skb */
2495 size = min(length, hdr_space);
2496 skb->tail += size;
2497 skb->len += size;
2498 length -= size;
2499
2500 num_frags = skb_shinfo(skb)->nr_frags;
2501 for (i = 0; i < num_frags; i++) {
2502 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2503
2504 if (length == 0) {
2505 /* don't need this page */
2506 __skb_frag_unref(frag, recycle: false);
2507 --skb_shinfo(skb)->nr_frags;
2508 } else {
2509 size = min(length, (unsigned) PAGE_SIZE);
2510
2511 skb_frag_size_set(frag, size);
2512 skb->data_len += size;
2513 skb->truesize += PAGE_SIZE;
2514 skb->len += size;
2515 length -= size;
2516 }
2517 }
2518}
2519
2520/* Normal packet - take skb from ring element and put in a new one */
2521static struct sk_buff *receive_new(struct sky2_port *sky2,
2522 struct rx_ring_info *re,
2523 unsigned int length)
2524{
2525 struct sk_buff *skb;
2526 struct rx_ring_info nre;
2527 unsigned hdr_space = sky2->rx_data_size;
2528
2529 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2530 if (unlikely(!nre.skb))
2531 goto nobuf;
2532
2533 if (sky2_rx_map_skb(pdev: sky2->hw->pdev, re: &nre, size: hdr_space))
2534 goto nomap;
2535
2536 skb = re->skb;
2537 sky2_rx_unmap_skb(pdev: sky2->hw->pdev, re);
2538 prefetch(skb->data);
2539 *re = nre;
2540
2541 if (skb_shinfo(skb)->nr_frags)
2542 skb_put_frags(skb, hdr_space, length);
2543 else
2544 skb_put(skb, len: length);
2545 return skb;
2546
2547nomap:
2548 dev_kfree_skb(nre.skb);
2549nobuf:
2550 return NULL;
2551}
2552
2553/*
2554 * Receive one packet.
2555 * For larger packets, get new buffer.
2556 */
2557static struct sk_buff *sky2_receive(struct net_device *dev,
2558 u16 length, u32 status)
2559{
2560 struct sky2_port *sky2 = netdev_priv(dev);
2561 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2562 struct sk_buff *skb = NULL;
2563 u16 count = (status & GMR_FS_LEN) >> 16;
2564
2565 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2566 "rx slot %u status 0x%x len %d\n",
2567 sky2->rx_next, status, length);
2568
2569 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2570 prefetch(sky2->rx_ring + sky2->rx_next);
2571
2572 if (skb_vlan_tag_present(re->skb))
2573 count -= VLAN_HLEN; /* Account for vlan tag */
2574
2575 /* This chip has hardware problems that generates bogus status.
2576 * So do only marginal checking and expect higher level protocols
2577 * to handle crap frames.
2578 */
2579 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2580 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2581 length != count)
2582 goto okay;
2583
2584 if (status & GMR_FS_ANY_ERR)
2585 goto error;
2586
2587 if (!(status & GMR_FS_RX_OK))
2588 goto resubmit;
2589
2590 /* if length reported by DMA does not match PHY, packet was truncated */
2591 if (length != count)
2592 goto error;
2593
2594okay:
2595 if (needs_copy(re, length))
2596 skb = receive_copy(sky2, re, length);
2597 else
2598 skb = receive_new(sky2, re, length);
2599
2600 dev->stats.rx_dropped += (skb == NULL);
2601
2602resubmit:
2603 sky2_rx_submit(sky2, re);
2604
2605 return skb;
2606
2607error:
2608 ++dev->stats.rx_errors;
2609
2610 if (net_ratelimit())
2611 netif_info(sky2, rx_err, dev,
2612 "rx error, status 0x%x length %d\n", status, length);
2613
2614 goto resubmit;
2615}
2616
2617/* Transmit complete */
2618static inline void sky2_tx_done(struct net_device *dev, u16 last)
2619{
2620 struct sky2_port *sky2 = netdev_priv(dev);
2621
2622 if (netif_running(dev)) {
2623 sky2_tx_complete(sky2, done: last);
2624
2625 /* Wake unless it's detached, and called e.g. from sky2_close() */
2626 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2627 netif_wake_queue(dev);
2628 }
2629}
2630
2631static inline void sky2_skb_rx(const struct sky2_port *sky2,
2632 struct sk_buff *skb)
2633{
2634 if (skb->ip_summed == CHECKSUM_NONE)
2635 netif_receive_skb(skb);
2636 else
2637 napi_gro_receive(napi: &sky2->hw->napi, skb);
2638}
2639
2640static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2641 unsigned packets, unsigned bytes)
2642{
2643 struct net_device *dev = hw->dev[port];
2644 struct sky2_port *sky2 = netdev_priv(dev);
2645
2646 if (packets == 0)
2647 return;
2648
2649 u64_stats_update_begin(syncp: &sky2->rx_stats.syncp);
2650 sky2->rx_stats.packets += packets;
2651 sky2->rx_stats.bytes += bytes;
2652 u64_stats_update_end(syncp: &sky2->rx_stats.syncp);
2653
2654 sky2->last_rx = jiffies;
2655 sky2_rx_update(sky2: netdev_priv(dev), rxq: rxqaddr[port]);
2656}
2657
2658static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2659{
2660 /* If this happens then driver assuming wrong format for chip type */
2661 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2662
2663 /* Both checksum counters are programmed to start at
2664 * the same offset, so unless there is a problem they
2665 * should match. This failure is an early indication that
2666 * hardware receive checksumming won't work.
2667 */
2668 if (likely((u16)(status >> 16) == (u16)status)) {
2669 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2670 skb->ip_summed = CHECKSUM_COMPLETE;
2671 skb->csum = le16_to_cpu(status);
2672 } else {
2673 dev_notice(&sky2->hw->pdev->dev,
2674 "%s: receive checksum problem (status = %#x)\n",
2675 sky2->netdev->name, status);
2676
2677 /* Disable checksum offload
2678 * It will be reenabled on next ndo_set_features, but if it's
2679 * really broken, will get disabled again
2680 */
2681 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2682 sky2_write32(hw: sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2683 val: BMU_DIS_RX_CHKSUM);
2684 }
2685}
2686
2687static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2688{
2689 struct sk_buff *skb;
2690
2691 skb = sky2->rx_ring[sky2->rx_next].skb;
2692 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length));
2693}
2694
2695static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2696{
2697 struct sk_buff *skb;
2698
2699 skb = sky2->rx_ring[sky2->rx_next].skb;
2700 skb_set_hash(skb, le32_to_cpu(status), type: PKT_HASH_TYPE_L3);
2701}
2702
2703/* Process status response ring */
2704static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2705{
2706 int work_done = 0;
2707 unsigned int total_bytes[2] = { 0 };
2708 unsigned int total_packets[2] = { 0 };
2709
2710 if (to_do <= 0)
2711 return work_done;
2712
2713 rmb();
2714 do {
2715 struct sky2_port *sky2;
2716 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2717 unsigned port;
2718 struct net_device *dev;
2719 struct sk_buff *skb;
2720 u32 status;
2721 u16 length;
2722 u8 opcode = le->opcode;
2723
2724 if (!(opcode & HW_OWNER))
2725 break;
2726
2727 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2728
2729 port = le->css & CSS_LINK_BIT;
2730 dev = hw->dev[port];
2731 sky2 = netdev_priv(dev);
2732 length = le16_to_cpu(le->length);
2733 status = le32_to_cpu(le->status);
2734
2735 le->opcode = 0;
2736 switch (opcode & ~HW_OWNER) {
2737 case OP_RXSTAT:
2738 total_packets[port]++;
2739 total_bytes[port] += length;
2740
2741 skb = sky2_receive(dev, length, status);
2742 if (!skb)
2743 break;
2744
2745 /* This chip reports checksum status differently */
2746 if (hw->flags & SKY2_HW_NEW_LE) {
2747 if ((dev->features & NETIF_F_RXCSUM) &&
2748 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2749 (le->css & CSS_TCPUDPCSOK))
2750 skb->ip_summed = CHECKSUM_UNNECESSARY;
2751 else
2752 skb->ip_summed = CHECKSUM_NONE;
2753 }
2754
2755 skb->protocol = eth_type_trans(skb, dev);
2756 sky2_skb_rx(sky2, skb);
2757
2758 /* Stop after net poll weight */
2759 if (++work_done >= to_do)
2760 goto exit_loop;
2761 break;
2762
2763 case OP_RXVLAN:
2764 sky2_rx_tag(sky2, length);
2765 break;
2766
2767 case OP_RXCHKSVLAN:
2768 sky2_rx_tag(sky2, length);
2769 fallthrough;
2770 case OP_RXCHKS:
2771 if (likely(dev->features & NETIF_F_RXCSUM))
2772 sky2_rx_checksum(sky2, status);
2773 break;
2774
2775 case OP_RSS_HASH:
2776 sky2_rx_hash(sky2, status);
2777 break;
2778
2779 case OP_TXINDEXLE:
2780 /* TX index reports status for both ports */
2781 sky2_tx_done(dev: hw->dev[0], last: status & 0xfff);
2782 if (hw->dev[1])
2783 sky2_tx_done(dev: hw->dev[1],
2784 last: ((status >> 24) & 0xff)
2785 | (u16)(length & 0xf) << 8);
2786 break;
2787
2788 default:
2789 if (net_ratelimit())
2790 pr_warn("unknown status opcode 0x%x\n", opcode);
2791 }
2792 } while (hw->st_idx != idx);
2793
2794 /* Fully processed status ring so clear irq */
2795 sky2_write32(hw, reg: STAT_CTRL, val: SC_STAT_CLR_IRQ);
2796
2797exit_loop:
2798 sky2_rx_done(hw, port: 0, packets: total_packets[0], bytes: total_bytes[0]);
2799 sky2_rx_done(hw, port: 1, packets: total_packets[1], bytes: total_bytes[1]);
2800
2801 return work_done;
2802}
2803
2804static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2805{
2806 struct net_device *dev = hw->dev[port];
2807
2808 if (net_ratelimit())
2809 netdev_info(dev, format: "hw error interrupt status 0x%x\n", status);
2810
2811 if (status & Y2_IS_PAR_RD1) {
2812 if (net_ratelimit())
2813 netdev_err(dev, format: "ram data read parity error\n");
2814 /* Clear IRQ */
2815 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), val: RI_CLR_RD_PERR);
2816 }
2817
2818 if (status & Y2_IS_PAR_WR1) {
2819 if (net_ratelimit())
2820 netdev_err(dev, format: "ram data write parity error\n");
2821
2822 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), val: RI_CLR_WR_PERR);
2823 }
2824
2825 if (status & Y2_IS_PAR_MAC1) {
2826 if (net_ratelimit())
2827 netdev_err(dev, format: "MAC parity error\n");
2828 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), val: GMF_CLI_TX_PE);
2829 }
2830
2831 if (status & Y2_IS_PAR_RX1) {
2832 if (net_ratelimit())
2833 netdev_err(dev, format: "RX parity error\n");
2834 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), val: BMU_CLR_IRQ_PAR);
2835 }
2836
2837 if (status & Y2_IS_TCP_TXA1) {
2838 if (net_ratelimit())
2839 netdev_err(dev, format: "TCP segmentation error\n");
2840 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), val: BMU_CLR_IRQ_TCP);
2841 }
2842}
2843
2844static void sky2_hw_intr(struct sky2_hw *hw)
2845{
2846 struct pci_dev *pdev = hw->pdev;
2847 u32 status = sky2_read32(hw, reg: B0_HWE_ISRC);
2848 u32 hwmsk = sky2_read32(hw, reg: B0_HWE_IMSK);
2849
2850 status &= hwmsk;
2851
2852 if (status & Y2_IS_TIST_OV)
2853 sky2_write8(hw, reg: GMAC_TI_ST_CTRL, val: GMT_ST_CLR_IRQ);
2854
2855 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2856 u16 pci_err;
2857
2858 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_ON);
2859 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2860 if (net_ratelimit())
2861 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2862 pci_err);
2863
2864 sky2_pci_write16(hw, PCI_STATUS,
2865 val: pci_err | PCI_STATUS_ERROR_BITS);
2866 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_OFF);
2867 }
2868
2869 if (status & Y2_IS_PCI_EXP) {
2870 /* PCI-Express uncorrectable Error occurred */
2871 u32 err;
2872
2873 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_ON);
2874 err = sky2_read32(hw, reg: Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2875 sky2_write32(hw, reg: Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2876 val: 0xfffffffful);
2877 if (net_ratelimit())
2878 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2879
2880 sky2_read32(hw, reg: Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2881 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_OFF);
2882 }
2883
2884 if (status & Y2_HWE_L1_MASK)
2885 sky2_hw_error(hw, port: 0, status);
2886 status >>= 8;
2887 if (status & Y2_HWE_L1_MASK)
2888 sky2_hw_error(hw, port: 1, status);
2889}
2890
2891static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2892{
2893 struct net_device *dev = hw->dev[port];
2894 struct sky2_port *sky2 = netdev_priv(dev);
2895 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2896
2897 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2898
2899 if (status & GM_IS_RX_CO_OV)
2900 gma_read16(hw, port, reg: GM_RX_IRQ_SRC);
2901
2902 if (status & GM_IS_TX_CO_OV)
2903 gma_read16(hw, port, reg: GM_TX_IRQ_SRC);
2904
2905 if (status & GM_IS_RX_FF_OR) {
2906 ++dev->stats.rx_fifo_errors;
2907 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), val: GMF_CLI_RX_FO);
2908 }
2909
2910 if (status & GM_IS_TX_FF_UR) {
2911 ++dev->stats.tx_fifo_errors;
2912 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), val: GMF_CLI_TX_FU);
2913 }
2914}
2915
2916/* This should never happen it is a bug. */
2917static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2918{
2919 struct net_device *dev = hw->dev[port];
2920 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2921
2922 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2923 dev->name, (unsigned) q, (unsigned) idx,
2924 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2925
2926 sky2_write32(hw, Q_ADDR(q, Q_CSR), val: BMU_CLR_IRQ_CHK);
2927}
2928
2929static int sky2_rx_hung(struct net_device *dev)
2930{
2931 struct sky2_port *sky2 = netdev_priv(dev);
2932 struct sky2_hw *hw = sky2->hw;
2933 unsigned port = sky2->port;
2934 unsigned rxq = rxqaddr[port];
2935 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2936 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2937 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2938 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2939
2940 /* If idle and MAC or PCI is stuck */
2941 if (sky2->check.last == sky2->last_rx &&
2942 ((mac_rp == sky2->check.mac_rp &&
2943 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2944 /* Check if the PCI RX hang */
2945 (fifo_rp == sky2->check.fifo_rp &&
2946 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2947 netdev_printk(KERN_DEBUG, dev,
2948 format: "hung mac %d:%d fifo %d (%d:%d)\n",
2949 mac_lev, mac_rp, fifo_lev,
2950 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2951 return 1;
2952 } else {
2953 sky2->check.last = sky2->last_rx;
2954 sky2->check.mac_rp = mac_rp;
2955 sky2->check.mac_lev = mac_lev;
2956 sky2->check.fifo_rp = fifo_rp;
2957 sky2->check.fifo_lev = fifo_lev;
2958 return 0;
2959 }
2960}
2961
2962static void sky2_watchdog(struct timer_list *t)
2963{
2964 struct sky2_hw *hw = timer_container_of(hw, t, watchdog_timer);
2965
2966 /* Check for lost IRQ once a second */
2967 if (sky2_read32(hw, reg: B0_ISRC)) {
2968 napi_schedule(n: &hw->napi);
2969 } else {
2970 int i, active = 0;
2971
2972 for (i = 0; i < hw->ports; i++) {
2973 struct net_device *dev = hw->dev[i];
2974 if (!netif_running(dev))
2975 continue;
2976 ++active;
2977
2978 /* For chips with Rx FIFO, check if stuck */
2979 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2980 sky2_rx_hung(dev)) {
2981 netdev_info(dev, format: "receiver hang detected\n");
2982 schedule_work(work: &hw->restart_work);
2983 return;
2984 }
2985 }
2986
2987 if (active == 0)
2988 return;
2989 }
2990
2991 mod_timer(timer: &hw->watchdog_timer, expires: round_jiffies(j: jiffies + HZ));
2992}
2993
2994/* Hardware/software error handling */
2995static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2996{
2997 if (net_ratelimit())
2998 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2999
3000 if (status & Y2_IS_HW_ERR)
3001 sky2_hw_intr(hw);
3002
3003 if (status & Y2_IS_IRQ_MAC1)
3004 sky2_mac_intr(hw, port: 0);
3005
3006 if (status & Y2_IS_IRQ_MAC2)
3007 sky2_mac_intr(hw, port: 1);
3008
3009 if (status & Y2_IS_CHK_RX1)
3010 sky2_le_error(hw, port: 0, q: Q_R1);
3011
3012 if (status & Y2_IS_CHK_RX2)
3013 sky2_le_error(hw, port: 1, q: Q_R2);
3014
3015 if (status & Y2_IS_CHK_TXA1)
3016 sky2_le_error(hw, port: 0, q: Q_XA1);
3017
3018 if (status & Y2_IS_CHK_TXA2)
3019 sky2_le_error(hw, port: 1, q: Q_XA2);
3020}
3021
3022static int sky2_poll(struct napi_struct *napi, int work_limit)
3023{
3024 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3025 u32 status = sky2_read32(hw, reg: B0_Y2_SP_EISR);
3026 int work_done = 0;
3027 u16 idx;
3028
3029 if (unlikely(status & Y2_IS_ERROR))
3030 sky2_err_intr(hw, status);
3031
3032 if (status & Y2_IS_IRQ_PHY1)
3033 sky2_phy_intr(hw, port: 0);
3034
3035 if (status & Y2_IS_IRQ_PHY2)
3036 sky2_phy_intr(hw, port: 1);
3037
3038 if (status & Y2_IS_PHY_QLNK)
3039 sky2_qlink_intr(hw);
3040
3041 while ((idx = sky2_read16(hw, reg: STAT_PUT_IDX)) != hw->st_idx) {
3042 work_done += sky2_status_intr(hw, to_do: work_limit - work_done, idx);
3043
3044 if (work_done >= work_limit)
3045 goto done;
3046 }
3047
3048 napi_complete_done(n: napi, work_done);
3049 sky2_read32(hw, reg: B0_Y2_SP_LISR);
3050done:
3051
3052 return work_done;
3053}
3054
3055static irqreturn_t sky2_intr(int irq, void *dev_id)
3056{
3057 struct sky2_hw *hw = dev_id;
3058 u32 status;
3059
3060 /* Reading this mask interrupts as side effect */
3061 status = sky2_read32(hw, reg: B0_Y2_SP_ISRC2);
3062 if (status == 0 || status == ~0) {
3063 sky2_write32(hw, reg: B0_Y2_SP_ICR, val: 2);
3064 return IRQ_NONE;
3065 }
3066
3067 prefetch(&hw->st_le[hw->st_idx]);
3068
3069 napi_schedule(n: &hw->napi);
3070
3071 return IRQ_HANDLED;
3072}
3073
3074#ifdef CONFIG_NET_POLL_CONTROLLER
3075static void sky2_netpoll(struct net_device *dev)
3076{
3077 struct sky2_port *sky2 = netdev_priv(dev);
3078
3079 napi_schedule(n: &sky2->hw->napi);
3080}
3081#endif
3082
3083/* Chip internal frequency for clock calculations */
3084static u32 sky2_mhz(const struct sky2_hw *hw)
3085{
3086 switch (hw->chip_id) {
3087 case CHIP_ID_YUKON_EC:
3088 case CHIP_ID_YUKON_EC_U:
3089 case CHIP_ID_YUKON_EX:
3090 case CHIP_ID_YUKON_SUPR:
3091 case CHIP_ID_YUKON_UL_2:
3092 case CHIP_ID_YUKON_OPT:
3093 case CHIP_ID_YUKON_PRM:
3094 case CHIP_ID_YUKON_OP_2:
3095 return 125;
3096
3097 case CHIP_ID_YUKON_FE:
3098 return 100;
3099
3100 case CHIP_ID_YUKON_FE_P:
3101 return 50;
3102
3103 case CHIP_ID_YUKON_XL:
3104 return 156;
3105
3106 default:
3107 BUG();
3108 }
3109}
3110
3111static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3112{
3113 return sky2_mhz(hw) * us;
3114}
3115
3116static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3117{
3118 return clk / sky2_mhz(hw);
3119}
3120
3121
3122static int sky2_init(struct sky2_hw *hw)
3123{
3124 u8 t8;
3125
3126 /* Enable all clocks and check for bad PCI access */
3127 sky2_pci_write32(hw, reg: PCI_DEV_REG3, val: 0);
3128
3129 sky2_write8(hw, reg: B0_CTST, val: CS_RST_CLR);
3130
3131 hw->chip_id = sky2_read8(hw, reg: B2_CHIP_ID);
3132 hw->chip_rev = (sky2_read8(hw, reg: B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3133
3134 switch (hw->chip_id) {
3135 case CHIP_ID_YUKON_XL:
3136 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3137 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3138 hw->flags |= SKY2_HW_RSS_BROKEN;
3139 break;
3140
3141 case CHIP_ID_YUKON_EC_U:
3142 hw->flags = SKY2_HW_GIGABIT
3143 | SKY2_HW_NEWER_PHY
3144 | SKY2_HW_ADV_POWER_CTL;
3145 break;
3146
3147 case CHIP_ID_YUKON_EX:
3148 hw->flags = SKY2_HW_GIGABIT
3149 | SKY2_HW_NEWER_PHY
3150 | SKY2_HW_NEW_LE
3151 | SKY2_HW_ADV_POWER_CTL
3152 | SKY2_HW_RSS_CHKSUM;
3153
3154 /* New transmit checksum */
3155 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3156 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3157 break;
3158
3159 case CHIP_ID_YUKON_EC:
3160 /* This rev is really old, and requires untested workarounds */
3161 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3162 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3163 return -EOPNOTSUPP;
3164 }
3165 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3166 break;
3167
3168 case CHIP_ID_YUKON_FE:
3169 hw->flags = SKY2_HW_RSS_BROKEN;
3170 break;
3171
3172 case CHIP_ID_YUKON_FE_P:
3173 hw->flags = SKY2_HW_NEWER_PHY
3174 | SKY2_HW_NEW_LE
3175 | SKY2_HW_AUTO_TX_SUM
3176 | SKY2_HW_ADV_POWER_CTL;
3177
3178 /* The workaround for status conflicts VLAN tag detection. */
3179 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3180 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3181 break;
3182
3183 case CHIP_ID_YUKON_SUPR:
3184 hw->flags = SKY2_HW_GIGABIT
3185 | SKY2_HW_NEWER_PHY
3186 | SKY2_HW_NEW_LE
3187 | SKY2_HW_AUTO_TX_SUM
3188 | SKY2_HW_ADV_POWER_CTL;
3189
3190 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3191 hw->flags |= SKY2_HW_RSS_CHKSUM;
3192 break;
3193
3194 case CHIP_ID_YUKON_UL_2:
3195 hw->flags = SKY2_HW_GIGABIT
3196 | SKY2_HW_ADV_POWER_CTL;
3197 break;
3198
3199 case CHIP_ID_YUKON_OPT:
3200 case CHIP_ID_YUKON_PRM:
3201 case CHIP_ID_YUKON_OP_2:
3202 hw->flags = SKY2_HW_GIGABIT
3203 | SKY2_HW_NEW_LE
3204 | SKY2_HW_ADV_POWER_CTL;
3205 break;
3206
3207 default:
3208 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3209 hw->chip_id);
3210 return -EOPNOTSUPP;
3211 }
3212
3213 hw->pmd_type = sky2_read8(hw, reg: B2_PMD_TYP);
3214 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3215 hw->flags |= SKY2_HW_FIBRE_PHY;
3216
3217 hw->ports = 1;
3218 t8 = sky2_read8(hw, reg: B2_Y2_HW_RES);
3219 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3220 if (!(sky2_read8(hw, reg: B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3221 ++hw->ports;
3222 }
3223
3224 if (sky2_read8(hw, reg: B2_E_0))
3225 hw->flags |= SKY2_HW_RAM_BUFFER;
3226
3227 return 0;
3228}
3229
3230static void sky2_reset(struct sky2_hw *hw)
3231{
3232 struct pci_dev *pdev = hw->pdev;
3233 u16 status;
3234 int i;
3235 u32 hwe_mask = Y2_HWE_ALL_MASK;
3236
3237 /* disable ASF */
3238 if (hw->chip_id == CHIP_ID_YUKON_EX
3239 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3240 sky2_write32(hw, reg: CPU_WDOG, val: 0);
3241 status = sky2_read16(hw, reg: HCU_CCSR);
3242 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3243 HCU_CCSR_UC_STATE_MSK);
3244 /*
3245 * CPU clock divider shouldn't be used because
3246 * - ASF firmware may malfunction
3247 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3248 */
3249 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3250 sky2_write16(hw, reg: HCU_CCSR, val: status);
3251 sky2_write32(hw, reg: CPU_WDOG, val: 0);
3252 } else
3253 sky2_write8(hw, reg: B28_Y2_ASF_STAT_CMD, val: Y2_ASF_RESET);
3254 sky2_write16(hw, reg: B0_CTST, val: Y2_ASF_DISABLE);
3255
3256 /* do a SW reset */
3257 sky2_write8(hw, reg: B0_CTST, val: CS_RST_SET);
3258 sky2_write8(hw, reg: B0_CTST, val: CS_RST_CLR);
3259
3260 /* allow writes to PCI config */
3261 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_ON);
3262
3263 /* clear PCI errors, if any */
3264 status = sky2_pci_read16(hw, PCI_STATUS);
3265 status |= PCI_STATUS_ERROR_BITS;
3266 sky2_pci_write16(hw, PCI_STATUS, val: status);
3267
3268 sky2_write8(hw, reg: B0_CTST, val: CS_MRST_CLR);
3269
3270 if (pci_is_pcie(dev: pdev)) {
3271 sky2_write32(hw, reg: Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3272 val: 0xfffffffful);
3273
3274 /* If error bit is stuck on ignore it */
3275 if (sky2_read32(hw, reg: B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3276 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3277 else
3278 hwe_mask |= Y2_IS_PCI_EXP;
3279 }
3280
3281 sky2_power_on(hw);
3282 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_OFF);
3283
3284 for (i = 0; i < hw->ports; i++) {
3285 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), val: GMLC_RST_SET);
3286 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), val: GMLC_RST_CLR);
3287
3288 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3289 hw->chip_id == CHIP_ID_YUKON_SUPR)
3290 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3291 val: GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3292 | GMC_BYP_RETR_ON);
3293
3294 }
3295
3296 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3297 /* enable MACSec clock gating */
3298 sky2_pci_write32(hw, reg: PCI_DEV_REG3, val: P_CLK_MACSEC_DIS);
3299 }
3300
3301 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3302 hw->chip_id == CHIP_ID_YUKON_PRM ||
3303 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3304 u16 reg;
3305
3306 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3307 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3308 sky2_write32(hw, reg: Y2_PEX_PHY_DATA, val: (0x80UL << 16) | (1 << 7));
3309
3310 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3311 reg = 10;
3312
3313 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3314 sky2_write32(hw, reg: Y2_PEX_PHY_DATA, val: PEX_DB_ACCESS | (0x08UL << 16));
3315 } else {
3316 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3317 reg = 3;
3318 }
3319
3320 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3321 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3322
3323 /* reset PHY Link Detect */
3324 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_ON);
3325 sky2_pci_write16(hw, reg: PSM_CONFIG_REG4, val: reg);
3326
3327 /* check if PSMv2 was running before */
3328 reg = sky2_pci_read16(hw, reg: PSM_CONFIG_REG3);
3329 if (reg & PCI_EXP_LNKCTL_ASPMC)
3330 /* restore the PCIe Link Control register */
3331 sky2_pci_write16(hw, reg: pdev->pcie_cap + PCI_EXP_LNKCTL,
3332 val: reg);
3333
3334 if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3335 hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3336 /* change PHY Interrupt polarity to low active */
3337 reg = sky2_read16(hw, reg: GPHY_CTRL);
3338 sky2_write16(hw, reg: GPHY_CTRL, val: reg | GPC_INTPOL);
3339
3340 /* adapt HW for low active PHY Interrupt */
3341 reg = sky2_read16(hw, reg: Y2_CFG_SPC + PCI_LDO_CTRL);
3342 sky2_write16(hw, reg: Y2_CFG_SPC + PCI_LDO_CTRL, val: reg | PHY_M_UNDOC1);
3343 }
3344
3345 sky2_write8(hw, reg: B2_TST_CTRL1, val: TST_CFG_WRITE_OFF);
3346
3347 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3348 sky2_write32(hw, reg: Y2_PEX_PHY_DATA, val: PEX_DB_ACCESS | (0x08UL << 16));
3349 }
3350
3351 /* Clear I2C IRQ noise */
3352 sky2_write32(hw, reg: B2_I2C_IRQ, val: 1);
3353
3354 /* turn off hardware timer (unused) */
3355 sky2_write8(hw, reg: B2_TI_CTRL, val: TIM_STOP);
3356 sky2_write8(hw, reg: B2_TI_CTRL, val: TIM_CLR_IRQ);
3357
3358 /* Turn off descriptor polling */
3359 sky2_write32(hw, reg: B28_DPT_CTRL, val: DPT_STOP);
3360
3361 /* Turn off receive timestamp */
3362 sky2_write8(hw, reg: GMAC_TI_ST_CTRL, val: GMT_ST_STOP);
3363 sky2_write8(hw, reg: GMAC_TI_ST_CTRL, val: GMT_ST_CLR_IRQ);
3364
3365 /* enable the Tx Arbiters */
3366 for (i = 0; i < hw->ports; i++)
3367 sky2_write8(hw, SK_REG(i, TXA_CTRL), val: TXA_ENA_ARB);
3368
3369 /* Initialize ram interface */
3370 for (i = 0; i < hw->ports; i++) {
3371 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), val: RI_RST_CLR);
3372
3373 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3374 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3375 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3376 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3377 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3378 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3379 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3380 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3383 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3385 }
3386
3387 sky2_write32(hw, reg: B0_HWE_IMSK, val: hwe_mask);
3388
3389 for (i = 0; i < hw->ports; i++)
3390 sky2_gmac_reset(hw, port: i);
3391
3392 memset(s: hw->st_le, c: 0, n: hw->st_size * sizeof(struct sky2_status_le));
3393 hw->st_idx = 0;
3394
3395 sky2_write32(hw, reg: STAT_CTRL, val: SC_STAT_RST_SET);
3396 sky2_write32(hw, reg: STAT_CTRL, val: SC_STAT_RST_CLR);
3397
3398 sky2_write32(hw, reg: STAT_LIST_ADDR_LO, val: hw->st_dma);
3399 sky2_write32(hw, reg: STAT_LIST_ADDR_HI, val: (u64) hw->st_dma >> 32);
3400
3401 /* Set the list last index */
3402 sky2_write16(hw, reg: STAT_LAST_IDX, val: hw->st_size - 1);
3403
3404 sky2_write16(hw, reg: STAT_TX_IDX_TH, val: 10);
3405 sky2_write8(hw, reg: STAT_FIFO_WM, val: 16);
3406
3407 /* set Status-FIFO ISR watermark */
3408 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3409 sky2_write8(hw, reg: STAT_FIFO_ISR_WM, val: 4);
3410 else
3411 sky2_write8(hw, reg: STAT_FIFO_ISR_WM, val: 16);
3412
3413 sky2_write32(hw, reg: STAT_TX_TIMER_INI, val: sky2_us2clk(hw, us: 1000));
3414 sky2_write32(hw, reg: STAT_ISR_TIMER_INI, val: sky2_us2clk(hw, us: 20));
3415 sky2_write32(hw, reg: STAT_LEV_TIMER_INI, val: sky2_us2clk(hw, us: 100));
3416
3417 /* enable status unit */
3418 sky2_write32(hw, reg: STAT_CTRL, val: SC_STAT_OP_ON);
3419
3420 sky2_write8(hw, reg: STAT_TX_TIMER_CTRL, val: TIM_START);
3421 sky2_write8(hw, reg: STAT_LEV_TIMER_CTRL, val: TIM_START);
3422 sky2_write8(hw, reg: STAT_ISR_TIMER_CTRL, val: TIM_START);
3423}
3424
3425/* Take device down (offline).
3426 * Equivalent to doing dev_stop() but this does not
3427 * inform upper layers of the transition.
3428 */
3429static void sky2_detach(struct net_device *dev)
3430{
3431 if (netif_running(dev)) {
3432 netif_tx_lock(dev);
3433 netif_device_detach(dev); /* stop txq */
3434 netif_tx_unlock(dev);
3435 sky2_close(dev);
3436 }
3437}
3438
3439/* Bring device back after doing sky2_detach */
3440static int sky2_reattach(struct net_device *dev)
3441{
3442 int err = 0;
3443
3444 if (netif_running(dev)) {
3445 err = sky2_open(dev);
3446 if (err) {
3447 netdev_info(dev, format: "could not restart %d\n", err);
3448 dev_close(dev);
3449 } else {
3450 netif_device_attach(dev);
3451 sky2_set_multicast(dev);
3452 }
3453 }
3454
3455 return err;
3456}
3457
3458static void sky2_all_down(struct sky2_hw *hw)
3459{
3460 int i;
3461
3462 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3463 sky2_write32(hw, reg: B0_IMSK, val: 0);
3464 sky2_read32(hw, reg: B0_IMSK);
3465
3466 synchronize_irq(irq: hw->pdev->irq);
3467 napi_disable(n: &hw->napi);
3468 }
3469
3470 for (i = 0; i < hw->ports; i++) {
3471 struct net_device *dev = hw->dev[i];
3472 struct sky2_port *sky2 = netdev_priv(dev);
3473
3474 if (!netif_running(dev))
3475 continue;
3476
3477 netif_carrier_off(dev);
3478 netif_tx_disable(dev);
3479 sky2_hw_down(sky2);
3480 }
3481}
3482
3483static void sky2_all_up(struct sky2_hw *hw)
3484{
3485 u32 imask = Y2_IS_BASE;
3486 int i;
3487
3488 for (i = 0; i < hw->ports; i++) {
3489 struct net_device *dev = hw->dev[i];
3490 struct sky2_port *sky2 = netdev_priv(dev);
3491
3492 if (!netif_running(dev))
3493 continue;
3494
3495 sky2_hw_up(sky2);
3496 sky2_set_multicast(dev);
3497 imask |= portirq_msk[i];
3498 netif_wake_queue(dev);
3499 }
3500
3501 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3502 sky2_write32(hw, reg: B0_IMSK, val: imask);
3503 sky2_read32(hw, reg: B0_IMSK);
3504 sky2_read32(hw, reg: B0_Y2_SP_LISR);
3505 napi_enable(n: &hw->napi);
3506 }
3507}
3508
3509static void sky2_restart(struct work_struct *work)
3510{
3511 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3512
3513 rtnl_lock();
3514
3515 sky2_all_down(hw);
3516 sky2_reset(hw);
3517 sky2_all_up(hw);
3518
3519 rtnl_unlock();
3520}
3521
3522static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3523{
3524 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3525}
3526
3527static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3528{
3529 const struct sky2_port *sky2 = netdev_priv(dev);
3530
3531 wol->supported = sky2_wol_supported(hw: sky2->hw);
3532 wol->wolopts = sky2->wol;
3533}
3534
3535static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3536{
3537 struct sky2_port *sky2 = netdev_priv(dev);
3538 struct sky2_hw *hw = sky2->hw;
3539 bool enable_wakeup = false;
3540 int i;
3541
3542 if ((wol->wolopts & ~sky2_wol_supported(hw: sky2->hw)) ||
3543 !device_can_wakeup(dev: &hw->pdev->dev))
3544 return -EOPNOTSUPP;
3545
3546 sky2->wol = wol->wolopts;
3547
3548 for (i = 0; i < hw->ports; i++) {
3549 struct net_device *dev = hw->dev[i];
3550 struct sky2_port *sky2 = netdev_priv(dev);
3551
3552 if (sky2->wol)
3553 enable_wakeup = true;
3554 }
3555 device_set_wakeup_enable(dev: &hw->pdev->dev, enable: enable_wakeup);
3556
3557 return 0;
3558}
3559
3560static u32 sky2_supported_modes(const struct sky2_hw *hw)
3561{
3562 if (sky2_is_copper(hw)) {
3563 u32 modes = SUPPORTED_10baseT_Half
3564 | SUPPORTED_10baseT_Full
3565 | SUPPORTED_100baseT_Half
3566 | SUPPORTED_100baseT_Full;
3567
3568 if (hw->flags & SKY2_HW_GIGABIT)
3569 modes |= SUPPORTED_1000baseT_Half
3570 | SUPPORTED_1000baseT_Full;
3571 return modes;
3572 } else
3573 return SUPPORTED_1000baseT_Half
3574 | SUPPORTED_1000baseT_Full;
3575}
3576
3577static int sky2_get_link_ksettings(struct net_device *dev,
3578 struct ethtool_link_ksettings *cmd)
3579{
3580 struct sky2_port *sky2 = netdev_priv(dev);
3581 struct sky2_hw *hw = sky2->hw;
3582 u32 supported, advertising;
3583
3584 supported = sky2_supported_modes(hw);
3585 cmd->base.phy_address = PHY_ADDR_MARV;
3586 if (sky2_is_copper(hw)) {
3587 cmd->base.port = PORT_TP;
3588 cmd->base.speed = sky2->speed;
3589 supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3590 } else {
3591 cmd->base.speed = SPEED_1000;
3592 cmd->base.port = PORT_FIBRE;
3593 supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3594 }
3595
3596 advertising = sky2->advertising;
3597 cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3598 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3599 cmd->base.duplex = sky2->duplex;
3600
3601 ethtool_convert_legacy_u32_to_link_mode(dst: cmd->link_modes.supported,
3602 legacy_u32: supported);
3603 ethtool_convert_legacy_u32_to_link_mode(dst: cmd->link_modes.advertising,
3604 legacy_u32: advertising);
3605
3606 return 0;
3607}
3608
3609static int sky2_set_link_ksettings(struct net_device *dev,
3610 const struct ethtool_link_ksettings *cmd)
3611{
3612 struct sky2_port *sky2 = netdev_priv(dev);
3613 const struct sky2_hw *hw = sky2->hw;
3614 u32 supported = sky2_supported_modes(hw);
3615 u32 new_advertising;
3616
3617 ethtool_convert_link_mode_to_legacy_u32(legacy_u32: &new_advertising,
3618 src: cmd->link_modes.advertising);
3619
3620 if (cmd->base.autoneg == AUTONEG_ENABLE) {
3621 if (new_advertising & ~supported)
3622 return -EINVAL;
3623
3624 if (sky2_is_copper(hw))
3625 sky2->advertising = new_advertising |
3626 ADVERTISED_TP |
3627 ADVERTISED_Autoneg;
3628 else
3629 sky2->advertising = new_advertising |
3630 ADVERTISED_FIBRE |
3631 ADVERTISED_Autoneg;
3632
3633 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3634 sky2->duplex = -1;
3635 sky2->speed = -1;
3636 } else {
3637 u32 setting;
3638 u32 speed = cmd->base.speed;
3639
3640 switch (speed) {
3641 case SPEED_1000:
3642 if (cmd->base.duplex == DUPLEX_FULL)
3643 setting = SUPPORTED_1000baseT_Full;
3644 else if (cmd->base.duplex == DUPLEX_HALF)
3645 setting = SUPPORTED_1000baseT_Half;
3646 else
3647 return -EINVAL;
3648 break;
3649 case SPEED_100:
3650 if (cmd->base.duplex == DUPLEX_FULL)
3651 setting = SUPPORTED_100baseT_Full;
3652 else if (cmd->base.duplex == DUPLEX_HALF)
3653 setting = SUPPORTED_100baseT_Half;
3654 else
3655 return -EINVAL;
3656 break;
3657
3658 case SPEED_10:
3659 if (cmd->base.duplex == DUPLEX_FULL)
3660 setting = SUPPORTED_10baseT_Full;
3661 else if (cmd->base.duplex == DUPLEX_HALF)
3662 setting = SUPPORTED_10baseT_Half;
3663 else
3664 return -EINVAL;
3665 break;
3666 default:
3667 return -EINVAL;
3668 }
3669
3670 if ((setting & supported) == 0)
3671 return -EINVAL;
3672
3673 sky2->speed = speed;
3674 sky2->duplex = cmd->base.duplex;
3675 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3676 }
3677
3678 if (netif_running(dev)) {
3679 sky2_phy_reinit(sky2);
3680 sky2_set_multicast(dev);
3681 }
3682
3683 return 0;
3684}
3685
3686static void sky2_get_drvinfo(struct net_device *dev,
3687 struct ethtool_drvinfo *info)
3688{
3689 struct sky2_port *sky2 = netdev_priv(dev);
3690
3691 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
3692 strscpy(info->version, DRV_VERSION, sizeof(info->version));
3693 strscpy(info->bus_info, pci_name(sky2->hw->pdev),
3694 sizeof(info->bus_info));
3695}
3696
3697static const struct sky2_stat {
3698 char name[ETH_GSTRING_LEN];
3699 u16 offset;
3700} sky2_stats[] = {
3701 { "tx_bytes", GM_TXO_OK_HI },
3702 { .name: "rx_bytes", .offset: GM_RXO_OK_HI },
3703 { .name: "tx_broadcast", .offset: GM_TXF_BC_OK },
3704 { .name: "rx_broadcast", .offset: GM_RXF_BC_OK },
3705 { .name: "tx_multicast", .offset: GM_TXF_MC_OK },
3706 { .name: "rx_multicast", .offset: GM_RXF_MC_OK },
3707 { .name: "tx_unicast", .offset: GM_TXF_UC_OK },
3708 { .name: "rx_unicast", .offset: GM_RXF_UC_OK },
3709 { .name: "tx_mac_pause", .offset: GM_TXF_MPAUSE },
3710 { .name: "rx_mac_pause", .offset: GM_RXF_MPAUSE },
3711 { .name: "collisions", .offset: GM_TXF_COL },
3712 { .name: "late_collision",.offset: GM_TXF_LAT_COL },
3713 { .name: "aborted", .offset: GM_TXF_ABO_COL },
3714 { .name: "single_collisions", .offset: GM_TXF_SNG_COL },
3715 { .name: "multi_collisions", .offset: GM_TXF_MUL_COL },
3716
3717 { .name: "rx_short", .offset: GM_RXF_SHT },
3718 { .name: "rx_runt", .offset: GM_RXE_FRAG },
3719 { .name: "rx_64_byte_packets", .offset: GM_RXF_64B },
3720 { .name: "rx_65_to_127_byte_packets", .offset: GM_RXF_127B },
3721 { .name: "rx_128_to_255_byte_packets", .offset: GM_RXF_255B },
3722 { .name: "rx_256_to_511_byte_packets", .offset: GM_RXF_511B },
3723 { .name: "rx_512_to_1023_byte_packets", .offset: GM_RXF_1023B },
3724 { .name: "rx_1024_to_1518_byte_packets", .offset: GM_RXF_1518B },
3725 { .name: "rx_1518_to_max_byte_packets", .offset: GM_RXF_MAX_SZ },
3726 { .name: "rx_too_long", .offset: GM_RXF_LNG_ERR },
3727 { .name: "rx_fifo_overflow", .offset: GM_RXE_FIFO_OV },
3728 { .name: "rx_jabber", .offset: GM_RXF_JAB_PKT },
3729 { .name: "rx_fcs_error", .offset: GM_RXF_FCS_ERR },
3730
3731 { .name: "tx_64_byte_packets", .offset: GM_TXF_64B },
3732 { .name: "tx_65_to_127_byte_packets", .offset: GM_TXF_127B },
3733 { .name: "tx_128_to_255_byte_packets", .offset: GM_TXF_255B },
3734 { .name: "tx_256_to_511_byte_packets", .offset: GM_TXF_511B },
3735 { .name: "tx_512_to_1023_byte_packets", .offset: GM_TXF_1023B },
3736 { .name: "tx_1024_to_1518_byte_packets", .offset: GM_TXF_1518B },
3737 { .name: "tx_1519_to_max_byte_packets", .offset: GM_TXF_MAX_SZ },
3738 { .name: "tx_fifo_underrun", .offset: GM_TXE_FIFO_UR },
3739};
3740
3741static u32 sky2_get_msglevel(struct net_device *netdev)
3742{
3743 struct sky2_port *sky2 = netdev_priv(dev: netdev);
3744 return sky2->msg_enable;
3745}
3746
3747static int sky2_nway_reset(struct net_device *dev)
3748{
3749 struct sky2_port *sky2 = netdev_priv(dev);
3750
3751 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3752 return -EINVAL;
3753
3754 sky2_phy_reinit(sky2);
3755 sky2_set_multicast(dev);
3756
3757 return 0;
3758}
3759
3760static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3761{
3762 struct sky2_hw *hw = sky2->hw;
3763 unsigned port = sky2->port;
3764 int i;
3765
3766 data[0] = get_stats64(hw, port, reg: GM_TXO_OK_LO);
3767 data[1] = get_stats64(hw, port, reg: GM_RXO_OK_LO);
3768
3769 for (i = 2; i < count; i++)
3770 data[i] = get_stats32(hw, port, reg: sky2_stats[i].offset);
3771}
3772
3773static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3774{
3775 struct sky2_port *sky2 = netdev_priv(dev: netdev);
3776 sky2->msg_enable = value;
3777}
3778
3779static int sky2_get_sset_count(struct net_device *dev, int sset)
3780{
3781 switch (sset) {
3782 case ETH_SS_STATS:
3783 return ARRAY_SIZE(sky2_stats);
3784 default:
3785 return -EOPNOTSUPP;
3786 }
3787}
3788
3789static void sky2_get_ethtool_stats(struct net_device *dev,
3790 struct ethtool_stats *stats, u64 * data)
3791{
3792 struct sky2_port *sky2 = netdev_priv(dev);
3793
3794 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3795}
3796
3797static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3798{
3799 int i;
3800
3801 switch (stringset) {
3802 case ETH_SS_STATS:
3803 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3804 ethtool_puts(data: &data, str: sky2_stats[i].name);
3805 break;
3806 }
3807}
3808
3809static int sky2_set_mac_address(struct net_device *dev, void *p)
3810{
3811 struct sky2_port *sky2 = netdev_priv(dev);
3812 struct sky2_hw *hw = sky2->hw;
3813 unsigned port = sky2->port;
3814 const struct sockaddr *addr = p;
3815
3816 if (!is_valid_ether_addr(addr: addr->sa_data))
3817 return -EADDRNOTAVAIL;
3818
3819 eth_hw_addr_set(dev, addr: addr->sa_data);
3820 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3821 dev->dev_addr, ETH_ALEN);
3822 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3823 dev->dev_addr, ETH_ALEN);
3824
3825 /* virtual address for data */
3826 gma_set_addr(hw, port, reg: GM_SRC_ADDR_2L, addr: dev->dev_addr);
3827
3828 /* physical address: used for pause frames */
3829 gma_set_addr(hw, port, reg: GM_SRC_ADDR_1L, addr: dev->dev_addr);
3830
3831 return 0;
3832}
3833
3834static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3835{
3836 u32 bit;
3837
3838 bit = ether_crc(ETH_ALEN, addr) & 63;
3839 filter[bit >> 3] |= 1 << (bit & 7);
3840}
3841
3842static void sky2_set_multicast(struct net_device *dev)
3843{
3844 struct sky2_port *sky2 = netdev_priv(dev);
3845 struct sky2_hw *hw = sky2->hw;
3846 unsigned port = sky2->port;
3847 struct netdev_hw_addr *ha;
3848 u16 reg;
3849 u8 filter[8];
3850 int rx_pause;
3851 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3852
3853 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3854 memset(s: filter, c: 0, n: sizeof(filter));
3855
3856 reg = gma_read16(hw, port, reg: GM_RX_CTRL);
3857 reg |= GM_RXCR_UCF_ENA;
3858
3859 if (dev->flags & IFF_PROMISC) /* promiscuous */
3860 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3861 else if (dev->flags & IFF_ALLMULTI)
3862 memset(s: filter, c: 0xff, n: sizeof(filter));
3863 else if (netdev_mc_empty(dev) && !rx_pause)
3864 reg &= ~GM_RXCR_MCF_ENA;
3865 else {
3866 reg |= GM_RXCR_MCF_ENA;
3867
3868 if (rx_pause)
3869 sky2_add_filter(filter, addr: pause_mc_addr);
3870
3871 netdev_for_each_mc_addr(ha, dev)
3872 sky2_add_filter(filter, addr: ha->addr);
3873 }
3874
3875 gma_write16(hw, port, r: GM_MC_ADDR_H1,
3876 v: (u16) filter[0] | ((u16) filter[1] << 8));
3877 gma_write16(hw, port, r: GM_MC_ADDR_H2,
3878 v: (u16) filter[2] | ((u16) filter[3] << 8));
3879 gma_write16(hw, port, r: GM_MC_ADDR_H3,
3880 v: (u16) filter[4] | ((u16) filter[5] << 8));
3881 gma_write16(hw, port, r: GM_MC_ADDR_H4,
3882 v: (u16) filter[6] | ((u16) filter[7] << 8));
3883
3884 gma_write16(hw, port, r: GM_RX_CTRL, v: reg);
3885}
3886
3887static void sky2_get_stats(struct net_device *dev,
3888 struct rtnl_link_stats64 *stats)
3889{
3890 struct sky2_port *sky2 = netdev_priv(dev);
3891 struct sky2_hw *hw = sky2->hw;
3892 unsigned port = sky2->port;
3893 unsigned int start;
3894 u64 _bytes, _packets;
3895
3896 do {
3897 start = u64_stats_fetch_begin(syncp: &sky2->rx_stats.syncp);
3898 _bytes = sky2->rx_stats.bytes;
3899 _packets = sky2->rx_stats.packets;
3900 } while (u64_stats_fetch_retry(syncp: &sky2->rx_stats.syncp, start));
3901
3902 stats->rx_packets = _packets;
3903 stats->rx_bytes = _bytes;
3904
3905 do {
3906 start = u64_stats_fetch_begin(syncp: &sky2->tx_stats.syncp);
3907 _bytes = sky2->tx_stats.bytes;
3908 _packets = sky2->tx_stats.packets;
3909 } while (u64_stats_fetch_retry(syncp: &sky2->tx_stats.syncp, start));
3910
3911 stats->tx_packets = _packets;
3912 stats->tx_bytes = _bytes;
3913
3914 stats->multicast = get_stats32(hw, port, reg: GM_RXF_MC_OK)
3915 + get_stats32(hw, port, reg: GM_RXF_BC_OK);
3916
3917 stats->collisions = get_stats32(hw, port, reg: GM_TXF_COL);
3918
3919 stats->rx_length_errors = get_stats32(hw, port, reg: GM_RXF_LNG_ERR);
3920 stats->rx_crc_errors = get_stats32(hw, port, reg: GM_RXF_FCS_ERR);
3921 stats->rx_frame_errors = get_stats32(hw, port, reg: GM_RXF_SHT)
3922 + get_stats32(hw, port, reg: GM_RXE_FRAG);
3923 stats->rx_over_errors = get_stats32(hw, port, reg: GM_RXE_FIFO_OV);
3924
3925 stats->rx_dropped = dev->stats.rx_dropped;
3926 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3927 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3928}
3929
3930/* Can have one global because blinking is controlled by
3931 * ethtool and that is always under RTNL mutex
3932 */
3933static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3934{
3935 struct sky2_hw *hw = sky2->hw;
3936 unsigned port = sky2->port;
3937
3938 spin_lock_bh(lock: &sky2->phy_lock);
3939 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3940 hw->chip_id == CHIP_ID_YUKON_EX ||
3941 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3942 u16 pg;
3943 pg = gm_phy_read(hw, port, reg: PHY_MARV_EXT_ADR);
3944 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: 3);
3945
3946 switch (mode) {
3947 case MO_LED_OFF:
3948 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL,
3949 PHY_M_LEDC_LOS_CTRL(8) |
3950 PHY_M_LEDC_INIT_CTRL(8) |
3951 PHY_M_LEDC_STA1_CTRL(8) |
3952 PHY_M_LEDC_STA0_CTRL(8));
3953 break;
3954 case MO_LED_ON:
3955 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL,
3956 PHY_M_LEDC_LOS_CTRL(9) |
3957 PHY_M_LEDC_INIT_CTRL(9) |
3958 PHY_M_LEDC_STA1_CTRL(9) |
3959 PHY_M_LEDC_STA0_CTRL(9));
3960 break;
3961 case MO_LED_BLINK:
3962 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL,
3963 PHY_M_LEDC_LOS_CTRL(0xa) |
3964 PHY_M_LEDC_INIT_CTRL(0xa) |
3965 PHY_M_LEDC_STA1_CTRL(0xa) |
3966 PHY_M_LEDC_STA0_CTRL(0xa));
3967 break;
3968 case MO_LED_NORM:
3969 gm_phy_write(hw, port, reg: PHY_MARV_PHY_CTRL,
3970 PHY_M_LEDC_LOS_CTRL(1) |
3971 PHY_M_LEDC_INIT_CTRL(8) |
3972 PHY_M_LEDC_STA1_CTRL(7) |
3973 PHY_M_LEDC_STA0_CTRL(7));
3974 }
3975
3976 gm_phy_write(hw, port, reg: PHY_MARV_EXT_ADR, val: pg);
3977 } else
3978 gm_phy_write(hw, port, reg: PHY_MARV_LED_OVER,
3979 PHY_M_LED_MO_DUP(mode) |
3980 PHY_M_LED_MO_10(mode) |
3981 PHY_M_LED_MO_100(mode) |
3982 PHY_M_LED_MO_1000(mode) |
3983 PHY_M_LED_MO_RX(mode) |
3984 PHY_M_LED_MO_TX(mode));
3985
3986 spin_unlock_bh(lock: &sky2->phy_lock);
3987}
3988
3989/* blink LED's for finding board */
3990static int sky2_set_phys_id(struct net_device *dev,
3991 enum ethtool_phys_id_state state)
3992{
3993 struct sky2_port *sky2 = netdev_priv(dev);
3994
3995 switch (state) {
3996 case ETHTOOL_ID_ACTIVE:
3997 return 1; /* cycle on/off once per second */
3998 case ETHTOOL_ID_INACTIVE:
3999 sky2_led(sky2, mode: MO_LED_NORM);
4000 break;
4001 case ETHTOOL_ID_ON:
4002 sky2_led(sky2, mode: MO_LED_ON);
4003 break;
4004 case ETHTOOL_ID_OFF:
4005 sky2_led(sky2, mode: MO_LED_OFF);
4006 break;
4007 }
4008
4009 return 0;
4010}
4011
4012static void sky2_get_pauseparam(struct net_device *dev,
4013 struct ethtool_pauseparam *ecmd)
4014{
4015 struct sky2_port *sky2 = netdev_priv(dev);
4016
4017 switch (sky2->flow_mode) {
4018 case FC_NONE:
4019 ecmd->tx_pause = ecmd->rx_pause = 0;
4020 break;
4021 case FC_TX:
4022 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4023 break;
4024 case FC_RX:
4025 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4026 break;
4027 case FC_BOTH:
4028 ecmd->tx_pause = ecmd->rx_pause = 1;
4029 }
4030
4031 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4032 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
4033}
4034
4035static int sky2_set_pauseparam(struct net_device *dev,
4036 struct ethtool_pauseparam *ecmd)
4037{
4038 struct sky2_port *sky2 = netdev_priv(dev);
4039
4040 if (ecmd->autoneg == AUTONEG_ENABLE)
4041 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4042 else
4043 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4044
4045 sky2->flow_mode = sky2_flow(rx: ecmd->rx_pause, tx: ecmd->tx_pause);
4046
4047 if (netif_running(dev))
4048 sky2_phy_reinit(sky2);
4049
4050 return 0;
4051}
4052
4053static int sky2_get_coalesce(struct net_device *dev,
4054 struct ethtool_coalesce *ecmd,
4055 struct kernel_ethtool_coalesce *kernel_coal,
4056 struct netlink_ext_ack *extack)
4057{
4058 struct sky2_port *sky2 = netdev_priv(dev);
4059 struct sky2_hw *hw = sky2->hw;
4060
4061 if (sky2_read8(hw, reg: STAT_TX_TIMER_CTRL) == TIM_STOP)
4062 ecmd->tx_coalesce_usecs = 0;
4063 else {
4064 u32 clks = sky2_read32(hw, reg: STAT_TX_TIMER_INI);
4065 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clk: clks);
4066 }
4067 ecmd->tx_max_coalesced_frames = sky2_read16(hw, reg: STAT_TX_IDX_TH);
4068
4069 if (sky2_read8(hw, reg: STAT_LEV_TIMER_CTRL) == TIM_STOP)
4070 ecmd->rx_coalesce_usecs = 0;
4071 else {
4072 u32 clks = sky2_read32(hw, reg: STAT_LEV_TIMER_INI);
4073 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clk: clks);
4074 }
4075 ecmd->rx_max_coalesced_frames = sky2_read8(hw, reg: STAT_FIFO_WM);
4076
4077 if (sky2_read8(hw, reg: STAT_ISR_TIMER_CTRL) == TIM_STOP)
4078 ecmd->rx_coalesce_usecs_irq = 0;
4079 else {
4080 u32 clks = sky2_read32(hw, reg: STAT_ISR_TIMER_INI);
4081 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clk: clks);
4082 }
4083
4084 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, reg: STAT_FIFO_ISR_WM);
4085
4086 return 0;
4087}
4088
4089/* Note: this affect both ports */
4090static int sky2_set_coalesce(struct net_device *dev,
4091 struct ethtool_coalesce *ecmd,
4092 struct kernel_ethtool_coalesce *kernel_coal,
4093 struct netlink_ext_ack *extack)
4094{
4095 struct sky2_port *sky2 = netdev_priv(dev);
4096 struct sky2_hw *hw = sky2->hw;
4097 const u32 tmax = sky2_clk2us(hw, clk: 0x0ffffff);
4098
4099 if (ecmd->tx_coalesce_usecs > tmax ||
4100 ecmd->rx_coalesce_usecs > tmax ||
4101 ecmd->rx_coalesce_usecs_irq > tmax)
4102 return -EINVAL;
4103
4104 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4105 return -EINVAL;
4106 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4107 return -EINVAL;
4108 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4109 return -EINVAL;
4110
4111 if (ecmd->tx_coalesce_usecs == 0)
4112 sky2_write8(hw, reg: STAT_TX_TIMER_CTRL, val: TIM_STOP);
4113 else {
4114 sky2_write32(hw, reg: STAT_TX_TIMER_INI,
4115 val: sky2_us2clk(hw, us: ecmd->tx_coalesce_usecs));
4116 sky2_write8(hw, reg: STAT_TX_TIMER_CTRL, val: TIM_START);
4117 }
4118 sky2_write16(hw, reg: STAT_TX_IDX_TH, val: ecmd->tx_max_coalesced_frames);
4119
4120 if (ecmd->rx_coalesce_usecs == 0)
4121 sky2_write8(hw, reg: STAT_LEV_TIMER_CTRL, val: TIM_STOP);
4122 else {
4123 sky2_write32(hw, reg: STAT_LEV_TIMER_INI,
4124 val: sky2_us2clk(hw, us: ecmd->rx_coalesce_usecs));
4125 sky2_write8(hw, reg: STAT_LEV_TIMER_CTRL, val: TIM_START);
4126 }
4127 sky2_write8(hw, reg: STAT_FIFO_WM, val: ecmd->rx_max_coalesced_frames);
4128
4129 if (ecmd->rx_coalesce_usecs_irq == 0)
4130 sky2_write8(hw, reg: STAT_ISR_TIMER_CTRL, val: TIM_STOP);
4131 else {
4132 sky2_write32(hw, reg: STAT_ISR_TIMER_INI,
4133 val: sky2_us2clk(hw, us: ecmd->rx_coalesce_usecs_irq));
4134 sky2_write8(hw, reg: STAT_ISR_TIMER_CTRL, val: TIM_START);
4135 }
4136 sky2_write8(hw, reg: STAT_FIFO_ISR_WM, val: ecmd->rx_max_coalesced_frames_irq);
4137 return 0;
4138}
4139
4140/*
4141 * Hardware is limited to min of 128 and max of 2048 for ring size
4142 * and rounded up to next power of two
4143 * to avoid division in modulus calculation
4144 */
4145static unsigned long roundup_ring_size(unsigned long pending)
4146{
4147 return max(128ul, roundup_pow_of_two(pending+1));
4148}
4149
4150static void sky2_get_ringparam(struct net_device *dev,
4151 struct ethtool_ringparam *ering,
4152 struct kernel_ethtool_ringparam *kernel_ering,
4153 struct netlink_ext_ack *extack)
4154{
4155 struct sky2_port *sky2 = netdev_priv(dev);
4156
4157 ering->rx_max_pending = RX_MAX_PENDING;
4158 ering->tx_max_pending = TX_MAX_PENDING;
4159
4160 ering->rx_pending = sky2->rx_pending;
4161 ering->tx_pending = sky2->tx_pending;
4162}
4163
4164static int sky2_set_ringparam(struct net_device *dev,
4165 struct ethtool_ringparam *ering,
4166 struct kernel_ethtool_ringparam *kernel_ering,
4167 struct netlink_ext_ack *extack)
4168{
4169 struct sky2_port *sky2 = netdev_priv(dev);
4170
4171 if (ering->rx_pending > RX_MAX_PENDING ||
4172 ering->rx_pending < 8 ||
4173 ering->tx_pending < TX_MIN_PENDING ||
4174 ering->tx_pending > TX_MAX_PENDING)
4175 return -EINVAL;
4176
4177 sky2_detach(dev);
4178
4179 sky2->rx_pending = ering->rx_pending;
4180 sky2->tx_pending = ering->tx_pending;
4181 sky2->tx_ring_size = roundup_ring_size(pending: sky2->tx_pending);
4182
4183 return sky2_reattach(dev);
4184}
4185
4186static int sky2_get_regs_len(struct net_device *dev)
4187{
4188 return 0x4000;
4189}
4190
4191static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4192{
4193 /* This complicated switch statement is to make sure and
4194 * only access regions that are unreserved.
4195 * Some blocks are only valid on dual port cards.
4196 */
4197 switch (b) {
4198 /* second port */
4199 case 5: /* Tx Arbiter 2 */
4200 case 9: /* RX2 */
4201 case 14 ... 15: /* TX2 */
4202 case 17: case 19: /* Ram Buffer 2 */
4203 case 22 ... 23: /* Tx Ram Buffer 2 */
4204 case 25: /* Rx MAC Fifo 1 */
4205 case 27: /* Tx MAC Fifo 2 */
4206 case 31: /* GPHY 2 */
4207 case 40 ... 47: /* Pattern Ram 2 */
4208 case 52: case 54: /* TCP Segmentation 2 */
4209 case 112 ... 116: /* GMAC 2 */
4210 return hw->ports > 1;
4211
4212 case 0: /* Control */
4213 case 2: /* Mac address */
4214 case 4: /* Tx Arbiter 1 */
4215 case 7: /* PCI express reg */
4216 case 8: /* RX1 */
4217 case 12 ... 13: /* TX1 */
4218 case 16: case 18:/* Rx Ram Buffer 1 */
4219 case 20 ... 21: /* Tx Ram Buffer 1 */
4220 case 24: /* Rx MAC Fifo 1 */
4221 case 26: /* Tx MAC Fifo 1 */
4222 case 28 ... 29: /* Descriptor and status unit */
4223 case 30: /* GPHY 1*/
4224 case 32 ... 39: /* Pattern Ram 1 */
4225 case 48: case 50: /* TCP Segmentation 1 */
4226 case 56 ... 60: /* PCI space */
4227 case 80 ... 84: /* GMAC 1 */
4228 return 1;
4229
4230 default:
4231 return 0;
4232 }
4233}
4234
4235/*
4236 * Returns copy of control register region
4237 * Note: ethtool_get_regs always provides full size (16k) buffer
4238 */
4239static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4240 void *p)
4241{
4242 const struct sky2_port *sky2 = netdev_priv(dev);
4243 const void __iomem *io = sky2->hw->regs;
4244 unsigned int b;
4245
4246 regs->version = 1;
4247
4248 for (b = 0; b < 128; b++) {
4249 /* skip poisonous diagnostic ram region in block 3 */
4250 if (b == 3)
4251 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4252 else if (sky2_reg_access_ok(hw: sky2->hw, b))
4253 memcpy_fromio(p, io, 128);
4254 else
4255 memset(s: p, c: 0, n: 128);
4256
4257 p += 128;
4258 io += 128;
4259 }
4260}
4261
4262static int sky2_get_eeprom_len(struct net_device *dev)
4263{
4264 struct sky2_port *sky2 = netdev_priv(dev);
4265 struct sky2_hw *hw = sky2->hw;
4266 u16 reg2;
4267
4268 reg2 = sky2_pci_read16(hw, reg: PCI_DEV_REG2);
4269 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4270}
4271
4272static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4273 u8 *data)
4274{
4275 struct sky2_port *sky2 = netdev_priv(dev);
4276 int rc;
4277
4278 eeprom->magic = SKY2_EEPROM_MAGIC;
4279 rc = pci_read_vpd_any(dev: sky2->hw->pdev, pos: eeprom->offset, count: eeprom->len,
4280 buf: data);
4281 if (rc < 0)
4282 return rc;
4283
4284 eeprom->len = rc;
4285
4286 return 0;
4287}
4288
4289static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4290 u8 *data)
4291{
4292 struct sky2_port *sky2 = netdev_priv(dev);
4293 int rc;
4294
4295 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4296 return -EINVAL;
4297
4298 rc = pci_write_vpd_any(dev: sky2->hw->pdev, pos: eeprom->offset, count: eeprom->len,
4299 buf: data);
4300
4301 return rc < 0 ? rc : 0;
4302}
4303
4304static netdev_features_t sky2_fix_features(struct net_device *dev,
4305 netdev_features_t features)
4306{
4307 const struct sky2_port *sky2 = netdev_priv(dev);
4308 const struct sky2_hw *hw = sky2->hw;
4309
4310 /* In order to do Jumbo packets on these chips, need to turn off the
4311 * transmit store/forward. Therefore checksum offload won't work.
4312 */
4313 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4314 netdev_info(dev, format: "checksum offload not possible with jumbo frames\n");
4315 features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK);
4316 }
4317
4318 /* Some hardware requires receive checksum for RSS to work. */
4319 if ( (features & NETIF_F_RXHASH) &&
4320 !(features & NETIF_F_RXCSUM) &&
4321 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4322 netdev_info(dev, format: "receive hashing forces receive checksum\n");
4323 features |= NETIF_F_RXCSUM;
4324 }
4325
4326 return features;
4327}
4328
4329static int sky2_set_features(struct net_device *dev, netdev_features_t features)
4330{
4331 struct sky2_port *sky2 = netdev_priv(dev);
4332 netdev_features_t changed = dev->features ^ features;
4333
4334 if ((changed & NETIF_F_RXCSUM) &&
4335 !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4336 sky2_write32(hw: sky2->hw,
4337 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4338 val: (features & NETIF_F_RXCSUM)
4339 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4340 }
4341
4342 if (changed & NETIF_F_RXHASH)
4343 rx_set_rss(dev, features);
4344
4345 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4346 sky2_vlan_mode(dev, features);
4347
4348 return 0;
4349}
4350
4351static const struct ethtool_ops sky2_ethtool_ops = {
4352 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
4353 ETHTOOL_COALESCE_MAX_FRAMES |
4354 ETHTOOL_COALESCE_RX_USECS_IRQ |
4355 ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ,
4356 .get_drvinfo = sky2_get_drvinfo,
4357 .get_wol = sky2_get_wol,
4358 .set_wol = sky2_set_wol,
4359 .get_msglevel = sky2_get_msglevel,
4360 .set_msglevel = sky2_set_msglevel,
4361 .nway_reset = sky2_nway_reset,
4362 .get_regs_len = sky2_get_regs_len,
4363 .get_regs = sky2_get_regs,
4364 .get_link = ethtool_op_get_link,
4365 .get_eeprom_len = sky2_get_eeprom_len,
4366 .get_eeprom = sky2_get_eeprom,
4367 .set_eeprom = sky2_set_eeprom,
4368 .get_strings = sky2_get_strings,
4369 .get_coalesce = sky2_get_coalesce,
4370 .set_coalesce = sky2_set_coalesce,
4371 .get_ringparam = sky2_get_ringparam,
4372 .set_ringparam = sky2_set_ringparam,
4373 .get_pauseparam = sky2_get_pauseparam,
4374 .set_pauseparam = sky2_set_pauseparam,
4375 .set_phys_id = sky2_set_phys_id,
4376 .get_sset_count = sky2_get_sset_count,
4377 .get_ethtool_stats = sky2_get_ethtool_stats,
4378 .get_link_ksettings = sky2_get_link_ksettings,
4379 .set_link_ksettings = sky2_set_link_ksettings,
4380};
4381
4382#ifdef CONFIG_SKY2_DEBUG
4383
4384static struct dentry *sky2_debug;
4385
4386static int sky2_debug_show(struct seq_file *seq, void *v)
4387{
4388 struct net_device *dev = seq->private;
4389 const struct sky2_port *sky2 = netdev_priv(dev);
4390 struct sky2_hw *hw = sky2->hw;
4391 unsigned port = sky2->port;
4392 unsigned idx, last;
4393 int sop;
4394
4395 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
4396 sky2_read32(hw, B0_ISRC),
4397 sky2_read32(hw, B0_IMSK),
4398 sky2_read32(hw, B0_Y2_SP_ICR));
4399
4400 if (!netif_running(dev)) {
4401 seq_puts(seq, "network not running\n");
4402 return 0;
4403 }
4404
4405 napi_disable(&hw->napi);
4406 last = sky2_read16(hw, STAT_PUT_IDX);
4407
4408 seq_printf(seq, "Status ring %u\n", hw->st_size);
4409 if (hw->st_idx == last)
4410 seq_puts(seq, "Status ring (empty)\n");
4411 else {
4412 seq_puts(seq, "Status ring\n");
4413 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4414 idx = RING_NEXT(idx, hw->st_size)) {
4415 const struct sky2_status_le *le = hw->st_le + idx;
4416 seq_printf(seq, "[%d] %#x %d %#x\n",
4417 idx, le->opcode, le->length, le->status);
4418 }
4419 seq_puts(seq, "\n");
4420 }
4421
4422 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4423 sky2->tx_cons, sky2->tx_prod,
4424 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4425 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4426
4427 /* Dump contents of tx ring */
4428 sop = 1;
4429 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4430 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4431 const struct sky2_tx_le *le = sky2->tx_le + idx;
4432 u32 a = le32_to_cpu(le->addr);
4433
4434 if (sop)
4435 seq_printf(seq, "%u:", idx);
4436 sop = 0;
4437
4438 switch (le->opcode & ~HW_OWNER) {
4439 case OP_ADDR64:
4440 seq_printf(seq, " %#x:", a);
4441 break;
4442 case OP_LRGLEN:
4443 seq_printf(seq, " mtu=%d", a);
4444 break;
4445 case OP_VLAN:
4446 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4447 break;
4448 case OP_TCPLISW:
4449 seq_printf(seq, " csum=%#x", a);
4450 break;
4451 case OP_LARGESEND:
4452 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4453 break;
4454 case OP_PACKET:
4455 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4456 break;
4457 case OP_BUFFER:
4458 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4459 break;
4460 default:
4461 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4462 a, le16_to_cpu(le->length));
4463 }
4464
4465 if (le->ctrl & EOP) {
4466 seq_putc(seq, '\n');
4467 sop = 1;
4468 }
4469 }
4470
4471 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4472 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4473 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4474 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4475
4476 sky2_read32(hw, B0_Y2_SP_LISR);
4477 napi_enable(&hw->napi);
4478 return 0;
4479}
4480DEFINE_SHOW_ATTRIBUTE(sky2_debug);
4481
4482/*
4483 * Use network device events to create/remove/rename
4484 * debugfs file entries
4485 */
4486static int sky2_device_event(struct notifier_block *unused,
4487 unsigned long event, void *ptr)
4488{
4489 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4490 struct sky2_port *sky2 = netdev_priv(dev);
4491
4492 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4493 return NOTIFY_DONE;
4494
4495 switch (event) {
4496 case NETDEV_CHANGENAME:
4497 debugfs_change_name(sky2->debugfs, "%s", dev->name);
4498 break;
4499
4500 case NETDEV_GOING_DOWN:
4501 if (sky2->debugfs) {
4502 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4503 debugfs_remove(sky2->debugfs);
4504 sky2->debugfs = NULL;
4505 }
4506 break;
4507
4508 case NETDEV_UP:
4509 sky2->debugfs = debugfs_create_file(dev->name, 0444,
4510 sky2_debug, dev,
4511 &sky2_debug_fops);
4512 if (IS_ERR(sky2->debugfs))
4513 sky2->debugfs = NULL;
4514 }
4515
4516 return NOTIFY_DONE;
4517}
4518
4519static struct notifier_block sky2_notifier = {
4520 .notifier_call = sky2_device_event,
4521};
4522
4523
4524static __init void sky2_debug_init(void)
4525{
4526 struct dentry *ent;
4527
4528 ent = debugfs_create_dir("sky2", NULL);
4529 if (IS_ERR(ent))
4530 return;
4531
4532 sky2_debug = ent;
4533 register_netdevice_notifier(&sky2_notifier);
4534}
4535
4536static __exit void sky2_debug_cleanup(void)
4537{
4538 if (sky2_debug) {
4539 unregister_netdevice_notifier(&sky2_notifier);
4540 debugfs_remove(sky2_debug);
4541 sky2_debug = NULL;
4542 }
4543}
4544
4545#else
4546#define sky2_debug_init()
4547#define sky2_debug_cleanup()
4548#endif
4549
4550/* Two copies of network device operations to handle special case of
4551 * not allowing netpoll on second port
4552 */
4553static const struct net_device_ops sky2_netdev_ops[2] = {
4554 {
4555 .ndo_open = sky2_open,
4556 .ndo_stop = sky2_close,
4557 .ndo_start_xmit = sky2_xmit_frame,
4558 .ndo_eth_ioctl = sky2_ioctl,
4559 .ndo_validate_addr = eth_validate_addr,
4560 .ndo_set_mac_address = sky2_set_mac_address,
4561 .ndo_set_rx_mode = sky2_set_multicast,
4562 .ndo_change_mtu = sky2_change_mtu,
4563 .ndo_fix_features = sky2_fix_features,
4564 .ndo_set_features = sky2_set_features,
4565 .ndo_tx_timeout = sky2_tx_timeout,
4566 .ndo_get_stats64 = sky2_get_stats,
4567#ifdef CONFIG_NET_POLL_CONTROLLER
4568 .ndo_poll_controller = sky2_netpoll,
4569#endif
4570 },
4571 {
4572 .ndo_open = sky2_open,
4573 .ndo_stop = sky2_close,
4574 .ndo_start_xmit = sky2_xmit_frame,
4575 .ndo_eth_ioctl = sky2_ioctl,
4576 .ndo_validate_addr = eth_validate_addr,
4577 .ndo_set_mac_address = sky2_set_mac_address,
4578 .ndo_set_rx_mode = sky2_set_multicast,
4579 .ndo_change_mtu = sky2_change_mtu,
4580 .ndo_fix_features = sky2_fix_features,
4581 .ndo_set_features = sky2_set_features,
4582 .ndo_tx_timeout = sky2_tx_timeout,
4583 .ndo_get_stats64 = sky2_get_stats,
4584 },
4585};
4586
4587/* Initialize network device */
4588static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
4589 int highmem, int wol)
4590{
4591 struct sky2_port *sky2;
4592 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4593 int ret;
4594
4595 if (!dev)
4596 return NULL;
4597
4598 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4599 dev->irq = hw->pdev->irq;
4600 dev->ethtool_ops = &sky2_ethtool_ops;
4601 dev->watchdog_timeo = TX_WATCHDOG;
4602 dev->netdev_ops = &sky2_netdev_ops[port];
4603
4604 sky2 = netdev_priv(dev);
4605 sky2->netdev = dev;
4606 sky2->hw = hw;
4607 sky2->msg_enable = netif_msg_init(debug_value: debug, default_msg_enable_bits: default_msg);
4608
4609 u64_stats_init(syncp: &sky2->tx_stats.syncp);
4610 u64_stats_init(syncp: &sky2->rx_stats.syncp);
4611
4612 /* Auto speed and flow control */
4613 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4614 if (hw->chip_id != CHIP_ID_YUKON_XL)
4615 dev->hw_features |= NETIF_F_RXCSUM;
4616
4617 sky2->flow_mode = FC_BOTH;
4618
4619 sky2->duplex = -1;
4620 sky2->speed = -1;
4621 sky2->advertising = sky2_supported_modes(hw);
4622 sky2->wol = wol;
4623
4624 spin_lock_init(&sky2->phy_lock);
4625
4626 sky2->tx_pending = TX_DEF_PENDING;
4627 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
4628 sky2->rx_pending = RX_DEF_PENDING;
4629
4630 hw->dev[port] = dev;
4631
4632 sky2->port = port;
4633
4634 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4635
4636 if (highmem)
4637 dev->features |= NETIF_F_HIGHDMA;
4638
4639 /* Enable receive hashing unless hardware is known broken */
4640 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4641 dev->hw_features |= NETIF_F_RXHASH;
4642
4643 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4644 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
4645 NETIF_F_HW_VLAN_CTAG_RX;
4646 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4647 }
4648
4649 dev->features |= dev->hw_features;
4650
4651 /* MTU range: 60 - 1500 or 9000 */
4652 dev->min_mtu = ETH_ZLEN;
4653 if (hw->chip_id == CHIP_ID_YUKON_FE ||
4654 hw->chip_id == CHIP_ID_YUKON_FE_P)
4655 dev->max_mtu = ETH_DATA_LEN;
4656 else
4657 dev->max_mtu = ETH_JUMBO_MTU;
4658
4659 /* try to get mac address in the following order:
4660 * 1) from device tree data
4661 * 2) from internal registers set by bootloader
4662 */
4663 ret = of_get_ethdev_address(np: hw->pdev->dev.of_node, dev);
4664 if (ret) {
4665 u8 addr[ETH_ALEN];
4666
4667 memcpy_fromio(addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4668 eth_hw_addr_set(dev, addr);
4669 }
4670
4671 /* if the address is invalid, use a random value */
4672 if (!is_valid_ether_addr(addr: dev->dev_addr)) {
4673 struct sockaddr sa = { AF_UNSPEC };
4674
4675 dev_warn(&hw->pdev->dev, "Invalid MAC address, defaulting to random\n");
4676 eth_hw_addr_random(dev);
4677 memcpy(to: sa.sa_data, from: dev->dev_addr, ETH_ALEN);
4678 if (sky2_set_mac_address(dev, p: &sa))
4679 dev_warn(&hw->pdev->dev, "Failed to set MAC address.\n");
4680 }
4681
4682 return dev;
4683}
4684
4685static void sky2_show_addr(struct net_device *dev)
4686{
4687 const struct sky2_port *sky2 = netdev_priv(dev);
4688
4689 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4690}
4691
4692/* Handle software interrupt used during MSI test */
4693static irqreturn_t sky2_test_intr(int irq, void *dev_id)
4694{
4695 struct sky2_hw *hw = dev_id;
4696 u32 status = sky2_read32(hw, reg: B0_Y2_SP_ISRC2);
4697
4698 if (status == 0)
4699 return IRQ_NONE;
4700
4701 if (status & Y2_IS_IRQ_SW) {
4702 hw->flags |= SKY2_HW_USE_MSI;
4703 wake_up(&hw->msi_wait);
4704 sky2_write8(hw, reg: B0_CTST, val: CS_CL_SW_IRQ);
4705 }
4706 sky2_write32(hw, reg: B0_Y2_SP_ICR, val: 2);
4707
4708 return IRQ_HANDLED;
4709}
4710
4711/* Test interrupt path by forcing a software IRQ */
4712static int sky2_test_msi(struct sky2_hw *hw)
4713{
4714 struct pci_dev *pdev = hw->pdev;
4715 int err;
4716
4717 init_waitqueue_head(&hw->msi_wait);
4718
4719 err = request_irq(irq: pdev->irq, handler: sky2_test_intr, flags: 0, DRV_NAME, dev: hw);
4720 if (err) {
4721 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4722 return err;
4723 }
4724
4725 sky2_write32(hw, reg: B0_IMSK, val: Y2_IS_IRQ_SW);
4726
4727 sky2_write8(hw, reg: B0_CTST, val: CS_ST_SW_IRQ);
4728 sky2_read8(hw, reg: B0_CTST);
4729
4730 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4731
4732 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4733 /* MSI test failed, go back to INTx mode */
4734 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4735 "switching to INTx mode.\n");
4736
4737 err = -EOPNOTSUPP;
4738 sky2_write8(hw, reg: B0_CTST, val: CS_CL_SW_IRQ);
4739 }
4740
4741 sky2_write32(hw, reg: B0_IMSK, val: 0);
4742 sky2_read32(hw, reg: B0_IMSK);
4743
4744 free_irq(pdev->irq, hw);
4745
4746 return err;
4747}
4748
4749/* This driver supports yukon2 chipset only */
4750static const char *sky2_name(u8 chipid, char *buf, int sz)
4751{
4752 static const char *const name[] = {
4753 "XL", /* 0xb3 */
4754 "EC Ultra", /* 0xb4 */
4755 "Extreme", /* 0xb5 */
4756 "EC", /* 0xb6 */
4757 "FE", /* 0xb7 */
4758 "FE+", /* 0xb8 */
4759 "Supreme", /* 0xb9 */
4760 "UL 2", /* 0xba */
4761 "Unknown", /* 0xbb */
4762 "Optima", /* 0xbc */
4763 "OptimaEEE", /* 0xbd */
4764 "Optima 2", /* 0xbe */
4765 };
4766
4767 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4768 snprintf(buf, size: sz, fmt: "%s", name[chipid - CHIP_ID_YUKON_XL]);
4769 else
4770 snprintf(buf, size: sz, fmt: "(chip %#x)", chipid);
4771 return buf;
4772}
4773
4774static const struct dmi_system_id msi_blacklist[] = {
4775 {
4776 .ident = "Dell Inspiron 1545",
4777 .matches = {
4778 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
4779 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 1545"),
4780 },
4781 },
4782 {
4783 .ident = "Gateway P-79",
4784 .matches = {
4785 DMI_MATCH(DMI_SYS_VENDOR, "Gateway"),
4786 DMI_MATCH(DMI_PRODUCT_NAME, "P-79"),
4787 },
4788 },
4789 {
4790 .ident = "ASUS P5W DH Deluxe",
4791 .matches = {
4792 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTEK COMPUTER INC"),
4793 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
4794 },
4795 },
4796 {
4797 .ident = "ASUS P6T",
4798 .matches = {
4799 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4800 DMI_MATCH(DMI_BOARD_NAME, "P6T"),
4801 },
4802 },
4803 {
4804 .ident = "ASUS P6X",
4805 .matches = {
4806 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4807 DMI_MATCH(DMI_BOARD_NAME, "P6X"),
4808 },
4809 },
4810 {}
4811};
4812
4813static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4814{
4815 struct net_device *dev, *dev1;
4816 struct sky2_hw *hw;
4817 int err, using_dac = 0, wol_default;
4818 u32 reg;
4819 char buf1[16];
4820
4821 err = pci_enable_device(dev: pdev);
4822 if (err) {
4823 dev_err(&pdev->dev, "cannot enable PCI device\n");
4824 goto err_out;
4825 }
4826
4827 /* Get configuration information
4828 * Note: only regular PCI config access once to test for HW issues
4829 * other PCI access through shared memory for speed and to
4830 * avoid MMCONFIG problems.
4831 */
4832 err = pci_read_config_dword(dev: pdev, where: PCI_DEV_REG2, val: &reg);
4833 if (err) {
4834 dev_err(&pdev->dev, "PCI read config failed\n");
4835 goto err_out_disable;
4836 }
4837
4838 if (~reg == 0) {
4839 dev_err(&pdev->dev, "PCI configuration read error\n");
4840 err = -EIO;
4841 goto err_out_disable;
4842 }
4843
4844 err = pci_request_regions(pdev, DRV_NAME);
4845 if (err) {
4846 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4847 goto err_out_disable;
4848 }
4849
4850 pci_set_master(dev: pdev);
4851
4852 if (sizeof(dma_addr_t) > sizeof(u32) &&
4853 !dma_set_mask(dev: &pdev->dev, DMA_BIT_MASK(64))) {
4854 using_dac = 1;
4855 err = dma_set_coherent_mask(dev: &pdev->dev, DMA_BIT_MASK(64));
4856 if (err < 0) {
4857 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4858 "for consistent allocations\n");
4859 goto err_out_free_regions;
4860 }
4861 } else {
4862 err = dma_set_mask(dev: &pdev->dev, DMA_BIT_MASK(32));
4863 if (err) {
4864 dev_err(&pdev->dev, "no usable DMA configuration\n");
4865 goto err_out_free_regions;
4866 }
4867 }
4868
4869
4870#ifdef __BIG_ENDIAN
4871 /* The sk98lin vendor driver uses hardware byte swapping but
4872 * this driver uses software swapping.
4873 */
4874 reg &= ~PCI_REV_DESC;
4875 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4876 if (err) {
4877 dev_err(&pdev->dev, "PCI write config failed\n");
4878 goto err_out_free_regions;
4879 }
4880#endif
4881
4882 wol_default = device_may_wakeup(dev: &pdev->dev) ? WAKE_MAGIC : 0;
4883
4884 err = -ENOMEM;
4885
4886 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4887 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4888 if (!hw)
4889 goto err_out_free_regions;
4890
4891 hw->pdev = pdev;
4892 sprintf(buf: hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4893
4894 hw->regs = ioremap(pci_resource_start(pdev, 0), size: 0x4000);
4895 if (!hw->regs) {
4896 dev_err(&pdev->dev, "cannot map device registers\n");
4897 goto err_out_free_hw;
4898 }
4899
4900 err = sky2_init(hw);
4901 if (err)
4902 goto err_out_iounmap;
4903
4904 /* ring for status responses */
4905 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4906 hw->st_le = dma_alloc_coherent(dev: &pdev->dev,
4907 size: hw->st_size * sizeof(struct sky2_status_le),
4908 dma_handle: &hw->st_dma, GFP_KERNEL);
4909 if (!hw->st_le) {
4910 err = -ENOMEM;
4911 goto err_out_reset;
4912 }
4913
4914 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4915 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4916
4917 sky2_reset(hw);
4918
4919 dev = sky2_init_netdev(hw, port: 0, highmem: using_dac, wol: wol_default);
4920 if (!dev) {
4921 err = -ENOMEM;
4922 goto err_out_free_pci;
4923 }
4924
4925 if (disable_msi == -1)
4926 disable_msi = !!dmi_check_system(list: msi_blacklist);
4927
4928 if (!disable_msi && pci_enable_msi(dev: pdev) == 0) {
4929 err = sky2_test_msi(hw);
4930 if (err) {
4931 pci_disable_msi(dev: pdev);
4932 if (err != -EOPNOTSUPP)
4933 goto err_out_free_netdev;
4934 }
4935 }
4936
4937 netif_napi_add(dev, napi: &hw->napi, poll: sky2_poll);
4938
4939 err = register_netdev(dev);
4940 if (err) {
4941 dev_err(&pdev->dev, "cannot register net device\n");
4942 goto err_out_free_netdev;
4943 }
4944
4945 netif_carrier_off(dev);
4946
4947 sky2_show_addr(dev);
4948
4949 if (hw->ports > 1) {
4950 dev1 = sky2_init_netdev(hw, port: 1, highmem: using_dac, wol: wol_default);
4951 if (!dev1) {
4952 err = -ENOMEM;
4953 goto err_out_unregister;
4954 }
4955
4956 err = register_netdev(dev: dev1);
4957 if (err) {
4958 dev_err(&pdev->dev, "cannot register second net device\n");
4959 goto err_out_free_dev1;
4960 }
4961
4962 err = sky2_setup_irq(hw, name: hw->irq_name);
4963 if (err)
4964 goto err_out_unregister_dev1;
4965
4966 sky2_show_addr(dev: dev1);
4967 }
4968
4969 timer_setup(&hw->watchdog_timer, sky2_watchdog, 0);
4970 INIT_WORK(&hw->restart_work, sky2_restart);
4971
4972 pci_set_drvdata(pdev, data: hw);
4973 pdev->d3hot_delay = 300;
4974
4975 return 0;
4976
4977err_out_unregister_dev1:
4978 unregister_netdev(dev: dev1);
4979err_out_free_dev1:
4980 free_netdev(dev: dev1);
4981err_out_unregister:
4982 unregister_netdev(dev);
4983err_out_free_netdev:
4984 if (hw->flags & SKY2_HW_USE_MSI)
4985 pci_disable_msi(dev: pdev);
4986 free_netdev(dev);
4987err_out_free_pci:
4988 dma_free_coherent(dev: &pdev->dev,
4989 size: hw->st_size * sizeof(struct sky2_status_le),
4990 cpu_addr: hw->st_le, dma_handle: hw->st_dma);
4991err_out_reset:
4992 sky2_write8(hw, reg: B0_CTST, val: CS_RST_SET);
4993err_out_iounmap:
4994 iounmap(addr: hw->regs);
4995err_out_free_hw:
4996 kfree(objp: hw);
4997err_out_free_regions:
4998 pci_release_regions(pdev);
4999err_out_disable:
5000 pci_disable_device(dev: pdev);
5001err_out:
5002 return err;
5003}
5004
5005static void sky2_remove(struct pci_dev *pdev)
5006{
5007 struct sky2_hw *hw = pci_get_drvdata(pdev);
5008 int i;
5009
5010 if (!hw)
5011 return;
5012
5013 timer_shutdown_sync(timer: &hw->watchdog_timer);
5014 cancel_work_sync(work: &hw->restart_work);
5015
5016 for (i = hw->ports-1; i >= 0; --i)
5017 unregister_netdev(dev: hw->dev[i]);
5018
5019 sky2_write32(hw, reg: B0_IMSK, val: 0);
5020 sky2_read32(hw, reg: B0_IMSK);
5021
5022 sky2_power_aux(hw);
5023
5024 sky2_write8(hw, reg: B0_CTST, val: CS_RST_SET);
5025 sky2_read8(hw, reg: B0_CTST);
5026
5027 if (hw->ports > 1) {
5028 napi_disable(n: &hw->napi);
5029 free_irq(pdev->irq, hw);
5030 }
5031
5032 if (hw->flags & SKY2_HW_USE_MSI)
5033 pci_disable_msi(dev: pdev);
5034 dma_free_coherent(dev: &pdev->dev,
5035 size: hw->st_size * sizeof(struct sky2_status_le),
5036 cpu_addr: hw->st_le, dma_handle: hw->st_dma);
5037 pci_release_regions(pdev);
5038 pci_disable_device(dev: pdev);
5039
5040 for (i = hw->ports-1; i >= 0; --i)
5041 free_netdev(dev: hw->dev[i]);
5042
5043 iounmap(addr: hw->regs);
5044 kfree(objp: hw);
5045}
5046
5047static int sky2_suspend(struct device *dev)
5048{
5049 struct sky2_hw *hw = dev_get_drvdata(dev);
5050 int i;
5051
5052 if (!hw)
5053 return 0;
5054
5055 timer_delete_sync(timer: &hw->watchdog_timer);
5056 cancel_work_sync(work: &hw->restart_work);
5057
5058 rtnl_lock();
5059
5060 sky2_all_down(hw);
5061 for (i = 0; i < hw->ports; i++) {
5062 struct net_device *dev = hw->dev[i];
5063 struct sky2_port *sky2 = netdev_priv(dev);
5064
5065 if (sky2->wol)
5066 sky2_wol_init(sky2);
5067 }
5068
5069 sky2_power_aux(hw);
5070 rtnl_unlock();
5071
5072 return 0;
5073}
5074
5075#ifdef CONFIG_PM_SLEEP
5076static int sky2_resume(struct device *dev)
5077{
5078 struct pci_dev *pdev = to_pci_dev(dev);
5079 struct sky2_hw *hw = pci_get_drvdata(pdev);
5080 int err;
5081
5082 if (!hw)
5083 return 0;
5084
5085 /* Re-enable all clocks */
5086 err = pci_write_config_dword(dev: pdev, where: PCI_DEV_REG3, val: 0);
5087 if (err) {
5088 dev_err(&pdev->dev, "PCI write config failed\n");
5089 goto out;
5090 }
5091
5092 rtnl_lock();
5093 sky2_reset(hw);
5094 sky2_all_up(hw);
5095 rtnl_unlock();
5096
5097 return 0;
5098out:
5099
5100 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5101 pci_disable_device(dev: pdev);
5102 return err;
5103}
5104
5105static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5106#define SKY2_PM_OPS (&sky2_pm_ops)
5107
5108#else
5109
5110#define SKY2_PM_OPS NULL
5111#endif
5112
5113static void sky2_shutdown(struct pci_dev *pdev)
5114{
5115 struct sky2_hw *hw = pci_get_drvdata(pdev);
5116 int port;
5117
5118 for (port = 0; port < hw->ports; port++) {
5119 struct net_device *ndev = hw->dev[port];
5120
5121 rtnl_lock();
5122 if (netif_running(dev: ndev)) {
5123 dev_close(dev: ndev);
5124 netif_device_detach(dev: ndev);
5125 }
5126 rtnl_unlock();
5127 }
5128 sky2_suspend(dev: &pdev->dev);
5129 pci_wake_from_d3(dev: pdev, enable: device_may_wakeup(dev: &pdev->dev));
5130 pci_set_power_state(dev: pdev, PCI_D3hot);
5131}
5132
5133static struct pci_driver sky2_driver = {
5134 .name = DRV_NAME,
5135 .id_table = sky2_id_table,
5136 .probe = sky2_probe,
5137 .remove = sky2_remove,
5138 .shutdown = sky2_shutdown,
5139 .driver.pm = SKY2_PM_OPS,
5140};
5141
5142static int __init sky2_init_module(void)
5143{
5144 pr_info("driver version " DRV_VERSION "\n");
5145
5146 sky2_debug_init();
5147 return pci_register_driver(&sky2_driver);
5148}
5149
5150static void __exit sky2_cleanup_module(void)
5151{
5152 pci_unregister_driver(dev: &sky2_driver);
5153 sky2_debug_cleanup();
5154}
5155
5156module_init(sky2_init_module);
5157module_exit(sky2_cleanup_module);
5158
5159MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5160MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5161MODULE_LICENSE("GPL");
5162MODULE_VERSION(DRV_VERSION);
5163