1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (c) 2001-2002 by David Brownell
4 */
5
6#ifndef __LINUX_EHCI_HCD_H
7#define __LINUX_EHCI_HCD_H
8
9/* definitions used for the EHCI driver */
10
11/*
12 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
13 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
14 * the host controller implementation.
15 *
16 * To facilitate the strongest possible byte-order checking from "sparse"
17 * and so on, we use __leXX unless that's not practical.
18 */
19#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
20typedef __u32 __bitwise __hc32;
21typedef __u16 __bitwise __hc16;
22#else
23#define __hc32 __le32
24#define __hc16 __le16
25#endif
26
27/* statistics can be kept for tuning/monitoring */
28#ifdef CONFIG_DYNAMIC_DEBUG
29#define EHCI_STATS
30#endif
31
32struct ehci_stats {
33 /* irq usage */
34 unsigned long normal;
35 unsigned long error;
36 unsigned long iaa;
37 unsigned long lost_iaa;
38
39 /* termination of urbs from core */
40 unsigned long complete;
41 unsigned long unlink;
42};
43
44/*
45 * Scheduling and budgeting information for periodic transfers, for both
46 * high-speed devices and full/low-speed devices lying behind a TT.
47 */
48struct ehci_per_sched {
49 struct usb_device *udev; /* access to the TT */
50 struct usb_host_endpoint *ep;
51 struct list_head ps_list; /* node on ehci_tt's ps_list */
52 u16 tt_usecs; /* time on the FS/LS bus */
53 u16 cs_mask; /* C-mask and S-mask bytes */
54 u16 period; /* actual period in frames */
55 u16 phase; /* actual phase, frame part */
56 u8 bw_phase; /* same, for bandwidth
57 reservation */
58 u8 phase_uf; /* uframe part of the phase */
59 u8 usecs, c_usecs; /* times on the HS bus */
60 u8 bw_uperiod; /* period in microframes, for
61 bandwidth reservation */
62 u8 bw_period; /* same, in frames */
63};
64#define NO_FRAME 29999 /* frame not assigned yet */
65
66/* ehci_hcd->lock guards shared data against other CPUs:
67 * ehci_hcd: async, unlink, periodic (and shadow), ...
68 * usb_host_endpoint: hcpriv
69 * ehci_qh: qh_next, qtd_list
70 * ehci_qtd: qtd_list
71 *
72 * Also, hold this lock when talking to HC registers or
73 * when updating hw_* fields in shared qh/qtd/... structures.
74 */
75
76#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
77
78/*
79 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
80 * controller may be doing DMA. Lower values mean there's no DMA.
81 */
82enum ehci_rh_state {
83 EHCI_RH_HALTED,
84 EHCI_RH_SUSPENDED,
85 EHCI_RH_RUNNING,
86 EHCI_RH_STOPPING
87};
88
89/*
90 * Timer events, ordered by increasing delay length.
91 * Always update event_delays_ns[] and event_handlers[] (defined in
92 * ehci-timer.c) in parallel with this list.
93 */
94enum ehci_hrtimer_event {
95 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */
96 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
97 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
98 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
99 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
100 EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */
101 EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
102 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
103 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
104 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
105 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
106 EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
107 EHCI_HRTIMER_NUM_EVENTS /* Must come last */
108};
109#define EHCI_HRTIMER_NO_EVENT 99
110
111struct ehci_hcd { /* one per controller */
112 /* timing support */
113 enum ehci_hrtimer_event next_hrtimer_event;
114 unsigned enabled_hrtimer_events;
115 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
116 struct hrtimer hrtimer;
117
118 int PSS_poll_count;
119 int ASS_poll_count;
120 int died_poll_count;
121
122 /* glue to PCI and HCD framework */
123 struct ehci_caps __iomem *caps;
124 struct ehci_regs __iomem *regs;
125 struct ehci_dbg_port __iomem *debug;
126
127 __u32 hcs_params; /* cached register copy */
128 spinlock_t lock;
129 enum ehci_rh_state rh_state;
130
131 /* general schedule support */
132 bool scanning:1;
133 bool need_rescan:1;
134 bool intr_unlinking:1;
135 bool iaa_in_progress:1;
136 bool async_unlinking:1;
137 bool shutdown:1;
138 struct ehci_qh *qh_scan_next;
139
140 /* async schedule support */
141 struct ehci_qh *async;
142 struct ehci_qh *dummy; /* For AMD quirk use */
143 struct list_head async_unlink;
144 struct list_head async_idle;
145 unsigned async_unlink_cycle;
146 unsigned async_count; /* async activity count */
147 __hc32 old_current; /* Test for QH becoming */
148 __hc32 old_token; /* inactive during unlink */
149
150 /* periodic schedule support */
151#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
152 unsigned periodic_size;
153 __hc32 *periodic; /* hw periodic table */
154 dma_addr_t periodic_dma;
155 struct list_head intr_qh_list;
156 unsigned i_thresh; /* uframes HC might cache */
157
158 union ehci_shadow *pshadow; /* mirror hw periodic table */
159 struct list_head intr_unlink_wait;
160 struct list_head intr_unlink;
161 unsigned intr_unlink_wait_cycle;
162 unsigned intr_unlink_cycle;
163 unsigned now_frame; /* frame from HC hardware */
164 unsigned last_iso_frame; /* last frame scanned for iso */
165 unsigned intr_count; /* intr activity count */
166 unsigned isoc_count; /* isoc activity count */
167 unsigned periodic_count; /* periodic activity count */
168 unsigned uframe_periodic_max; /* max periodic time per uframe */
169
170
171 /* list of itds & sitds completed while now_frame was still active */
172 struct list_head cached_itd_list;
173 struct ehci_itd *last_itd_to_free;
174 struct list_head cached_sitd_list;
175 struct ehci_sitd *last_sitd_to_free;
176
177 /* per root hub port */
178 unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
179
180 /* bit vectors (one bit per port) */
181 unsigned long bus_suspended; /* which ports were
182 already suspended at the start of a bus suspend */
183 unsigned long companion_ports; /* which ports are
184 dedicated to the companion controller */
185 unsigned long owned_ports; /* which ports are
186 owned by the companion during a bus suspend */
187 unsigned long port_c_suspend; /* which ports have
188 the change-suspend feature turned on */
189 unsigned long suspended_ports; /* which ports are
190 suspended */
191 unsigned long resuming_ports; /* which ports have
192 started to resume */
193
194 /* per-HC memory pools (could be per-bus, but ...) */
195 struct dma_pool *qh_pool; /* qh per active urb */
196 struct dma_pool *qtd_pool; /* one or more per qh */
197 struct dma_pool *itd_pool; /* itd per iso urb */
198 struct dma_pool *sitd_pool; /* sitd per split iso urb */
199
200 unsigned random_frame;
201 unsigned long next_statechange;
202 ktime_t last_periodic_enable;
203 u32 command;
204
205 /* SILICON QUIRKS */
206 unsigned no_selective_suspend:1;
207 unsigned has_fsl_port_bug:1; /* FreeScale */
208 unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */
209 unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */
210 unsigned has_ci_pec_bug:1; /* ChipIdea PEC bug */
211 unsigned big_endian_mmio:1;
212 unsigned big_endian_desc:1;
213 unsigned big_endian_capbase:1;
214 unsigned has_amcc_usb23:1;
215 unsigned need_io_watchdog:1;
216 unsigned amd_pll_fix:1;
217 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
218 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
219 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
220 unsigned need_oc_pp_cycle:1; /* MPC834X port power */
221 unsigned imx28_write_fix:1; /* For Freescale i.MX28 */
222 unsigned spurious_oc:1;
223 unsigned is_aspeed:1;
224 unsigned zx_wakeup_clear_needed:1;
225
226 /* required for usb32 quirk */
227 #define OHCI_CTRL_HCFS (3 << 6)
228 #define OHCI_USB_OPER (2 << 6)
229 #define OHCI_USB_SUSPEND (3 << 6)
230
231 #define OHCI_HCCTRL_OFFSET 0x4
232 #define OHCI_HCCTRL_LEN 0x4
233 __hc32 *ohci_hcctrl_reg;
234 unsigned has_hostpc:1;
235 unsigned has_tdi_phy_lpm:1;
236 unsigned has_ppcd:1; /* support per-port change bits */
237 u8 sbrn; /* packed release number */
238
239 /* irq statistics */
240#ifdef EHCI_STATS
241 struct ehci_stats stats;
242# define INCR(x) ((x)++)
243#else
244# define INCR(x) do {} while (0)
245#endif
246
247 /* debug files */
248#ifdef CONFIG_DYNAMIC_DEBUG
249 struct dentry *debug_dir;
250#endif
251
252 /* bandwidth usage */
253#define EHCI_BANDWIDTH_SIZE 64
254#define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3)
255 u8 bandwidth[EHCI_BANDWIDTH_SIZE];
256 /* us allocated per uframe */
257 u8 tt_budget[EHCI_BANDWIDTH_SIZE];
258 /* us budgeted per uframe */
259 struct list_head tt_list;
260
261 /* platform-specific data -- must come last */
262 unsigned long priv[] __aligned(sizeof(s64));
263};
264
265/* convert between an HCD pointer and the corresponding EHCI_HCD */
266static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
267{
268 return (struct ehci_hcd *) (hcd->hcd_priv);
269}
270static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
271{
272 return container_of((void *) ehci, struct usb_hcd, hcd_priv);
273}
274
275/*-------------------------------------------------------------------------*/
276
277#include <linux/usb/ehci_def.h>
278
279/*-------------------------------------------------------------------------*/
280
281#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
282
283/*
284 * EHCI Specification 0.95 Section 3.5
285 * QTD: describe data transfer components (buffer, direction, ...)
286 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
287 *
288 * These are associated only with "QH" (Queue Head) structures,
289 * used with control, bulk, and interrupt transfers.
290 */
291struct ehci_qtd {
292 /* first part defined by EHCI spec */
293 __hc32 hw_next; /* see EHCI 3.5.1 */
294 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
295 __hc32 hw_token; /* see EHCI 3.5.3 */
296#define QTD_TOGGLE (1 << 31) /* data toggle */
297#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
298#define QTD_IOC (1 << 15) /* interrupt on complete */
299#define QTD_CERR(tok) (((tok)>>10) & 0x3)
300#define QTD_PID(tok) (((tok)>>8) & 0x3)
301#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
302#define QTD_STS_HALT (1 << 6) /* halted on error */
303#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
304#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
305#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
306#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
307#define QTD_STS_STS (1 << 1) /* split transaction state */
308#define QTD_STS_PING (1 << 0) /* issue PING? */
309
310#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
311#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
312#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
313
314 __hc32 hw_buf[5]; /* see EHCI 3.5.4 */
315 __hc32 hw_buf_hi[5]; /* Appendix B */
316
317 /* the rest is HCD-private */
318 dma_addr_t qtd_dma; /* qtd address */
319 struct list_head qtd_list; /* sw qtd list */
320 struct urb *urb; /* qtd's urb */
321 size_t length; /* length of buffer */
322} __aligned(32);
323
324/* PID Codes that are used here, from EHCI specification, Table 3-16. */
325#define PID_CODE_OUT 0
326#define PID_CODE_IN 1
327#define PID_CODE_SETUP 2
328
329/* mask NakCnt+T in qh->hw_alt_next */
330#define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f)
331
332#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && \
333 QTD_PID(token) == PID_CODE_IN)
334
335/*-------------------------------------------------------------------------*/
336
337/* type tag from {qh,itd,sitd,fstn}->hw_next */
338#define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
339
340/*
341 * Now the following defines are not converted using the
342 * cpu_to_le32() macro anymore, since we have to support
343 * "dynamic" switching between be and le support, so that the driver
344 * can be used on one system with SoC EHCI controller using big-endian
345 * descriptors as well as a normal little-endian PCI EHCI controller.
346 */
347/* values for that type tag */
348#define Q_TYPE_ITD (0 << 1)
349#define Q_TYPE_QH (1 << 1)
350#define Q_TYPE_SITD (2 << 1)
351#define Q_TYPE_FSTN (3 << 1)
352
353/* next async queue entry, or pointer to interrupt/periodic QH */
354#define QH_NEXT(ehci, dma) \
355 (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
356
357/* for periodic/async schedules and qtd lists, mark end of list */
358#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
359
360/*
361 * Entries in periodic shadow table are pointers to one of four kinds
362 * of data structure. That's dictated by the hardware; a type tag is
363 * encoded in the low bits of the hardware's periodic schedule. Use
364 * Q_NEXT_TYPE to get the tag.
365 *
366 * For entries in the async schedule, the type tag always says "qh".
367 */
368union ehci_shadow {
369 struct ehci_qh *qh; /* Q_TYPE_QH */
370 struct ehci_itd *itd; /* Q_TYPE_ITD */
371 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
372 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
373 __hc32 *hw_next; /* (all types) */
374 void *ptr;
375};
376
377/*-------------------------------------------------------------------------*/
378
379/*
380 * EHCI Specification 0.95 Section 3.6
381 * QH: describes control/bulk/interrupt endpoints
382 * See Fig 3-7 "Queue Head Structure Layout".
383 *
384 * These appear in both the async and (for interrupt) periodic schedules.
385 */
386
387/* first part defined by EHCI spec */
388struct ehci_qh_hw {
389 __hc32 hw_next; /* see EHCI 3.6.1 */
390 __hc32 hw_info1; /* see EHCI 3.6.2 */
391#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
392#define QH_HEAD (1 << 15) /* Head of async reclamation list */
393#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
394#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
395#define QH_LOW_SPEED (1 << 12)
396#define QH_FULL_SPEED (0 << 12)
397#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
398 __hc32 hw_info2; /* see EHCI 3.6.2 */
399#define QH_SMASK 0x000000ff
400#define QH_CMASK 0x0000ff00
401#define QH_HUBADDR 0x007f0000
402#define QH_HUBPORT 0x3f800000
403#define QH_MULT 0xc0000000
404 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
405
406 /* qtd overlay (hardware parts of a struct ehci_qtd) */
407 __hc32 hw_qtd_next;
408 __hc32 hw_alt_next;
409 __hc32 hw_token;
410 __hc32 hw_buf[5];
411 __hc32 hw_buf_hi[5];
412} __aligned(32);
413
414struct ehci_qh {
415 struct ehci_qh_hw *hw; /* Must come first */
416 /* the rest is HCD-private */
417 dma_addr_t qh_dma; /* address of qh */
418 union ehci_shadow qh_next; /* ptr to qh; or periodic */
419 struct list_head qtd_list; /* sw qtd list */
420 struct list_head intr_node; /* list of intr QHs */
421 struct ehci_qtd *dummy;
422 struct list_head unlink_node;
423 struct ehci_per_sched ps; /* scheduling info */
424
425 unsigned unlink_cycle;
426
427 u8 qh_state;
428#define QH_STATE_LINKED 1 /* HC sees this */
429#define QH_STATE_UNLINK 2 /* HC may still see this */
430#define QH_STATE_IDLE 3 /* HC doesn't see this */
431#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
432#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
433
434 u8 xacterrs; /* XactErr retry counter */
435#define QH_XACTERR_MAX 32 /* XactErr retry limit */
436
437 u8 unlink_reason;
438#define QH_UNLINK_HALTED 0x01 /* Halt flag is set */
439#define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */
440#define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */
441#define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */
442#define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */
443#define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */
444
445 u8 gap_uf; /* uframes split/csplit gap */
446
447 unsigned is_out:1; /* bulk or intr OUT */
448 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
449 unsigned dequeue_during_giveback:1;
450 unsigned should_be_inactive:1;
451};
452
453/*-------------------------------------------------------------------------*/
454
455/* description of one iso transaction (up to 3 KB data if highspeed) */
456struct ehci_iso_packet {
457 /* These will be copied to iTD when scheduling */
458 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
459 __hc32 transaction; /* itd->hw_transaction[i] |= */
460 u8 cross; /* buf crosses pages */
461 /* for full speed OUT splits */
462 u32 buf1;
463};
464
465/* temporary schedule data for packets from iso urbs (both speeds)
466 * each packet is one logical usb transaction to the device (not TT),
467 * beginning at stream->next_uframe
468 */
469struct ehci_iso_sched {
470 struct list_head td_list;
471 unsigned span;
472 unsigned first_packet;
473 struct ehci_iso_packet packet[];
474};
475
476/*
477 * ehci_iso_stream - groups all (s)itds for this endpoint.
478 * acts like a qh would, if EHCI had them for ISO.
479 */
480struct ehci_iso_stream {
481 /* first field matches ehci_qh, but is NULL */
482 struct ehci_qh_hw *hw;
483
484 u8 bEndpointAddress;
485 u8 highspeed;
486 struct list_head td_list; /* queued itds/sitds */
487 struct list_head free_list; /* list of unused itds/sitds */
488
489 /* output of (re)scheduling */
490 struct ehci_per_sched ps; /* scheduling info */
491 unsigned next_uframe;
492 __hc32 splits;
493
494 /* the rest is derived from the endpoint descriptor,
495 * including the extra info for hw_bufp[0..2]
496 */
497 u16 uperiod; /* period in uframes */
498 u16 maxp;
499 unsigned bandwidth;
500
501 /* This is used to initialize iTD's hw_bufp fields */
502 __hc32 buf0;
503 __hc32 buf1;
504 __hc32 buf2;
505
506 /* this is used to initialize sITD's tt info */
507 __hc32 address;
508};
509
510/*-------------------------------------------------------------------------*/
511
512/*
513 * EHCI Specification 0.95 Section 3.3
514 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
515 *
516 * Schedule records for high speed iso xfers
517 */
518struct ehci_itd {
519 /* first part defined by EHCI spec */
520 __hc32 hw_next; /* see EHCI 3.3.1 */
521 __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
522#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
523#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
524#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
525#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
526#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
527#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
528
529#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
530
531 __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
532 __hc32 hw_bufp_hi[7]; /* Appendix B */
533
534 /* the rest is HCD-private */
535 dma_addr_t itd_dma; /* for this itd */
536 union ehci_shadow itd_next; /* ptr to periodic q entry */
537
538 struct urb *urb;
539 struct ehci_iso_stream *stream; /* endpoint's queue */
540 struct list_head itd_list; /* list of stream's itds */
541
542 /* any/all hw_transactions here may be used by that urb */
543 unsigned frame; /* where scheduled */
544 unsigned pg;
545 unsigned index[8]; /* in urb->iso_frame_desc */
546} __aligned(32);
547
548/*-------------------------------------------------------------------------*/
549
550/*
551 * EHCI Specification 0.95 Section 3.4
552 * siTD, aka split-transaction isochronous Transfer Descriptor
553 * ... describe full speed iso xfers through TT in hubs
554 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
555 */
556struct ehci_sitd {
557 /* first part defined by EHCI spec */
558 __hc32 hw_next;
559/* uses bit field macros above - see EHCI 0.95 Table 3-8 */
560 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
561 __hc32 hw_uframe; /* EHCI table 3-10 */
562 __hc32 hw_results; /* EHCI table 3-11 */
563#define SITD_IOC (1 << 31) /* interrupt on completion */
564#define SITD_PAGE (1 << 30) /* buffer 0/1 */
565#define SITD_LENGTH(x) (((x) >> 16) & 0x3ff)
566#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
567#define SITD_STS_ERR (1 << 6) /* error from TT */
568#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
569#define SITD_STS_BABBLE (1 << 4) /* device was babbling */
570#define SITD_STS_XACT (1 << 3) /* illegal IN response */
571#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
572#define SITD_STS_STS (1 << 1) /* split transaction state */
573
574#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
575
576 __hc32 hw_buf[2]; /* EHCI table 3-12 */
577 __hc32 hw_backpointer; /* EHCI table 3-13 */
578 __hc32 hw_buf_hi[2]; /* Appendix B */
579
580 /* the rest is HCD-private */
581 dma_addr_t sitd_dma;
582 union ehci_shadow sitd_next; /* ptr to periodic q entry */
583
584 struct urb *urb;
585 struct ehci_iso_stream *stream; /* endpoint's queue */
586 struct list_head sitd_list; /* list of stream's sitds */
587 unsigned frame;
588 unsigned index;
589} __aligned(32);
590
591/*-------------------------------------------------------------------------*/
592
593/*
594 * EHCI Specification 0.96 Section 3.7
595 * Periodic Frame Span Traversal Node (FSTN)
596 *
597 * Manages split interrupt transactions (using TT) that span frame boundaries
598 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
599 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
600 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
601 */
602struct ehci_fstn {
603 __hc32 hw_next; /* any periodic q entry */
604 __hc32 hw_prev; /* qh or EHCI_LIST_END */
605
606 /* the rest is HCD-private */
607 dma_addr_t fstn_dma;
608 union ehci_shadow fstn_next; /* ptr to periodic q entry */
609} __aligned(32);
610
611/*-------------------------------------------------------------------------*/
612
613/*
614 * USB-2.0 Specification Sections 11.14 and 11.18
615 * Scheduling and budgeting split transactions using TTs
616 *
617 * A hub can have a single TT for all its ports, or multiple TTs (one for each
618 * port). The bandwidth and budgeting information for the full/low-speed bus
619 * below each TT is self-contained and independent of the other TTs or the
620 * high-speed bus.
621 *
622 * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
623 * to an interrupt or isochronous endpoint for each frame. "Budget" refers to
624 * the best-case estimate of the number of full-speed bytes allocated to an
625 * endpoint for each microframe within an allocated frame.
626 *
627 * Removal of an endpoint invalidates a TT's budget. Instead of trying to
628 * keep an up-to-date record, we recompute the budget when it is needed.
629 */
630
631struct ehci_tt {
632 u16 bandwidth[EHCI_BANDWIDTH_FRAMES];
633
634 struct list_head tt_list; /* List of all ehci_tt's */
635 struct list_head ps_list; /* Items using this TT */
636 struct usb_tt *usb_tt;
637 int tt_port; /* TT port number */
638};
639
640/*-------------------------------------------------------------------------*/
641
642/* Prepare the PORTSC wakeup flags during controller suspend/resume */
643
644#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
645 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
646
647#define ehci_prepare_ports_for_controller_resume(ehci) \
648 ehci_adjust_port_wakeup_flags(ehci, false, false)
649
650/*-------------------------------------------------------------------------*/
651
652#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
653
654/*
655 * Some EHCI controllers have a Transaction Translator built into the
656 * root hub. This is a non-standard feature. Each controller will need
657 * to add code to the following inline functions, and call them as
658 * needed (mostly in root hub code).
659 */
660
661#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
662
663/* Returns the speed of a device attached to a port on the root hub. */
664static inline unsigned int
665ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
666{
667 if (ehci_is_TDI(ehci)) {
668 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
669 case 0:
670 return 0;
671 case 1:
672 return USB_PORT_STAT_LOW_SPEED;
673 case 2:
674 default:
675 return USB_PORT_STAT_HIGH_SPEED;
676 }
677 }
678 return USB_PORT_STAT_HIGH_SPEED;
679}
680
681#else
682
683#define ehci_is_TDI(e) (0)
684
685#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
686#endif
687
688/*-------------------------------------------------------------------------*/
689
690#ifdef CONFIG_PPC_83xx
691/* Some Freescale processors have an erratum in which the TT
692 * port number in the queue head was 0..N-1 instead of 1..N.
693 */
694#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
695#else
696#define ehci_has_fsl_portno_bug(e) (0)
697#endif
698
699#define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */
700
701#if defined(CONFIG_PPC_85xx)
702/* Some Freescale processors have an erratum (USB A-005275) in which
703 * incoming packets get corrupted in HS mode
704 */
705#define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
706#else
707#define ehci_has_fsl_hs_errata(e) (0)
708#endif
709
710/*
711 * Some Freescale/NXP processors have an erratum (USB A-005697)
712 * in which we need to wait for 10ms for bus to enter suspend mode
713 * after setting SUSP bit.
714 */
715#define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
716
717/*
718 * Some Freescale/NXP processors using ChipIdea IP have a bug in which
719 * disabling the port (PE is cleared) does not cause PEC to be asserted
720 * when frame babble is detected.
721 */
722#define ehci_has_ci_pec_bug(e, portsc) \
723 ((e)->has_ci_pec_bug && ((e)->command & CMD_PSE) \
724 && !(portsc & PORT_PEC) && !(portsc & PORT_PE))
725
726/*
727 * While most USB host controllers implement their registers in
728 * little-endian format, a minority (celleb companion chip) implement
729 * them in big endian format.
730 *
731 * This attempts to support either format at compile time without a
732 * runtime penalty, or both formats with the additional overhead
733 * of checking a flag bit.
734 *
735 * ehci_big_endian_capbase is a special quirk for controllers that
736 * implement the HC capability registers as separate registers and not
737 * as fields of a 32-bit register.
738 */
739
740#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
741#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
742#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
743#else
744#define ehci_big_endian_mmio(e) 0
745#define ehci_big_endian_capbase(e) 0
746#endif
747
748/*
749 * Big-endian read/write functions are arch-specific.
750 * Other arches can be added if/when they're needed.
751 */
752#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
753#define readl_be(addr) __raw_readl((__force unsigned *)addr)
754#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
755#endif
756
757static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
758 __u32 __iomem *regs)
759{
760#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
761 return ehci_big_endian_mmio(ehci) ?
762 readl_be(regs) :
763 readl(regs);
764#else
765 return readl(addr: regs);
766#endif
767}
768
769#ifdef CONFIG_SOC_IMX28
770static inline void imx28_ehci_writel(const unsigned int val,
771 volatile __u32 __iomem *addr)
772{
773 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
774}
775#else
776static inline void imx28_ehci_writel(const unsigned int val,
777 volatile __u32 __iomem *addr)
778{
779}
780#endif
781static inline void ehci_writel(const struct ehci_hcd *ehci,
782 const unsigned int val, __u32 __iomem *regs)
783{
784#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
785 ehci_big_endian_mmio(ehci) ?
786 writel_be(val, regs) :
787 writel(val, regs);
788#else
789 if (ehci->imx28_write_fix)
790 imx28_ehci_writel(val, addr: regs);
791 else
792 writel(val, addr: regs);
793#endif
794}
795
796/*
797 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
798 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
799 * Other common bits are dependent on has_amcc_usb23 quirk flag.
800 */
801#ifdef CONFIG_44x
802static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
803{
804 u32 hc_control;
805
806 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
807 if (operational)
808 hc_control |= OHCI_USB_OPER;
809 else
810 hc_control |= OHCI_USB_SUSPEND;
811
812 writel_be(hc_control, ehci->ohci_hcctrl_reg);
813 (void) readl_be(ehci->ohci_hcctrl_reg);
814}
815#else
816static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
817{ }
818#endif
819
820/*-------------------------------------------------------------------------*/
821
822/*
823 * The AMCC 440EPx not only implements its EHCI registers in big-endian
824 * format, but also its DMA data structures (descriptors).
825 *
826 * EHCI controllers accessed through PCI work normally (little-endian
827 * everywhere), so we won't bother supporting a BE-only mode for now.
828 */
829#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
830#define ehci_big_endian_desc(e) ((e)->big_endian_desc)
831
832/* cpu to ehci */
833static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
834{
835 return ehci_big_endian_desc(ehci)
836 ? (__force __hc32)cpu_to_be32(x)
837 : (__force __hc32)cpu_to_le32(x);
838}
839
840/* ehci to cpu */
841static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
842{
843 return ehci_big_endian_desc(ehci)
844 ? be32_to_cpu((__force __be32)x)
845 : le32_to_cpu((__force __le32)x);
846}
847
848static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
849{
850 return ehci_big_endian_desc(ehci)
851 ? be32_to_cpup((__force __be32 *)x)
852 : le32_to_cpup((__force __le32 *)x);
853}
854
855#else
856
857/* cpu to ehci */
858static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
859{
860 return cpu_to_le32(x);
861}
862
863/* ehci to cpu */
864static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
865{
866 return le32_to_cpu(x);
867}
868
869static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
870{
871 return le32_to_cpup(p: x);
872}
873
874#endif
875
876/*-------------------------------------------------------------------------*/
877
878#define ehci_dbg(ehci, fmt, args...) \
879 dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
880#define ehci_err(ehci, fmt, args...) \
881 dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
882#define ehci_info(ehci, fmt, args...) \
883 dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
884#define ehci_warn(ehci, fmt, args...) \
885 dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
886
887/*-------------------------------------------------------------------------*/
888
889/* Declarations of things exported for use by ehci platform drivers */
890
891struct ehci_driver_overrides {
892 size_t extra_priv_size;
893 int (*reset)(struct usb_hcd *hcd);
894 int (*port_power)(struct usb_hcd *hcd,
895 int portnum, bool enable);
896};
897
898extern void ehci_init_driver(struct hc_driver *drv,
899 const struct ehci_driver_overrides *over);
900extern int ehci_setup(struct usb_hcd *hcd);
901extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
902 u32 mask, u32 done, int usec);
903extern int ehci_reset(struct ehci_hcd *ehci);
904
905extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
906extern int ehci_resume(struct usb_hcd *hcd, bool force_reset);
907extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
908 bool suspending, bool do_wakeup);
909
910extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
911 u16 wIndex, char *buf, u16 wLength);
912
913#endif /* __LINUX_EHCI_HCD_H */
914