1// SPDX-License-Identifier: GPL-2.0-only
2/* cpu_feature_enabled() cannot be used this early */
3#define USE_EARLY_PGTABLE_L5
4
5#include <linux/memblock.h>
6#include <linux/linkage.h>
7#include <linux/bitops.h>
8#include <linux/kernel.h>
9#include <linux/export.h>
10#include <linux/percpu.h>
11#include <linux/string.h>
12#include <linux/ctype.h>
13#include <linux/delay.h>
14#include <linux/sched/mm.h>
15#include <linux/sched/clock.h>
16#include <linux/sched/task.h>
17#include <linux/sched/smt.h>
18#include <linux/init.h>
19#include <linux/kprobes.h>
20#include <linux/kgdb.h>
21#include <linux/mem_encrypt.h>
22#include <linux/smp.h>
23#include <linux/cpu.h>
24#include <linux/io.h>
25#include <linux/syscore_ops.h>
26#include <linux/pgtable.h>
27#include <linux/stackprotector.h>
28#include <linux/utsname.h>
29#include <linux/efi.h>
30
31#include <asm/alternative.h>
32#include <asm/cmdline.h>
33#include <asm/cpuid/api.h>
34#include <asm/perf_event.h>
35#include <asm/mmu_context.h>
36#include <asm/doublefault.h>
37#include <asm/archrandom.h>
38#include <asm/hypervisor.h>
39#include <asm/processor.h>
40#include <asm/tlbflush.h>
41#include <asm/debugreg.h>
42#include <asm/sections.h>
43#include <asm/vsyscall.h>
44#include <linux/topology.h>
45#include <linux/cpumask.h>
46#include <linux/atomic.h>
47#include <asm/proto.h>
48#include <asm/setup.h>
49#include <asm/apic.h>
50#include <asm/desc.h>
51#include <asm/fpu/api.h>
52#include <asm/mtrr.h>
53#include <asm/hwcap2.h>
54#include <linux/numa.h>
55#include <asm/numa.h>
56#include <asm/asm.h>
57#include <asm/bugs.h>
58#include <asm/cpu.h>
59#include <asm/mce.h>
60#include <asm/msr.h>
61#include <asm/cacheinfo.h>
62#include <asm/memtype.h>
63#include <asm/microcode.h>
64#include <asm/intel-family.h>
65#include <asm/cpu_device_id.h>
66#include <asm/fred.h>
67#include <asm/uv/uv.h>
68#include <asm/ia32.h>
69#include <asm/set_memory.h>
70#include <asm/traps.h>
71#include <asm/sev.h>
72#include <asm/tdx.h>
73#include <asm/posted_intr.h>
74#include <asm/runtime-const.h>
75
76#include "cpu.h"
77
78DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
79EXPORT_PER_CPU_SYMBOL(cpu_info);
80
81u32 elf_hwcap2 __read_mostly;
82
83/* Number of siblings per CPU package */
84unsigned int __max_threads_per_core __ro_after_init = 1;
85EXPORT_SYMBOL(__max_threads_per_core);
86
87unsigned int __max_dies_per_package __ro_after_init = 1;
88EXPORT_SYMBOL(__max_dies_per_package);
89
90unsigned int __max_logical_packages __ro_after_init = 1;
91EXPORT_SYMBOL(__max_logical_packages);
92
93unsigned int __num_cores_per_package __ro_after_init = 1;
94EXPORT_SYMBOL(__num_cores_per_package);
95
96unsigned int __num_threads_per_package __ro_after_init = 1;
97EXPORT_SYMBOL(__num_threads_per_package);
98
99static struct ppin_info {
100 int feature;
101 int msr_ppin_ctl;
102 int msr_ppin;
103} ppin_info[] = {
104 [X86_VENDOR_INTEL] = {
105 .feature = X86_FEATURE_INTEL_PPIN,
106 .msr_ppin_ctl = MSR_PPIN_CTL,
107 .msr_ppin = MSR_PPIN
108 },
109 [X86_VENDOR_AMD] = {
110 .feature = X86_FEATURE_AMD_PPIN,
111 .msr_ppin_ctl = MSR_AMD_PPIN_CTL,
112 .msr_ppin = MSR_AMD_PPIN
113 },
114};
115
116static const struct x86_cpu_id ppin_cpuids[] = {
117 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
118 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),
119
120 /* Legacy models without CPUID enumeration */
121 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
122 X86_MATCH_VFM(INTEL_HASWELL_X, &ppin_info[X86_VENDOR_INTEL]),
123 X86_MATCH_VFM(INTEL_BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]),
124 X86_MATCH_VFM(INTEL_BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]),
125 X86_MATCH_VFM(INTEL_SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]),
126 X86_MATCH_VFM(INTEL_ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]),
127 X86_MATCH_VFM(INTEL_ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]),
128 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
129 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
130 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]),
131 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]),
132
133 {}
134};
135
136static void ppin_init(struct cpuinfo_x86 *c)
137{
138 const struct x86_cpu_id *id;
139 unsigned long long val;
140 struct ppin_info *info;
141
142 id = x86_match_cpu(match: ppin_cpuids);
143 if (!id)
144 return;
145
146 /*
147 * Testing the presence of the MSR is not enough. Need to check
148 * that the PPIN_CTL allows reading of the PPIN.
149 */
150 info = (struct ppin_info *)id->driver_data;
151
152 if (rdmsrq_safe(msr: info->msr_ppin_ctl, p: &val))
153 goto clear_ppin;
154
155 if ((val & 3UL) == 1UL) {
156 /* PPIN locked in disabled mode */
157 goto clear_ppin;
158 }
159
160 /* If PPIN is disabled, try to enable */
161 if (!(val & 2UL)) {
162 wrmsrq_safe(msr: info->msr_ppin_ctl, val: val | 2UL);
163 rdmsrq_safe(msr: info->msr_ppin_ctl, p: &val);
164 }
165
166 /* Is the enable bit set? */
167 if (val & 2UL) {
168 c->ppin = native_rdmsrq(msr: info->msr_ppin);
169 set_cpu_cap(c, info->feature);
170 return;
171 }
172
173clear_ppin:
174 setup_clear_cpu_cap(info->feature);
175}
176
177static void default_init(struct cpuinfo_x86 *c)
178{
179#ifdef CONFIG_X86_64
180 cpu_detect_cache_sizes(c);
181#else
182 /* Not much we can do here... */
183 /* Check if at least it has cpuid */
184 if (c->cpuid_level == -1) {
185 /* No cpuid. It must be an ancient CPU */
186 if (c->x86 == 4)
187 strcpy(c->x86_model_id, "486");
188 else if (c->x86 == 3)
189 strcpy(c->x86_model_id, "386");
190 }
191#endif
192}
193
194static const struct cpu_dev default_cpu = {
195 .c_init = default_init,
196 .c_vendor = "Unknown",
197 .c_x86_vendor = X86_VENDOR_UNKNOWN,
198};
199
200static const struct cpu_dev *this_cpu = &default_cpu;
201
202DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
203#ifdef CONFIG_X86_64
204 /*
205 * We need valid kernel segments for data and code in long mode too
206 * IRET will check the segment types kkeil 2000/10/28
207 * Also sysret mandates a special GDT layout
208 *
209 * TLS descriptors are currently at a different place compared to i386.
210 * Hopefully nobody expects them at a fixed place (Wine?)
211 */
212 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
213 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff),
214 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff),
215 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
216 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff),
217 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff),
218#else
219 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
220 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
221 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
222 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff),
223 /*
224 * Segments used for calling PnP BIOS have byte granularity.
225 * They code segments and data segments have fixed 64k limits,
226 * the transfer segment sizes are set at run time.
227 */
228 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff),
229 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff),
230 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff),
231 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0),
232 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0),
233 /*
234 * The APM segments have byte granularity and their bases
235 * are set at run time. All have 64k limits.
236 */
237 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff),
238 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff),
239 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff),
240
241 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
242 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
243#endif
244} };
245EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
246SYM_PIC_ALIAS(gdt_page);
247
248#ifdef CONFIG_X86_64
249static int __init x86_nopcid_setup(char *s)
250{
251 /* nopcid doesn't accept parameters */
252 if (s)
253 return -EINVAL;
254
255 /* do not emit a message if the feature is not present */
256 if (!boot_cpu_has(X86_FEATURE_PCID))
257 return 0;
258
259 setup_clear_cpu_cap(X86_FEATURE_PCID);
260 pr_info("nopcid: PCID feature disabled\n");
261 return 0;
262}
263early_param("nopcid", x86_nopcid_setup);
264#endif
265
266static int __init x86_noinvpcid_setup(char *s)
267{
268 /* noinvpcid doesn't accept parameters */
269 if (s)
270 return -EINVAL;
271
272 /* do not emit a message if the feature is not present */
273 if (!boot_cpu_has(X86_FEATURE_INVPCID))
274 return 0;
275
276 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
277 pr_info("noinvpcid: INVPCID feature disabled\n");
278 return 0;
279}
280early_param("noinvpcid", x86_noinvpcid_setup);
281
282/* Standard macro to see if a specific flag is changeable */
283static inline bool flag_is_changeable_p(unsigned long flag)
284{
285 unsigned long f1, f2;
286
287 if (!IS_ENABLED(CONFIG_X86_32))
288 return true;
289
290 /*
291 * Cyrix and IDT cpus allow disabling of CPUID
292 * so the code below may return different results
293 * when it is executed before and after enabling
294 * the CPUID. Add "volatile" to not allow gcc to
295 * optimize the subsequent calls to this function.
296 */
297 asm volatile ("pushfl \n\t"
298 "pushfl \n\t"
299 "popl %0 \n\t"
300 "movl %0, %1 \n\t"
301 "xorl %2, %0 \n\t"
302 "pushl %0 \n\t"
303 "popfl \n\t"
304 "pushfl \n\t"
305 "popl %0 \n\t"
306 "popfl \n\t"
307
308 : "=&r" (f1), "=&r" (f2)
309 : "ir" (flag));
310
311 return (f1 ^ f2) & flag;
312}
313
314#ifdef CONFIG_X86_32
315static int cachesize_override = -1;
316static int disable_x86_serial_nr = 1;
317
318static int __init cachesize_setup(char *str)
319{
320 get_option(&str, &cachesize_override);
321 return 1;
322}
323__setup("cachesize=", cachesize_setup);
324
325/* Probe for the CPUID instruction */
326bool cpuid_feature(void)
327{
328 return flag_is_changeable_p(X86_EFLAGS_ID);
329}
330
331static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
332{
333 unsigned long lo, hi;
334
335 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
336 return;
337
338 /* Disable processor serial number: */
339
340 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
341 lo |= 0x200000;
342 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
343
344 pr_notice("CPU serial number disabled.\n");
345 clear_cpu_cap(c, X86_FEATURE_PN);
346
347 /* Disabling the serial number may affect the cpuid level */
348 c->cpuid_level = cpuid_eax(0);
349}
350
351static int __init x86_serial_nr_setup(char *s)
352{
353 disable_x86_serial_nr = 0;
354 return 1;
355}
356__setup("serialnumber", x86_serial_nr_setup);
357#else
358static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
359{
360}
361#endif
362
363static __always_inline void setup_smep(struct cpuinfo_x86 *c)
364{
365 if (cpu_has(c, X86_FEATURE_SMEP))
366 cr4_set_bits(X86_CR4_SMEP);
367}
368
369static __always_inline void setup_smap(struct cpuinfo_x86 *c)
370{
371 unsigned long eflags = native_save_fl();
372
373 /* This should have been cleared long ago */
374 BUG_ON(eflags & X86_EFLAGS_AC);
375
376 if (cpu_has(c, X86_FEATURE_SMAP))
377 cr4_set_bits(X86_CR4_SMAP);
378}
379
380static __always_inline void setup_umip(struct cpuinfo_x86 *c)
381{
382 /* Check the boot processor, plus build option for UMIP. */
383 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
384 goto out;
385
386 /* Check the current processor's cpuid bits. */
387 if (!cpu_has(c, X86_FEATURE_UMIP))
388 goto out;
389
390 cr4_set_bits(X86_CR4_UMIP);
391
392 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
393
394 return;
395
396out:
397 /*
398 * Make sure UMIP is disabled in case it was enabled in a
399 * previous boot (e.g., via kexec).
400 */
401 cr4_clear_bits(X86_CR4_UMIP);
402}
403
404/* These bits should not change their value after CPU init is finished. */
405static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
406 X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED;
407static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
408static unsigned long cr4_pinned_bits __ro_after_init;
409
410void native_write_cr0(unsigned long val)
411{
412 unsigned long bits_missing = 0;
413
414set_register:
415 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
416
417 if (static_branch_likely(&cr_pinning)) {
418 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
419 bits_missing = X86_CR0_WP;
420 val |= bits_missing;
421 goto set_register;
422 }
423 /* Warn after we've set the missing bits. */
424 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
425 }
426}
427EXPORT_SYMBOL(native_write_cr0);
428
429void __no_profile native_write_cr4(unsigned long val)
430{
431 unsigned long bits_changed = 0;
432
433set_register:
434 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
435
436 if (static_branch_likely(&cr_pinning)) {
437 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
438 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
439 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
440 goto set_register;
441 }
442 /* Warn after we've corrected the changed bits. */
443 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
444 bits_changed);
445 }
446}
447#if IS_MODULE(CONFIG_LKDTM)
448EXPORT_SYMBOL_GPL(native_write_cr4);
449#endif
450
451void cr4_update_irqsoff(unsigned long set, unsigned long clear)
452{
453 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
454
455 lockdep_assert_irqs_disabled();
456
457 newval = (cr4 & ~clear) | set;
458 if (newval != cr4) {
459 this_cpu_write(cpu_tlbstate.cr4, newval);
460 __write_cr4(x: newval);
461 }
462}
463EXPORT_SYMBOL(cr4_update_irqsoff);
464
465/* Read the CR4 shadow. */
466unsigned long cr4_read_shadow(void)
467{
468 return this_cpu_read(cpu_tlbstate.cr4);
469}
470EXPORT_SYMBOL_GPL(cr4_read_shadow);
471
472void cr4_init(void)
473{
474 unsigned long cr4 = __read_cr4();
475
476 if (boot_cpu_has(X86_FEATURE_PCID))
477 cr4 |= X86_CR4_PCIDE;
478 if (static_branch_likely(&cr_pinning))
479 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
480
481 __write_cr4(x: cr4);
482
483 /* Initialize cr4 shadow for this CPU. */
484 this_cpu_write(cpu_tlbstate.cr4, cr4);
485}
486
487/*
488 * Once CPU feature detection is finished (and boot params have been
489 * parsed), record any of the sensitive CR bits that are set, and
490 * enable CR pinning.
491 */
492static void __init setup_cr_pinning(void)
493{
494 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
495 static_key_enable(key: &cr_pinning.key);
496}
497
498static __init int x86_nofsgsbase_setup(char *arg)
499{
500 /* Require an exact match without trailing characters. */
501 if (strlen(arg))
502 return 0;
503
504 /* Do not emit a message if the feature is not present. */
505 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
506 return 1;
507
508 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
509 pr_info("FSGSBASE disabled via kernel command line\n");
510 return 1;
511}
512__setup("nofsgsbase", x86_nofsgsbase_setup);
513
514/*
515 * Protection Keys are not available in 32-bit mode.
516 */
517static bool pku_disabled;
518
519static __always_inline void setup_pku(struct cpuinfo_x86 *c)
520{
521 if (c == &boot_cpu_data) {
522 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
523 return;
524 /*
525 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
526 * bit to be set. Enforce it.
527 */
528 setup_force_cpu_cap(X86_FEATURE_OSPKE);
529
530 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
531 return;
532 }
533
534 cr4_set_bits(X86_CR4_PKE);
535 /* Load the default PKRU value */
536 pkru_write_default();
537}
538
539#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
540static __init int setup_disable_pku(char *arg)
541{
542 /*
543 * Do not clear the X86_FEATURE_PKU bit. All of the
544 * runtime checks are against OSPKE so clearing the
545 * bit does nothing.
546 *
547 * This way, we will see "pku" in cpuinfo, but not
548 * "ospke", which is exactly what we want. It shows
549 * that the CPU has PKU, but the OS has not enabled it.
550 * This happens to be exactly how a system would look
551 * if we disabled the config option.
552 */
553 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
554 pku_disabled = true;
555 return 1;
556}
557__setup("nopku", setup_disable_pku);
558#endif
559
560#ifdef CONFIG_X86_KERNEL_IBT
561
562__noendbr u64 ibt_save(bool disable)
563{
564 u64 msr = 0;
565
566 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
567 rdmsrq(MSR_IA32_S_CET, msr);
568 if (disable)
569 wrmsrq(MSR_IA32_S_CET, val: msr & ~CET_ENDBR_EN);
570 }
571
572 return msr;
573}
574
575__noendbr void ibt_restore(u64 save)
576{
577 u64 msr;
578
579 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
580 rdmsrq(MSR_IA32_S_CET, msr);
581 msr &= ~CET_ENDBR_EN;
582 msr |= (save & CET_ENDBR_EN);
583 wrmsrq(MSR_IA32_S_CET, val: msr);
584 }
585}
586
587#endif
588
589static __always_inline void setup_cet(struct cpuinfo_x86 *c)
590{
591 bool user_shstk, kernel_ibt;
592
593 if (!IS_ENABLED(CONFIG_X86_CET))
594 return;
595
596 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT);
597 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) &&
598 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK);
599
600 if (!kernel_ibt && !user_shstk)
601 return;
602
603 if (user_shstk)
604 set_cpu_cap(c, X86_FEATURE_USER_SHSTK);
605
606 if (kernel_ibt)
607 wrmsrq(MSR_IA32_S_CET, CET_ENDBR_EN);
608 else
609 wrmsrq(MSR_IA32_S_CET, val: 0);
610
611 cr4_set_bits(X86_CR4_CET);
612
613 if (kernel_ibt && ibt_selftest()) {
614 pr_err("IBT selftest: Failed!\n");
615 wrmsrq(MSR_IA32_S_CET, val: 0);
616 setup_clear_cpu_cap(X86_FEATURE_IBT);
617 }
618}
619
620__noendbr void cet_disable(void)
621{
622 if (!(cpu_feature_enabled(X86_FEATURE_IBT) ||
623 cpu_feature_enabled(X86_FEATURE_SHSTK)))
624 return;
625
626 wrmsrq(MSR_IA32_S_CET, val: 0);
627 wrmsrq(MSR_IA32_U_CET, val: 0);
628}
629
630/*
631 * Some CPU features depend on higher CPUID levels, which may not always
632 * be available due to CPUID level capping or broken virtualization
633 * software. Add those features to this table to auto-disable them.
634 */
635struct cpuid_dependent_feature {
636 u32 feature;
637 u32 level;
638};
639
640static const struct cpuid_dependent_feature
641cpuid_dependent_features[] = {
642 { X86_FEATURE_MWAIT, CPUID_LEAF_MWAIT },
643 { X86_FEATURE_DCA, CPUID_LEAF_DCA },
644 { X86_FEATURE_XSAVE, CPUID_LEAF_XSTATE },
645 { 0, 0 }
646};
647
648static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
649{
650 const struct cpuid_dependent_feature *df;
651
652 for (df = cpuid_dependent_features; df->feature; df++) {
653
654 if (!cpu_has(c, df->feature))
655 continue;
656 /*
657 * Note: cpuid_level is set to -1 if unavailable, but
658 * extended_extended_level is set to 0 if unavailable
659 * and the legitimate extended levels are all negative
660 * when signed; hence the weird messing around with
661 * signs here...
662 */
663 if (!((s32)df->level < 0 ?
664 (u32)df->level > (u32)c->extended_cpuid_level :
665 (s32)df->level > (s32)c->cpuid_level))
666 continue;
667
668 clear_cpu_cap(c, bit: df->feature);
669 if (!warn)
670 continue;
671
672 pr_warn("CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
673 x86_cap_flags[df->feature], df->level);
674 }
675}
676
677/*
678 * Naming convention should be: <Name> [(<Codename>)]
679 * This table only is used unless init_<vendor>() below doesn't set it;
680 * in particular, if CPUID levels 0x80000002..4 are supported, this
681 * isn't used
682 */
683
684/* Look up CPU names by table lookup. */
685static const char *table_lookup_model(struct cpuinfo_x86 *c)
686{
687#ifdef CONFIG_X86_32
688 const struct legacy_cpu_model_info *info;
689
690 if (c->x86_model >= 16)
691 return NULL; /* Range check */
692
693 if (!this_cpu)
694 return NULL;
695
696 info = this_cpu->legacy_models;
697
698 while (info->family) {
699 if (info->family == c->x86)
700 return info->model_names[c->x86_model];
701 info++;
702 }
703#endif
704 return NULL; /* Not found */
705}
706
707/* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
708__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
709__u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
710
711#ifdef CONFIG_X86_32
712/* The 32-bit entry code needs to find cpu_entry_area. */
713DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
714#endif
715
716/* Load the original GDT from the per-cpu structure */
717void load_direct_gdt(int cpu)
718{
719 struct desc_ptr gdt_descr;
720
721 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
722 gdt_descr.size = GDT_SIZE - 1;
723 load_gdt(&gdt_descr);
724}
725EXPORT_SYMBOL_GPL(load_direct_gdt);
726
727/* Load a fixmap remapping of the per-cpu GDT */
728void load_fixmap_gdt(int cpu)
729{
730 struct desc_ptr gdt_descr;
731
732 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
733 gdt_descr.size = GDT_SIZE - 1;
734 load_gdt(&gdt_descr);
735}
736EXPORT_SYMBOL_GPL(load_fixmap_gdt);
737
738/**
739 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base
740 * @cpu: The CPU number for which this is invoked
741 *
742 * Invoked during early boot to switch from early GDT and early per CPU to
743 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base
744 * switch is implicit by loading the direct GDT. On 64bit this requires
745 * to update GSBASE.
746 */
747void __init switch_gdt_and_percpu_base(int cpu)
748{
749 load_direct_gdt(cpu);
750
751#ifdef CONFIG_X86_64
752 /*
753 * No need to load %gs. It is already correct.
754 *
755 * Writing %gs on 64bit would zero GSBASE which would make any per
756 * CPU operation up to the point of the wrmsrq() fault.
757 *
758 * Set GSBASE to the new offset. Until the wrmsrq() happens the
759 * early mapping is still valid. That means the GSBASE update will
760 * lose any prior per CPU data which was not copied over in
761 * setup_per_cpu_areas().
762 *
763 * This works even with stackprotector enabled because the
764 * per CPU stack canary is 0 in both per CPU areas.
765 */
766 wrmsrq(MSR_GS_BASE, val: cpu_kernelmode_gs_base(cpu));
767#else
768 /*
769 * %fs is already set to __KERNEL_PERCPU, but after switching GDT
770 * it is required to load FS again so that the 'hidden' part is
771 * updated from the new GDT. Up to this point the early per CPU
772 * translation is active. Any content of the early per CPU data
773 * which was not copied over in setup_per_cpu_areas() is lost.
774 */
775 loadsegment(fs, __KERNEL_PERCPU);
776#endif
777}
778
779static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
780
781static void get_model_name(struct cpuinfo_x86 *c)
782{
783 unsigned int *v;
784 char *p, *q, *s;
785
786 if (c->extended_cpuid_level < 0x80000004)
787 return;
788
789 v = (unsigned int *)c->x86_model_id;
790 cpuid(op: 0x80000002, eax: &v[0], ebx: &v[1], ecx: &v[2], edx: &v[3]);
791 cpuid(op: 0x80000003, eax: &v[4], ebx: &v[5], ecx: &v[6], edx: &v[7]);
792 cpuid(op: 0x80000004, eax: &v[8], ebx: &v[9], ecx: &v[10], edx: &v[11]);
793 c->x86_model_id[48] = 0;
794
795 /* Trim whitespace */
796 p = q = s = &c->x86_model_id[0];
797
798 while (*p == ' ')
799 p++;
800
801 while (*p) {
802 /* Note the last non-whitespace index */
803 if (!isspace(*p))
804 s = q;
805
806 *q++ = *p++;
807 }
808
809 *(s + 1) = '\0';
810}
811
812void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
813{
814 unsigned int n, dummy, ebx, ecx, edx, l2size;
815
816 n = c->extended_cpuid_level;
817
818 if (n >= 0x80000005) {
819 cpuid(op: 0x80000005, eax: &dummy, ebx: &ebx, ecx: &ecx, edx: &edx);
820 c->x86_cache_size = (ecx>>24) + (edx>>24);
821#ifdef CONFIG_X86_64
822 /* On K8 L1 TLB is inclusive, so don't count it */
823 c->x86_tlbsize = 0;
824#endif
825 }
826
827 if (n < 0x80000006) /* Some chips just has a large L1. */
828 return;
829
830 cpuid(op: 0x80000006, eax: &dummy, ebx: &ebx, ecx: &ecx, edx: &edx);
831 l2size = ecx >> 16;
832
833#ifdef CONFIG_X86_64
834 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
835#else
836 /* do processor-specific cache resizing */
837 if (this_cpu->legacy_cache_size)
838 l2size = this_cpu->legacy_cache_size(c, l2size);
839
840 /* Allow user to override all this if necessary. */
841 if (cachesize_override != -1)
842 l2size = cachesize_override;
843
844 if (l2size == 0)
845 return; /* Again, no L2 cache is possible */
846#endif
847
848 c->x86_cache_size = l2size;
849}
850
851u16 __read_mostly tlb_lli_4k;
852u16 __read_mostly tlb_lli_2m;
853u16 __read_mostly tlb_lli_4m;
854u16 __read_mostly tlb_lld_4k;
855u16 __read_mostly tlb_lld_2m;
856u16 __read_mostly tlb_lld_4m;
857u16 __read_mostly tlb_lld_1g;
858
859static void cpu_detect_tlb(struct cpuinfo_x86 *c)
860{
861 if (this_cpu->c_detect_tlb)
862 this_cpu->c_detect_tlb(c);
863
864 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
865 tlb_lli_4k, tlb_lli_2m, tlb_lli_4m);
866
867 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
868 tlb_lld_4k, tlb_lld_2m, tlb_lld_4m, tlb_lld_1g);
869}
870
871void get_cpu_vendor(struct cpuinfo_x86 *c)
872{
873 char *v = c->x86_vendor_id;
874 int i;
875
876 for (i = 0; i < X86_VENDOR_NUM; i++) {
877 if (!cpu_devs[i])
878 break;
879
880 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
881 (cpu_devs[i]->c_ident[1] &&
882 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
883
884 this_cpu = cpu_devs[i];
885 c->x86_vendor = this_cpu->c_x86_vendor;
886 return;
887 }
888 }
889
890 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
891 "CPU: Your system may be unstable.\n", v);
892
893 c->x86_vendor = X86_VENDOR_UNKNOWN;
894 this_cpu = &default_cpu;
895}
896
897void cpu_detect(struct cpuinfo_x86 *c)
898{
899 /* Get vendor name */
900 cpuid(op: 0x00000000, eax: (unsigned int *)&c->cpuid_level,
901 ebx: (unsigned int *)&c->x86_vendor_id[0],
902 ecx: (unsigned int *)&c->x86_vendor_id[8],
903 edx: (unsigned int *)&c->x86_vendor_id[4]);
904
905 c->x86 = 4;
906 /* Intel-defined flags: level 0x00000001 */
907 if (c->cpuid_level >= 0x00000001) {
908 u32 junk, tfms, cap0, misc;
909
910 cpuid(op: 0x00000001, eax: &tfms, ebx: &misc, ecx: &junk, edx: &cap0);
911 c->x86 = x86_family(sig: tfms);
912 c->x86_model = x86_model(sig: tfms);
913 c->x86_stepping = x86_stepping(sig: tfms);
914
915 if (cap0 & (1<<19)) {
916 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
917 c->x86_cache_alignment = c->x86_clflush_size;
918 }
919 }
920}
921
922static void apply_forced_caps(struct cpuinfo_x86 *c)
923{
924 int i;
925
926 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
927 c->x86_capability[i] &= ~cpu_caps_cleared[i];
928 c->x86_capability[i] |= cpu_caps_set[i];
929 }
930}
931
932static void init_speculation_control(struct cpuinfo_x86 *c)
933{
934 /*
935 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
936 * and they also have a different bit for STIBP support. Also,
937 * a hypervisor might have set the individual AMD bits even on
938 * Intel CPUs, for finer-grained selection of what's available.
939 */
940 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
941 set_cpu_cap(c, X86_FEATURE_IBRS);
942 set_cpu_cap(c, X86_FEATURE_IBPB);
943 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
944 }
945
946 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
947 set_cpu_cap(c, X86_FEATURE_STIBP);
948
949 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
950 cpu_has(c, X86_FEATURE_VIRT_SSBD))
951 set_cpu_cap(c, X86_FEATURE_SSBD);
952
953 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
954 set_cpu_cap(c, X86_FEATURE_IBRS);
955 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
956 }
957
958 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
959 set_cpu_cap(c, X86_FEATURE_IBPB);
960
961 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
962 set_cpu_cap(c, X86_FEATURE_STIBP);
963 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
964 }
965
966 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
967 set_cpu_cap(c, X86_FEATURE_SSBD);
968 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
969 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
970 }
971}
972
973void get_cpu_cap(struct cpuinfo_x86 *c)
974{
975 u32 eax, ebx, ecx, edx;
976
977 /* Intel-defined flags: level 0x00000001 */
978 if (c->cpuid_level >= 0x00000001) {
979 cpuid(op: 0x00000001, eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
980
981 c->x86_capability[CPUID_1_ECX] = ecx;
982 c->x86_capability[CPUID_1_EDX] = edx;
983 }
984
985 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
986 if (c->cpuid_level >= 0x00000006)
987 c->x86_capability[CPUID_6_EAX] = cpuid_eax(op: 0x00000006);
988
989 /* Additional Intel-defined flags: level 0x00000007 */
990 if (c->cpuid_level >= 0x00000007) {
991 cpuid_count(op: 0x00000007, count: 0, eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
992 c->x86_capability[CPUID_7_0_EBX] = ebx;
993 c->x86_capability[CPUID_7_ECX] = ecx;
994 c->x86_capability[CPUID_7_EDX] = edx;
995
996 /* Check valid sub-leaf index before accessing it */
997 if (eax >= 1) {
998 cpuid_count(op: 0x00000007, count: 1, eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
999 c->x86_capability[CPUID_7_1_EAX] = eax;
1000 }
1001 }
1002
1003 /* Extended state features: level 0x0000000d */
1004 if (c->cpuid_level >= 0x0000000d) {
1005 cpuid_count(op: 0x0000000d, count: 1, eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
1006
1007 c->x86_capability[CPUID_D_1_EAX] = eax;
1008 }
1009
1010 /*
1011 * Check if extended CPUID leaves are implemented: Max extended
1012 * CPUID leaf must be in the 0x80000001-0x8000ffff range.
1013 */
1014 eax = cpuid_eax(op: 0x80000000);
1015 c->extended_cpuid_level = ((eax & 0xffff0000) == 0x80000000) ? eax : 0;
1016
1017 if (c->extended_cpuid_level >= 0x80000001) {
1018 cpuid(op: 0x80000001, eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
1019
1020 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
1021 c->x86_capability[CPUID_8000_0001_EDX] = edx;
1022 }
1023
1024 if (c->extended_cpuid_level >= 0x80000007) {
1025 cpuid(op: 0x80000007, eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
1026
1027 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
1028 c->x86_power = edx;
1029 }
1030
1031 if (c->extended_cpuid_level >= 0x80000008) {
1032 cpuid(op: 0x80000008, eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
1033 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
1034 }
1035
1036 if (c->extended_cpuid_level >= 0x8000000a)
1037 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(op: 0x8000000a);
1038
1039 if (c->extended_cpuid_level >= 0x8000001f)
1040 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(op: 0x8000001f);
1041
1042 if (c->extended_cpuid_level >= 0x80000021)
1043 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(op: 0x80000021);
1044
1045 init_scattered_cpuid_features(c);
1046 init_speculation_control(c);
1047
1048 /*
1049 * Clear/Set all flags overridden by options, after probe.
1050 * This needs to happen each time we re-probe, which may happen
1051 * several times during CPU initialization.
1052 */
1053 apply_forced_caps(c);
1054}
1055
1056void get_cpu_address_sizes(struct cpuinfo_x86 *c)
1057{
1058 u32 eax, ebx, ecx, edx;
1059
1060 if (!cpu_has(c, X86_FEATURE_CPUID) ||
1061 (c->extended_cpuid_level < 0x80000008)) {
1062 if (IS_ENABLED(CONFIG_X86_64)) {
1063 c->x86_clflush_size = 64;
1064 c->x86_phys_bits = 36;
1065 c->x86_virt_bits = 48;
1066 } else {
1067 c->x86_clflush_size = 32;
1068 c->x86_virt_bits = 32;
1069 c->x86_phys_bits = 32;
1070
1071 if (cpu_has(c, X86_FEATURE_PAE) ||
1072 cpu_has(c, X86_FEATURE_PSE36))
1073 c->x86_phys_bits = 36;
1074 }
1075 } else {
1076 cpuid(op: 0x80000008, eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
1077
1078 c->x86_virt_bits = (eax >> 8) & 0xff;
1079 c->x86_phys_bits = eax & 0xff;
1080
1081 /* Provide a sane default if not enumerated: */
1082 if (!c->x86_clflush_size)
1083 c->x86_clflush_size = 32;
1084 }
1085
1086 c->x86_cache_bits = c->x86_phys_bits;
1087 c->x86_cache_alignment = c->x86_clflush_size;
1088}
1089
1090static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1091{
1092 int i;
1093
1094 /*
1095 * First of all, decide if this is a 486 or higher
1096 * It's a 486 if we can modify the AC flag
1097 */
1098 if (flag_is_changeable_p(X86_EFLAGS_AC))
1099 c->x86 = 4;
1100 else
1101 c->x86 = 3;
1102
1103 for (i = 0; i < X86_VENDOR_NUM; i++)
1104 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1105 c->x86_vendor_id[0] = 0;
1106 cpu_devs[i]->c_identify(c);
1107 if (c->x86_vendor_id[0]) {
1108 get_cpu_vendor(c);
1109 break;
1110 }
1111 }
1112}
1113
1114#define NO_SPECULATION BIT(0)
1115#define NO_MELTDOWN BIT(1)
1116#define NO_SSB BIT(2)
1117#define NO_L1TF BIT(3)
1118#define NO_MDS BIT(4)
1119#define MSBDS_ONLY BIT(5)
1120#define NO_SWAPGS BIT(6)
1121#define NO_ITLB_MULTIHIT BIT(7)
1122#define NO_SPECTRE_V2 BIT(8)
1123#define NO_MMIO BIT(9)
1124#define NO_EIBRS_PBRSB BIT(10)
1125#define NO_BHI BIT(11)
1126
1127#define VULNWL(vendor, family, model, whitelist) \
1128 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1129
1130#define VULNWL_INTEL(vfm, whitelist) \
1131 X86_MATCH_VFM(vfm, whitelist)
1132
1133#define VULNWL_AMD(family, whitelist) \
1134 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1135
1136#define VULNWL_HYGON(family, whitelist) \
1137 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1138
1139static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1140 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1141 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1142 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1143 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1144 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION),
1145 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION),
1146
1147 /* Intel Family 6 */
1148 VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO),
1149 VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO),
1150 VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO),
1151 VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO),
1152
1153 VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1154 VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1155 VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1156 VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1157 VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1158
1159 VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1160 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1161 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1162 VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1163 VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1164 VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1165
1166 VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB),
1167
1168 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID2,NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),
1169 VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1170
1171 VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1172 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1173 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1174
1175 /*
1176 * Technically, swapgs isn't serializing on AMD (despite it previously
1177 * being documented as such in the APM). But according to AMD, %gs is
1178 * updated non-speculatively, and the issuing of %gs-relative memory
1179 * operands will be blocked until the %gs update completes, which is
1180 * good enough for our purposes.
1181 */
1182
1183 VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB),
1184 VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB),
1185 VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
1186
1187 /* AMD Family 0xf - 0x12 */
1188 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1189 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1190 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1191 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1192
1193 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1194 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI),
1195 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI),
1196
1197 /* Zhaoxin Family 7 */
1198 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI),
1199 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI),
1200 {}
1201};
1202
1203#define VULNBL(vendor, family, model, blacklist) \
1204 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1205
1206#define VULNBL_INTEL_STEPS(vfm, max_stepping, issues) \
1207 X86_MATCH_VFM_STEPS(vfm, X86_STEP_MIN, max_stepping, issues)
1208
1209#define VULNBL_INTEL_TYPE(vfm, cpu_type, issues) \
1210 X86_MATCH_VFM_CPU_TYPE(vfm, INTEL_CPU_TYPE_##cpu_type, issues)
1211
1212#define VULNBL_AMD(family, blacklist) \
1213 VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
1214
1215#define VULNBL_HYGON(family, blacklist) \
1216 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist)
1217
1218#define SRBDS BIT(0)
1219/* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1220#define MMIO BIT(1)
1221/* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1222#define MMIO_SBDS BIT(2)
1223/* CPU is affected by RETbleed, speculating where you would not expect it */
1224#define RETBLEED BIT(3)
1225/* CPU is affected by SMT (cross-thread) return predictions */
1226#define SMT_RSB BIT(4)
1227/* CPU is affected by SRSO */
1228#define SRSO BIT(5)
1229/* CPU is affected by GDS */
1230#define GDS BIT(6)
1231/* CPU is affected by Register File Data Sampling */
1232#define RFDS BIT(7)
1233/* CPU is affected by Indirect Target Selection */
1234#define ITS BIT(8)
1235/* CPU is affected by Indirect Target Selection, but guest-host isolation is not affected */
1236#define ITS_NATIVE_ONLY BIT(9)
1237/* CPU is affected by Transient Scheduler Attacks */
1238#define TSA BIT(10)
1239/* CPU is affected by VMSCAPE */
1240#define VMSCAPE BIT(11)
1241
1242static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1243 VULNBL_INTEL_STEPS(INTEL_SANDYBRIDGE_X, X86_STEP_MAX, VMSCAPE),
1244 VULNBL_INTEL_STEPS(INTEL_SANDYBRIDGE, X86_STEP_MAX, VMSCAPE),
1245 VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE_X, X86_STEP_MAX, VMSCAPE),
1246 VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE, X86_STEP_MAX, SRBDS | VMSCAPE),
1247 VULNBL_INTEL_STEPS(INTEL_HASWELL, X86_STEP_MAX, SRBDS | VMSCAPE),
1248 VULNBL_INTEL_STEPS(INTEL_HASWELL_L, X86_STEP_MAX, SRBDS | VMSCAPE),
1249 VULNBL_INTEL_STEPS(INTEL_HASWELL_G, X86_STEP_MAX, SRBDS | VMSCAPE),
1250 VULNBL_INTEL_STEPS(INTEL_HASWELL_X, X86_STEP_MAX, MMIO | VMSCAPE),
1251 VULNBL_INTEL_STEPS(INTEL_BROADWELL_D, X86_STEP_MAX, MMIO | VMSCAPE),
1252 VULNBL_INTEL_STEPS(INTEL_BROADWELL_X, X86_STEP_MAX, MMIO | VMSCAPE),
1253 VULNBL_INTEL_STEPS(INTEL_BROADWELL_G, X86_STEP_MAX, SRBDS | VMSCAPE),
1254 VULNBL_INTEL_STEPS(INTEL_BROADWELL, X86_STEP_MAX, SRBDS | VMSCAPE),
1255 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, 0x5, MMIO | RETBLEED | GDS | VMSCAPE),
1256 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS | VMSCAPE),
1257 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE),
1258 VULNBL_INTEL_STEPS(INTEL_SKYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE),
1259 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, 0xb, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE),
1260 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS | VMSCAPE),
1261 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, 0xc, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE),
1262 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS | VMSCAPE),
1263 VULNBL_INTEL_STEPS(INTEL_CANNONLAKE_L, X86_STEP_MAX, RETBLEED | VMSCAPE),
1264 VULNBL_INTEL_STEPS(INTEL_ICELAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | ITS_NATIVE_ONLY),
1265 VULNBL_INTEL_STEPS(INTEL_ICELAKE_D, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY),
1266 VULNBL_INTEL_STEPS(INTEL_ICELAKE_X, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY),
1267 VULNBL_INTEL_STEPS(INTEL_COMETLAKE, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | VMSCAPE),
1268 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED | ITS | VMSCAPE),
1269 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | VMSCAPE),
1270 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE_L, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY),
1271 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY),
1272 VULNBL_INTEL_STEPS(INTEL_LAKEFIELD, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED),
1273 VULNBL_INTEL_STEPS(INTEL_ROCKETLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS | ITS_NATIVE_ONLY),
1274 VULNBL_INTEL_TYPE(INTEL_ALDERLAKE, ATOM, RFDS | VMSCAPE),
1275 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE, X86_STEP_MAX, VMSCAPE),
1276 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE_L, X86_STEP_MAX, RFDS | VMSCAPE),
1277 VULNBL_INTEL_TYPE(INTEL_RAPTORLAKE, ATOM, RFDS | VMSCAPE),
1278 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE, X86_STEP_MAX, VMSCAPE),
1279 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_P, X86_STEP_MAX, RFDS | VMSCAPE),
1280 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_S, X86_STEP_MAX, RFDS | VMSCAPE),
1281 VULNBL_INTEL_STEPS(INTEL_METEORLAKE_L, X86_STEP_MAX, VMSCAPE),
1282 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE_H, X86_STEP_MAX, VMSCAPE),
1283 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE, X86_STEP_MAX, VMSCAPE),
1284 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE_U, X86_STEP_MAX, VMSCAPE),
1285 VULNBL_INTEL_STEPS(INTEL_LUNARLAKE_M, X86_STEP_MAX, VMSCAPE),
1286 VULNBL_INTEL_STEPS(INTEL_SAPPHIRERAPIDS_X, X86_STEP_MAX, VMSCAPE),
1287 VULNBL_INTEL_STEPS(INTEL_GRANITERAPIDS_X, X86_STEP_MAX, VMSCAPE),
1288 VULNBL_INTEL_STEPS(INTEL_EMERALDRAPIDS_X, X86_STEP_MAX, VMSCAPE),
1289 VULNBL_INTEL_STEPS(INTEL_ATOM_GRACEMONT, X86_STEP_MAX, RFDS | VMSCAPE),
1290 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS),
1291 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MAX, MMIO | RFDS),
1292 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS),
1293 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT, X86_STEP_MAX, RFDS),
1294 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_D, X86_STEP_MAX, RFDS),
1295 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEP_MAX, RFDS),
1296 VULNBL_INTEL_STEPS(INTEL_ATOM_CRESTMONT_X, X86_STEP_MAX, VMSCAPE),
1297
1298 VULNBL_AMD(0x15, RETBLEED),
1299 VULNBL_AMD(0x16, RETBLEED),
1300 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO | VMSCAPE),
1301 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO | VMSCAPE),
1302 VULNBL_AMD(0x19, SRSO | TSA | VMSCAPE),
1303 VULNBL_AMD(0x1a, SRSO | VMSCAPE),
1304 {}
1305};
1306
1307static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1308{
1309 const struct x86_cpu_id *m = x86_match_cpu(match: table);
1310
1311 return m && !!(m->driver_data & which);
1312}
1313
1314u64 x86_read_arch_cap_msr(void)
1315{
1316 u64 x86_arch_cap_msr = 0;
1317
1318 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1319 rdmsrq(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr);
1320
1321 return x86_arch_cap_msr;
1322}
1323
1324static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr)
1325{
1326 return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO &&
1327 x86_arch_cap_msr & ARCH_CAP_PSDP_NO &&
1328 x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO);
1329}
1330
1331static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr)
1332{
1333 /* The "immunity" bit trumps everything else: */
1334 if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO)
1335 return false;
1336
1337 /*
1338 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to
1339 * indicate that mitigation is needed because guest is running on a
1340 * vulnerable hardware or may migrate to such hardware:
1341 */
1342 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR)
1343 return true;
1344
1345 /* Only consult the blacklist when there is no enumeration: */
1346 return cpu_matches(table: cpu_vuln_blacklist, RFDS);
1347}
1348
1349static bool __init vulnerable_to_its(u64 x86_arch_cap_msr)
1350{
1351 /* The "immunity" bit trumps everything else: */
1352 if (x86_arch_cap_msr & ARCH_CAP_ITS_NO)
1353 return false;
1354 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
1355 return false;
1356
1357 /* None of the affected CPUs have BHI_CTRL */
1358 if (boot_cpu_has(X86_FEATURE_BHI_CTRL))
1359 return false;
1360
1361 /*
1362 * If a VMM did not expose ITS_NO, assume that a guest could
1363 * be running on a vulnerable hardware or may migrate to such
1364 * hardware.
1365 */
1366 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1367 return true;
1368
1369 if (cpu_matches(table: cpu_vuln_blacklist, ITS))
1370 return true;
1371
1372 return false;
1373}
1374
1375static struct x86_cpu_id cpu_latest_microcode[] = {
1376#include "microcode/intel-ucode-defs.h"
1377 {}
1378};
1379
1380static bool __init cpu_has_old_microcode(void)
1381{
1382 const struct x86_cpu_id *m = x86_match_cpu(match: cpu_latest_microcode);
1383
1384 /* Give unknown CPUs a pass: */
1385 if (!m) {
1386 /* Intel CPUs should be in the list. Warn if not: */
1387 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1388 pr_info("x86/CPU: Model not found in latest microcode list\n");
1389 return false;
1390 }
1391
1392 /*
1393 * Hosts usually lie to guests with a super high microcode
1394 * version. Just ignore what hosts tell guests:
1395 */
1396 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1397 return false;
1398
1399 /* Consider all debug microcode to be old: */
1400 if (boot_cpu_data.microcode & BIT(31))
1401 return true;
1402
1403 /* Give new microcode a pass: */
1404 if (boot_cpu_data.microcode >= m->driver_data)
1405 return false;
1406
1407 /* Uh oh, too old: */
1408 return true;
1409}
1410
1411static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1412{
1413 u64 x86_arch_cap_msr = x86_read_arch_cap_msr();
1414
1415 if (cpu_has_old_microcode()) {
1416 pr_warn("x86/CPU: Running old microcode\n");
1417 setup_force_cpu_bug(X86_BUG_OLD_MICROCODE);
1418 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1419 }
1420
1421 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1422 if (!cpu_matches(table: cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1423 !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO))
1424 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1425
1426 if (cpu_matches(table: cpu_vuln_whitelist, NO_SPECULATION))
1427 return;
1428
1429 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1430
1431 if (!cpu_matches(table: cpu_vuln_whitelist, NO_SPECTRE_V2)) {
1432 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1433 setup_force_cpu_bug(X86_BUG_SPECTRE_V2_USER);
1434 }
1435
1436 if (!cpu_matches(table: cpu_vuln_whitelist, NO_SSB) &&
1437 !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) &&
1438 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1439 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1440
1441 /*
1442 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature
1443 * flag and protect from vendor-specific bugs via the whitelist.
1444 *
1445 * Don't use AutoIBRS when SNP is enabled because it degrades host
1446 * userspace indirect branch performance.
1447 */
1448 if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) ||
1449 (cpu_has(c, X86_FEATURE_AUTOIBRS) &&
1450 !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) {
1451 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1452 if (!cpu_matches(table: cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
1453 !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO))
1454 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
1455 }
1456
1457 if (!cpu_matches(table: cpu_vuln_whitelist, NO_MDS) &&
1458 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) {
1459 setup_force_cpu_bug(X86_BUG_MDS);
1460 if (cpu_matches(table: cpu_vuln_whitelist, MSBDS_ONLY))
1461 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1462 }
1463
1464 if (!cpu_matches(table: cpu_vuln_whitelist, NO_SWAPGS))
1465 setup_force_cpu_bug(X86_BUG_SWAPGS);
1466
1467 /*
1468 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1469 * - TSX is supported or
1470 * - TSX_CTRL is present
1471 *
1472 * TSX_CTRL check is needed for cases when TSX could be disabled before
1473 * the kernel boot e.g. kexec.
1474 * TSX_CTRL check alone is not sufficient for cases when the microcode
1475 * update is not present or running as guest that don't get TSX_CTRL.
1476 */
1477 if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) &&
1478 (cpu_has(c, X86_FEATURE_RTM) ||
1479 (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR)))
1480 setup_force_cpu_bug(X86_BUG_TAA);
1481
1482 /*
1483 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1484 * in the vulnerability blacklist.
1485 *
1486 * Some of the implications and mitigation of Shared Buffers Data
1487 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1488 * SRBDS.
1489 */
1490 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1491 cpu_has(c, X86_FEATURE_RDSEED)) &&
1492 cpu_matches(table: cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1493 setup_force_cpu_bug(X86_BUG_SRBDS);
1494
1495 /*
1496 * Processor MMIO Stale Data bug enumeration
1497 *
1498 * Affected CPU list is generally enough to enumerate the vulnerability,
1499 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1500 * not want the guest to enumerate the bug.
1501 */
1502 if (!arch_cap_mmio_immune(x86_arch_cap_msr)) {
1503 if (cpu_matches(table: cpu_vuln_blacklist, MMIO))
1504 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1505 }
1506
1507 if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
1508 if (cpu_matches(table: cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA))
1509 setup_force_cpu_bug(X86_BUG_RETBLEED);
1510 }
1511
1512 if (cpu_matches(table: cpu_vuln_blacklist, SMT_RSB))
1513 setup_force_cpu_bug(X86_BUG_SMT_RSB);
1514
1515 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) {
1516 if (cpu_matches(table: cpu_vuln_blacklist, SRSO))
1517 setup_force_cpu_bug(X86_BUG_SRSO);
1518 }
1519
1520 /*
1521 * Check if CPU is vulnerable to GDS. If running in a virtual machine on
1522 * an affected processor, the VMM may have disabled the use of GATHER by
1523 * disabling AVX2. The only way to do this in HW is to clear XCR0[2],
1524 * which means that AVX will be disabled.
1525 */
1526 if (cpu_matches(table: cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) &&
1527 boot_cpu_has(X86_FEATURE_AVX))
1528 setup_force_cpu_bug(X86_BUG_GDS);
1529
1530 if (vulnerable_to_rfds(x86_arch_cap_msr))
1531 setup_force_cpu_bug(X86_BUG_RFDS);
1532
1533 /*
1534 * Intel parts with eIBRS are vulnerable to BHI attacks. Parts with
1535 * BHI_NO still need to use the BHI mitigation to prevent Intra-mode
1536 * attacks. When virtualized, eIBRS could be hidden, assume vulnerable.
1537 */
1538 if (!cpu_matches(table: cpu_vuln_whitelist, NO_BHI) &&
1539 (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) ||
1540 boot_cpu_has(X86_FEATURE_HYPERVISOR)))
1541 setup_force_cpu_bug(X86_BUG_BHI);
1542
1543 if (cpu_has(c, X86_FEATURE_AMD_IBPB) && !cpu_has(c, X86_FEATURE_AMD_IBPB_RET))
1544 setup_force_cpu_bug(X86_BUG_IBPB_NO_RET);
1545
1546 if (vulnerable_to_its(x86_arch_cap_msr)) {
1547 setup_force_cpu_bug(X86_BUG_ITS);
1548 if (cpu_matches(table: cpu_vuln_blacklist, ITS_NATIVE_ONLY))
1549 setup_force_cpu_bug(X86_BUG_ITS_NATIVE_ONLY);
1550 }
1551
1552 if (c->x86_vendor == X86_VENDOR_AMD) {
1553 if (!cpu_has(c, X86_FEATURE_TSA_SQ_NO) ||
1554 !cpu_has(c, X86_FEATURE_TSA_L1_NO)) {
1555 if (cpu_matches(table: cpu_vuln_blacklist, TSA) ||
1556 /* Enable bug on Zen guests to allow for live migration. */
1557 (cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_ZEN)))
1558 setup_force_cpu_bug(X86_BUG_TSA);
1559 }
1560 }
1561
1562 /*
1563 * Set the bug only on bare-metal. A nested hypervisor should already be
1564 * deploying IBPB to isolate itself from nested guests.
1565 */
1566 if (cpu_matches(table: cpu_vuln_blacklist, VMSCAPE) &&
1567 !boot_cpu_has(X86_FEATURE_HYPERVISOR))
1568 setup_force_cpu_bug(X86_BUG_VMSCAPE);
1569
1570 if (cpu_matches(table: cpu_vuln_whitelist, NO_MELTDOWN))
1571 return;
1572
1573 /* Rogue Data Cache Load? No! */
1574 if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO)
1575 return;
1576
1577 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1578
1579 if (cpu_matches(table: cpu_vuln_whitelist, NO_L1TF))
1580 return;
1581
1582 setup_force_cpu_bug(X86_BUG_L1TF);
1583}
1584
1585/*
1586 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1587 * unfortunately, that's not true in practice because of early VIA
1588 * chips and (more importantly) broken virtualizers that are not easy
1589 * to detect. In the latter case it doesn't even *fail* reliably, so
1590 * probing for it doesn't even work. Disable it completely on 32-bit
1591 * unless we can find a reliable way to detect all the broken cases.
1592 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1593 */
1594static void detect_nopl(void)
1595{
1596#ifdef CONFIG_X86_32
1597 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1598#else
1599 setup_force_cpu_cap(X86_FEATURE_NOPL);
1600#endif
1601}
1602
1603static inline bool parse_set_clear_cpuid(char *arg, bool set)
1604{
1605 char *opt;
1606 int taint = 0;
1607
1608 while (arg) {
1609 bool found __maybe_unused = false;
1610 unsigned int bit;
1611
1612 opt = strsep(&arg, ",");
1613
1614 /*
1615 * Handle naked numbers first for feature flags which don't
1616 * have names. It doesn't make sense for a bug not to have a
1617 * name so don't handle bug flags here.
1618 */
1619 if (!kstrtouint(s: opt, base: 10, res: &bit)) {
1620 if (bit < NCAPINTS * 32) {
1621
1622 if (set) {
1623 pr_warn("setcpuid: force-enabling CPU feature flag:");
1624 setup_force_cpu_cap(bit);
1625 } else {
1626 pr_warn("clearcpuid: force-disabling CPU feature flag:");
1627 setup_clear_cpu_cap(bit);
1628 }
1629 /* empty-string, i.e., ""-defined feature flags */
1630 if (!x86_cap_flags[bit])
1631 pr_cont(" %d:%d\n", bit >> 5, bit & 31);
1632 else
1633 pr_cont(" %s\n", x86_cap_flags[bit]);
1634
1635 taint++;
1636 }
1637 /*
1638 * The assumption is that there are no feature names with only
1639 * numbers in the name thus go to the next argument.
1640 */
1641 continue;
1642 }
1643
1644 for (bit = 0; bit < 32 * (NCAPINTS + NBUGINTS); bit++) {
1645 const char *flag;
1646 const char *kind;
1647
1648 if (bit < 32 * NCAPINTS) {
1649 flag = x86_cap_flags[bit];
1650 kind = "feature";
1651 } else {
1652 kind = "bug";
1653 flag = x86_bug_flags[bit - (32 * NCAPINTS)];
1654 }
1655
1656 if (!flag)
1657 continue;
1658
1659 if (strcmp(flag, opt))
1660 continue;
1661
1662 if (set) {
1663 pr_warn("setcpuid: force-enabling CPU %s flag: %s\n",
1664 kind, flag);
1665 setup_force_cpu_cap(bit);
1666 } else {
1667 pr_warn("clearcpuid: force-disabling CPU %s flag: %s\n",
1668 kind, flag);
1669 setup_clear_cpu_cap(bit);
1670 }
1671 taint++;
1672 found = true;
1673 break;
1674 }
1675
1676 if (!found)
1677 pr_warn("%s: unknown CPU flag: %s", set ? "setcpuid" : "clearcpuid", opt);
1678 }
1679
1680 return taint;
1681}
1682
1683
1684/*
1685 * We parse cpu parameters early because fpu__init_system() is executed
1686 * before parse_early_param().
1687 */
1688static void __init cpu_parse_early_param(void)
1689{
1690 bool cpuid_taint = false;
1691 char arg[128];
1692 int arglen;
1693
1694#ifdef CONFIG_X86_32
1695 if (cmdline_find_option_bool(boot_command_line, "no387"))
1696#ifdef CONFIG_MATH_EMULATION
1697 setup_clear_cpu_cap(X86_FEATURE_FPU);
1698#else
1699 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1700#endif
1701
1702 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1703 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1704#endif
1705
1706 if (cmdline_find_option_bool(cmdline_ptr: boot_command_line, option: "noxsave"))
1707 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1708
1709 if (cmdline_find_option_bool(cmdline_ptr: boot_command_line, option: "noxsaveopt"))
1710 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1711
1712 if (cmdline_find_option_bool(cmdline_ptr: boot_command_line, option: "noxsaves"))
1713 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1714
1715 if (cmdline_find_option_bool(cmdline_ptr: boot_command_line, option: "nousershstk"))
1716 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK);
1717
1718 /* Minimize the gap between FRED is available and available but disabled. */
1719 arglen = cmdline_find_option(cmdline_ptr: boot_command_line, option: "fred", buffer: arg, bufsize: sizeof(arg));
1720 if (arglen != 2 || strncmp(arg, "on", 2))
1721 setup_clear_cpu_cap(X86_FEATURE_FRED);
1722
1723 arglen = cmdline_find_option(cmdline_ptr: boot_command_line, option: "clearcpuid", buffer: arg, bufsize: sizeof(arg));
1724 if (arglen > 0)
1725 cpuid_taint |= parse_set_clear_cpuid(arg, set: false);
1726
1727 arglen = cmdline_find_option(cmdline_ptr: boot_command_line, option: "setcpuid", buffer: arg, bufsize: sizeof(arg));
1728 if (arglen > 0)
1729 cpuid_taint |= parse_set_clear_cpuid(arg, set: true);
1730
1731 if (cpuid_taint) {
1732 pr_warn("!!! setcpuid=/clearcpuid= in use, this is for TESTING ONLY, may break things horribly. Tainting kernel.\n");
1733 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1734 }
1735}
1736
1737/*
1738 * Do minimum CPU detection early.
1739 * Fields really needed: vendor, cpuid_level, family, model, mask,
1740 * cache alignment.
1741 * The others are not touched to avoid unwanted side effects.
1742 *
1743 * WARNING: this function is only called on the boot CPU. Don't add code
1744 * here that is supposed to run on all CPUs.
1745 */
1746static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1747{
1748 memset(s: &c->x86_capability, c: 0, n: sizeof(c->x86_capability));
1749 c->extended_cpuid_level = 0;
1750
1751 if (!cpuid_feature())
1752 identify_cpu_without_cpuid(c);
1753
1754 /* cyrix could have cpuid enabled via c_identify()*/
1755 if (cpuid_feature()) {
1756 cpu_detect(c);
1757 get_cpu_vendor(c);
1758 intel_unlock_cpuid_leafs(c);
1759 get_cpu_cap(c);
1760 setup_force_cpu_cap(X86_FEATURE_CPUID);
1761 get_cpu_address_sizes(c);
1762 cpu_parse_early_param();
1763
1764 cpu_init_topology(c);
1765
1766 if (this_cpu->c_early_init)
1767 this_cpu->c_early_init(c);
1768
1769 c->cpu_index = 0;
1770 filter_cpuid_features(c, warn: false);
1771 check_cpufeature_deps(c);
1772
1773 if (this_cpu->c_bsp_init)
1774 this_cpu->c_bsp_init(c);
1775 } else {
1776 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1777 get_cpu_address_sizes(c);
1778 cpu_init_topology(c);
1779 }
1780
1781 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1782
1783 cpu_set_bug_bits(c);
1784
1785 sld_setup(c);
1786
1787#ifdef CONFIG_X86_32
1788 /*
1789 * Regardless of whether PCID is enumerated, the SDM says
1790 * that it can't be enabled in 32-bit mode.
1791 */
1792 setup_clear_cpu_cap(X86_FEATURE_PCID);
1793#endif
1794
1795 /*
1796 * Later in the boot process pgtable_l5_enabled() relies on
1797 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1798 * enabled by this point we need to clear the feature bit to avoid
1799 * false-positives at the later stage.
1800 *
1801 * pgtable_l5_enabled() can be false here for several reasons:
1802 * - 5-level paging is disabled compile-time;
1803 * - it's 32-bit kernel;
1804 * - machine doesn't support 5-level paging;
1805 * - user specified 'no5lvl' in kernel command line.
1806 */
1807 if (!pgtable_l5_enabled())
1808 setup_clear_cpu_cap(X86_FEATURE_LA57);
1809
1810 detect_nopl();
1811 mca_bsp_init(c);
1812}
1813
1814void __init init_cpu_devs(void)
1815{
1816 const struct cpu_dev *const *cdev;
1817 int count = 0;
1818
1819 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1820 const struct cpu_dev *cpudev = *cdev;
1821
1822 if (count >= X86_VENDOR_NUM)
1823 break;
1824 cpu_devs[count] = cpudev;
1825 count++;
1826 }
1827}
1828
1829void __init early_cpu_init(void)
1830{
1831#ifdef CONFIG_PROCESSOR_SELECT
1832 unsigned int i, j;
1833
1834 pr_info("KERNEL supported cpus:\n");
1835#endif
1836
1837 init_cpu_devs();
1838
1839#ifdef CONFIG_PROCESSOR_SELECT
1840 for (i = 0; i < X86_VENDOR_NUM && cpu_devs[i]; i++) {
1841 for (j = 0; j < 2; j++) {
1842 if (!cpu_devs[i]->c_ident[j])
1843 continue;
1844 pr_info(" %s %s\n", cpu_devs[i]->c_vendor,
1845 cpu_devs[i]->c_ident[j]);
1846 }
1847 }
1848#endif
1849
1850 early_identify_cpu(c: &boot_cpu_data);
1851}
1852
1853static bool detect_null_seg_behavior(void)
1854{
1855 /*
1856 * Empirically, writing zero to a segment selector on AMD does
1857 * not clear the base, whereas writing zero to a segment
1858 * selector on Intel does clear the base. Intel's behavior
1859 * allows slightly faster context switches in the common case
1860 * where GS is unused by the prev and next threads.
1861 *
1862 * Since neither vendor documents this anywhere that I can see,
1863 * detect it directly instead of hard-coding the choice by
1864 * vendor.
1865 *
1866 * I've designated AMD's behavior as the "bug" because it's
1867 * counterintuitive and less friendly.
1868 */
1869
1870 unsigned long old_base, tmp;
1871 rdmsrq(MSR_FS_BASE, old_base);
1872 wrmsrq(MSR_FS_BASE, val: 1);
1873 loadsegment(fs, 0);
1874 rdmsrq(MSR_FS_BASE, tmp);
1875 wrmsrq(MSR_FS_BASE, val: old_base);
1876 return tmp == 0;
1877}
1878
1879void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1880{
1881 /* BUG_NULL_SEG is only relevant with 64bit userspace */
1882 if (!IS_ENABLED(CONFIG_X86_64))
1883 return;
1884
1885 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE))
1886 return;
1887
1888 /*
1889 * CPUID bit above wasn't set. If this kernel is still running
1890 * as a HV guest, then the HV has decided not to advertize
1891 * that CPUID bit for whatever reason. For example, one
1892 * member of the migration pool might be vulnerable. Which
1893 * means, the bug is present: set the BUG flag and return.
1894 */
1895 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1896 set_cpu_bug(c, X86_BUG_NULL_SEG);
1897 return;
1898 }
1899
1900 /*
1901 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1902 * 0x18 is the respective family for Hygon.
1903 */
1904 if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1905 detect_null_seg_behavior())
1906 return;
1907
1908 /* All the remaining ones are affected */
1909 set_cpu_bug(c, X86_BUG_NULL_SEG);
1910}
1911
1912static void generic_identify(struct cpuinfo_x86 *c)
1913{
1914 c->extended_cpuid_level = 0;
1915
1916 if (!cpuid_feature())
1917 identify_cpu_without_cpuid(c);
1918
1919 /* cyrix could have cpuid enabled via c_identify()*/
1920 if (!cpuid_feature())
1921 return;
1922
1923 cpu_detect(c);
1924
1925 get_cpu_vendor(c);
1926 intel_unlock_cpuid_leafs(c);
1927 get_cpu_cap(c);
1928
1929 get_cpu_address_sizes(c);
1930
1931 get_model_name(c); /* Default name */
1932
1933 /*
1934 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1935 * systems that run Linux at CPL > 0 may or may not have the
1936 * issue, but, even if they have the issue, there's absolutely
1937 * nothing we can do about it because we can't use the real IRET
1938 * instruction.
1939 *
1940 * NB: For the time being, only 32-bit kernels support
1941 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1942 * whether to apply espfix using paravirt hooks. If any
1943 * non-paravirt system ever shows up that does *not* have the
1944 * ESPFIX issue, we can change this.
1945 */
1946#ifdef CONFIG_X86_32
1947 set_cpu_bug(c, X86_BUG_ESPFIX);
1948#endif
1949}
1950
1951/*
1952 * This does the hard work of actually picking apart the CPU stuff...
1953 */
1954static void identify_cpu(struct cpuinfo_x86 *c)
1955{
1956 int i;
1957
1958 c->loops_per_jiffy = loops_per_jiffy;
1959 c->x86_cache_size = 0;
1960 c->x86_vendor = X86_VENDOR_UNKNOWN;
1961 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1962 c->x86_vendor_id[0] = '\0'; /* Unset */
1963 c->x86_model_id[0] = '\0'; /* Unset */
1964#ifdef CONFIG_X86_64
1965 c->x86_clflush_size = 64;
1966 c->x86_phys_bits = 36;
1967 c->x86_virt_bits = 48;
1968#else
1969 c->cpuid_level = -1; /* CPUID not detected */
1970 c->x86_clflush_size = 32;
1971 c->x86_phys_bits = 32;
1972 c->x86_virt_bits = 32;
1973#endif
1974 c->x86_cache_alignment = c->x86_clflush_size;
1975 memset(s: &c->x86_capability, c: 0, n: sizeof(c->x86_capability));
1976#ifdef CONFIG_X86_VMX_FEATURE_NAMES
1977 memset(s: &c->vmx_capability, c: 0, n: sizeof(c->vmx_capability));
1978#endif
1979
1980 generic_identify(c);
1981
1982 cpu_parse_topology(c);
1983
1984 if (this_cpu->c_identify)
1985 this_cpu->c_identify(c);
1986
1987 /* Clear/Set all flags overridden by options, after probe */
1988 apply_forced_caps(c);
1989
1990 /*
1991 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and
1992 * Hygon will clear it in ->c_init() below.
1993 */
1994 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
1995
1996 /*
1997 * Vendor-specific initialization. In this section we
1998 * canonicalize the feature flags, meaning if there are
1999 * features a certain CPU supports which CPUID doesn't
2000 * tell us, CPUID claiming incorrect flags, or other bugs,
2001 * we handle them here.
2002 *
2003 * At the end of this section, c->x86_capability better
2004 * indicate the features this CPU genuinely supports!
2005 */
2006 if (this_cpu->c_init)
2007 this_cpu->c_init(c);
2008
2009 bus_lock_init();
2010
2011 /* Disable the PN if appropriate */
2012 squash_the_stupid_serial_number(c);
2013
2014 /* Set up SMEP/SMAP/UMIP */
2015 setup_smep(c);
2016 setup_smap(c);
2017 setup_umip(c);
2018
2019 /* Enable FSGSBASE instructions if available. */
2020 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
2021 cr4_set_bits(X86_CR4_FSGSBASE);
2022 elf_hwcap2 |= HWCAP2_FSGSBASE;
2023 }
2024
2025 /*
2026 * The vendor-specific functions might have changed features.
2027 * Now we do "generic changes."
2028 */
2029
2030 /* Filter out anything that depends on CPUID levels we don't have */
2031 filter_cpuid_features(c, warn: true);
2032
2033 /* Check for unmet dependencies based on the CPUID dependency table */
2034 check_cpufeature_deps(c);
2035
2036 /* If the model name is still unset, do table lookup. */
2037 if (!c->x86_model_id[0]) {
2038 const char *p;
2039 p = table_lookup_model(c);
2040 if (p)
2041 strcpy(c->x86_model_id, p);
2042 else
2043 /* Last resort... */
2044 sprintf(buf: c->x86_model_id, fmt: "%02x/%02x",
2045 c->x86, c->x86_model);
2046 }
2047
2048 x86_init_rdrand(c);
2049 setup_pku(c);
2050 setup_cet(c);
2051
2052 /*
2053 * Clear/Set all flags overridden by options, need do it
2054 * before following smp all cpus cap AND.
2055 */
2056 apply_forced_caps(c);
2057
2058 /*
2059 * On SMP, boot_cpu_data holds the common feature set between
2060 * all CPUs; so make sure that we indicate which features are
2061 * common between the CPUs. The first time this routine gets
2062 * executed, c == &boot_cpu_data.
2063 */
2064 if (c != &boot_cpu_data) {
2065 /* AND the already accumulated flags with these */
2066 for (i = 0; i < NCAPINTS; i++)
2067 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
2068
2069 /* OR, i.e. replicate the bug flags */
2070 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
2071 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
2072 }
2073
2074 ppin_init(c);
2075
2076 /* Init Machine Check Exception if available. */
2077 mcheck_cpu_init(c);
2078
2079 numa_add_cpu(smp_processor_id());
2080}
2081
2082/*
2083 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
2084 * on 32-bit kernels:
2085 */
2086#ifdef CONFIG_X86_32
2087void enable_sep_cpu(void)
2088{
2089 struct tss_struct *tss;
2090 int cpu;
2091
2092 if (!boot_cpu_has(X86_FEATURE_SEP))
2093 return;
2094
2095 cpu = get_cpu();
2096 tss = &per_cpu(cpu_tss_rw, cpu);
2097
2098 /*
2099 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
2100 * see the big comment in struct x86_hw_tss's definition.
2101 */
2102
2103 tss->x86_tss.ss1 = __KERNEL_CS;
2104 wrmsrq(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1);
2105 wrmsrq(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1));
2106 wrmsrq(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32);
2107
2108 put_cpu();
2109}
2110#endif
2111
2112static __init void identify_boot_cpu(void)
2113{
2114 identify_cpu(c: &boot_cpu_data);
2115 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
2116 pr_info("CET detected: Indirect Branch Tracking enabled\n");
2117#ifdef CONFIG_X86_32
2118 enable_sep_cpu();
2119#endif
2120 cpu_detect_tlb(c: &boot_cpu_data);
2121 setup_cr_pinning();
2122
2123 tsx_init();
2124 tdx_init();
2125 lkgs_init();
2126}
2127
2128void identify_secondary_cpu(unsigned int cpu)
2129{
2130 struct cpuinfo_x86 *c = &cpu_data(cpu);
2131
2132 /* Copy boot_cpu_data only on the first bringup */
2133 if (!c->initialized)
2134 *c = boot_cpu_data;
2135 c->cpu_index = cpu;
2136
2137 identify_cpu(c);
2138#ifdef CONFIG_X86_32
2139 enable_sep_cpu();
2140#endif
2141 x86_spec_ctrl_setup_ap();
2142 update_srbds_msr();
2143 if (boot_cpu_has_bug(X86_BUG_GDS))
2144 update_gds_msr();
2145
2146 tsx_ap_init();
2147 c->initialized = true;
2148}
2149
2150void print_cpu_info(struct cpuinfo_x86 *c)
2151{
2152 const char *vendor = NULL;
2153
2154 if (c->x86_vendor < X86_VENDOR_NUM) {
2155 vendor = this_cpu->c_vendor;
2156 } else {
2157 if (c->cpuid_level >= 0)
2158 vendor = c->x86_vendor_id;
2159 }
2160
2161 if (vendor && !strstr(c->x86_model_id, vendor))
2162 pr_cont("%s ", vendor);
2163
2164 if (c->x86_model_id[0])
2165 pr_cont("%s", c->x86_model_id);
2166 else
2167 pr_cont("%d86", c->x86);
2168
2169 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
2170
2171 if (c->x86_stepping || c->cpuid_level >= 0)
2172 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
2173 else
2174 pr_cont(")\n");
2175}
2176
2177/*
2178 * clearcpuid= and setcpuid= were already parsed in cpu_parse_early_param().
2179 * These dummy functions prevent them from becoming an environment variable for
2180 * init.
2181 */
2182
2183static __init int setup_clearcpuid(char *arg)
2184{
2185 return 1;
2186}
2187__setup("clearcpuid=", setup_clearcpuid);
2188
2189static __init int setup_setcpuid(char *arg)
2190{
2191 return 1;
2192}
2193__setup("setcpuid=", setup_setcpuid);
2194
2195DEFINE_PER_CPU_CACHE_HOT(struct task_struct *, current_task) = &init_task;
2196EXPORT_PER_CPU_SYMBOL(current_task);
2197EXPORT_PER_CPU_SYMBOL(const_current_task);
2198
2199DEFINE_PER_CPU_CACHE_HOT(int, __preempt_count) = INIT_PREEMPT_COUNT;
2200EXPORT_PER_CPU_SYMBOL(__preempt_count);
2201
2202DEFINE_PER_CPU_CACHE_HOT(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK;
2203
2204#ifdef CONFIG_X86_64
2205/*
2206 * Note: Do not make this dependant on CONFIG_MITIGATION_CALL_DEPTH_TRACKING
2207 * so that this space is reserved in the hot cache section even when the
2208 * mitigation is disabled.
2209 */
2210DEFINE_PER_CPU_CACHE_HOT(u64, __x86_call_depth);
2211EXPORT_PER_CPU_SYMBOL(__x86_call_depth);
2212
2213static void wrmsrq_cstar(unsigned long val)
2214{
2215 /*
2216 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
2217 * is so far ignored by the CPU, but raises a #VE trap in a TDX
2218 * guest. Avoid the pointless write on all Intel CPUs.
2219 */
2220 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2221 wrmsrq(MSR_CSTAR, val);
2222}
2223
2224static inline void idt_syscall_init(void)
2225{
2226 wrmsrq(MSR_LSTAR, val: (unsigned long)entry_SYSCALL_64);
2227
2228 if (ia32_enabled()) {
2229 wrmsrq_cstar(val: (unsigned long)entry_SYSCALL_compat);
2230 /*
2231 * This only works on Intel CPUs.
2232 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
2233 * This does not cause SYSENTER to jump to the wrong location, because
2234 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
2235 */
2236 wrmsrq_safe(MSR_IA32_SYSENTER_CS, val: (u64)__KERNEL_CS);
2237 wrmsrq_safe(MSR_IA32_SYSENTER_ESP,
2238 val: (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
2239 wrmsrq_safe(MSR_IA32_SYSENTER_EIP, val: (u64)entry_SYSENTER_compat);
2240 } else {
2241 wrmsrq_cstar(val: (unsigned long)entry_SYSCALL32_ignore);
2242 wrmsrq_safe(MSR_IA32_SYSENTER_CS, val: (u64)GDT_ENTRY_INVALID_SEG);
2243 wrmsrq_safe(MSR_IA32_SYSENTER_ESP, val: 0ULL);
2244 wrmsrq_safe(MSR_IA32_SYSENTER_EIP, val: 0ULL);
2245 }
2246
2247 /*
2248 * Flags to clear on syscall; clear as much as possible
2249 * to minimize user space-kernel interference.
2250 */
2251 wrmsrq(MSR_SYSCALL_MASK,
2252 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
2253 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
2254 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
2255 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
2256 X86_EFLAGS_AC|X86_EFLAGS_ID);
2257}
2258
2259/* May not be marked __init: used by software suspend */
2260void syscall_init(void)
2261{
2262 /* The default user and kernel segments */
2263 wrmsr(MSR_STAR, low: 0, high: (__USER32_CS << 16) | __KERNEL_CS);
2264
2265 /*
2266 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and
2267 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED
2268 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit
2269 * instruction to return to ring 3 (both sysexit and sysret cause
2270 * #UD when FRED is enabled).
2271 */
2272 if (!cpu_feature_enabled(X86_FEATURE_FRED))
2273 idt_syscall_init();
2274}
2275#endif /* CONFIG_X86_64 */
2276
2277#ifdef CONFIG_STACKPROTECTOR
2278DEFINE_PER_CPU_CACHE_HOT(unsigned long, __stack_chk_guard);
2279#ifndef CONFIG_SMP
2280EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
2281#endif
2282#endif
2283
2284static void initialize_debug_regs(void)
2285{
2286 /* Control register first -- to make sure everything is disabled. */
2287 set_debugreg(DR7_FIXED_1, 7);
2288 set_debugreg(DR6_RESERVED, 6);
2289 /* dr5 and dr4 don't exist */
2290 set_debugreg(0, 3);
2291 set_debugreg(0, 2);
2292 set_debugreg(0, 1);
2293 set_debugreg(0, 0);
2294}
2295
2296#ifdef CONFIG_KGDB
2297/*
2298 * Restore debug regs if using kgdbwait and you have a kernel debugger
2299 * connection established.
2300 */
2301static void dbg_restore_debug_regs(void)
2302{
2303 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
2304 arch_kgdb_ops.correct_hw_break();
2305}
2306#else /* ! CONFIG_KGDB */
2307#define dbg_restore_debug_regs()
2308#endif /* ! CONFIG_KGDB */
2309
2310static inline void setup_getcpu(int cpu)
2311{
2312 unsigned long cpudata = vdso_encode_cpunode(cpu, node: early_cpu_to_node(cpu));
2313 struct desc_struct d = { };
2314
2315 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2316 wrmsrq(MSR_TSC_AUX, val: cpudata);
2317
2318 /* Store CPU and node number in limit. */
2319 d.limit0 = cpudata;
2320 d.limit1 = cpudata >> 16;
2321
2322 d.type = 5; /* RO data, expand down, accessed */
2323 d.dpl = 3; /* Visible to user code */
2324 d.s = 1; /* Not a system segment */
2325 d.p = 1; /* Present */
2326 d.d = 1; /* 32-bit */
2327
2328 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2329}
2330
2331#ifdef CONFIG_X86_64
2332static inline void tss_setup_ist(struct tss_struct *tss)
2333{
2334 /* Set up the per-CPU TSS IST stacks */
2335 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2336 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2337 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2338 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2339 /* Only mapped when SEV-ES is active */
2340 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2341}
2342#else /* CONFIG_X86_64 */
2343static inline void tss_setup_ist(struct tss_struct *tss) { }
2344#endif /* !CONFIG_X86_64 */
2345
2346static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2347{
2348 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2349
2350#ifdef CONFIG_X86_IOPL_IOPERM
2351 tss->io_bitmap.prev_max = 0;
2352 tss->io_bitmap.prev_sequence = 0;
2353 memset(s: tss->io_bitmap.bitmap, c: 0xff, n: sizeof(tss->io_bitmap.bitmap));
2354 /*
2355 * Invalidate the extra array entry past the end of the all
2356 * permission bitmap as required by the hardware.
2357 */
2358 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2359#endif
2360}
2361
2362/*
2363 * Setup everything needed to handle exceptions from the IDT, including the IST
2364 * exceptions which use paranoid_entry().
2365 */
2366void cpu_init_exception_handling(bool boot_cpu)
2367{
2368 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2369 int cpu = raw_smp_processor_id();
2370
2371 /* paranoid_entry() gets the CPU number from the GDT */
2372 setup_getcpu(cpu);
2373
2374 /* For IDT mode, IST vectors need to be set in TSS. */
2375 if (!cpu_feature_enabled(X86_FEATURE_FRED))
2376 tss_setup_ist(tss);
2377 tss_setup_io_bitmap(tss);
2378 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2379
2380 load_TR_desc();
2381
2382 /* GHCB needs to be setup to handle #VC. */
2383 setup_ghcb();
2384
2385 if (cpu_feature_enabled(X86_FEATURE_FRED)) {
2386 /* The boot CPU has enabled FRED during early boot */
2387 if (!boot_cpu)
2388 cpu_init_fred_exceptions();
2389
2390 cpu_init_fred_rsps();
2391 } else {
2392 load_current_idt();
2393 }
2394}
2395
2396void __init cpu_init_replace_early_idt(void)
2397{
2398 if (cpu_feature_enabled(X86_FEATURE_FRED))
2399 cpu_init_fred_exceptions();
2400 else
2401 idt_setup_early_pf();
2402}
2403
2404/*
2405 * cpu_init() initializes state that is per-CPU. Some data is already
2406 * initialized (naturally) in the bootstrap process, such as the GDT. We
2407 * reload it nevertheless, this function acts as a 'CPU state barrier',
2408 * nothing should get across.
2409 */
2410void cpu_init(void)
2411{
2412 struct task_struct *cur = current;
2413 int cpu = raw_smp_processor_id();
2414
2415#ifdef CONFIG_NUMA
2416 if (this_cpu_read(numa_node) == 0 &&
2417 early_cpu_to_node(cpu) != NUMA_NO_NODE)
2418 set_numa_node(early_cpu_to_node(cpu));
2419#endif
2420 pr_debug("Initializing CPU#%d\n", cpu);
2421
2422 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2423 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2424 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2425
2426 if (IS_ENABLED(CONFIG_X86_64)) {
2427 loadsegment(fs, 0);
2428 memset(s: cur->thread.tls_array, c: 0, GDT_ENTRY_TLS_ENTRIES * 8);
2429 syscall_init();
2430
2431 wrmsrq(MSR_FS_BASE, val: 0);
2432 wrmsrq(MSR_KERNEL_GS_BASE, val: 0);
2433 barrier();
2434
2435 x2apic_setup();
2436
2437 intel_posted_msi_init();
2438 }
2439
2440 mmgrab(mm: &init_mm);
2441 cur->active_mm = &init_mm;
2442 BUG_ON(cur->mm);
2443 initialize_tlbstate_and_flush();
2444 enter_lazy_tlb(mm: &init_mm, tsk: cur);
2445
2446 /*
2447 * sp0 points to the entry trampoline stack regardless of what task
2448 * is running.
2449 */
2450 load_sp0(sp0: (unsigned long)(cpu_entry_stack(cpu) + 1));
2451
2452 load_mm_ldt(mm: &init_mm);
2453
2454 initialize_debug_regs();
2455 dbg_restore_debug_regs();
2456
2457 doublefault_init_cpu_tss();
2458
2459 if (is_uv_system())
2460 uv_cpu_init();
2461
2462 load_fixmap_gdt(cpu);
2463}
2464
2465#ifdef CONFIG_MICROCODE_LATE_LOADING
2466/**
2467 * store_cpu_caps() - Store a snapshot of CPU capabilities
2468 * @curr_info: Pointer where to store it
2469 *
2470 * Returns: None
2471 */
2472void store_cpu_caps(struct cpuinfo_x86 *curr_info)
2473{
2474 /* Reload CPUID max function as it might've changed. */
2475 curr_info->cpuid_level = cpuid_eax(0);
2476
2477 /* Copy all capability leafs and pick up the synthetic ones. */
2478 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability,
2479 sizeof(curr_info->x86_capability));
2480
2481 /* Get the hardware CPUID leafs */
2482 get_cpu_cap(curr_info);
2483}
2484
2485/**
2486 * microcode_check() - Check if any CPU capabilities changed after an update.
2487 * @prev_info: CPU capabilities stored before an update.
2488 *
2489 * The microcode loader calls this upon late microcode load to recheck features,
2490 * only when microcode has been updated. Caller holds and CPU hotplug lock.
2491 *
2492 * Return: None
2493 */
2494void microcode_check(struct cpuinfo_x86 *prev_info)
2495{
2496 struct cpuinfo_x86 curr_info;
2497
2498 perf_check_microcode();
2499
2500 amd_check_microcode();
2501
2502 store_cpu_caps(&curr_info);
2503
2504 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
2505 sizeof(prev_info->x86_capability)))
2506 return;
2507
2508 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2509 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2510}
2511#endif
2512
2513/*
2514 * Invoked from core CPU hotplug code after hotplug operations
2515 */
2516void arch_smt_update(void)
2517{
2518 /* Handle the speculative execution misfeatures */
2519 cpu_bugs_smt_update();
2520 /* Check whether IPI broadcasting can be enabled */
2521 apic_smt_update();
2522}
2523
2524void __init arch_cpu_finalize_init(void)
2525{
2526 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info);
2527
2528 identify_boot_cpu();
2529
2530 select_idle_routine();
2531
2532 /*
2533 * identify_boot_cpu() initialized SMT support information, let the
2534 * core code know.
2535 */
2536 cpu_smt_set_num_threads(num_threads: __max_threads_per_core, max_threads: __max_threads_per_core);
2537
2538 if (!IS_ENABLED(CONFIG_SMP)) {
2539 pr_info("CPU: ");
2540 print_cpu_info(c: &boot_cpu_data);
2541 }
2542
2543 cpu_select_mitigations();
2544
2545 arch_smt_update();
2546
2547 if (IS_ENABLED(CONFIG_X86_32)) {
2548 /*
2549 * Check whether this is a real i386 which is not longer
2550 * supported and fixup the utsname.
2551 */
2552 if (boot_cpu_data.x86 < 4)
2553 panic(fmt: "Kernel requires i486+ for 'invlpg' and other features");
2554
2555 init_utsname()->machine[1] =
2556 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
2557 }
2558
2559 /*
2560 * Must be before alternatives because it might set or clear
2561 * feature bits.
2562 */
2563 fpu__init_system();
2564 fpu__init_cpu();
2565
2566 /*
2567 * This needs to follow the FPU initializtion, since EFI depends on it.
2568 */
2569 if (efi_enabled(EFI_RUNTIME_SERVICES))
2570 efi_enter_virtual_mode();
2571
2572 /*
2573 * Ensure that access to the per CPU representation has the initial
2574 * boot CPU configuration.
2575 */
2576 *c = boot_cpu_data;
2577 c->initialized = true;
2578
2579 alternative_instructions();
2580
2581 if (IS_ENABLED(CONFIG_X86_64)) {
2582 unsigned long USER_PTR_MAX = TASK_SIZE_MAX;
2583
2584 /*
2585 * Enable this when LAM is gated on LASS support
2586 if (cpu_feature_enabled(X86_FEATURE_LAM))
2587 USER_PTR_MAX = (1ul << 63) - PAGE_SIZE;
2588 */
2589 runtime_const_init(ptr, USER_PTR_MAX);
2590
2591 /*
2592 * Make sure the first 2MB area is not mapped by huge pages
2593 * There are typically fixed size MTRRs in there and overlapping
2594 * MTRRs into large pages causes slow downs.
2595 *
2596 * Right now we don't do that with gbpages because there seems
2597 * very little benefit for that case.
2598 */
2599 if (!direct_gbpages)
2600 set_memory_4k(addr: (unsigned long)__va(0), numpages: 1);
2601 } else {
2602 fpu__init_check_bugs();
2603 }
2604
2605 /*
2606 * This needs to be called before any devices perform DMA
2607 * operations that might use the SWIOTLB bounce buffers. It will
2608 * mark the bounce buffers as decrypted so that their usage will
2609 * not cause "plain-text" data to be decrypted when accessed. It
2610 * must be called after late_time_init() so that Hyper-V x86/x64
2611 * hypercalls work when the SWIOTLB bounce buffers are decrypted.
2612 */
2613 mem_encrypt_init();
2614}
2615