1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24/**
25 * DOC: Frame Buffer Compression (FBC)
26 *
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
30 *
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
34 *
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
39 */
40
41#include <linux/debugfs.h>
42#include <linux/string_helpers.h>
43
44#include <drm/drm_blend.h>
45#include <drm/drm_fourcc.h>
46
47#include "gem/i915_gem_stolen.h"
48
49#include "gt/intel_gt_types.h"
50
51#include "i915_drv.h"
52#include "i915_utils.h"
53#include "i915_vgpu.h"
54#include "i915_vma.h"
55#include "i9xx_plane_regs.h"
56#include "intel_cdclk.h"
57#include "intel_de.h"
58#include "intel_display_device.h"
59#include "intel_display_regs.h"
60#include "intel_display_rpm.h"
61#include "intel_display_trace.h"
62#include "intel_display_types.h"
63#include "intel_display_wa.h"
64#include "intel_fbc.h"
65#include "intel_fbc_regs.h"
66#include "intel_frontbuffer.h"
67
68#define for_each_fbc_id(__display, __fbc_id) \
69 for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
70 for_each_if(DISPLAY_RUNTIME_INFO(__display)->fbc_mask & BIT(__fbc_id))
71
72#define for_each_intel_fbc(__display, __fbc, __fbc_id) \
73 for_each_fbc_id((__display), (__fbc_id)) \
74 for_each_if((__fbc) = (__display)->fbc[(__fbc_id)])
75
76struct intel_fbc_funcs {
77 void (*activate)(struct intel_fbc *fbc);
78 void (*deactivate)(struct intel_fbc *fbc);
79 bool (*is_active)(struct intel_fbc *fbc);
80 bool (*is_compressing)(struct intel_fbc *fbc);
81 void (*nuke)(struct intel_fbc *fbc);
82 void (*program_cfb)(struct intel_fbc *fbc);
83 void (*set_false_color)(struct intel_fbc *fbc, bool enable);
84};
85
86struct intel_fbc_state {
87 struct intel_plane *plane;
88 unsigned int cfb_stride;
89 unsigned int cfb_size;
90 unsigned int fence_y_offset;
91 u16 override_cfb_stride;
92 u16 interval;
93 s8 fence_id;
94 struct drm_rect dirty_rect;
95};
96
97struct intel_fbc {
98 struct intel_display *display;
99 const struct intel_fbc_funcs *funcs;
100
101 /* This is always the outer lock when overlapping with stolen_lock */
102 struct mutex lock;
103 unsigned int busy_bits;
104
105 struct i915_stolen_fb compressed_fb, compressed_llb;
106
107 enum intel_fbc_id id;
108
109 u8 limit;
110
111 bool false_color;
112
113 bool active;
114 bool activated;
115 bool flip_pending;
116
117 bool underrun_detected;
118 struct work_struct underrun_work;
119
120 /*
121 * This structure contains everything that's relevant to program the
122 * hardware registers. When we want to figure out if we need to disable
123 * and re-enable FBC for a new configuration we just check if there's
124 * something different in the struct. The genx_fbc_activate functions
125 * are supposed to read from it in order to program the registers.
126 */
127 struct intel_fbc_state state;
128 const char *no_fbc_reason;
129};
130
131/* plane stride in pixels */
132static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
133{
134 const struct drm_framebuffer *fb = plane_state->hw.fb;
135 unsigned int stride;
136
137 stride = plane_state->view.color_plane[0].mapping_stride;
138 if (!drm_rotation_90_or_270(rotation: plane_state->hw.rotation))
139 stride /= fb->format->cpp[0];
140
141 return stride;
142}
143
144static unsigned int intel_fbc_cfb_cpp(void)
145{
146 return 4; /* FBC always 4 bytes per pixel */
147}
148
149/* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
150static unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state *plane_state)
151{
152 unsigned int cpp = intel_fbc_cfb_cpp();
153
154 return intel_fbc_plane_stride(plane_state) * cpp;
155}
156
157/* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */
158static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display,
159 unsigned int cpp, unsigned int width)
160{
161 unsigned int limit = 4; /* 1:4 compression limit is the worst case */
162 unsigned int height = 4; /* FBC segment is 4 lines */
163 unsigned int stride;
164
165 /* minimum segment stride we can use */
166 stride = width * cpp * height / limit;
167
168 /*
169 * Wa_16011863758: icl+
170 * Avoid some hardware segment address miscalculation.
171 */
172 if (DISPLAY_VER(display) >= 11)
173 stride += 64;
174
175 /*
176 * At least some of the platforms require each 4 line segment to
177 * be 512 byte aligned. Just do it always for simplicity.
178 */
179 stride = ALIGN(stride, 512);
180
181 /* convert back to single line equivalent with 1:1 compression limit */
182 return stride * limit / height;
183}
184
185/* properly aligned cfb stride in bytes, assuming 1:1 compression limit */
186static unsigned int _intel_fbc_cfb_stride(struct intel_display *display,
187 unsigned int cpp, unsigned int width,
188 unsigned int stride)
189{
190 /*
191 * At least some of the platforms require each 4 line segment to
192 * be 512 byte aligned. Aligning each line to 512 bytes guarantees
193 * that regardless of the compression limit we choose later.
194 */
195 if (DISPLAY_VER(display) >= 9)
196 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width));
197 else
198 return stride;
199}
200
201static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
202{
203 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
204 unsigned int stride = intel_fbc_plane_cfb_stride(plane_state);
205 unsigned int width = drm_rect_width(r: &plane_state->uapi.src) >> 16;
206 unsigned int cpp = intel_fbc_cfb_cpp();
207
208 return _intel_fbc_cfb_stride(display, cpp, width, stride);
209}
210
211/*
212 * Maximum height the hardware will compress, on HSW+
213 * additional lines (up to the actual plane height) will
214 * remain uncompressed.
215 */
216static unsigned int intel_fbc_max_cfb_height(struct intel_display *display)
217{
218 if (DISPLAY_VER(display) >= 8)
219 return 2560;
220 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
221 return 2048;
222 else
223 return 1536;
224}
225
226static unsigned int _intel_fbc_cfb_size(struct intel_display *display,
227 unsigned int height, unsigned int stride)
228{
229 return min(height, intel_fbc_max_cfb_height(display)) * stride;
230}
231
232static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state)
233{
234 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
235 unsigned int height = drm_rect_height(r: &plane_state->uapi.src) >> 16;
236
237 return _intel_fbc_cfb_size(display, height, stride: intel_fbc_cfb_stride(plane_state));
238}
239
240static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state)
241{
242 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
243 unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);
244 unsigned int stride = intel_fbc_plane_cfb_stride(plane_state);
245 const struct drm_framebuffer *fb = plane_state->hw.fb;
246
247 /*
248 * Override stride in 64 byte units per 4 line segment.
249 *
250 * Gen9 hw miscalculates cfb stride for linear as
251 * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
252 * we always need to use the override there.
253 *
254 * wa_14022269668 For bmg, always program the FBC_STRIDE before fbc enable
255 */
256 if (stride != stride_aligned ||
257 (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR) ||
258 display->platform.battlemage)
259 return stride_aligned * 4 / 64;
260
261 return 0;
262}
263
264static bool intel_fbc_has_fences(struct intel_display *display)
265{
266 struct drm_i915_private __maybe_unused *i915 = to_i915(dev: display->drm);
267
268 return intel_gt_support_legacy_fencing(to_gt(i915));
269}
270
271static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
272{
273 struct intel_display *display = fbc->display;
274 const struct intel_fbc_state *fbc_state = &fbc->state;
275 unsigned int cfb_stride;
276 u32 fbc_ctl;
277
278 cfb_stride = fbc_state->cfb_stride / fbc->limit;
279
280 /* FBC_CTL wants 32B or 64B units */
281 if (DISPLAY_VER(display) == 2)
282 cfb_stride = (cfb_stride / 32) - 1;
283 else
284 cfb_stride = (cfb_stride / 64) - 1;
285
286 fbc_ctl = FBC_CTL_PERIODIC |
287 FBC_CTL_INTERVAL(fbc_state->interval) |
288 FBC_CTL_STRIDE(cfb_stride);
289
290 if (display->platform.i945gm)
291 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
292
293 if (fbc_state->fence_id >= 0)
294 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id);
295
296 return fbc_ctl;
297}
298
299static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
300{
301 const struct intel_fbc_state *fbc_state = &fbc->state;
302 u32 fbc_ctl2;
303
304 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
305 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);
306
307 if (fbc_state->fence_id >= 0)
308 fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
309
310 return fbc_ctl2;
311}
312
313static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
314{
315 struct intel_display *display = fbc->display;
316 u32 fbc_ctl;
317
318 /* Disable compression */
319 fbc_ctl = intel_de_read(display, FBC_CONTROL);
320 if ((fbc_ctl & FBC_CTL_EN) == 0)
321 return;
322
323 fbc_ctl &= ~FBC_CTL_EN;
324 intel_de_write(display, FBC_CONTROL, val: fbc_ctl);
325
326 /* Wait for compressing bit to clear */
327 if (intel_de_wait_for_clear(display, FBC_STATUS,
328 FBC_STAT_COMPRESSING, timeout_ms: 10)) {
329 drm_dbg_kms(display->drm, "FBC idle timed out\n");
330 return;
331 }
332}
333
334static void i8xx_fbc_activate(struct intel_fbc *fbc)
335{
336 struct intel_display *display = fbc->display;
337 const struct intel_fbc_state *fbc_state = &fbc->state;
338 int i;
339
340 /* Clear old tags */
341 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
342 intel_de_write(display, FBC_TAG(i), val: 0);
343
344 if (DISPLAY_VER(display) == 4) {
345 intel_de_write(display, FBC_CONTROL2,
346 val: i965_fbc_ctl2(fbc));
347 intel_de_write(display, FBC_FENCE_OFF,
348 val: fbc_state->fence_y_offset);
349 }
350
351 intel_de_write(display, FBC_CONTROL,
352 FBC_CTL_EN | i8xx_fbc_ctl(fbc));
353}
354
355static bool i8xx_fbc_is_active(struct intel_fbc *fbc)
356{
357 return intel_de_read(display: fbc->display, FBC_CONTROL) & FBC_CTL_EN;
358}
359
360static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
361{
362 return intel_de_read(display: fbc->display, FBC_STATUS) &
363 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
364}
365
366static void i8xx_fbc_nuke(struct intel_fbc *fbc)
367{
368 struct intel_display *display = fbc->display;
369 struct intel_fbc_state *fbc_state = &fbc->state;
370 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
371
372 intel_de_write_fw(display, DSPADDR(display, i9xx_plane),
373 val: intel_de_read_fw(display, DSPADDR(display, i9xx_plane)));
374}
375
376static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
377{
378 struct intel_display *display = fbc->display;
379 struct drm_i915_private *i915 = to_i915(dev: display->drm);
380
381 drm_WARN_ON(display->drm,
382 range_end_overflows_t(u64, i915_gem_stolen_area_address(i915),
383 i915_gem_stolen_node_offset(&fbc->compressed_fb),
384 U32_MAX));
385 drm_WARN_ON(display->drm,
386 range_end_overflows_t(u64, i915_gem_stolen_area_address(i915),
387 i915_gem_stolen_node_offset(&fbc->compressed_llb),
388 U32_MAX));
389 intel_de_write(display, FBC_CFB_BASE,
390 val: i915_gem_stolen_node_address(i915, node: &fbc->compressed_fb));
391 intel_de_write(display, FBC_LL_BASE,
392 val: i915_gem_stolen_node_address(i915, node: &fbc->compressed_llb));
393}
394
395static const struct intel_fbc_funcs i8xx_fbc_funcs = {
396 .activate = i8xx_fbc_activate,
397 .deactivate = i8xx_fbc_deactivate,
398 .is_active = i8xx_fbc_is_active,
399 .is_compressing = i8xx_fbc_is_compressing,
400 .nuke = i8xx_fbc_nuke,
401 .program_cfb = i8xx_fbc_program_cfb,
402};
403
404static void i965_fbc_nuke(struct intel_fbc *fbc)
405{
406 struct intel_display *display = fbc->display;
407 struct intel_fbc_state *fbc_state = &fbc->state;
408 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
409
410 intel_de_write_fw(display, DSPSURF(display, i9xx_plane),
411 val: intel_de_read_fw(display, DSPSURF(display, i9xx_plane)));
412}
413
414static const struct intel_fbc_funcs i965_fbc_funcs = {
415 .activate = i8xx_fbc_activate,
416 .deactivate = i8xx_fbc_deactivate,
417 .is_active = i8xx_fbc_is_active,
418 .is_compressing = i8xx_fbc_is_compressing,
419 .nuke = i965_fbc_nuke,
420 .program_cfb = i8xx_fbc_program_cfb,
421};
422
423static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
424{
425 switch (fbc->limit) {
426 default:
427 MISSING_CASE(fbc->limit);
428 fallthrough;
429 case 1:
430 return DPFC_CTL_LIMIT_1X;
431 case 2:
432 return DPFC_CTL_LIMIT_2X;
433 case 4:
434 return DPFC_CTL_LIMIT_4X;
435 }
436}
437
438static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
439{
440 struct intel_display *display = fbc->display;
441 const struct intel_fbc_state *fbc_state = &fbc->state;
442 u32 dpfc_ctl;
443
444 dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
445 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);
446
447 if (display->platform.g4x)
448 dpfc_ctl |= DPFC_CTL_SR_EN;
449
450 if (fbc_state->fence_id >= 0) {
451 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X;
452
453 if (DISPLAY_VER(display) < 6)
454 dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id);
455 }
456
457 return dpfc_ctl;
458}
459
460static void g4x_fbc_activate(struct intel_fbc *fbc)
461{
462 struct intel_display *display = fbc->display;
463 const struct intel_fbc_state *fbc_state = &fbc->state;
464
465 intel_de_write(display, DPFC_FENCE_YOFF,
466 val: fbc_state->fence_y_offset);
467
468 intel_de_write(display, DPFC_CONTROL,
469 DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
470}
471
472static void g4x_fbc_deactivate(struct intel_fbc *fbc)
473{
474 struct intel_display *display = fbc->display;
475 u32 dpfc_ctl;
476
477 /* Disable compression */
478 dpfc_ctl = intel_de_read(display, DPFC_CONTROL);
479 if (dpfc_ctl & DPFC_CTL_EN) {
480 dpfc_ctl &= ~DPFC_CTL_EN;
481 intel_de_write(display, DPFC_CONTROL, val: dpfc_ctl);
482 }
483}
484
485static bool g4x_fbc_is_active(struct intel_fbc *fbc)
486{
487 return intel_de_read(display: fbc->display, DPFC_CONTROL) & DPFC_CTL_EN;
488}
489
490static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
491{
492 return intel_de_read(display: fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
493}
494
495static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
496{
497 struct intel_display *display = fbc->display;
498
499 intel_de_write(display, DPFC_CB_BASE,
500 val: i915_gem_stolen_node_offset(node: &fbc->compressed_fb));
501}
502
503static const struct intel_fbc_funcs g4x_fbc_funcs = {
504 .activate = g4x_fbc_activate,
505 .deactivate = g4x_fbc_deactivate,
506 .is_active = g4x_fbc_is_active,
507 .is_compressing = g4x_fbc_is_compressing,
508 .nuke = i965_fbc_nuke,
509 .program_cfb = g4x_fbc_program_cfb,
510};
511
512static void ilk_fbc_activate(struct intel_fbc *fbc)
513{
514 struct intel_display *display = fbc->display;
515 struct intel_fbc_state *fbc_state = &fbc->state;
516
517 intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id),
518 val: fbc_state->fence_y_offset);
519
520 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
521 DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
522}
523
524static void fbc_compressor_clkgate_disable_wa(struct intel_fbc *fbc,
525 bool disable)
526{
527 struct intel_display *display = fbc->display;
528
529 if (display->platform.dg2)
530 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, DG2_DPFC_GATING_DIS,
531 set: disable ? DG2_DPFC_GATING_DIS : 0);
532 else if (DISPLAY_VER(display) >= 14)
533 intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc->id),
534 MTL_DPFC_GATING_DIS,
535 set: disable ? MTL_DPFC_GATING_DIS : 0);
536}
537
538static void ilk_fbc_deactivate(struct intel_fbc *fbc)
539{
540 struct intel_display *display = fbc->display;
541 u32 dpfc_ctl;
542
543 if (HAS_FBC_DIRTY_RECT(display))
544 intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), val: 0);
545
546 /* Disable compression */
547 dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));
548 if (dpfc_ctl & DPFC_CTL_EN) {
549 dpfc_ctl &= ~DPFC_CTL_EN;
550 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), val: dpfc_ctl);
551 }
552}
553
554static bool ilk_fbc_is_active(struct intel_fbc *fbc)
555{
556 return intel_de_read(display: fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
557}
558
559static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
560{
561 return intel_de_read(display: fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
562}
563
564static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
565{
566 struct intel_display *display = fbc->display;
567
568 intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
569 val: i915_gem_stolen_node_offset(node: &fbc->compressed_fb));
570}
571
572static const struct intel_fbc_funcs ilk_fbc_funcs = {
573 .activate = ilk_fbc_activate,
574 .deactivate = ilk_fbc_deactivate,
575 .is_active = ilk_fbc_is_active,
576 .is_compressing = ilk_fbc_is_compressing,
577 .nuke = i965_fbc_nuke,
578 .program_cfb = ilk_fbc_program_cfb,
579};
580
581static void snb_fbc_program_fence(struct intel_fbc *fbc)
582{
583 struct intel_display *display = fbc->display;
584 const struct intel_fbc_state *fbc_state = &fbc->state;
585 u32 ctl = 0;
586
587 if (fbc_state->fence_id >= 0)
588 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id);
589
590 intel_de_write(display, SNB_DPFC_CTL_SA, val: ctl);
591 intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, val: fbc_state->fence_y_offset);
592}
593
594static void snb_fbc_activate(struct intel_fbc *fbc)
595{
596 snb_fbc_program_fence(fbc);
597
598 ilk_fbc_activate(fbc);
599}
600
601static void snb_fbc_nuke(struct intel_fbc *fbc)
602{
603 struct intel_display *display = fbc->display;
604
605 intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
606 intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id));
607}
608
609static const struct intel_fbc_funcs snb_fbc_funcs = {
610 .activate = snb_fbc_activate,
611 .deactivate = ilk_fbc_deactivate,
612 .is_active = ilk_fbc_is_active,
613 .is_compressing = ilk_fbc_is_compressing,
614 .nuke = snb_fbc_nuke,
615 .program_cfb = ilk_fbc_program_cfb,
616};
617
618static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
619{
620 struct intel_display *display = fbc->display;
621 const struct intel_fbc_state *fbc_state = &fbc->state;
622 u32 val = 0;
623
624 if (fbc_state->override_cfb_stride)
625 val |= FBC_STRIDE_OVERRIDE |
626 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
627
628 intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val);
629}
630
631static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
632{
633 struct intel_display *display = fbc->display;
634 const struct intel_fbc_state *fbc_state = &fbc->state;
635 u32 val = 0;
636
637 /* Display WA #0529: skl, kbl, bxt. */
638 if (fbc_state->override_cfb_stride)
639 val |= CHICKEN_FBC_STRIDE_OVERRIDE |
640 CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
641
642 intel_de_rmw(display, CHICKEN_MISC_4,
643 CHICKEN_FBC_STRIDE_OVERRIDE |
644 CHICKEN_FBC_STRIDE_MASK, set: val);
645}
646
647static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
648{
649 struct intel_display *display = fbc->display;
650 const struct intel_fbc_state *fbc_state = &fbc->state;
651 u32 dpfc_ctl;
652
653 dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
654
655 if (display->platform.ivybridge)
656 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane);
657
658 if (DISPLAY_VER(display) >= 20)
659 dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id);
660
661 if (fbc_state->fence_id >= 0)
662 dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
663
664 if (fbc->false_color)
665 dpfc_ctl |= DPFC_CTL_FALSE_COLOR;
666
667 return dpfc_ctl;
668}
669
670static void ivb_fbc_activate(struct intel_fbc *fbc)
671{
672 struct intel_display *display = fbc->display;
673 u32 dpfc_ctl;
674
675 if (DISPLAY_VER(display) >= 10)
676 glk_fbc_program_cfb_stride(fbc);
677 else if (DISPLAY_VER(display) == 9)
678 skl_fbc_program_cfb_stride(fbc);
679
680 if (intel_fbc_has_fences(display))
681 snb_fbc_program_fence(fbc);
682
683 /* wa_14019417088 Alternative WA*/
684 dpfc_ctl = ivb_dpfc_ctl(fbc);
685 if (DISPLAY_VER(display) >= 20)
686 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), val: dpfc_ctl);
687
688 if (HAS_FBC_DIRTY_RECT(display))
689 intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),
690 FBC_DIRTY_RECT_EN);
691
692 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
693 DPFC_CTL_EN | dpfc_ctl);
694}
695
696static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
697{
698 return intel_de_read(display: fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
699}
700
701static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
702 bool enable)
703{
704 intel_de_rmw(display: fbc->display, ILK_DPFC_CONTROL(fbc->id),
705 DPFC_CTL_FALSE_COLOR, set: enable ? DPFC_CTL_FALSE_COLOR : 0);
706}
707
708static const struct intel_fbc_funcs ivb_fbc_funcs = {
709 .activate = ivb_fbc_activate,
710 .deactivate = ilk_fbc_deactivate,
711 .is_active = ilk_fbc_is_active,
712 .is_compressing = ivb_fbc_is_compressing,
713 .nuke = snb_fbc_nuke,
714 .program_cfb = ilk_fbc_program_cfb,
715 .set_false_color = ivb_fbc_set_false_color,
716};
717
718static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
719{
720 return fbc->funcs->is_active(fbc);
721}
722
723static void intel_fbc_hw_activate(struct intel_fbc *fbc)
724{
725 trace_intel_fbc_activate(plane: fbc->state.plane);
726
727 fbc->active = true;
728 fbc->activated = true;
729
730 fbc->funcs->activate(fbc);
731}
732
733static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
734{
735 trace_intel_fbc_deactivate(plane: fbc->state.plane);
736
737 fbc->active = false;
738
739 fbc->funcs->deactivate(fbc);
740}
741
742static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
743{
744 return fbc->funcs->is_compressing(fbc);
745}
746
747static void intel_fbc_nuke(struct intel_fbc *fbc)
748{
749 struct intel_display *display = fbc->display;
750
751 lockdep_assert_held(&fbc->lock);
752 drm_WARN_ON(display->drm, fbc->flip_pending);
753
754 trace_intel_fbc_nuke(plane: fbc->state.plane);
755
756 fbc->funcs->nuke(fbc);
757}
758
759static void intel_fbc_activate(struct intel_fbc *fbc)
760{
761 struct intel_display *display = fbc->display;
762
763 lockdep_assert_held(&fbc->lock);
764
765 /* only the fence can change for a flip nuke */
766 if (fbc->active && !intel_fbc_has_fences(display))
767 return;
768 /*
769 * In case of FBC dirt rect, any updates to the FBC registers will
770 * trigger the nuke.
771 */
772 drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display));
773
774 intel_fbc_hw_activate(fbc);
775 intel_fbc_nuke(fbc);
776
777 fbc->no_fbc_reason = NULL;
778}
779
780static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason)
781{
782 lockdep_assert_held(&fbc->lock);
783
784 if (fbc->active)
785 intel_fbc_hw_deactivate(fbc);
786
787 fbc->no_fbc_reason = reason;
788}
789
790static u64 intel_fbc_cfb_base_max(struct intel_display *display)
791{
792 if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
793 return BIT_ULL(28);
794 else
795 return BIT_ULL(32);
796}
797
798static u64 intel_fbc_stolen_end(struct intel_display *display)
799{
800 struct drm_i915_private __maybe_unused *i915 = to_i915(dev: display->drm);
801 u64 end;
802
803 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
804 * reserved range size, so it always assumes the maximum (8mb) is used.
805 * If we enable FBC using a CFB on that memory range we'll get FIFO
806 * underruns, even if that range is not reserved by the BIOS. */
807 if (display->platform.broadwell ||
808 (DISPLAY_VER(display) == 9 && !display->platform.broxton))
809 end = i915_gem_stolen_area_size(i915) - 8 * 1024 * 1024;
810 else
811 end = U64_MAX;
812
813 return min(end, intel_fbc_cfb_base_max(display));
814}
815
816static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)
817{
818 return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;
819}
820
821static int intel_fbc_max_limit(struct intel_display *display)
822{
823 /* WaFbcOnly1to1Ratio:ctg */
824 if (display->platform.g4x)
825 return 1;
826
827 /*
828 * FBC2 can only do 1:1, 1:2, 1:4, we limit
829 * FBC1 to the same out of convenience.
830 */
831 return 4;
832}
833
834static int find_compression_limit(struct intel_fbc *fbc,
835 unsigned int size, int min_limit)
836{
837 struct intel_display *display = fbc->display;
838 struct drm_i915_private *i915 = to_i915(dev: display->drm);
839 u64 end = intel_fbc_stolen_end(display);
840 int ret, limit = min_limit;
841
842 size /= limit;
843
844 /* Try to over-allocate to reduce reallocations and fragmentation. */
845 ret = i915_gem_stolen_insert_node_in_range(i915, node: &fbc->compressed_fb,
846 size: size <<= 1, alignment: 4096, start: 0, end);
847 if (ret == 0)
848 return limit;
849
850 for (; limit <= intel_fbc_max_limit(display); limit <<= 1) {
851 ret = i915_gem_stolen_insert_node_in_range(i915, node: &fbc->compressed_fb,
852 size: size >>= 1, alignment: 4096, start: 0, end);
853 if (ret == 0)
854 return limit;
855 }
856
857 return 0;
858}
859
860static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
861 unsigned int size, int min_limit)
862{
863 struct intel_display *display = fbc->display;
864 struct drm_i915_private *i915 = to_i915(dev: display->drm);
865 int ret;
866
867 drm_WARN_ON(display->drm,
868 i915_gem_stolen_node_allocated(&fbc->compressed_fb));
869 drm_WARN_ON(display->drm,
870 i915_gem_stolen_node_allocated(&fbc->compressed_llb));
871
872 if (DISPLAY_VER(display) < 5 && !display->platform.g4x) {
873 ret = i915_gem_stolen_insert_node(i915, node: &fbc->compressed_llb,
874 size: 4096, alignment: 4096);
875 if (ret)
876 goto err;
877 }
878
879 ret = find_compression_limit(fbc, size, min_limit);
880 if (!ret)
881 goto err_llb;
882 else if (ret > min_limit)
883 drm_info_once(display->drm,
884 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
885
886 fbc->limit = ret;
887
888 drm_dbg_kms(display->drm,
889 "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n",
890 i915_gem_stolen_node_size(&fbc->compressed_fb), fbc->limit);
891 return 0;
892
893err_llb:
894 if (i915_gem_stolen_node_allocated(node: &fbc->compressed_llb))
895 i915_gem_stolen_remove_node(i915, node: &fbc->compressed_llb);
896err:
897 if (i915_gem_stolen_initialized(i915))
898 drm_info_once(display->drm,
899 "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
900 return -ENOSPC;
901}
902
903static void intel_fbc_program_cfb(struct intel_fbc *fbc)
904{
905 fbc->funcs->program_cfb(fbc);
906}
907
908static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
909{
910 struct intel_display *display = fbc->display;
911
912 if (display->platform.skylake || display->platform.broxton) {
913 /*
914 * WaFbcHighMemBwCorruptionAvoidance:skl,bxt
915 * Display WA #0883: skl,bxt
916 */
917 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
918 clear: 0, DPFC_DISABLE_DUMMY0);
919 }
920
921 if (display->platform.skylake || display->platform.kabylake ||
922 display->platform.coffeelake || display->platform.cometlake) {
923 /*
924 * WaFbcNukeOnHostModify:skl,kbl,cfl
925 * Display WA #0873: skl,kbl,cfl
926 */
927 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
928 clear: 0, DPFC_NUKE_ON_ANY_MODIFICATION);
929 }
930
931 /* Wa_1409120013:icl,jsl,tgl,dg1 */
932 if (IS_DISPLAY_VER(display, 11, 12))
933 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
934 clear: 0, DPFC_CHICKEN_COMP_DUMMY_PIXEL);
935
936 /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp,mtl */
937 if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
938 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
939 clear: 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
940
941 /* wa_18038517565 Disable DPFC clock gating before FBC enable */
942 if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
943 fbc_compressor_clkgate_disable_wa(fbc, disable: true);
944}
945
946static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
947{
948 struct intel_display *display = fbc->display;
949 struct drm_i915_private *i915 = to_i915(dev: display->drm);
950
951 if (WARN_ON(intel_fbc_hw_is_active(fbc)))
952 return;
953
954 if (i915_gem_stolen_node_allocated(node: &fbc->compressed_llb))
955 i915_gem_stolen_remove_node(i915, node: &fbc->compressed_llb);
956 if (i915_gem_stolen_node_allocated(node: &fbc->compressed_fb))
957 i915_gem_stolen_remove_node(i915, node: &fbc->compressed_fb);
958}
959
960void intel_fbc_cleanup(struct intel_display *display)
961{
962 struct intel_fbc *fbc;
963 enum intel_fbc_id fbc_id;
964
965 for_each_intel_fbc(display, fbc, fbc_id) {
966 mutex_lock(lock: &fbc->lock);
967 __intel_fbc_cleanup_cfb(fbc);
968 mutex_unlock(lock: &fbc->lock);
969
970 kfree(objp: fbc);
971 }
972}
973
974static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
975{
976 const struct drm_framebuffer *fb = plane_state->hw.fb;
977 unsigned int stride = intel_fbc_plane_stride(plane_state) *
978 fb->format->cpp[0];
979
980 return stride == 4096 || stride == 8192;
981}
982
983static bool i965_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
984{
985 const struct drm_framebuffer *fb = plane_state->hw.fb;
986 unsigned int stride = intel_fbc_plane_stride(plane_state) *
987 fb->format->cpp[0];
988
989 return stride >= 2048 && stride <= 16384;
990}
991
992static bool g4x_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
993{
994 return true;
995}
996
997static bool skl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
998{
999 const struct drm_framebuffer *fb = plane_state->hw.fb;
1000 unsigned int stride = intel_fbc_plane_stride(plane_state) *
1001 fb->format->cpp[0];
1002
1003 /* Display WA #1105: skl,bxt,kbl,cfl,glk */
1004 if (fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
1005 return false;
1006
1007 return true;
1008}
1009
1010static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
1011{
1012 return true;
1013}
1014
1015static bool stride_is_valid(const struct intel_plane_state *plane_state)
1016{
1017 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1018
1019 if (DISPLAY_VER(display) >= 11)
1020 return icl_fbc_stride_is_valid(plane_state);
1021 else if (DISPLAY_VER(display) >= 9)
1022 return skl_fbc_stride_is_valid(plane_state);
1023 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
1024 return g4x_fbc_stride_is_valid(plane_state);
1025 else if (DISPLAY_VER(display) == 4)
1026 return i965_fbc_stride_is_valid(plane_state);
1027 else
1028 return i8xx_fbc_stride_is_valid(plane_state);
1029}
1030
1031static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
1032{
1033 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1034 const struct drm_framebuffer *fb = plane_state->hw.fb;
1035
1036 switch (fb->format->format) {
1037 case DRM_FORMAT_XRGB8888:
1038 case DRM_FORMAT_XBGR8888:
1039 return true;
1040 case DRM_FORMAT_XRGB1555:
1041 case DRM_FORMAT_RGB565:
1042 /* 16bpp not supported on gen2 */
1043 if (DISPLAY_VER(display) == 2)
1044 return false;
1045 return true;
1046 default:
1047 return false;
1048 }
1049}
1050
1051static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
1052{
1053 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1054 const struct drm_framebuffer *fb = plane_state->hw.fb;
1055
1056 switch (fb->format->format) {
1057 case DRM_FORMAT_XRGB8888:
1058 case DRM_FORMAT_XBGR8888:
1059 return true;
1060 case DRM_FORMAT_RGB565:
1061 /* WaFbcOnly1to1Ratio:ctg */
1062 if (display->platform.g4x)
1063 return false;
1064 return true;
1065 default:
1066 return false;
1067 }
1068}
1069
1070static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
1071{
1072 const struct drm_framebuffer *fb = plane_state->hw.fb;
1073
1074 switch (fb->format->format) {
1075 case DRM_FORMAT_XRGB8888:
1076 case DRM_FORMAT_XBGR8888:
1077 case DRM_FORMAT_ARGB8888:
1078 case DRM_FORMAT_ABGR8888:
1079 case DRM_FORMAT_RGB565:
1080 return true;
1081 default:
1082 return false;
1083 }
1084}
1085
1086static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
1087{
1088 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1089
1090 if (DISPLAY_VER(display) >= 20)
1091 return lnl_fbc_pixel_format_is_valid(plane_state);
1092 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
1093 return g4x_fbc_pixel_format_is_valid(plane_state);
1094 else
1095 return i8xx_fbc_pixel_format_is_valid(plane_state);
1096}
1097
1098static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
1099{
1100 return plane_state->hw.rotation == DRM_MODE_ROTATE_0;
1101}
1102
1103static bool g4x_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
1104{
1105 return true;
1106}
1107
1108static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
1109{
1110 const struct drm_framebuffer *fb = plane_state->hw.fb;
1111 unsigned int rotation = plane_state->hw.rotation;
1112
1113 if (fb->format->format == DRM_FORMAT_RGB565 &&
1114 drm_rotation_90_or_270(rotation))
1115 return false;
1116
1117 return true;
1118}
1119
1120static bool rotation_is_valid(const struct intel_plane_state *plane_state)
1121{
1122 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1123
1124 if (DISPLAY_VER(display) >= 9)
1125 return skl_fbc_rotation_is_valid(plane_state);
1126 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
1127 return g4x_fbc_rotation_is_valid(plane_state);
1128 else
1129 return i8xx_fbc_rotation_is_valid(plane_state);
1130}
1131
1132static void intel_fbc_max_surface_size(struct intel_display *display,
1133 unsigned int *w, unsigned int *h)
1134{
1135 if (DISPLAY_VER(display) >= 11) {
1136 *w = 8192;
1137 *h = 4096;
1138 } else if (DISPLAY_VER(display) >= 10) {
1139 *w = 5120;
1140 *h = 4096;
1141 } else if (DISPLAY_VER(display) >= 7) {
1142 *w = 4096;
1143 *h = 4096;
1144 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {
1145 *w = 4096;
1146 *h = 2048;
1147 } else {
1148 *w = 2048;
1149 *h = 1536;
1150 }
1151}
1152
1153/*
1154 * For some reason, the hardware tracking starts looking at whatever we
1155 * programmed as the display plane base address register. It does not look at
1156 * the X and Y offset registers. That's why we include the src x/y offsets
1157 * instead of just looking at the plane size.
1158 */
1159static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_state)
1160{
1161 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1162 unsigned int effective_w, effective_h, max_w, max_h;
1163
1164 intel_fbc_max_surface_size(display, w: &max_w, h: &max_h);
1165
1166 effective_w = plane_state->view.color_plane[0].x +
1167 (drm_rect_width(r: &plane_state->uapi.src) >> 16);
1168 effective_h = plane_state->view.color_plane[0].y +
1169 (drm_rect_height(r: &plane_state->uapi.src) >> 16);
1170
1171 return effective_w <= max_w && effective_h <= max_h;
1172}
1173
1174static void intel_fbc_max_plane_size(struct intel_display *display,
1175 unsigned int *w, unsigned int *h)
1176{
1177 if (DISPLAY_VER(display) >= 10) {
1178 *w = 5120;
1179 *h = 4096;
1180 } else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) {
1181 *w = 4096;
1182 *h = 4096;
1183 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {
1184 *w = 4096;
1185 *h = 2048;
1186 } else {
1187 *w = 2048;
1188 *h = 1536;
1189 }
1190}
1191
1192static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state)
1193{
1194 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1195 unsigned int w, h, max_w, max_h;
1196
1197 intel_fbc_max_plane_size(display, w: &max_w, h: &max_h);
1198
1199 w = drm_rect_width(r: &plane_state->uapi.src) >> 16;
1200 h = drm_rect_height(r: &plane_state->uapi.src) >> 16;
1201
1202 return w <= max_w && h <= max_h;
1203}
1204
1205static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state)
1206{
1207 const struct drm_framebuffer *fb = plane_state->hw.fb;
1208
1209 return fb->modifier == I915_FORMAT_MOD_X_TILED;
1210}
1211
1212static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state)
1213{
1214 return true;
1215}
1216
1217static bool tiling_is_valid(const struct intel_plane_state *plane_state)
1218{
1219 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1220
1221 if (DISPLAY_VER(display) >= 9)
1222 return skl_fbc_tiling_valid(plane_state);
1223 else
1224 return i8xx_fbc_tiling_valid(plane_state);
1225}
1226
1227static void
1228intel_fbc_invalidate_dirty_rect(struct intel_fbc *fbc)
1229{
1230 lockdep_assert_held(&fbc->lock);
1231
1232 fbc->state.dirty_rect = DRM_RECT_INIT(0, 0, 0, 0);
1233}
1234
1235static void
1236intel_fbc_program_dirty_rect(struct intel_dsb *dsb, struct intel_fbc *fbc,
1237 const struct drm_rect *fbc_dirty_rect)
1238{
1239 struct intel_display *display = fbc->display;
1240
1241 drm_WARN_ON(display->drm, fbc_dirty_rect->y2 == 0);
1242
1243 intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
1244 FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) |
1245 FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2 - 1));
1246}
1247
1248static void
1249intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_fbc *fbc)
1250{
1251 const struct drm_rect *fbc_dirty_rect = &fbc->state.dirty_rect;
1252
1253 lockdep_assert_held(&fbc->lock);
1254
1255 if (!drm_rect_visible(r: fbc_dirty_rect))
1256 return;
1257
1258 intel_fbc_program_dirty_rect(dsb, fbc, fbc_dirty_rect);
1259}
1260
1261void
1262intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
1263 struct intel_plane *plane)
1264{
1265 struct intel_display *display = to_intel_display(plane);
1266 struct intel_fbc *fbc = plane->fbc;
1267
1268 if (!HAS_FBC_DIRTY_RECT(display))
1269 return;
1270
1271 mutex_lock(lock: &fbc->lock);
1272
1273 if (fbc->state.plane == plane)
1274 intel_fbc_dirty_rect_update(dsb, fbc);
1275
1276 mutex_unlock(lock: &fbc->lock);
1277}
1278
1279static void
1280intel_fbc_hw_intialize_dirty_rect(struct intel_fbc *fbc,
1281 const struct intel_plane_state *plane_state)
1282{
1283 struct drm_rect src;
1284
1285 /*
1286 * Initializing the FBC HW with the whole plane area as the dirty rect.
1287 * This is to ensure that we have valid coords be written to the
1288 * HW as dirty rect.
1289 */
1290 drm_rect_fp_to_int(dst: &src, src: &plane_state->uapi.src);
1291
1292 intel_fbc_program_dirty_rect(NULL, fbc, fbc_dirty_rect: &src);
1293}
1294
1295static void intel_fbc_update_state(struct intel_atomic_state *state,
1296 struct intel_crtc *crtc,
1297 struct intel_plane *plane)
1298{
1299 struct intel_display *display = to_intel_display(state->base.dev);
1300 const struct intel_crtc_state *crtc_state =
1301 intel_atomic_get_new_crtc_state(state, crtc);
1302 const struct intel_plane_state *plane_state =
1303 intel_atomic_get_new_plane_state(state, plane);
1304 struct intel_fbc *fbc = plane->fbc;
1305 struct intel_fbc_state *fbc_state = &fbc->state;
1306
1307 WARN_ON(plane_state->no_fbc_reason);
1308 WARN_ON(fbc_state->plane && fbc_state->plane != plane);
1309
1310 fbc_state->plane = plane;
1311
1312 /* FBC1 compression interval: arbitrary choice of 1 second */
1313 fbc_state->interval = drm_mode_vrefresh(mode: &crtc_state->hw.adjusted_mode);
1314
1315 fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);
1316
1317 drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE &&
1318 !intel_fbc_has_fences(display));
1319
1320 if (plane_state->flags & PLANE_HAS_FENCE)
1321 fbc_state->fence_id = i915_vma_fence_id(vma: plane_state->ggtt_vma);
1322 else
1323 fbc_state->fence_id = -1;
1324
1325 fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);
1326 fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);
1327 fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
1328}
1329
1330static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
1331{
1332 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1333
1334 /*
1335 * The use of a CPU fence is one of two ways to detect writes by the
1336 * CPU to the scanout and trigger updates to the FBC.
1337 *
1338 * The other method is by software tracking (see
1339 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
1340 * the current compressed buffer and recompress it.
1341 *
1342 * Note that is possible for a tiled surface to be unmappable (and
1343 * so have no fence associated with it) due to aperture constraints
1344 * at the time of pinning.
1345 */
1346 return DISPLAY_VER(display) >= 9 ||
1347 (plane_state->flags & PLANE_HAS_FENCE &&
1348 i915_vma_fence_id(vma: plane_state->ggtt_vma) != -1);
1349}
1350
1351static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)
1352{
1353 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1354 struct intel_fbc *fbc = plane->fbc;
1355
1356 return intel_fbc_min_limit(plane_state) <= fbc->limit &&
1357 intel_fbc_cfb_size(plane_state) <= fbc->limit *
1358 i915_gem_stolen_node_size(node: &fbc->compressed_fb);
1359}
1360
1361static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)
1362{
1363 return !plane_state->no_fbc_reason &&
1364 intel_fbc_is_fence_ok(plane_state) &&
1365 intel_fbc_is_cfb_ok(plane_state);
1366}
1367
1368static void
1369__intel_fbc_prepare_dirty_rect(const struct intel_plane_state *plane_state,
1370 const struct intel_crtc_state *crtc_state)
1371{
1372 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1373 struct intel_fbc *fbc = plane->fbc;
1374 struct drm_rect *fbc_dirty_rect = &fbc->state.dirty_rect;
1375 int width = drm_rect_width(r: &plane_state->uapi.src) >> 16;
1376 const struct drm_rect *damage = &plane_state->damage;
1377 int y_offset = plane_state->view.color_plane[0].y;
1378
1379 lockdep_assert_held(&fbc->lock);
1380
1381 if (intel_crtc_needs_modeset(crtc_state) ||
1382 !intel_fbc_is_ok(plane_state)) {
1383 intel_fbc_invalidate_dirty_rect(fbc);
1384 return;
1385 }
1386
1387 if (drm_rect_visible(r: damage))
1388 *fbc_dirty_rect = *damage;
1389 else
1390 /* dirty rect must cover at least one line */
1391 *fbc_dirty_rect = DRM_RECT_INIT(0, y_offset, width, 1);
1392}
1393
1394void
1395intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
1396 struct intel_crtc *crtc)
1397{
1398 struct intel_display *display = to_intel_display(state);
1399 const struct intel_crtc_state *crtc_state =
1400 intel_atomic_get_new_crtc_state(state, crtc);
1401 struct intel_plane_state *plane_state;
1402 struct intel_plane *plane;
1403 int i;
1404
1405 if (!HAS_FBC_DIRTY_RECT(display))
1406 return;
1407
1408 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1409 struct intel_fbc *fbc = plane->fbc;
1410
1411 if (!fbc || plane->pipe != crtc->pipe)
1412 continue;
1413
1414 mutex_lock(lock: &fbc->lock);
1415
1416 if (fbc->state.plane == plane)
1417 __intel_fbc_prepare_dirty_rect(plane_state,
1418 crtc_state);
1419
1420 mutex_unlock(lock: &fbc->lock);
1421 }
1422}
1423
1424static int intel_fbc_check_plane(struct intel_atomic_state *state,
1425 struct intel_plane *plane)
1426{
1427 struct intel_display *display = to_intel_display(state->base.dev);
1428 struct drm_i915_private *i915 = to_i915(dev: display->drm);
1429 struct intel_plane_state *plane_state =
1430 intel_atomic_get_new_plane_state(state, plane);
1431 const struct drm_framebuffer *fb = plane_state->hw.fb;
1432 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1433 const struct intel_crtc_state *crtc_state;
1434 struct intel_fbc *fbc = plane->fbc;
1435
1436 if (!fbc)
1437 return 0;
1438
1439 if (!i915_gem_stolen_initialized(i915)) {
1440 plane_state->no_fbc_reason = "stolen memory not initialised";
1441 return 0;
1442 }
1443
1444 if (intel_vgpu_active(i915)) {
1445 plane_state->no_fbc_reason = "VGPU active";
1446 return 0;
1447 }
1448
1449 if (!display->params.enable_fbc) {
1450 plane_state->no_fbc_reason = "disabled per module param or by default";
1451 return 0;
1452 }
1453
1454 if (!plane_state->uapi.visible) {
1455 plane_state->no_fbc_reason = "plane not visible";
1456 return 0;
1457 }
1458
1459 if (intel_display_wa(display, 16023588340)) {
1460 plane_state->no_fbc_reason = "Wa_16023588340";
1461 return 0;
1462 }
1463
1464 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1465 if (i915_vtd_active(i915) && (display->platform.skylake || display->platform.broxton)) {
1466 plane_state->no_fbc_reason = "VT-d enabled";
1467 return 0;
1468 }
1469
1470 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1471
1472 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1473 plane_state->no_fbc_reason = "interlaced mode not supported";
1474 return 0;
1475 }
1476
1477 if (crtc_state->double_wide) {
1478 plane_state->no_fbc_reason = "double wide pipe not supported";
1479 return 0;
1480 }
1481
1482 /*
1483 * Display 12+ is not supporting FBC with PSR2.
1484 * Recommendation is to keep this combination disabled
1485 * Bspec: 50422 HSD: 14010260002
1486 *
1487 * TODO: Implement a logic to select between PSR2 selective fetch and
1488 * FBC based on Bspec: 68881 in xe2lpd onwards.
1489 *
1490 * As we still see some strange underruns in those platforms while
1491 * disabling PSR2, keep FBC disabled in case of selective update is on
1492 * until the selection logic is implemented.
1493 */
1494 if (DISPLAY_VER(display) >= 12 && crtc_state->has_sel_update) {
1495 plane_state->no_fbc_reason = "Selective update enabled";
1496 return 0;
1497 }
1498
1499 /* Wa_14016291713 */
1500 if ((IS_DISPLAY_VER(display, 12, 13) ||
1501 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) &&
1502 crtc_state->has_psr && !crtc_state->has_panel_replay) {
1503 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
1504 return 0;
1505 }
1506
1507 if (!pixel_format_is_valid(plane_state)) {
1508 plane_state->no_fbc_reason = "pixel format not supported";
1509 return 0;
1510 }
1511
1512 if (!tiling_is_valid(plane_state)) {
1513 plane_state->no_fbc_reason = "tiling not supported";
1514 return 0;
1515 }
1516
1517 if (!rotation_is_valid(plane_state)) {
1518 plane_state->no_fbc_reason = "rotation not supported";
1519 return 0;
1520 }
1521
1522 if (!stride_is_valid(plane_state)) {
1523 plane_state->no_fbc_reason = "stride not supported";
1524 return 0;
1525 }
1526
1527 if (DISPLAY_VER(display) < 20 &&
1528 plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
1529 fb->format->has_alpha) {
1530 plane_state->no_fbc_reason = "per-pixel alpha not supported";
1531 return 0;
1532 }
1533
1534 if (!intel_fbc_plane_size_valid(plane_state)) {
1535 plane_state->no_fbc_reason = "plane size too big";
1536 return 0;
1537 }
1538
1539 if (!intel_fbc_surface_size_ok(plane_state)) {
1540 plane_state->no_fbc_reason = "surface size too big";
1541 return 0;
1542 }
1543
1544 /*
1545 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
1546 * having a Y offset that isn't divisible by 4 causes FIFO underrun
1547 * and screen flicker.
1548 */
1549 if (IS_DISPLAY_VER(display, 9, 12) &&
1550 plane_state->view.color_plane[0].y & 3) {
1551 plane_state->no_fbc_reason = "plane start Y offset misaligned";
1552 return 0;
1553 }
1554
1555 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
1556 if (IS_DISPLAY_VER(display, 9, 12) &&
1557 (plane_state->view.color_plane[0].y +
1558 (drm_rect_height(r: &plane_state->uapi.src) >> 16)) & 3) {
1559 plane_state->no_fbc_reason = "plane end Y offset misaligned";
1560 return 0;
1561 }
1562
1563 /* WaFbcExceedCdClockThreshold:hsw,bdw */
1564 if (display->platform.haswell || display->platform.broadwell) {
1565 const struct intel_cdclk_state *cdclk_state;
1566
1567 cdclk_state = intel_atomic_get_cdclk_state(state);
1568 if (IS_ERR(ptr: cdclk_state))
1569 return PTR_ERR(ptr: cdclk_state);
1570
1571 if (crtc_state->pixel_rate >= intel_cdclk_logical(cdclk_state) * 95 / 100) {
1572 plane_state->no_fbc_reason = "pixel rate too high";
1573 return 0;
1574 }
1575 }
1576
1577 plane_state->no_fbc_reason = NULL;
1578
1579 return 0;
1580}
1581
1582
1583static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
1584 struct intel_crtc *crtc,
1585 struct intel_plane *plane)
1586{
1587 const struct intel_crtc_state *new_crtc_state =
1588 intel_atomic_get_new_crtc_state(state, crtc);
1589 const struct intel_plane_state *old_plane_state =
1590 intel_atomic_get_old_plane_state(state, plane);
1591 const struct intel_plane_state *new_plane_state =
1592 intel_atomic_get_new_plane_state(state, plane);
1593 const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
1594 const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
1595
1596 if (intel_crtc_needs_modeset(crtc_state: new_crtc_state))
1597 return false;
1598
1599 if (!intel_fbc_is_ok(plane_state: old_plane_state) ||
1600 !intel_fbc_is_ok(plane_state: new_plane_state))
1601 return false;
1602
1603 if (old_fb->format->format != new_fb->format->format)
1604 return false;
1605
1606 if (old_fb->modifier != new_fb->modifier)
1607 return false;
1608
1609 if (intel_fbc_plane_stride(plane_state: old_plane_state) !=
1610 intel_fbc_plane_stride(plane_state: new_plane_state))
1611 return false;
1612
1613 if (intel_fbc_cfb_stride(plane_state: old_plane_state) !=
1614 intel_fbc_cfb_stride(plane_state: new_plane_state))
1615 return false;
1616
1617 if (intel_fbc_cfb_size(plane_state: old_plane_state) !=
1618 intel_fbc_cfb_size(plane_state: new_plane_state))
1619 return false;
1620
1621 if (intel_fbc_override_cfb_stride(plane_state: old_plane_state) !=
1622 intel_fbc_override_cfb_stride(plane_state: new_plane_state))
1623 return false;
1624
1625 return true;
1626}
1627
1628static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
1629 struct intel_crtc *crtc,
1630 struct intel_plane *plane)
1631{
1632 struct intel_display *display = to_intel_display(state->base.dev);
1633 struct intel_fbc *fbc = plane->fbc;
1634 bool need_vblank_wait = false;
1635
1636 lockdep_assert_held(&fbc->lock);
1637
1638 fbc->flip_pending = true;
1639
1640 if (intel_fbc_can_flip_nuke(state, crtc, plane))
1641 return need_vblank_wait;
1642
1643 intel_fbc_deactivate(fbc, reason: "update pending");
1644
1645 /*
1646 * Display WA #1198: glk+
1647 * Need an extra vblank wait between FBC disable and most plane
1648 * updates. Bspec says this is only needed for plane disable, but
1649 * that is not true. Touching most plane registers will cause the
1650 * corruption to appear. Also SKL/derivatives do not seem to be
1651 * affected.
1652 *
1653 * TODO: could optimize this a bit by sampling the frame
1654 * counter when we disable FBC (if it was already done earlier)
1655 * and skipping the extra vblank wait before the plane update
1656 * if at least one frame has already passed.
1657 */
1658 if (fbc->activated && DISPLAY_VER(display) >= 10)
1659 need_vblank_wait = true;
1660 fbc->activated = false;
1661
1662 return need_vblank_wait;
1663}
1664
1665bool intel_fbc_pre_update(struct intel_atomic_state *state,
1666 struct intel_crtc *crtc)
1667{
1668 const struct intel_plane_state __maybe_unused *plane_state;
1669 bool need_vblank_wait = false;
1670 struct intel_plane *plane;
1671 int i;
1672
1673 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1674 struct intel_fbc *fbc = plane->fbc;
1675
1676 if (!fbc || plane->pipe != crtc->pipe)
1677 continue;
1678
1679 mutex_lock(lock: &fbc->lock);
1680
1681 if (fbc->state.plane == plane)
1682 need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);
1683
1684 mutex_unlock(lock: &fbc->lock);
1685 }
1686
1687 return need_vblank_wait;
1688}
1689
1690static void __intel_fbc_disable(struct intel_fbc *fbc)
1691{
1692 struct intel_display *display = fbc->display;
1693 struct intel_plane *plane = fbc->state.plane;
1694
1695 lockdep_assert_held(&fbc->lock);
1696 drm_WARN_ON(display->drm, fbc->active);
1697
1698 drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n",
1699 plane->base.base.id, plane->base.name);
1700
1701 intel_fbc_invalidate_dirty_rect(fbc);
1702
1703 __intel_fbc_cleanup_cfb(fbc);
1704
1705 /* wa_18038517565 Enable DPFC clock gating after FBC disable */
1706 if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
1707 fbc_compressor_clkgate_disable_wa(fbc, disable: false);
1708
1709 fbc->state.plane = NULL;
1710 fbc->flip_pending = false;
1711 fbc->busy_bits = 0;
1712}
1713
1714static void __intel_fbc_post_update(struct intel_fbc *fbc)
1715{
1716 lockdep_assert_held(&fbc->lock);
1717
1718 fbc->flip_pending = false;
1719 fbc->busy_bits = 0;
1720
1721 intel_fbc_activate(fbc);
1722}
1723
1724void intel_fbc_post_update(struct intel_atomic_state *state,
1725 struct intel_crtc *crtc)
1726{
1727 const struct intel_plane_state __maybe_unused *plane_state;
1728 struct intel_plane *plane;
1729 int i;
1730
1731 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1732 struct intel_fbc *fbc = plane->fbc;
1733
1734 if (!fbc || plane->pipe != crtc->pipe)
1735 continue;
1736
1737 mutex_lock(lock: &fbc->lock);
1738
1739 if (fbc->state.plane == plane)
1740 __intel_fbc_post_update(fbc);
1741
1742 mutex_unlock(lock: &fbc->lock);
1743 }
1744}
1745
1746static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1747{
1748 if (fbc->state.plane)
1749 return fbc->state.plane->frontbuffer_bit;
1750 else
1751 return 0;
1752}
1753
1754static void __intel_fbc_invalidate(struct intel_fbc *fbc,
1755 unsigned int frontbuffer_bits,
1756 enum fb_op_origin origin)
1757{
1758 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1759 return;
1760
1761 mutex_lock(lock: &fbc->lock);
1762
1763 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1764 if (!frontbuffer_bits)
1765 goto out;
1766
1767 fbc->busy_bits |= frontbuffer_bits;
1768 intel_fbc_deactivate(fbc, reason: "frontbuffer write");
1769
1770out:
1771 mutex_unlock(lock: &fbc->lock);
1772}
1773
1774void intel_fbc_invalidate(struct intel_display *display,
1775 unsigned int frontbuffer_bits,
1776 enum fb_op_origin origin)
1777{
1778 struct intel_fbc *fbc;
1779 enum intel_fbc_id fbc_id;
1780
1781 for_each_intel_fbc(display, fbc, fbc_id)
1782 __intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
1783
1784}
1785
1786static void __intel_fbc_flush(struct intel_fbc *fbc,
1787 unsigned int frontbuffer_bits,
1788 enum fb_op_origin origin)
1789{
1790 mutex_lock(lock: &fbc->lock);
1791
1792 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1793 if (!frontbuffer_bits)
1794 goto out;
1795
1796 fbc->busy_bits &= ~frontbuffer_bits;
1797
1798 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1799 goto out;
1800
1801 if (fbc->busy_bits || fbc->flip_pending)
1802 goto out;
1803
1804 if (fbc->active)
1805 intel_fbc_nuke(fbc);
1806 else
1807 intel_fbc_activate(fbc);
1808
1809out:
1810 mutex_unlock(lock: &fbc->lock);
1811}
1812
1813void intel_fbc_flush(struct intel_display *display,
1814 unsigned int frontbuffer_bits,
1815 enum fb_op_origin origin)
1816{
1817 struct intel_fbc *fbc;
1818 enum intel_fbc_id fbc_id;
1819
1820 for_each_intel_fbc(display, fbc, fbc_id)
1821 __intel_fbc_flush(fbc, frontbuffer_bits, origin);
1822}
1823
1824int intel_fbc_atomic_check(struct intel_atomic_state *state)
1825{
1826 struct intel_plane_state __maybe_unused *plane_state;
1827 struct intel_plane *plane;
1828 int i;
1829
1830 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1831 int ret;
1832
1833 ret = intel_fbc_check_plane(state, plane);
1834 if (ret)
1835 return ret;
1836 }
1837
1838 return 0;
1839}
1840
1841static void __intel_fbc_enable(struct intel_atomic_state *state,
1842 struct intel_crtc *crtc,
1843 struct intel_plane *plane)
1844{
1845 struct intel_display *display = to_intel_display(state->base.dev);
1846 const struct intel_plane_state *plane_state =
1847 intel_atomic_get_new_plane_state(state, plane);
1848 struct intel_fbc *fbc = plane->fbc;
1849
1850 lockdep_assert_held(&fbc->lock);
1851
1852 if (fbc->state.plane) {
1853 if (fbc->state.plane != plane)
1854 return;
1855
1856 if (intel_fbc_is_ok(plane_state)) {
1857 intel_fbc_update_state(state, crtc, plane);
1858 return;
1859 }
1860
1861 __intel_fbc_disable(fbc);
1862 }
1863
1864 drm_WARN_ON(display->drm, fbc->active);
1865
1866 fbc->no_fbc_reason = plane_state->no_fbc_reason;
1867 if (fbc->no_fbc_reason)
1868 return;
1869
1870 if (!intel_fbc_is_fence_ok(plane_state)) {
1871 fbc->no_fbc_reason = "framebuffer not fenced";
1872 return;
1873 }
1874
1875 if (fbc->underrun_detected) {
1876 fbc->no_fbc_reason = "FIFO underrun";
1877 return;
1878 }
1879
1880 if (intel_fbc_alloc_cfb(fbc, size: intel_fbc_cfb_size(plane_state),
1881 min_limit: intel_fbc_min_limit(plane_state))) {
1882 fbc->no_fbc_reason = "not enough stolen memory";
1883 return;
1884 }
1885
1886 drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n",
1887 plane->base.base.id, plane->base.name);
1888 fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1889
1890 intel_fbc_update_state(state, crtc, plane);
1891
1892 if (HAS_FBC_DIRTY_RECT(display))
1893 intel_fbc_hw_intialize_dirty_rect(fbc, plane_state);
1894
1895 intel_fbc_program_workarounds(fbc);
1896 intel_fbc_program_cfb(fbc);
1897}
1898
1899/**
1900 * intel_fbc_disable - disable FBC if it's associated with crtc
1901 * @crtc: the CRTC
1902 *
1903 * This function disables FBC if it's associated with the provided CRTC.
1904 */
1905void intel_fbc_disable(struct intel_crtc *crtc)
1906{
1907 struct intel_display *display = to_intel_display(crtc->base.dev);
1908 struct intel_plane *plane;
1909
1910 for_each_intel_plane(display->drm, plane) {
1911 struct intel_fbc *fbc = plane->fbc;
1912
1913 if (!fbc || plane->pipe != crtc->pipe)
1914 continue;
1915
1916 mutex_lock(lock: &fbc->lock);
1917 if (fbc->state.plane == plane)
1918 __intel_fbc_disable(fbc);
1919 mutex_unlock(lock: &fbc->lock);
1920 }
1921}
1922
1923void intel_fbc_update(struct intel_atomic_state *state,
1924 struct intel_crtc *crtc)
1925{
1926 const struct intel_crtc_state *crtc_state =
1927 intel_atomic_get_new_crtc_state(state, crtc);
1928 const struct intel_plane_state *plane_state;
1929 struct intel_plane *plane;
1930 int i;
1931
1932 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1933 struct intel_fbc *fbc = plane->fbc;
1934
1935 if (!fbc || plane->pipe != crtc->pipe)
1936 continue;
1937
1938 mutex_lock(lock: &fbc->lock);
1939
1940 if (intel_crtc_needs_fastset(crtc_state) &&
1941 plane_state->no_fbc_reason) {
1942 if (fbc->state.plane == plane)
1943 __intel_fbc_disable(fbc);
1944 } else {
1945 __intel_fbc_enable(state, crtc, plane);
1946 }
1947
1948 mutex_unlock(lock: &fbc->lock);
1949 }
1950}
1951
1952static void intel_fbc_underrun_work_fn(struct work_struct *work)
1953{
1954 struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work);
1955 struct intel_display *display = fbc->display;
1956
1957 mutex_lock(lock: &fbc->lock);
1958
1959 /* Maybe we were scheduled twice. */
1960 if (fbc->underrun_detected || !fbc->state.plane)
1961 goto out;
1962
1963 drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n");
1964 fbc->underrun_detected = true;
1965
1966 intel_fbc_deactivate(fbc, reason: "FIFO underrun");
1967 if (!fbc->flip_pending)
1968 intel_crtc_wait_for_next_vblank(crtc: intel_crtc_for_pipe(display, pipe: fbc->state.plane->pipe));
1969 __intel_fbc_disable(fbc);
1970out:
1971 mutex_unlock(lock: &fbc->lock);
1972}
1973
1974static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
1975{
1976 struct intel_display *display = fbc->display;
1977
1978 cancel_work_sync(work: &fbc->underrun_work);
1979
1980 mutex_lock(lock: &fbc->lock);
1981
1982 if (fbc->underrun_detected) {
1983 drm_dbg_kms(display->drm,
1984 "Re-allowing FBC after fifo underrun\n");
1985 fbc->no_fbc_reason = "FIFO underrun cleared";
1986 }
1987
1988 fbc->underrun_detected = false;
1989 mutex_unlock(lock: &fbc->lock);
1990}
1991
1992/*
1993 * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1994 * @display: display
1995 *
1996 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1997 * want to re-enable FBC after an underrun to increase test coverage.
1998 */
1999void intel_fbc_reset_underrun(struct intel_display *display)
2000{
2001 struct intel_fbc *fbc;
2002 enum intel_fbc_id fbc_id;
2003
2004 for_each_intel_fbc(display, fbc, fbc_id)
2005 __intel_fbc_reset_underrun(fbc);
2006}
2007
2008static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
2009{
2010 struct intel_display *display = fbc->display;
2011
2012 /*
2013 * There's no guarantee that underrun_detected won't be set to true
2014 * right after this check and before the work is scheduled, but that's
2015 * not a problem since we'll check it again under the work function
2016 * while FBC is locked. This check here is just to prevent us from
2017 * unnecessarily scheduling the work, and it relies on the fact that we
2018 * never switch underrun_detect back to false after it's true.
2019 */
2020 if (READ_ONCE(fbc->underrun_detected))
2021 return;
2022
2023 queue_work(wq: display->wq.unordered, work: &fbc->underrun_work);
2024}
2025
2026/**
2027 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
2028 * @display: display
2029 *
2030 * Without FBC, most underruns are harmless and don't really cause too many
2031 * problems, except for an annoying message on dmesg. With FBC, underruns can
2032 * become black screens or even worse, especially when paired with bad
2033 * watermarks. So in order for us to be on the safe side, completely disable FBC
2034 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
2035 * already suggests that watermarks may be bad, so try to be as safe as
2036 * possible.
2037 *
2038 * This function is called from the IRQ handler.
2039 */
2040void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)
2041{
2042 struct intel_fbc *fbc;
2043 enum intel_fbc_id fbc_id;
2044
2045 for_each_intel_fbc(display, fbc, fbc_id)
2046 __intel_fbc_handle_fifo_underrun_irq(fbc);
2047}
2048
2049/*
2050 * The DDX driver changes its behavior depending on the value it reads from
2051 * i915.enable_fbc, so sanitize it by translating the default value into either
2052 * 0 or 1 in order to allow it to know what's going on.
2053 *
2054 * Notice that this is done at driver initialization and we still allow user
2055 * space to change the value during runtime without sanitizing it again. IGT
2056 * relies on being able to change i915.enable_fbc at runtime.
2057 */
2058static int intel_sanitize_fbc_option(struct intel_display *display)
2059{
2060 if (display->params.enable_fbc >= 0)
2061 return !!display->params.enable_fbc;
2062
2063 if (!HAS_FBC(display))
2064 return 0;
2065
2066 if (display->platform.broadwell || DISPLAY_VER(display) >= 9)
2067 return 1;
2068
2069 return 0;
2070}
2071
2072void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
2073{
2074 plane->fbc = fbc;
2075}
2076
2077static struct intel_fbc *intel_fbc_create(struct intel_display *display,
2078 enum intel_fbc_id fbc_id)
2079{
2080 struct intel_fbc *fbc;
2081
2082 fbc = kzalloc(sizeof(*fbc), GFP_KERNEL);
2083 if (!fbc)
2084 return NULL;
2085
2086 fbc->id = fbc_id;
2087 fbc->display = display;
2088 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
2089 mutex_init(&fbc->lock);
2090
2091 if (DISPLAY_VER(display) >= 7)
2092 fbc->funcs = &ivb_fbc_funcs;
2093 else if (DISPLAY_VER(display) == 6)
2094 fbc->funcs = &snb_fbc_funcs;
2095 else if (DISPLAY_VER(display) == 5)
2096 fbc->funcs = &ilk_fbc_funcs;
2097 else if (display->platform.g4x)
2098 fbc->funcs = &g4x_fbc_funcs;
2099 else if (DISPLAY_VER(display) == 4)
2100 fbc->funcs = &i965_fbc_funcs;
2101 else
2102 fbc->funcs = &i8xx_fbc_funcs;
2103
2104 return fbc;
2105}
2106
2107/**
2108 * intel_fbc_init - Initialize FBC
2109 * @display: display
2110 *
2111 * This function might be called during PM init process.
2112 */
2113void intel_fbc_init(struct intel_display *display)
2114{
2115 enum intel_fbc_id fbc_id;
2116
2117 display->params.enable_fbc = intel_sanitize_fbc_option(display);
2118 drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n",
2119 display->params.enable_fbc);
2120
2121 for_each_fbc_id(display, fbc_id)
2122 display->fbc[fbc_id] = intel_fbc_create(display, fbc_id);
2123}
2124
2125/**
2126 * intel_fbc_sanitize - Sanitize FBC
2127 * @display: display
2128 *
2129 * Make sure FBC is initially disabled since we have no
2130 * idea eg. into which parts of stolen it might be scribbling
2131 * into.
2132 */
2133void intel_fbc_sanitize(struct intel_display *display)
2134{
2135 struct intel_fbc *fbc;
2136 enum intel_fbc_id fbc_id;
2137
2138 for_each_intel_fbc(display, fbc, fbc_id) {
2139 if (intel_fbc_hw_is_active(fbc))
2140 intel_fbc_hw_deactivate(fbc);
2141 }
2142}
2143
2144static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
2145{
2146 struct intel_fbc *fbc = m->private;
2147 struct intel_display *display = fbc->display;
2148 struct intel_plane *plane;
2149 struct ref_tracker *wakeref;
2150
2151 drm_modeset_lock_all(dev: display->drm);
2152
2153 wakeref = intel_display_rpm_get(display);
2154 mutex_lock(lock: &fbc->lock);
2155
2156 if (fbc->active) {
2157 seq_puts(m, s: "FBC enabled\n");
2158 seq_printf(m, fmt: "Compressing: %s\n",
2159 str_yes_no(v: intel_fbc_is_compressing(fbc)));
2160 } else {
2161 seq_printf(m, fmt: "FBC disabled: %s\n", fbc->no_fbc_reason);
2162 }
2163
2164 for_each_intel_plane(display->drm, plane) {
2165 const struct intel_plane_state *plane_state =
2166 to_intel_plane_state(plane->base.state);
2167
2168 if (plane->fbc != fbc)
2169 continue;
2170
2171 seq_printf(m, fmt: "%c [PLANE:%d:%s]: %s\n",
2172 fbc->state.plane == plane ? '*' : ' ',
2173 plane->base.base.id, plane->base.name,
2174 plane_state->no_fbc_reason ?: "FBC possible");
2175 }
2176
2177 mutex_unlock(lock: &fbc->lock);
2178 intel_display_rpm_put(display, wakeref);
2179
2180 drm_modeset_unlock_all(dev: display->drm);
2181
2182 return 0;
2183}
2184
2185DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status);
2186
2187static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
2188{
2189 struct intel_fbc *fbc = data;
2190
2191 *val = fbc->false_color;
2192
2193 return 0;
2194}
2195
2196static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
2197{
2198 struct intel_fbc *fbc = data;
2199
2200 mutex_lock(lock: &fbc->lock);
2201
2202 fbc->false_color = val;
2203
2204 if (fbc->active)
2205 fbc->funcs->set_false_color(fbc, fbc->false_color);
2206
2207 mutex_unlock(lock: &fbc->lock);
2208
2209 return 0;
2210}
2211
2212DEFINE_DEBUGFS_ATTRIBUTE(intel_fbc_debugfs_false_color_fops,
2213 intel_fbc_debugfs_false_color_get,
2214 intel_fbc_debugfs_false_color_set,
2215 "%llu\n");
2216
2217static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
2218 struct dentry *parent)
2219{
2220 debugfs_create_file("i915_fbc_status", 0444, parent,
2221 fbc, &intel_fbc_debugfs_status_fops);
2222
2223 if (fbc->funcs->set_false_color)
2224 debugfs_create_file_unsafe(name: "i915_fbc_false_color", mode: 0644, parent,
2225 data: fbc, fops: &intel_fbc_debugfs_false_color_fops);
2226}
2227
2228void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
2229{
2230 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2231
2232 if (plane->fbc)
2233 intel_fbc_debugfs_add(fbc: plane->fbc, parent: crtc->base.debugfs_entry);
2234}
2235
2236/* FIXME: remove this once igt is on board with per-crtc stuff */
2237void intel_fbc_debugfs_register(struct intel_display *display)
2238{
2239 struct intel_fbc *fbc;
2240
2241 fbc = display->fbc[INTEL_FBC_A];
2242 if (fbc)
2243 intel_fbc_debugfs_add(fbc, parent: display->drm->debugfs_root);
2244}
2245