1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Author: Damien Lespiau <damien.lespiau@intel.com>
24 *
25 */
26
27#include <linux/ctype.h>
28#include <linux/debugfs.h>
29#include <linux/seq_file.h>
30
31#include "i915_drv.h"
32#include "i915_irq.h"
33#include "intel_atomic.h"
34#include "intel_de.h"
35#include "intel_display_irq.h"
36#include "intel_display_regs.h"
37#include "intel_display_types.h"
38#include "intel_pipe_crc.h"
39#include "intel_pipe_crc_regs.h"
40
41static const char * const pipe_crc_sources[] = {
42 [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
43 [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
44 [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
45 [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
46 [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
47 [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
48 [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
49 [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
50 [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
51 [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
52 [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
53 [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
54 [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
55 [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
56};
57
58static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
59 u32 *val)
60{
61 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
62 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
63
64 switch (*source) {
65 case INTEL_PIPE_CRC_SOURCE_PIPE:
66 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
67 break;
68 case INTEL_PIPE_CRC_SOURCE_NONE:
69 *val = 0;
70 break;
71 default:
72 return -EINVAL;
73 }
74
75 return 0;
76}
77
78static void i9xx_pipe_crc_auto_source(struct intel_display *display,
79 enum pipe pipe,
80 enum intel_pipe_crc_source *source)
81{
82 struct intel_encoder *encoder;
83 struct intel_crtc *crtc;
84 struct intel_digital_port *dig_port;
85
86 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
87
88 drm_modeset_lock_all(dev: display->drm);
89 for_each_intel_encoder(display->drm, encoder) {
90 if (!encoder->base.crtc)
91 continue;
92
93 crtc = to_intel_crtc(encoder->base.crtc);
94
95 if (crtc->pipe != pipe)
96 continue;
97
98 switch (encoder->type) {
99 case INTEL_OUTPUT_TVOUT:
100 *source = INTEL_PIPE_CRC_SOURCE_TV;
101 break;
102 case INTEL_OUTPUT_DP:
103 case INTEL_OUTPUT_EDP:
104 dig_port = enc_to_dig_port(encoder);
105 switch (dig_port->base.port) {
106 case PORT_B:
107 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
108 break;
109 case PORT_C:
110 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
111 break;
112 case PORT_D:
113 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
114 break;
115 default:
116 drm_WARN(display->drm, 1, "nonexisting DP port %c\n",
117 port_name(dig_port->base.port));
118 break;
119 }
120 break;
121 default:
122 break;
123 }
124 }
125 drm_modeset_unlock_all(dev: display->drm);
126}
127
128static int vlv_pipe_crc_ctl_reg(struct intel_display *display,
129 enum pipe pipe,
130 enum intel_pipe_crc_source *source,
131 u32 *val)
132{
133 bool need_stable_symbols = false;
134
135 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
136 i9xx_pipe_crc_auto_source(display, pipe, source);
137
138 switch (*source) {
139 case INTEL_PIPE_CRC_SOURCE_PIPE:
140 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
141 break;
142 case INTEL_PIPE_CRC_SOURCE_DP_B:
143 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
144 need_stable_symbols = true;
145 break;
146 case INTEL_PIPE_CRC_SOURCE_DP_C:
147 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
148 need_stable_symbols = true;
149 break;
150 case INTEL_PIPE_CRC_SOURCE_DP_D:
151 if (!display->platform.cherryview)
152 return -EINVAL;
153 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
154 need_stable_symbols = true;
155 break;
156 case INTEL_PIPE_CRC_SOURCE_NONE:
157 *val = 0;
158 break;
159 default:
160 return -EINVAL;
161 }
162
163 /*
164 * When the pipe CRC tap point is after the transcoders we need
165 * to tweak symbol-level features to produce a deterministic series of
166 * symbols for a given frame. We need to reset those features only once
167 * a frame (instead of every nth symbol):
168 * - DC-balance: used to ensure a better clock recovery from the data
169 * link (SDVO)
170 * - DisplayPort scrambling: used for EMI reduction
171 */
172 if (need_stable_symbols) {
173 u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));
174
175 tmp |= DC_BALANCE_RESET_VLV;
176 switch (pipe) {
177 case PIPE_A:
178 tmp |= PIPE_A_SCRAMBLE_RESET;
179 break;
180 case PIPE_B:
181 tmp |= PIPE_B_SCRAMBLE_RESET;
182 break;
183 case PIPE_C:
184 tmp |= PIPE_C_SCRAMBLE_RESET;
185 break;
186 default:
187 return -EINVAL;
188 }
189 intel_de_write(display, PORT_DFT2_G4X(display), val: tmp);
190 }
191
192 return 0;
193}
194
195static int i9xx_pipe_crc_ctl_reg(struct intel_display *display,
196 enum pipe pipe,
197 enum intel_pipe_crc_source *source,
198 u32 *val)
199{
200 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
201 i9xx_pipe_crc_auto_source(display, pipe, source);
202
203 switch (*source) {
204 case INTEL_PIPE_CRC_SOURCE_PIPE:
205 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
206 break;
207 case INTEL_PIPE_CRC_SOURCE_TV:
208 if (!SUPPORTS_TV(display))
209 return -EINVAL;
210 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
211 break;
212 case INTEL_PIPE_CRC_SOURCE_NONE:
213 *val = 0;
214 break;
215 default:
216 /*
217 * The DP CRC source doesn't work on g4x.
218 * It can be made to work to some degree by selecting
219 * the correct CRC source before the port is enabled,
220 * and not touching the CRC source bits again until
221 * the port is disabled. But even then the bits
222 * eventually get stuck and a reboot is needed to get
223 * working CRCs on the pipe again. Let's simply
224 * refuse to use DP CRCs on g4x.
225 */
226 return -EINVAL;
227 }
228
229 return 0;
230}
231
232static void vlv_undo_pipe_scramble_reset(struct intel_display *display,
233 enum pipe pipe)
234{
235 u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));
236
237 switch (pipe) {
238 case PIPE_A:
239 tmp &= ~PIPE_A_SCRAMBLE_RESET;
240 break;
241 case PIPE_B:
242 tmp &= ~PIPE_B_SCRAMBLE_RESET;
243 break;
244 case PIPE_C:
245 tmp &= ~PIPE_C_SCRAMBLE_RESET;
246 break;
247 default:
248 return;
249 }
250 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
251 tmp &= ~DC_BALANCE_RESET_VLV;
252 intel_de_write(display, PORT_DFT2_G4X(display), val: tmp);
253}
254
255static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
256 u32 *val)
257{
258 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
259 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
260
261 switch (*source) {
262 case INTEL_PIPE_CRC_SOURCE_PLANE1:
263 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
264 break;
265 case INTEL_PIPE_CRC_SOURCE_PLANE2:
266 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
267 break;
268 case INTEL_PIPE_CRC_SOURCE_PIPE:
269 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
270 break;
271 case INTEL_PIPE_CRC_SOURCE_NONE:
272 *val = 0;
273 break;
274 default:
275 return -EINVAL;
276 }
277
278 return 0;
279}
280
281static void
282intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
283{
284 struct intel_display *display = to_intel_display(crtc);
285 struct intel_crtc_state *pipe_config;
286 struct drm_atomic_state *state;
287 struct drm_modeset_acquire_ctx ctx;
288 int ret;
289
290 if (display->platform.i945gm || display->platform.i915gm)
291 i915gm_irq_cstate_wa(display, enable);
292
293 drm_modeset_acquire_init(ctx: &ctx, flags: 0);
294
295 state = drm_atomic_state_alloc(dev: display->drm);
296 if (!state) {
297 ret = -ENOMEM;
298 goto unlock;
299 }
300
301 state->acquire_ctx = &ctx;
302 to_intel_atomic_state(state)->internal = true;
303
304retry:
305 pipe_config = intel_atomic_get_crtc_state(state, crtc);
306 if (IS_ERR(ptr: pipe_config)) {
307 ret = PTR_ERR(ptr: pipe_config);
308 goto put_state;
309 }
310
311 pipe_config->uapi.mode_changed = pipe_config->has_psr;
312 pipe_config->crc_enabled = enable;
313
314 if (display->platform.haswell &&
315 pipe_config->hw.active && crtc->pipe == PIPE_A &&
316 pipe_config->cpu_transcoder == TRANSCODER_EDP)
317 pipe_config->uapi.mode_changed = true;
318
319 ret = drm_atomic_commit(state);
320
321put_state:
322 if (ret == -EDEADLK) {
323 drm_atomic_state_clear(state);
324 drm_modeset_backoff(ctx: &ctx);
325 goto retry;
326 }
327
328 drm_atomic_state_put(state);
329unlock:
330 drm_WARN(display->drm, ret,
331 "Toggling workaround to %i returns %i\n", enable, ret);
332 drm_modeset_drop_locks(ctx: &ctx);
333 drm_modeset_acquire_fini(ctx: &ctx);
334}
335
336static int ivb_pipe_crc_ctl_reg(struct intel_display *display,
337 enum pipe pipe,
338 enum intel_pipe_crc_source *source,
339 u32 *val)
340{
341 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
342 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
343
344 switch (*source) {
345 case INTEL_PIPE_CRC_SOURCE_PLANE1:
346 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
347 break;
348 case INTEL_PIPE_CRC_SOURCE_PLANE2:
349 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
350 break;
351 case INTEL_PIPE_CRC_SOURCE_PIPE:
352 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
353 break;
354 case INTEL_PIPE_CRC_SOURCE_NONE:
355 *val = 0;
356 break;
357 default:
358 return -EINVAL;
359 }
360
361 return 0;
362}
363
364static int skl_pipe_crc_ctl_reg(struct intel_display *display,
365 enum pipe pipe,
366 enum intel_pipe_crc_source *source,
367 u32 *val)
368{
369 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
370 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
371
372 switch (*source) {
373 case INTEL_PIPE_CRC_SOURCE_PLANE1:
374 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
375 break;
376 case INTEL_PIPE_CRC_SOURCE_PLANE2:
377 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
378 break;
379 case INTEL_PIPE_CRC_SOURCE_PLANE3:
380 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
381 break;
382 case INTEL_PIPE_CRC_SOURCE_PLANE4:
383 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
384 break;
385 case INTEL_PIPE_CRC_SOURCE_PLANE5:
386 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
387 break;
388 case INTEL_PIPE_CRC_SOURCE_PLANE6:
389 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
390 break;
391 case INTEL_PIPE_CRC_SOURCE_PLANE7:
392 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
393 break;
394 case INTEL_PIPE_CRC_SOURCE_PIPE:
395 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
396 break;
397 case INTEL_PIPE_CRC_SOURCE_NONE:
398 *val = 0;
399 break;
400 default:
401 return -EINVAL;
402 }
403
404 return 0;
405}
406
407static int get_new_crc_ctl_reg(struct intel_display *display,
408 enum pipe pipe,
409 enum intel_pipe_crc_source *source, u32 *val)
410{
411 if (DISPLAY_VER(display) == 2)
412 return i8xx_pipe_crc_ctl_reg(source, val);
413 else if (DISPLAY_VER(display) < 5)
414 return i9xx_pipe_crc_ctl_reg(display, pipe, source, val);
415 else if (display->platform.valleyview || display->platform.cherryview)
416 return vlv_pipe_crc_ctl_reg(display, pipe, source, val);
417 else if (display->platform.ironlake || display->platform.sandybridge)
418 return ilk_pipe_crc_ctl_reg(source, val);
419 else if (DISPLAY_VER(display) < 9)
420 return ivb_pipe_crc_ctl_reg(display, pipe, source, val);
421 else
422 return skl_pipe_crc_ctl_reg(display, pipe, source, val);
423}
424
425static int
426display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
427{
428 int i;
429
430 if (!buf) {
431 *s = INTEL_PIPE_CRC_SOURCE_NONE;
432 return 0;
433 }
434
435 i = match_string(array: pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), string: buf);
436 if (i < 0)
437 return i;
438
439 *s = i;
440 return 0;
441}
442
443void intel_crtc_crc_init(struct intel_crtc *crtc)
444{
445 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
446
447 spin_lock_init(&pipe_crc->lock);
448}
449
450static int i8xx_crc_source_valid(struct intel_display *display,
451 const enum intel_pipe_crc_source source)
452{
453 switch (source) {
454 case INTEL_PIPE_CRC_SOURCE_PIPE:
455 case INTEL_PIPE_CRC_SOURCE_NONE:
456 return 0;
457 default:
458 return -EINVAL;
459 }
460}
461
462static int i9xx_crc_source_valid(struct intel_display *display,
463 const enum intel_pipe_crc_source source)
464{
465 switch (source) {
466 case INTEL_PIPE_CRC_SOURCE_PIPE:
467 case INTEL_PIPE_CRC_SOURCE_TV:
468 case INTEL_PIPE_CRC_SOURCE_NONE:
469 return 0;
470 default:
471 return -EINVAL;
472 }
473}
474
475static int vlv_crc_source_valid(struct intel_display *display,
476 const enum intel_pipe_crc_source source)
477{
478 switch (source) {
479 case INTEL_PIPE_CRC_SOURCE_PIPE:
480 case INTEL_PIPE_CRC_SOURCE_DP_B:
481 case INTEL_PIPE_CRC_SOURCE_DP_C:
482 case INTEL_PIPE_CRC_SOURCE_DP_D:
483 case INTEL_PIPE_CRC_SOURCE_NONE:
484 return 0;
485 default:
486 return -EINVAL;
487 }
488}
489
490static int ilk_crc_source_valid(struct intel_display *display,
491 const enum intel_pipe_crc_source source)
492{
493 switch (source) {
494 case INTEL_PIPE_CRC_SOURCE_PIPE:
495 case INTEL_PIPE_CRC_SOURCE_PLANE1:
496 case INTEL_PIPE_CRC_SOURCE_PLANE2:
497 case INTEL_PIPE_CRC_SOURCE_NONE:
498 return 0;
499 default:
500 return -EINVAL;
501 }
502}
503
504static int ivb_crc_source_valid(struct intel_display *display,
505 const enum intel_pipe_crc_source source)
506{
507 switch (source) {
508 case INTEL_PIPE_CRC_SOURCE_PIPE:
509 case INTEL_PIPE_CRC_SOURCE_PLANE1:
510 case INTEL_PIPE_CRC_SOURCE_PLANE2:
511 case INTEL_PIPE_CRC_SOURCE_NONE:
512 return 0;
513 default:
514 return -EINVAL;
515 }
516}
517
518static int skl_crc_source_valid(struct intel_display *display,
519 const enum intel_pipe_crc_source source)
520{
521 switch (source) {
522 case INTEL_PIPE_CRC_SOURCE_PIPE:
523 case INTEL_PIPE_CRC_SOURCE_PLANE1:
524 case INTEL_PIPE_CRC_SOURCE_PLANE2:
525 case INTEL_PIPE_CRC_SOURCE_PLANE3:
526 case INTEL_PIPE_CRC_SOURCE_PLANE4:
527 case INTEL_PIPE_CRC_SOURCE_PLANE5:
528 case INTEL_PIPE_CRC_SOURCE_PLANE6:
529 case INTEL_PIPE_CRC_SOURCE_PLANE7:
530 case INTEL_PIPE_CRC_SOURCE_NONE:
531 return 0;
532 default:
533 return -EINVAL;
534 }
535}
536
537static int
538intel_is_valid_crc_source(struct intel_display *display,
539 const enum intel_pipe_crc_source source)
540{
541 if (DISPLAY_VER(display) == 2)
542 return i8xx_crc_source_valid(display, source);
543 else if (DISPLAY_VER(display) < 5)
544 return i9xx_crc_source_valid(display, source);
545 else if (display->platform.valleyview || display->platform.cherryview)
546 return vlv_crc_source_valid(display, source);
547 else if (display->platform.ironlake || display->platform.sandybridge)
548 return ilk_crc_source_valid(display, source);
549 else if (DISPLAY_VER(display) < 9)
550 return ivb_crc_source_valid(display, source);
551 else
552 return skl_crc_source_valid(display, source);
553}
554
555const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
556 size_t *count)
557{
558 *count = ARRAY_SIZE(pipe_crc_sources);
559 return pipe_crc_sources;
560}
561
562int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
563 size_t *values_cnt)
564{
565 struct intel_display *display = to_intel_display(crtc->dev);
566 enum intel_pipe_crc_source source;
567
568 if (display_crc_ctl_parse_source(buf: source_name, s: &source) < 0) {
569 drm_dbg_kms(display->drm, "unknown source %s\n", source_name);
570 return -EINVAL;
571 }
572
573 if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
574 intel_is_valid_crc_source(display, source) == 0) {
575 *values_cnt = 5;
576 return 0;
577 }
578
579 return -EINVAL;
580}
581
582int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
583{
584 struct intel_crtc *crtc = to_intel_crtc(_crtc);
585 struct intel_display *display = to_intel_display(crtc);
586 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
587 enum intel_display_power_domain power_domain;
588 enum intel_pipe_crc_source source;
589 enum pipe pipe = crtc->pipe;
590 intel_wakeref_t wakeref;
591 u32 val = 0; /* shut up gcc */
592 int ret = 0;
593 bool enable;
594
595 if (display_crc_ctl_parse_source(buf: source_name, s: &source) < 0) {
596 drm_dbg_kms(display->drm, "unknown source %s\n", source_name);
597 return -EINVAL;
598 }
599
600 power_domain = POWER_DOMAIN_PIPE(pipe);
601 wakeref = intel_display_power_get_if_enabled(display, domain: power_domain);
602 if (!wakeref) {
603 drm_dbg_kms(display->drm,
604 "Trying to capture CRC while pipe is off\n");
605 return -EIO;
606 }
607
608 enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
609 if (enable)
610 intel_crtc_crc_setup_workarounds(crtc, enable: true);
611
612 ret = get_new_crc_ctl_reg(display, pipe, source: &source, val: &val);
613 if (ret != 0)
614 goto out;
615
616 pipe_crc->source = source;
617 intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);
618 intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));
619
620 if (!source) {
621 if (display->platform.valleyview || display->platform.cherryview)
622 vlv_undo_pipe_scramble_reset(display, pipe);
623 }
624
625 pipe_crc->skipped = 0;
626
627out:
628 if (!enable)
629 intel_crtc_crc_setup_workarounds(crtc, enable: false);
630
631 intel_display_power_put(display, domain: power_domain, wakeref);
632
633 return ret;
634}
635
636void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
637{
638 struct intel_display *display = to_intel_display(crtc);
639 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
640 enum pipe pipe = crtc->pipe;
641 u32 val = 0;
642
643 if (!crtc->base.crc.opened)
644 return;
645
646 if (get_new_crc_ctl_reg(display, pipe, source: &pipe_crc->source, val: &val) < 0)
647 return;
648
649 /* Don't need pipe_crc->lock here, IRQs are not generated. */
650 pipe_crc->skipped = 0;
651
652 intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);
653 intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));
654}
655
656void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
657{
658 struct intel_display *display = to_intel_display(crtc);
659 struct drm_i915_private *dev_priv = to_i915(dev: display->drm);
660 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
661 enum pipe pipe = crtc->pipe;
662
663 /* Swallow crc's until we stop generating them. */
664 spin_lock_irq(lock: &pipe_crc->lock);
665 pipe_crc->skipped = INT_MIN;
666 spin_unlock_irq(lock: &pipe_crc->lock);
667
668 intel_de_write(display, PIPE_CRC_CTL(display, pipe), val: 0);
669 intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));
670 intel_synchronize_irq(i915: dev_priv);
671}
672