1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022-2023 Intel Corporation
4 */
5
6#include <linux/iopoll.h>
7
8#include <drm/drm_vblank.h>
9
10#include "i915_drv.h"
11#include "i915_utils.h"
12#include "intel_color.h"
13#include "intel_crtc.h"
14#include "intel_de.h"
15#include "intel_display_regs.h"
16#include "intel_display_types.h"
17#include "intel_vblank.h"
18#include "intel_vrr.h"
19
20/*
21 * This timing diagram depicts the video signal in and
22 * around the vertical blanking period.
23 *
24 * Assumptions about the fictitious mode used in this example:
25 * vblank_start >= 3
26 * vsync_start = vblank_start + 1
27 * vsync_end = vblank_start + 2
28 * vtotal = vblank_start + 3
29 *
30 * start of vblank:
31 * latch double buffered registers
32 * increment frame counter (ctg+)
33 * generate start of vblank interrupt (gen4+)
34 * |
35 * | frame start:
36 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
37 * | may be shifted forward 1-3 extra lines via TRANSCONF
38 * | |
39 * | | start of vsync:
40 * | | generate vsync interrupt
41 * | | |
42 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
43 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
44 * ----va---> <-----------------vb--------------------> <--------va-------------
45 * | | <----vs-----> |
46 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
47 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
48 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
49 * | | |
50 * last visible pixel first visible pixel
51 * | increment frame counter (gen3/4)
52 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
53 *
54 * x = horizontal active
55 * _ = horizontal blanking
56 * hs = horizontal sync
57 * va = vertical active
58 * vb = vertical blanking
59 * vs = vertical sync
60 * vbs = vblank_start (number)
61 *
62 * Summary:
63 * - most events happen at the start of horizontal sync
64 * - frame start happens at the start of horizontal blank, 1-4 lines
65 * (depending on TRANSCONF settings) after the start of vblank
66 * - gen3/4 pixel and frame counter are synchronized with the start
67 * of horizontal active on the first line of vertical active
68 */
69
70/*
71 * Called from drm generic code, passed a 'crtc', which we use as a pipe index.
72 */
73u32 i915_get_vblank_counter(struct drm_crtc *crtc)
74{
75 struct intel_display *display = to_intel_display(crtc->dev);
76 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
77 const struct drm_display_mode *mode = &vblank->hwmode;
78 enum pipe pipe = to_intel_crtc(crtc)->pipe;
79 u32 pixel, vbl_start, hsync_start, htotal;
80 u64 frame;
81
82 /*
83 * On i965gm TV output the frame counter only works up to
84 * the point when we enable the TV encoder. After that the
85 * frame counter ceases to work and reads zero. We need a
86 * vblank wait before enabling the TV encoder and so we
87 * have to enable vblank interrupts while the frame counter
88 * is still in a working state. However the core vblank code
89 * does not like us returning non-zero frame counter values
90 * when we've told it that we don't have a working frame
91 * counter. Thus we must stop non-zero values leaking out.
92 */
93 if (!vblank->max_vblank_count)
94 return 0;
95
96 htotal = mode->crtc_htotal;
97 hsync_start = mode->crtc_hsync_start;
98 vbl_start = intel_mode_vblank_start(mode);
99
100 /* Convert to pixel count */
101 vbl_start *= htotal;
102
103 /* Start of vblank event occurs at start of hsync */
104 vbl_start -= htotal - hsync_start;
105
106 /*
107 * High & low register fields aren't synchronized, so make sure
108 * we get a low value that's stable across two reads of the high
109 * register.
110 */
111 frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),
112 PIPEFRAME(display, pipe));
113
114 pixel = frame & PIPE_PIXEL_MASK;
115 frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
116
117 /*
118 * The frame counter increments at beginning of active.
119 * Cook up a vblank counter by also checking the pixel
120 * counter against vblank start.
121 */
122 return (frame + (pixel >= vbl_start)) & 0xffffff;
123}
124
125u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
126{
127 struct intel_display *display = to_intel_display(crtc->dev);
128 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
129 enum pipe pipe = to_intel_crtc(crtc)->pipe;
130
131 if (!vblank->max_vblank_count)
132 return 0;
133
134 return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
135}
136
137static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
138{
139 struct intel_display *display = to_intel_display(crtc);
140 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc: &crtc->base);
141 const struct drm_display_mode *mode = &vblank->hwmode;
142 u32 htotal = mode->crtc_htotal;
143 u32 clock = mode->crtc_clock;
144 u32 scan_prev_time, scan_curr_time, scan_post_time;
145
146 /*
147 * To avoid the race condition where we might cross into the
148 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
149 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
150 * during the same frame.
151 */
152 do {
153 /*
154 * This field provides read back of the display
155 * pipe frame time stamp. The time stamp value
156 * is sampled at every start of vertical blank.
157 */
158 scan_prev_time = intel_de_read_fw(display,
159 PIPE_FRMTMSTMP(crtc->pipe));
160
161 /*
162 * The TIMESTAMP_CTR register has the current
163 * time stamp value.
164 */
165 scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);
166
167 scan_post_time = intel_de_read_fw(display,
168 PIPE_FRMTMSTMP(crtc->pipe));
169 } while (scan_post_time != scan_prev_time);
170
171 return div_u64(dividend: mul_u32_u32(a: scan_curr_time - scan_prev_time,
172 b: clock), divisor: 1000 * htotal);
173}
174
175/*
176 * On certain encoders on certain platforms, pipe
177 * scanline register will not work to get the scanline,
178 * since the timings are driven from the PORT or issues
179 * with scanline register updates.
180 * This function will use Framestamp and current
181 * timestamp registers to calculate the scanline.
182 */
183static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
184{
185 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc: &crtc->base);
186 const struct drm_display_mode *mode = &vblank->hwmode;
187 u32 vblank_start = mode->crtc_vblank_start;
188 u32 vtotal = mode->crtc_vtotal;
189 u32 scanline;
190
191 scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
192 scanline = min(scanline, vtotal - 1);
193 scanline = (scanline + vblank_start) % vtotal;
194
195 return scanline;
196}
197
198int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
199{
200 struct intel_display *display = to_intel_display(crtc_state);
201
202 /*
203 * The scanline counter increments at the leading edge of hsync.
204 *
205 * On most platforms it starts counting from vtotal-1 on the
206 * first active line. That means the scanline counter value is
207 * always one less than what we would expect. Ie. just after
208 * start of vblank, which also occurs at start of hsync (on the
209 * last active line), the scanline counter will read vblank_start-1.
210 *
211 * On gen2 the scanline counter starts counting from 1 instead
212 * of vtotal-1, so we have to subtract one.
213 *
214 * On HSW+ the behaviour of the scanline counter depends on the output
215 * type. For DP ports it behaves like most other platforms, but on HDMI
216 * there's an extra 1 line difference. So we need to add two instead of
217 * one to the value.
218 *
219 * On VLV/CHV DSI the scanline counter would appear to increment
220 * approx. 1/3 of a scanline before start of vblank. Unfortunately
221 * that means we can't tell whether we're in vblank or not while
222 * we're on that particular line. We must still set scanline_offset
223 * to 1 so that the vblank timestamps come out correct when we query
224 * the scanline counter from within the vblank interrupt handler.
225 * However if queried just before the start of vblank we'll get an
226 * answer that's slightly in the future.
227 */
228 if (DISPLAY_VER(display) >= 20 || display->platform.battlemage)
229 return 1;
230 else if (DISPLAY_VER(display) >= 9 ||
231 display->platform.broadwell || display->platform.haswell)
232 return intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI) ? 2 : 1;
233 else if (DISPLAY_VER(display) >= 3)
234 return 1;
235 else
236 return -1;
237}
238
239/*
240 * intel_de_read_fw(), only for fast reads of display block, no need for
241 * forcewake etc.
242 */
243static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
244{
245 struct intel_display *display = to_intel_display(crtc);
246 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc: &crtc->base);
247 const struct drm_display_mode *mode = &vblank->hwmode;
248 enum pipe pipe = crtc->pipe;
249 int position, vtotal;
250
251 if (!crtc->active)
252 return 0;
253
254 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
255 return __intel_get_crtc_scanline_from_timestamp(crtc);
256
257 vtotal = intel_mode_vtotal(mode);
258
259 position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
260
261 /*
262 * On HSW, the DSL reg (0x70000) appears to return 0 if we
263 * read it just before the start of vblank. So try it again
264 * so we don't accidentally end up spanning a vblank frame
265 * increment, causing the pipe_update_end() code to squak at us.
266 *
267 * The nature of this problem means we can't simply check the ISR
268 * bit and return the vblank start value; nor can we use the scanline
269 * debug register in the transcoder as it appears to have the same
270 * problem. We may need to extend this to include other platforms,
271 * but so far testing only shows the problem on HSW.
272 */
273 if (HAS_DDI(display) && !position) {
274 int i, temp;
275
276 for (i = 0; i < 100; i++) {
277 udelay(usec: 1);
278 temp = intel_de_read_fw(display,
279 PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
280 if (temp != position) {
281 position = temp;
282 break;
283 }
284 }
285 }
286
287 /*
288 * See update_scanline_offset() for the details on the
289 * scanline_offset adjustment.
290 */
291 return (position + vtotal + crtc->scanline_offset) % vtotal;
292}
293
294/*
295 * The uncore version of the spin lock functions is used to decide
296 * whether we need to lock the uncore lock or not. This is only
297 * needed in i915, not in Xe.
298 *
299 * This lock in i915 is needed because some old platforms (at least
300 * IVB and possibly HSW as well), which are not supported in Xe, need
301 * all register accesses to the same cacheline to be serialized,
302 * otherwise they may hang.
303 */
304#ifdef I915
305static void intel_vblank_section_enter(struct intel_display *display)
306 __acquires(i915->uncore.lock)
307{
308 struct drm_i915_private *i915 = to_i915(dev: display->drm);
309 spin_lock(lock: &i915->uncore.lock);
310}
311
312static void intel_vblank_section_exit(struct intel_display *display)
313 __releases(i915->uncore.lock)
314{
315 struct drm_i915_private *i915 = to_i915(dev: display->drm);
316 spin_unlock(lock: &i915->uncore.lock);
317}
318#else
319static void intel_vblank_section_enter(struct intel_display *display)
320{
321}
322
323static void intel_vblank_section_exit(struct intel_display *display)
324{
325}
326#endif
327
328static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
329 bool in_vblank_irq,
330 int *vpos, int *hpos,
331 ktime_t *stime, ktime_t *etime,
332 const struct drm_display_mode *mode)
333{
334 struct intel_display *display = to_intel_display(_crtc->dev);
335 struct intel_crtc *crtc = to_intel_crtc(_crtc);
336 enum pipe pipe = crtc->pipe;
337 int position;
338 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
339 unsigned long irqflags;
340 bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||
341 display->platform.g4x || DISPLAY_VER(display) == 2 ||
342 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
343
344 if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {
345 drm_dbg(display->drm,
346 "trying to get scanoutpos for disabled pipe %c\n",
347 pipe_name(pipe));
348 return false;
349 }
350
351 htotal = mode->crtc_htotal;
352 hsync_start = mode->crtc_hsync_start;
353 vtotal = intel_mode_vtotal(mode);
354 vbl_start = intel_mode_vblank_start(mode);
355 vbl_end = intel_mode_vblank_end(mode);
356
357 /*
358 * Enter vblank critical section, as we will do multiple
359 * timing critical raw register reads, potentially with
360 * preemption disabled, so the following code must not block.
361 */
362 local_irq_save(irqflags);
363 intel_vblank_section_enter(display);
364
365 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
366
367 /* Get optional system timestamp before query. */
368 if (stime)
369 *stime = ktime_get();
370
371 if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
372 int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
373
374 position = __intel_get_crtc_scanline(crtc);
375
376 /*
377 * Already exiting vblank? If so, shift our position
378 * so it looks like we're already approaching the full
379 * vblank end. This should make the generated timestamp
380 * more or less match when the active portion will start.
381 */
382 if (position >= vbl_start && scanlines < position)
383 position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
384 } else if (use_scanline_counter) {
385 /* No obvious pixelcount register. Only query vertical
386 * scanout position from Display scan line register.
387 */
388 position = __intel_get_crtc_scanline(crtc);
389 } else {
390 /*
391 * Have access to pixelcount since start of frame.
392 * We can split this into vertical and horizontal
393 * scanout position.
394 */
395 position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
396
397 /* convert to pixel counts */
398 vbl_start *= htotal;
399 vbl_end *= htotal;
400 vtotal *= htotal;
401
402 /*
403 * In interlaced modes, the pixel counter counts all pixels,
404 * so one field will have htotal more pixels. In order to avoid
405 * the reported position from jumping backwards when the pixel
406 * counter is beyond the length of the shorter field, just
407 * clamp the position the length of the shorter field. This
408 * matches how the scanline counter based position works since
409 * the scanline counter doesn't count the two half lines.
410 */
411 position = min(position, vtotal - 1);
412
413 /*
414 * Start of vblank interrupt is triggered at start of hsync,
415 * just prior to the first active line of vblank. However we
416 * consider lines to start at the leading edge of horizontal
417 * active. So, should we get here before we've crossed into
418 * the horizontal active of the first line in vblank, we would
419 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
420 * always add htotal-hsync_start to the current pixel position.
421 */
422 position = (position + htotal - hsync_start) % vtotal;
423 }
424
425 /* Get optional system timestamp after query. */
426 if (etime)
427 *etime = ktime_get();
428
429 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
430
431 intel_vblank_section_exit(display);
432 local_irq_restore(irqflags);
433
434 /*
435 * While in vblank, position will be negative
436 * counting up towards 0 at vbl_end. And outside
437 * vblank, position will be positive counting
438 * up since vbl_end.
439 */
440 if (position >= vbl_start)
441 position -= vbl_end;
442 else
443 position += vtotal - vbl_end;
444
445 if (use_scanline_counter) {
446 *vpos = position;
447 *hpos = 0;
448 } else {
449 *vpos = position / htotal;
450 *hpos = position - (*vpos * htotal);
451 }
452
453 return true;
454}
455
456bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
457 ktime_t *vblank_time, bool in_vblank_irq)
458{
459 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
460 crtc, max_error, vblank_time, in_vblank_irq,
461 get_scanout_position: i915_get_crtc_scanoutpos);
462}
463
464int intel_get_crtc_scanline(struct intel_crtc *crtc)
465{
466 struct intel_display *display = to_intel_display(crtc);
467 unsigned long irqflags;
468 int position;
469
470 local_irq_save(irqflags);
471 intel_vblank_section_enter(display);
472
473 position = __intel_get_crtc_scanline(crtc);
474
475 intel_vblank_section_exit(display);
476 local_irq_restore(irqflags);
477
478 return position;
479}
480
481static bool pipe_scanline_is_moving(struct intel_display *display,
482 enum pipe pipe)
483{
484 i915_reg_t reg = PIPEDSL(display, pipe);
485 u32 line1, line2;
486
487 line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
488 msleep(msecs: 5);
489 line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
490
491 return line1 != line2;
492}
493
494static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
495{
496 struct intel_display *display = to_intel_display(crtc);
497 enum pipe pipe = crtc->pipe;
498 bool is_moving;
499 int ret;
500
501 /* Wait for the display line to settle/start moving */
502 ret = poll_timeout_us(is_moving = pipe_scanline_is_moving(display, pipe),
503 is_moving == state,
504 500, 100 * 1000, false);
505 if (ret)
506 drm_err(display->drm,
507 "pipe %c scanline %s wait timed out\n",
508 pipe_name(pipe), str_on_off(state));
509}
510
511void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
512{
513 wait_for_pipe_scanline_moving(crtc, state: false);
514}
515
516void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
517{
518 wait_for_pipe_scanline_moving(crtc, state: true);
519}
520
521static void intel_crtc_active_timings(struct drm_display_mode *mode,
522 int *vmax_vblank_start,
523 const struct intel_crtc_state *crtc_state,
524 bool vrr_enable)
525{
526 drm_mode_init(dst: mode, src: &crtc_state->hw.adjusted_mode);
527 *vmax_vblank_start = 0;
528
529 if (!vrr_enable)
530 return;
531
532 mode->crtc_vtotal = intel_vrr_vmax_vtotal(crtc_state);
533 mode->crtc_vblank_end = intel_vrr_vmax_vtotal(crtc_state);
534 mode->crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
535 *vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
536}
537
538void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
539 bool vrr_enable)
540{
541 struct intel_display *display = to_intel_display(crtc_state);
542 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
543 u8 mode_flags = crtc_state->mode_flags;
544 struct drm_display_mode adjusted_mode;
545 int vmax_vblank_start = 0;
546 unsigned long irqflags;
547
548 intel_crtc_active_timings(mode: &adjusted_mode, vmax_vblank_start: &vmax_vblank_start,
549 crtc_state, vrr_enable);
550
551 if (vrr_enable)
552 drm_WARN_ON(display->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);
553 else
554 mode_flags &= ~I915_MODE_FLAG_VRR;
555
556 /*
557 * Belts and suspenders locking to guarantee everyone sees 100%
558 * consistent state during fastset seamless refresh rate changes.
559 *
560 * vblank_time_lock takes care of all drm_vblank.c stuff, and
561 * uncore.lock takes care of __intel_get_crtc_scanline() which
562 * may get called elsewhere as well.
563 *
564 * TODO maybe just protect everything (including
565 * __intel_get_crtc_scanline()) with vblank_time_lock?
566 * Need to audit everything to make sure it's safe.
567 */
568 spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags);
569 intel_vblank_section_enter(display);
570
571 drm_calc_timestamping_constants(crtc: &crtc->base, mode: &adjusted_mode);
572
573 crtc->vmax_vblank_start = vmax_vblank_start;
574
575 crtc->mode_flags = mode_flags;
576
577 crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
578 intel_vblank_section_exit(display);
579 spin_unlock_irqrestore(lock: &display->drm->vblank_time_lock, flags: irqflags);
580}
581
582int intel_mode_vdisplay(const struct drm_display_mode *mode)
583{
584 int vdisplay = mode->crtc_vdisplay;
585
586 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
587 vdisplay = DIV_ROUND_UP(vdisplay, 2);
588
589 return vdisplay;
590}
591
592int intel_mode_vblank_start(const struct drm_display_mode *mode)
593{
594 int vblank_start = mode->crtc_vblank_start;
595
596 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
597 vblank_start = DIV_ROUND_UP(vblank_start, 2);
598
599 return vblank_start;
600}
601
602int intel_mode_vblank_end(const struct drm_display_mode *mode)
603{
604 int vblank_end = mode->crtc_vblank_end;
605
606 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
607 vblank_end /= 2;
608
609 return vblank_end;
610}
611
612int intel_mode_vtotal(const struct drm_display_mode *mode)
613{
614 int vtotal = mode->crtc_vtotal;
615
616 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
617 vtotal /= 2;
618
619 return vtotal;
620}
621
622int intel_mode_vblank_delay(const struct drm_display_mode *mode)
623{
624 return intel_mode_vblank_start(mode) - intel_mode_vdisplay(mode);
625}
626
627static const struct intel_crtc_state *
628pre_commit_crtc_state(const struct intel_crtc_state *old_crtc_state,
629 const struct intel_crtc_state *new_crtc_state)
630{
631 /*
632 * During fastsets/etc. the transcoder is still
633 * running with the old timings at this point.
634 */
635 if (intel_crtc_needs_modeset(crtc_state: new_crtc_state))
636 return new_crtc_state;
637 else
638 return old_crtc_state;
639}
640
641const struct intel_crtc_state *
642intel_pre_commit_crtc_state(struct intel_atomic_state *state,
643 struct intel_crtc *crtc)
644{
645 const struct intel_crtc_state *old_crtc_state =
646 intel_atomic_get_old_crtc_state(state, crtc);
647 const struct intel_crtc_state *new_crtc_state =
648 intel_atomic_get_new_crtc_state(state, crtc);
649
650 return pre_commit_crtc_state(old_crtc_state, new_crtc_state);
651}
652
653void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
654 const struct intel_crtc_state *new_crtc_state,
655 struct intel_vblank_evade_ctx *evade)
656{
657 struct intel_display *display = to_intel_display(new_crtc_state);
658 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
659 const struct intel_crtc_state *crtc_state;
660 const struct drm_display_mode *adjusted_mode;
661 int vblank_delay;
662
663 evade->crtc = crtc;
664
665 evade->need_vlv_dsi_wa = (display->platform.valleyview ||
666 display->platform.cherryview) &&
667 intel_crtc_has_type(crtc_state: new_crtc_state, type: INTEL_OUTPUT_DSI);
668
669 /* TODO: maybe just use the active timings here? */
670 crtc_state = pre_commit_crtc_state(old_crtc_state, new_crtc_state);
671
672 adjusted_mode = &crtc_state->hw.adjusted_mode;
673
674 if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
675 /* timing changes should happen with VRR disabled */
676 drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
677 new_crtc_state->update_m_n || new_crtc_state->update_lrr);
678
679 if (intel_vrr_is_push_sent(crtc_state))
680 evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
681 else
682 evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
683
684 vblank_delay = intel_vrr_vblank_delay(crtc_state);
685 } else {
686 evade->vblank_start = intel_mode_vblank_start(mode: adjusted_mode);
687
688 vblank_delay = intel_mode_vblank_delay(mode: adjusted_mode);
689 }
690
691 /* FIXME needs to be calibrated sensibly */
692 evade->min = evade->vblank_start - intel_usecs_to_scanlines(adjusted_mode,
693 VBLANK_EVASION_TIME_US);
694 evade->max = evade->vblank_start - 1;
695
696 /*
697 * M/N and TRANS_VTOTAL are double buffered on the transcoder's
698 * undelayed vblank, so with seamless M/N and LRR we must evade
699 * both vblanks.
700 *
701 * DSB execution waits for the transcoder's undelayed vblank,
702 * hence we must kick off the commit before that.
703 */
704 if (intel_color_uses_dsb(crtc_state: new_crtc_state) ||
705 new_crtc_state->update_m_n || new_crtc_state->update_lrr)
706 evade->min -= vblank_delay;
707}
708
709/* must be called with vblank interrupt already enabled! */
710int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
711{
712 struct intel_crtc *crtc = evade->crtc;
713 struct intel_display *display = to_intel_display(crtc);
714 long timeout = msecs_to_jiffies_timeout(m: 1);
715 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(crtc: &crtc->base);
716 DEFINE_WAIT(wait);
717 int scanline;
718
719 if (evade->min <= 0 || evade->max <= 0)
720 return 0;
721
722 for (;;) {
723 /*
724 * prepare_to_wait() has a memory barrier, which guarantees
725 * other CPUs can see the task state update by the time we
726 * read the scanline.
727 */
728 prepare_to_wait(wq_head: wq, wq_entry: &wait, TASK_UNINTERRUPTIBLE);
729
730 scanline = intel_get_crtc_scanline(crtc);
731 if (scanline < evade->min || scanline > evade->max)
732 break;
733
734 if (!timeout) {
735 drm_dbg_kms(display->drm,
736 "Potential atomic update failure on pipe %c\n",
737 pipe_name(crtc->pipe));
738 break;
739 }
740
741 local_irq_enable();
742
743 timeout = schedule_timeout(timeout);
744
745 local_irq_disable();
746 }
747
748 finish_wait(wq_head: wq, wq_entry: &wait);
749
750 /*
751 * On VLV/CHV DSI the scanline counter would appear to
752 * increment approx. 1/3 of a scanline before start of vblank.
753 * The registers still get latched at start of vblank however.
754 * This means we must not write any registers on the first
755 * line of vblank (since not the whole line is actually in
756 * vblank). And unfortunately we can't use the interrupt to
757 * wait here since it will fire too soon. We could use the
758 * frame start interrupt instead since it will fire after the
759 * critical scanline, but that would require more changes
760 * in the interrupt code. So for now we'll just do the nasty
761 * thing and poll for the bad scanline to pass us by.
762 *
763 * FIXME figure out if BXT+ DSI suffers from this as well
764 */
765 while (evade->need_vlv_dsi_wa && scanline == evade->vblank_start)
766 scanline = intel_get_crtc_scanline(crtc);
767
768 return scanline;
769}
770