1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2008 Intel Corporation
4 */
5
6#include <linux/string.h>
7#include <linux/bitops.h>
8
9#include "i915_drv.h"
10#include "i915_gem.h"
11#include "i915_gem_ioctls.h"
12#include "i915_gem_mman.h"
13#include "i915_gem_object.h"
14#include "i915_gem_tiling.h"
15#include "i915_reg.h"
16
17/**
18 * DOC: buffer object tiling
19 *
20 * i915_gem_set_tiling_ioctl() and i915_gem_get_tiling_ioctl() is the userspace
21 * interface to declare fence register requirements.
22 *
23 * In principle GEM doesn't care at all about the internal data layout of an
24 * object, and hence it also doesn't care about tiling or swizzling. There's two
25 * exceptions:
26 *
27 * - For X and Y tiling the hardware provides detilers for CPU access, so called
28 * fences. Since there's only a limited amount of them the kernel must manage
29 * these, and therefore userspace must tell the kernel the object tiling if it
30 * wants to use fences for detiling.
31 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
32 * depends upon the physical page frame number. When swapping such objects the
33 * page frame number might change and the kernel must be able to fix this up
34 * and hence now the tiling. Note that on a subset of platforms with
35 * asymmetric memory channel population the swizzling pattern changes in an
36 * unknown way, and for those the kernel simply forbids swapping completely.
37 *
38 * Since neither of this applies for new tiling layouts on modern platforms like
39 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
40 * Anything else can be handled in userspace entirely without the kernel's
41 * involvement.
42 */
43
44/**
45 * i915_gem_fence_size - required global GTT size for a fence
46 * @i915: i915 device
47 * @size: object size
48 * @tiling: tiling mode
49 * @stride: tiling stride
50 *
51 * Return the required global GTT size for a fence (view of a tiled object),
52 * taking into account potential fence register mapping.
53 */
54u32 i915_gem_fence_size(struct drm_i915_private *i915,
55 u32 size, unsigned int tiling, unsigned int stride)
56{
57 u32 ggtt_size;
58
59 GEM_BUG_ON(!size);
60
61 if (tiling == I915_TILING_NONE)
62 return size;
63
64 GEM_BUG_ON(!stride);
65
66 if (GRAPHICS_VER(i915) >= 4) {
67 stride *= i915_gem_tile_height(tiling);
68 GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
69 return roundup(size, stride);
70 }
71
72 /* Previous chips need a power-of-two fence region when tiling */
73 if (GRAPHICS_VER(i915) == 3)
74 ggtt_size = 1024*1024;
75 else
76 ggtt_size = 512*1024;
77
78 while (ggtt_size < size)
79 ggtt_size <<= 1;
80
81 return ggtt_size;
82}
83
84/**
85 * i915_gem_fence_alignment - required global GTT alignment for a fence
86 * @i915: i915 device
87 * @size: object size
88 * @tiling: tiling mode
89 * @stride: tiling stride
90 *
91 * Return the required global GTT alignment for a fence (a view of a tiled
92 * object), taking into account potential fence register mapping.
93 */
94u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
95 unsigned int tiling, unsigned int stride)
96{
97 GEM_BUG_ON(!size);
98
99 /*
100 * Minimum alignment is 4k (GTT page size), but might be greater
101 * if a fence register is needed for the object.
102 */
103 if (tiling == I915_TILING_NONE)
104 return I915_GTT_MIN_ALIGNMENT;
105
106 if (GRAPHICS_VER(i915) >= 4)
107 return I965_FENCE_PAGE;
108
109 /*
110 * Previous chips need to be aligned to the size of the smallest
111 * fence register that can contain the object.
112 */
113 return i915_gem_fence_size(i915, size, tiling, stride);
114}
115
116/* Check pitch constraints for all chips & tiling formats */
117static bool
118i915_tiling_ok(struct drm_i915_gem_object *obj,
119 unsigned int tiling, unsigned int stride)
120{
121 struct drm_i915_private *i915 = to_i915(dev: obj->base.dev);
122 unsigned int tile_width;
123
124 /* Linear is always fine */
125 if (tiling == I915_TILING_NONE)
126 return true;
127
128 if (tiling > I915_TILING_LAST)
129 return false;
130
131 /* check maximum stride & object size */
132 /* i965+ stores the end address of the gtt mapping in the fence
133 * reg, so dont bother to check the size */
134 if (GRAPHICS_VER(i915) >= 7) {
135 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
136 return false;
137 } else if (GRAPHICS_VER(i915) >= 4) {
138 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
139 return false;
140 } else {
141 if (stride > 8192)
142 return false;
143
144 if (!is_power_of_2(n: stride))
145 return false;
146 }
147
148 if (GRAPHICS_VER(i915) == 2 ||
149 (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
150 tile_width = 128;
151 else
152 tile_width = 512;
153
154 if (!stride || !IS_ALIGNED(stride, tile_width))
155 return false;
156
157 return true;
158}
159
160static bool i915_vma_fence_prepare(struct i915_vma *vma,
161 int tiling_mode, unsigned int stride)
162{
163 struct drm_i915_private *i915 = vma->vm->i915;
164 u32 size, alignment;
165
166 if (!i915_vma_is_map_and_fenceable(vma))
167 return true;
168
169 size = i915_gem_fence_size(i915, size: vma->size, tiling: tiling_mode, stride);
170 if (i915_vma_size(vma) < size)
171 return false;
172
173 alignment = i915_gem_fence_alignment(i915, size: vma->size, tiling: tiling_mode, stride);
174 if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment))
175 return false;
176
177 return true;
178}
179
180/* Make the current GTT allocation valid for the change in tiling. */
181static int
182i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
183 int tiling_mode, unsigned int stride)
184{
185 struct drm_i915_private *i915 = to_i915(dev: obj->base.dev);
186 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
187 struct i915_vma *vma, *vn;
188 LIST_HEAD(unbind);
189 int ret = 0;
190
191 if (tiling_mode == I915_TILING_NONE)
192 return 0;
193
194 mutex_lock(lock: &ggtt->vm.mutex);
195
196 spin_lock(lock: &obj->vma.lock);
197 for_each_ggtt_vma(vma, obj) {
198 GEM_BUG_ON(vma->vm != &ggtt->vm);
199
200 if (i915_vma_fence_prepare(vma, tiling_mode, stride))
201 continue;
202
203 list_move(list: &vma->vm_link, head: &unbind);
204 }
205 spin_unlock(lock: &obj->vma.lock);
206
207 list_for_each_entry_safe(vma, vn, &unbind, vm_link) {
208 ret = __i915_vma_unbind(vma);
209 if (ret) {
210 /* Restore the remaining vma on an error */
211 list_splice(list: &unbind, head: &ggtt->vm.bound_list);
212 break;
213 }
214 }
215
216 mutex_unlock(lock: &ggtt->vm.mutex);
217
218 return ret;
219}
220
221bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
222{
223 struct drm_i915_private *i915 = to_i915(dev: obj->base.dev);
224
225 return to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
226 i915_gem_object_is_tiled(obj);
227}
228
229int
230i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
231 unsigned int tiling, unsigned int stride)
232{
233 struct drm_i915_private *i915 = to_i915(dev: obj->base.dev);
234 struct i915_vma *vma;
235 int err;
236
237 /* Make sure we don't cross-contaminate obj->tiling_and_stride */
238 BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
239
240 GEM_BUG_ON(!i915_tiling_ok(obj, tiling, stride));
241 GEM_BUG_ON(!stride ^ (tiling == I915_TILING_NONE));
242
243 if ((tiling | stride) == obj->tiling_and_stride)
244 return 0;
245
246 if (i915_gem_object_is_framebuffer(obj))
247 return -EBUSY;
248
249 /* We need to rebind the object if its current allocation
250 * no longer meets the alignment restrictions for its new
251 * tiling mode. Otherwise we can just leave it alone, but
252 * need to ensure that any fence register is updated before
253 * the next fenced (either through the GTT or by the BLT unit
254 * on older GPUs) access.
255 *
256 * After updating the tiling parameters, we then flag whether
257 * we need to update an associated fence register. Note this
258 * has to also include the unfenced register the GPU uses
259 * whilst executing a fenced command for an untiled object.
260 */
261
262 i915_gem_object_lock(obj, NULL);
263 if (i915_gem_object_is_framebuffer(obj)) {
264 i915_gem_object_unlock(obj);
265 return -EBUSY;
266 }
267
268 err = i915_gem_object_fence_prepare(obj, tiling_mode: tiling, stride);
269 if (err) {
270 i915_gem_object_unlock(obj);
271 return err;
272 }
273
274 /* If the memory has unknown (i.e. varying) swizzling, we pin the
275 * pages to prevent them being swapped out and causing corruption
276 * due to the change in swizzling.
277 */
278 if (i915_gem_object_has_pages(obj) &&
279 obj->mm.madv == I915_MADV_WILLNEED &&
280 i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
281 if (tiling == I915_TILING_NONE) {
282 GEM_BUG_ON(!i915_gem_object_has_tiling_quirk(obj));
283 i915_gem_object_clear_tiling_quirk(obj);
284 i915_gem_object_make_shrinkable(obj);
285 }
286 if (!i915_gem_object_is_tiled(obj)) {
287 GEM_BUG_ON(i915_gem_object_has_tiling_quirk(obj));
288 i915_gem_object_make_unshrinkable(obj);
289 i915_gem_object_set_tiling_quirk(obj);
290 }
291 }
292
293 spin_lock(lock: &obj->vma.lock);
294 for_each_ggtt_vma(vma, obj) {
295 vma->fence_size =
296 i915_gem_fence_size(i915, size: vma->size, tiling, stride);
297 vma->fence_alignment =
298 i915_gem_fence_alignment(i915,
299 size: vma->size, tiling, stride);
300
301 if (vma->fence)
302 vma->fence->dirty = true;
303 }
304 spin_unlock(lock: &obj->vma.lock);
305
306 obj->tiling_and_stride = tiling | stride;
307
308 /* Try to preallocate memory required to save swizzling on put-pages */
309 if (i915_gem_object_needs_bit17_swizzle(obj)) {
310 if (!obj->bit_17) {
311 obj->bit_17 = bitmap_zalloc(nbits: obj->base.size >> PAGE_SHIFT,
312 GFP_KERNEL);
313 }
314 } else {
315 bitmap_free(bitmap: obj->bit_17);
316 obj->bit_17 = NULL;
317 }
318
319 i915_gem_object_unlock(obj);
320
321 /* Force the fence to be reacquired for GTT access */
322 i915_gem_object_release_mmap_gtt(obj);
323
324 return 0;
325}
326
327/**
328 * i915_gem_set_tiling_ioctl - IOCTL handler to set tiling mode
329 * @dev: DRM device
330 * @data: data pointer for the ioctl
331 * @file: DRM file for the ioctl call
332 *
333 * Sets the tiling mode of an object, returning the required swizzling of
334 * bit 6 of addresses in the object.
335 *
336 * Called by the user via ioctl.
337 *
338 * Returns:
339 * Zero on success, negative errno on failure.
340 */
341int
342i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
343 struct drm_file *file)
344{
345 struct drm_i915_private *i915 = to_i915(dev);
346 struct drm_i915_gem_set_tiling *args = data;
347 struct drm_i915_gem_object *obj;
348 int err;
349
350 if (!to_gt(i915)->ggtt->num_fences)
351 return -EOPNOTSUPP;
352
353 obj = i915_gem_object_lookup(file, handle: args->handle);
354 if (!obj)
355 return -ENOENT;
356
357 /*
358 * The tiling mode of proxy objects is handled by its generator, and
359 * not allowed to be changed by userspace.
360 */
361 if (i915_gem_object_is_proxy(obj)) {
362 err = -ENXIO;
363 goto err;
364 }
365
366 if (!i915_tiling_ok(obj, tiling: args->tiling_mode, stride: args->stride)) {
367 err = -EINVAL;
368 goto err;
369 }
370
371 if (args->tiling_mode == I915_TILING_NONE) {
372 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
373 args->stride = 0;
374 } else {
375 if (args->tiling_mode == I915_TILING_X)
376 args->swizzle_mode = to_gt(i915)->ggtt->bit_6_swizzle_x;
377 else
378 args->swizzle_mode = to_gt(i915)->ggtt->bit_6_swizzle_y;
379
380 /* Hide bit 17 swizzling from the user. This prevents old Mesa
381 * from aborting the application on sw fallbacks to bit 17,
382 * and we use the pread/pwrite bit17 paths to swizzle for it.
383 * If there was a user that was relying on the swizzle
384 * information for drm_intel_bo_map()ed reads/writes this would
385 * break it, but we don't have any of those.
386 */
387 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
388 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
389 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
390 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
391
392 /* If we can't handle the swizzling, make it untiled. */
393 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
394 args->tiling_mode = I915_TILING_NONE;
395 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
396 args->stride = 0;
397 }
398 }
399
400 err = i915_gem_object_set_tiling(obj, tiling: args->tiling_mode, stride: args->stride);
401
402 /* We have to maintain this existing ABI... */
403 args->stride = i915_gem_object_get_stride(obj);
404 args->tiling_mode = i915_gem_object_get_tiling(obj);
405
406err:
407 i915_gem_object_put(obj);
408 return err;
409}
410
411/**
412 * i915_gem_get_tiling_ioctl - IOCTL handler to get tiling mode
413 * @dev: DRM device
414 * @data: data pointer for the ioctl
415 * @file: DRM file for the ioctl call
416 *
417 * Returns the current tiling mode and required bit 6 swizzling for the object.
418 *
419 * Called by the user via ioctl.
420 *
421 * Returns:
422 * Zero on success, negative errno on failure.
423 */
424int
425i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
426 struct drm_file *file)
427{
428 struct drm_i915_gem_get_tiling *args = data;
429 struct drm_i915_private *i915 = to_i915(dev);
430 struct drm_i915_gem_object *obj;
431 int err = -ENOENT;
432
433 if (!to_gt(i915)->ggtt->num_fences)
434 return -EOPNOTSUPP;
435
436 rcu_read_lock();
437 obj = i915_gem_object_lookup_rcu(file, handle: args->handle);
438 if (obj) {
439 args->tiling_mode =
440 READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
441 err = 0;
442 }
443 rcu_read_unlock();
444 if (unlikely(err))
445 return err;
446
447 switch (args->tiling_mode) {
448 case I915_TILING_X:
449 args->swizzle_mode = to_gt(i915)->ggtt->bit_6_swizzle_x;
450 break;
451 case I915_TILING_Y:
452 args->swizzle_mode = to_gt(i915)->ggtt->bit_6_swizzle_y;
453 break;
454 default:
455 case I915_TILING_NONE:
456 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
457 break;
458 }
459
460 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
461 if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
462 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
463 else
464 args->phys_swizzle_mode = args->swizzle_mode;
465 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
466 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
467 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
468 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
469
470 return 0;
471}
472