1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9#undef DEBUG
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/string.h>
13#include <linux/kernel.h>
14#include <linux/math.h>
15#include <linux/slab.h>
16#include <linux/delay.h>
17#include <linux/tty.h>
18#include <linux/serial_reg.h>
19#include <linux/serial_core.h>
20#include <linux/8250_pci.h>
21#include <linux/bitops.h>
22#include <linux/bitfield.h>
23
24#include <asm/byteorder.h>
25#include <asm/io.h>
26
27#include "8250.h"
28#include "8250_pcilib.h"
29
30#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32#define PCI_DEVICE_ID_OCTPRO 0x0001
33#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39#define PCI_VENDOR_ID_ADVANTECH 0x13fe
40#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41#define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42#define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46#define PCI_DEVICE_ID_TITAN_200I 0x8028
47#define PCI_DEVICE_ID_TITAN_400I 0x8048
48#define PCI_DEVICE_ID_TITAN_800I 0x8088
49#define PCI_DEVICE_ID_TITAN_800EH 0xA007
50#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51#define PCI_DEVICE_ID_TITAN_400EH 0xA009
52#define PCI_DEVICE_ID_TITAN_100E 0xA010
53#define PCI_DEVICE_ID_TITAN_200E 0xA012
54#define PCI_DEVICE_ID_TITAN_400E 0xA013
55#define PCI_DEVICE_ID_TITAN_800E 0xA014
56#define PCI_DEVICE_ID_TITAN_200EI 0xA016
57#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58#define PCI_DEVICE_ID_TITAN_200V3 0xA306
59#define PCI_DEVICE_ID_TITAN_400V3 0xA310
60#define PCI_DEVICE_ID_TITAN_410V3 0xA312
61#define PCI_DEVICE_ID_TITAN_800V3 0xA314
62#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
67
68#define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253
69#define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173
70
71#define PCI_VENDOR_ID_AGESTAR 0x5372
72#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
73#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
74#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
75
76#define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470
77#define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853
78
79#define PCI_DEVICE_ID_MOXA_CP102E 0x1024
80#define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
81#define PCI_DEVICE_ID_MOXA_CP102N 0x1027
82#define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
83#define PCI_DEVICE_ID_MOXA_CP104N 0x1046
84#define PCI_DEVICE_ID_MOXA_CP112N 0x1121
85#define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
86#define PCI_DEVICE_ID_MOXA_CP114N 0x1145
87#define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
88#define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
89#define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
90#define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
91#define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
92#define PCI_DEVICE_ID_MOXA_CP132N 0x1323
93#define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
94#define PCI_DEVICE_ID_MOXA_CP134N 0x1343
95#define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
96#define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
97
98/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
99#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
100#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
101
102/*
103 * init function returns:
104 * > 0 - number of ports
105 * = 0 - use board->num_ports
106 * < 0 - error
107 */
108struct pci_serial_quirk {
109 u32 vendor;
110 u32 device;
111 u32 subvendor;
112 u32 subdevice;
113 int (*probe)(struct pci_dev *dev);
114 int (*init)(struct pci_dev *dev);
115 int (*setup)(struct serial_private *,
116 const struct pciserial_board *,
117 struct uart_8250_port *, int);
118 void (*exit)(struct pci_dev *dev);
119};
120
121struct f815xxa_data {
122 spinlock_t lock;
123 int idx;
124};
125
126struct serial_private {
127 struct pci_dev *dev;
128 unsigned int nr;
129 struct pci_serial_quirk *quirk;
130 const struct pciserial_board *board;
131 int line[];
132};
133
134#define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
135
136static const struct pci_device_id pci_use_msi[] = {
137 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
138 0xA000, 0x1000) },
139 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
140 0xA000, 0x1000) },
141 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
142 0xA000, 0x1000) },
143 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
144 0xA000, 0x1000) },
145 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
146 PCI_ANY_ID, PCI_ANY_ID) },
147 { }
148};
149
150static int pci_default_setup(struct serial_private*,
151 const struct pciserial_board*, struct uart_8250_port *, int);
152
153static void moan_device(const char *str, struct pci_dev *dev)
154{
155 pci_err(dev, "%s\n"
156 "Please send the output of lspci -vv, this\n"
157 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
158 "manufacturer and name of serial board or\n"
159 "modem board to <linux-serial@vger.kernel.org>.\n",
160 str, dev->vendor, dev->device,
161 dev->subsystem_vendor, dev->subsystem_device);
162}
163
164static int
165setup_port(struct serial_private *priv, struct uart_8250_port *port,
166 u8 bar, unsigned int offset, int regshift)
167{
168 return serial8250_pci_setup_port(dev: priv->dev, port, bar, offset, regshift);
169}
170
171/*
172 * ADDI-DATA GmbH communication cards <info@addi-data.com>
173 */
174static int addidata_apci7800_setup(struct serial_private *priv,
175 const struct pciserial_board *board,
176 struct uart_8250_port *port, int idx)
177{
178 unsigned int bar = 0, offset = board->first_offset;
179 bar = FL_GET_BASE(board->flags);
180
181 if (idx < 2) {
182 offset += idx * board->uart_offset;
183 } else if ((idx >= 2) && (idx < 4)) {
184 bar += 1;
185 offset += ((idx - 2) * board->uart_offset);
186 } else if ((idx >= 4) && (idx < 6)) {
187 bar += 2;
188 offset += ((idx - 4) * board->uart_offset);
189 } else if (idx >= 6) {
190 bar += 3;
191 offset += ((idx - 6) * board->uart_offset);
192 }
193
194 return setup_port(priv, port, bar, offset, regshift: board->reg_shift);
195}
196
197/*
198 * AFAVLAB uses a different mixture of BARs and offsets
199 * Not that ugly ;) -- HW
200 */
201static int
202afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
203 struct uart_8250_port *port, int idx)
204{
205 unsigned int bar, offset = board->first_offset;
206
207 bar = FL_GET_BASE(board->flags);
208 if (idx < 4)
209 bar += idx;
210 else {
211 bar = 4;
212 offset += (idx - 4) * board->uart_offset;
213 }
214
215 return setup_port(priv, port, bar, offset, regshift: board->reg_shift);
216}
217
218/*
219 * HP's Remote Management Console. The Diva chip came in several
220 * different versions. N-class, L2000 and A500 have two Diva chips, each
221 * with 3 UARTs (the third UART on the second chip is unused). Superdome
222 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
223 * one Diva chip, but it has been expanded to 5 UARTs.
224 */
225static int pci_hp_diva_init(struct pci_dev *dev)
226{
227 int rc = 0;
228
229 switch (dev->subsystem_device) {
230 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
231 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
232 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
233 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
234 rc = 3;
235 break;
236 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
237 rc = 2;
238 break;
239 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
240 rc = 4;
241 break;
242 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
243 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
244 rc = 1;
245 break;
246 }
247
248 return rc;
249}
250
251/*
252 * HP's Diva chip puts the 4th/5th serial port further out, and
253 * some serial ports are supposed to be hidden on certain models.
254 */
255static int
256pci_hp_diva_setup(struct serial_private *priv,
257 const struct pciserial_board *board,
258 struct uart_8250_port *port, int idx)
259{
260 unsigned int offset = board->first_offset;
261 unsigned int bar = FL_GET_BASE(board->flags);
262
263 switch (priv->dev->subsystem_device) {
264 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
265 if (idx == 3)
266 idx++;
267 break;
268 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
269 if (idx > 0)
270 idx++;
271 if (idx > 2)
272 idx++;
273 break;
274 }
275 if (idx > 2)
276 offset = 0x18;
277
278 offset += idx * board->uart_offset;
279
280 return setup_port(priv, port, bar, offset, regshift: board->reg_shift);
281}
282
283/*
284 * Added for EKF Intel i960 serial boards
285 */
286static int pci_inteli960ni_init(struct pci_dev *dev)
287{
288 u32 oldval;
289
290 if (!(dev->subsystem_device & 0x1000))
291 return -ENODEV;
292
293 /* is firmware started? */
294 pci_read_config_dword(dev, where: 0x44, val: &oldval);
295 if (oldval == 0x00001000L) { /* RESET value */
296 pci_dbg(dev, "Local i960 firmware missing\n");
297 return -ENODEV;
298 }
299 return 0;
300}
301
302/*
303 * Some PCI serial cards using the PLX 9050 PCI interface chip require
304 * that the card interrupt be explicitly enabled or disabled. This
305 * seems to be mainly needed on card using the PLX which also use I/O
306 * mapped memory.
307 */
308static int pci_plx9050_init(struct pci_dev *dev)
309{
310 u8 irq_config;
311 void __iomem *p;
312
313 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
314 moan_device(str: "no memory in bar 0", dev);
315 return 0;
316 }
317
318 irq_config = 0x41;
319 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
320 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
321 irq_config = 0x43;
322
323 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
324 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
325 /*
326 * As the megawolf cards have the int pins active
327 * high, and have 2 UART chips, both ints must be
328 * enabled on the 9050. Also, the UARTS are set in
329 * 16450 mode by default, so we have to enable the
330 * 16C950 'enhanced' mode so that we can use the
331 * deep FIFOs
332 */
333 irq_config = 0x5b;
334 /*
335 * enable/disable interrupts
336 */
337 p = ioremap(pci_resource_start(dev, 0), size: 0x80);
338 if (p == NULL)
339 return -ENOMEM;
340 writel(val: irq_config, addr: p + 0x4c);
341
342 /*
343 * Read the register back to ensure that it took effect.
344 */
345 readl(addr: p + 0x4c);
346 iounmap(addr: p);
347
348 return 0;
349}
350
351static void pci_plx9050_exit(struct pci_dev *dev)
352{
353 u8 __iomem *p;
354
355 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
356 return;
357
358 /*
359 * disable interrupts
360 */
361 p = ioremap(pci_resource_start(dev, 0), size: 0x80);
362 if (p != NULL) {
363 writel(val: 0, addr: p + 0x4c);
364
365 /*
366 * Read the register back to ensure that it took effect.
367 */
368 readl(addr: p + 0x4c);
369 iounmap(addr: p);
370 }
371}
372
373#define NI8420_INT_ENABLE_REG 0x38
374#define NI8420_INT_ENABLE_BIT 0x2000
375
376static void pci_ni8420_exit(struct pci_dev *dev)
377{
378 void __iomem *p;
379 unsigned int bar = 0;
380
381 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
382 moan_device(str: "no memory in bar", dev);
383 return;
384 }
385
386 p = pci_ioremap_bar(pdev: dev, bar);
387 if (p == NULL)
388 return;
389
390 /* Disable the CPU Interrupt */
391 writel(readl(addr: p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
392 addr: p + NI8420_INT_ENABLE_REG);
393 iounmap(addr: p);
394}
395
396
397/* MITE registers */
398#define MITE_IOWBSR1 0xc4
399#define MITE_IOWCR1 0xf4
400#define MITE_LCIMR1 0x08
401#define MITE_LCIMR2 0x10
402
403#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
404
405static void pci_ni8430_exit(struct pci_dev *dev)
406{
407 void __iomem *p;
408 unsigned int bar = 0;
409
410 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
411 moan_device(str: "no memory in bar", dev);
412 return;
413 }
414
415 p = pci_ioremap_bar(pdev: dev, bar);
416 if (p == NULL)
417 return;
418
419 /* Disable the CPU Interrupt */
420 writel(MITE_LCIMR2_CLR_CPU_IE, addr: p + MITE_LCIMR2);
421 iounmap(addr: p);
422}
423
424/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
425static int
426sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
427 struct uart_8250_port *port, int idx)
428{
429 unsigned int bar, offset = board->first_offset;
430
431 bar = 0;
432
433 if (idx < 4) {
434 /* first four channels map to 0, 0x100, 0x200, 0x300 */
435 offset += idx * board->uart_offset;
436 } else if (idx < 8) {
437 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
438 offset += idx * board->uart_offset + 0xC00;
439 } else /* we have only 8 ports on PMC-OCTALPRO */
440 return 1;
441
442 return setup_port(priv, port, bar, offset, regshift: board->reg_shift);
443}
444
445/*
446* This does initialization for PMC OCTALPRO cards:
447* maps the device memory, resets the UARTs (needed, bc
448* if the module is removed and inserted again, the card
449* is in the sleep mode) and enables global interrupt.
450*/
451
452/* global control register offset for SBS PMC-OctalPro */
453#define OCT_REG_CR_OFF 0x500
454
455static int sbs_init(struct pci_dev *dev)
456{
457 u8 __iomem *p;
458
459 p = pci_ioremap_bar(pdev: dev, bar: 0);
460
461 if (p == NULL)
462 return -ENOMEM;
463 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
464 writeb(val: 0x10, addr: p + OCT_REG_CR_OFF);
465 udelay(usec: 50);
466 writeb(val: 0x0, addr: p + OCT_REG_CR_OFF);
467
468 /* Set bit-2 (INTENABLE) of Control Register */
469 writeb(val: 0x4, addr: p + OCT_REG_CR_OFF);
470 iounmap(addr: p);
471
472 return 0;
473}
474
475/*
476 * Disables the global interrupt of PMC-OctalPro
477 */
478
479static void sbs_exit(struct pci_dev *dev)
480{
481 u8 __iomem *p;
482
483 p = pci_ioremap_bar(pdev: dev, bar: 0);
484 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
485 if (p != NULL)
486 writeb(val: 0, addr: p + OCT_REG_CR_OFF);
487 iounmap(addr: p);
488}
489
490/*
491 * SIIG serial cards have an PCI interface chip which also controls
492 * the UART clocking frequency. Each UART can be clocked independently
493 * (except cards equipped with 4 UARTs) and initial clocking settings
494 * are stored in the EEPROM chip. It can cause problems because this
495 * version of serial driver doesn't support differently clocked UART's
496 * on single PCI card. To prevent this, initialization functions set
497 * high frequency clocking for all UART's on given card. It is safe (I
498 * hope) because it doesn't touch EEPROM settings to prevent conflicts
499 * with other OSes (like M$ DOS).
500 *
501 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
502 *
503 * There is two family of SIIG serial cards with different PCI
504 * interface chip and different configuration methods:
505 * - 10x cards have control registers in IO and/or memory space;
506 * - 20x cards have control registers in standard PCI configuration space.
507 *
508 * Note: all 10x cards have PCI device ids 0x10..
509 * all 20x cards have PCI device ids 0x20..
510 *
511 * There are also Quartet Serial cards which use Oxford Semiconductor
512 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
513 *
514 * Note: some SIIG cards are probed by the parport_serial object.
515 */
516
517#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
518#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
519
520static int pci_siig10x_init(struct pci_dev *dev)
521{
522 u16 data;
523 void __iomem *p;
524
525 switch (dev->device & 0xfff8) {
526 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
527 data = 0xffdf;
528 break;
529 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
530 data = 0xf7ff;
531 break;
532 default: /* 1S1P, 4S */
533 data = 0xfffb;
534 break;
535 }
536
537 p = ioremap(pci_resource_start(dev, 0), size: 0x80);
538 if (p == NULL)
539 return -ENOMEM;
540
541 writew(readw(addr: p + 0x28) & data, addr: p + 0x28);
542 readw(addr: p + 0x28);
543 iounmap(addr: p);
544 return 0;
545}
546
547#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
548#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
549
550static int pci_siig20x_init(struct pci_dev *dev)
551{
552 u8 data;
553
554 /* Change clock frequency for the first UART. */
555 pci_read_config_byte(dev, where: 0x6f, val: &data);
556 pci_write_config_byte(dev, where: 0x6f, val: data & 0xef);
557
558 /* If this card has 2 UART, we have to do the same with second UART. */
559 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
560 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
561 pci_read_config_byte(dev, where: 0x73, val: &data);
562 pci_write_config_byte(dev, where: 0x73, val: data & 0xef);
563 }
564 return 0;
565}
566
567static int pci_siig_init(struct pci_dev *dev)
568{
569 unsigned int type = dev->device & 0xff00;
570
571 if (type == 0x1000)
572 return pci_siig10x_init(dev);
573 if (type == 0x2000)
574 return pci_siig20x_init(dev);
575
576 moan_device(str: "Unknown SIIG card", dev);
577 return -ENODEV;
578}
579
580static int pci_siig_setup(struct serial_private *priv,
581 const struct pciserial_board *board,
582 struct uart_8250_port *port, int idx)
583{
584 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
585
586 if (idx > 3) {
587 bar = 4;
588 offset = (idx - 4) * 8;
589 }
590
591 return setup_port(priv, port, bar, offset, regshift: 0);
592}
593
594/*
595 * Timedia has an explosion of boards, and to avoid the PCI table from
596 * growing *huge*, we use this function to collapse some 70 entries
597 * in the PCI table into one, for sanity's and compactness's sake.
598 */
599static const unsigned short timedia_single_port[] = {
600 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
601};
602
603static const unsigned short timedia_dual_port[] = {
604 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
605 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
606 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
607 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
608 0xD079, 0
609};
610
611static const unsigned short timedia_quad_port[] = {
612 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
613 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
614 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
615 0xB157, 0
616};
617
618static const unsigned short timedia_eight_port[] = {
619 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
620 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
621};
622
623static const struct timedia_struct {
624 int num;
625 const unsigned short *ids;
626} timedia_data[] = {
627 { 1, timedia_single_port },
628 { .num: 2, .ids: timedia_dual_port },
629 { .num: 4, .ids: timedia_quad_port },
630 { .num: 8, .ids: timedia_eight_port }
631};
632
633/*
634 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
635 * listing them individually, this driver merely grabs them all with
636 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
637 * and should be left free to be claimed by parport_serial instead.
638 */
639static int pci_timedia_probe(struct pci_dev *dev)
640{
641 /*
642 * Check the third digit of the subdevice ID
643 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
644 */
645 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
646 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
647 dev->subsystem_device);
648 return -ENODEV;
649 }
650
651 return 0;
652}
653
654static int pci_timedia_init(struct pci_dev *dev)
655{
656 const unsigned short *ids;
657 int i, j;
658
659 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
660 ids = timedia_data[i].ids;
661 for (j = 0; ids[j]; j++)
662 if (dev->subsystem_device == ids[j])
663 return timedia_data[i].num;
664 }
665 return 0;
666}
667
668/*
669 * Timedia/SUNIX uses a mixture of BARs and offsets
670 * Ugh, this is ugly as all hell --- TYT
671 */
672static int
673pci_timedia_setup(struct serial_private *priv,
674 const struct pciserial_board *board,
675 struct uart_8250_port *port, int idx)
676{
677 unsigned int bar = 0, offset = board->first_offset;
678
679 switch (idx) {
680 case 0:
681 bar = 0;
682 break;
683 case 1:
684 offset = board->uart_offset;
685 bar = 0;
686 break;
687 case 2:
688 bar = 1;
689 break;
690 case 3:
691 offset = board->uart_offset;
692 fallthrough;
693 case 4: /* BAR 2 */
694 case 5: /* BAR 3 */
695 case 6: /* BAR 4 */
696 case 7: /* BAR 5 */
697 bar = idx - 2;
698 }
699
700 return setup_port(priv, port, bar, offset, regshift: board->reg_shift);
701}
702
703/*
704 * Some Titan cards are also a little weird
705 */
706static int
707titan_400l_800l_setup(struct serial_private *priv,
708 const struct pciserial_board *board,
709 struct uart_8250_port *port, int idx)
710{
711 unsigned int bar, offset = board->first_offset;
712
713 switch (idx) {
714 case 0:
715 bar = 1;
716 break;
717 case 1:
718 bar = 2;
719 break;
720 default:
721 bar = 4;
722 offset = (idx - 2) * board->uart_offset;
723 }
724
725 return setup_port(priv, port, bar, offset, regshift: board->reg_shift);
726}
727
728static int pci_xircom_init(struct pci_dev *dev)
729{
730 msleep(msecs: 100);
731 return 0;
732}
733
734static int pci_ni8420_init(struct pci_dev *dev)
735{
736 void __iomem *p;
737 unsigned int bar = 0;
738
739 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
740 moan_device(str: "no memory in bar", dev);
741 return 0;
742 }
743
744 p = pci_ioremap_bar(pdev: dev, bar);
745 if (p == NULL)
746 return -ENOMEM;
747
748 /* Enable CPU Interrupt */
749 writel(readl(addr: p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
750 addr: p + NI8420_INT_ENABLE_REG);
751
752 iounmap(addr: p);
753 return 0;
754}
755
756#define MITE_IOWBSR1_WSIZE 0xa
757#define MITE_IOWBSR1_WIN_OFFSET 0x800
758#define MITE_IOWBSR1_WENAB (1 << 7)
759#define MITE_LCIMR1_IO_IE_0 (1 << 24)
760#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
761#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
762
763static int pci_ni8430_init(struct pci_dev *dev)
764{
765 void __iomem *p;
766 struct pci_bus_region region;
767 u32 device_window;
768 unsigned int bar = 0;
769
770 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
771 moan_device(str: "no memory in bar", dev);
772 return 0;
773 }
774
775 p = pci_ioremap_bar(pdev: dev, bar);
776 if (p == NULL)
777 return -ENOMEM;
778
779 /*
780 * Set device window address and size in BAR0, while acknowledging that
781 * the resource structure may contain a translated address that differs
782 * from the address the device responds to.
783 */
784 pcibios_resource_to_bus(bus: dev->bus, region: &region, res: &dev->resource[bar]);
785 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
786 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
787 writel(val: device_window, addr: p + MITE_IOWBSR1);
788
789 /* Set window access to go to RAMSEL IO address space */
790 writel(val: (readl(addr: p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
791 addr: p + MITE_IOWCR1);
792
793 /* Enable IO Bus Interrupt 0 */
794 writel(MITE_LCIMR1_IO_IE_0, addr: p + MITE_LCIMR1);
795
796 /* Enable CPU Interrupt */
797 writel(MITE_LCIMR2_SET_CPU_IE, addr: p + MITE_LCIMR2);
798
799 iounmap(addr: p);
800 return 0;
801}
802
803/* UART Port Control Register */
804#define NI8430_PORTCON 0x0f
805#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
806
807static int
808pci_ni8430_setup(struct serial_private *priv,
809 const struct pciserial_board *board,
810 struct uart_8250_port *port, int idx)
811{
812 struct pci_dev *dev = priv->dev;
813 void __iomem *p;
814 unsigned int bar, offset = board->first_offset;
815
816 if (idx >= board->num_ports)
817 return 1;
818
819 bar = FL_GET_BASE(board->flags);
820 offset += idx * board->uart_offset;
821
822 p = pci_ioremap_bar(pdev: dev, bar);
823 if (!p)
824 return -ENOMEM;
825
826 /* enable the transceiver */
827 writeb(readb(addr: p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
828 addr: p + offset + NI8430_PORTCON);
829
830 iounmap(addr: p);
831
832 return setup_port(priv, port, bar, offset, regshift: board->reg_shift);
833}
834
835static int pci_netmos_9900_setup(struct serial_private *priv,
836 const struct pciserial_board *board,
837 struct uart_8250_port *port, int idx)
838{
839 unsigned int bar;
840
841 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
842 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
843 /* netmos apparently orders BARs by datasheet layout, so serial
844 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
845 */
846 bar = 3 * idx;
847
848 return setup_port(priv, port, bar, offset: 0, regshift: board->reg_shift);
849 }
850
851 return pci_default_setup(priv, board, port, idx);
852}
853
854/* the 99xx series comes with a range of device IDs and a variety
855 * of capabilities:
856 *
857 * 9900 has varying capabilities and can cascade to sub-controllers
858 * (cascading should be purely internal)
859 * 9904 is hardwired with 4 serial ports
860 * 9912 and 9922 are hardwired with 2 serial ports
861 */
862static int pci_netmos_9900_numports(struct pci_dev *dev)
863{
864 unsigned int c = dev->class;
865 unsigned int pi;
866 unsigned short sub_serports;
867
868 pi = c & 0xff;
869
870 if (pi == 2)
871 return 1;
872
873 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
874 /* two possibilities: 0x30ps encodes number of parallel and
875 * serial ports, or 0x1000 indicates *something*. This is not
876 * immediately obvious, since the 2s1p+4s configuration seems
877 * to offer all functionality on functions 0..2, while still
878 * advertising the same function 3 as the 4s+2s1p config.
879 */
880 sub_serports = dev->subsystem_device & 0xf;
881 if (sub_serports > 0)
882 return sub_serports;
883
884 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
885 return 0;
886 }
887
888 moan_device(str: "unknown NetMos/Mostech program interface", dev);
889 return 0;
890}
891
892static int pci_netmos_init(struct pci_dev *dev)
893{
894 /* subdevice 0x00PS means <P> parallel, <S> serial */
895 unsigned int num_serial = dev->subsystem_device & 0xf;
896
897 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
898 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
899 return 0;
900
901 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
902 dev->subsystem_device == 0x0299)
903 return 0;
904
905 switch (dev->device) { /* FALLTHROUGH on all */
906 case PCI_DEVICE_ID_NETMOS_9904:
907 case PCI_DEVICE_ID_NETMOS_9912:
908 case PCI_DEVICE_ID_NETMOS_9922:
909 case PCI_DEVICE_ID_NETMOS_9900:
910 num_serial = pci_netmos_9900_numports(dev);
911 break;
912
913 default:
914 break;
915 }
916
917 if (num_serial == 0) {
918 moan_device(str: "unknown NetMos/Mostech device", dev);
919 return -ENODEV;
920 }
921
922 return num_serial;
923}
924
925/*
926 * These chips are available with optionally one parallel port and up to
927 * two serial ports. Unfortunately they all have the same product id.
928 *
929 * Basic configuration is done over a region of 32 I/O ports. The base
930 * ioport is called INTA or INTC, depending on docs/other drivers.
931 *
932 * The region of the 32 I/O ports is configured in POSIO0R...
933 */
934
935/* registers */
936#define ITE_887x_MISCR 0x9c
937#define ITE_887x_INTCBAR 0x78
938#define ITE_887x_UARTBAR 0x7c
939#define ITE_887x_PS0BAR 0x10
940#define ITE_887x_POSIO0 0x60
941
942/* I/O space size */
943#define ITE_887x_IOSIZE 32
944/* I/O space size (bits 26-24; 8 bytes = 011b) */
945#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
946/* I/O space size (bits 26-24; 32 bytes = 101b) */
947#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
948/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
949#define ITE_887x_POSIO_SPEED (3 << 29)
950/* enable IO_Space bit */
951#define ITE_887x_POSIO_ENABLE (1 << 31)
952
953/* inta_addr are the configuration addresses of the ITE */
954static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
955static int pci_ite887x_init(struct pci_dev *dev)
956{
957 int ret, i, type;
958 struct resource *iobase = NULL;
959 u32 miscr, uartbar, ioport;
960
961 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
962 return serial_8250_warn_need_ioport(dev);
963
964 /* search for the base-ioport */
965 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
966 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
967 "ite887x");
968 if (iobase != NULL) {
969 /* write POSIO0R - speed | size | ioport */
970 pci_write_config_dword(dev, ITE_887x_POSIO0,
971 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
972 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
973 /* write INTCBAR - ioport */
974 pci_write_config_dword(dev, ITE_887x_INTCBAR,
975 val: inta_addr[i]);
976 ret = inb(port: inta_addr[i]);
977 if (ret != 0xff) {
978 /* ioport connected */
979 break;
980 }
981 release_region(iobase->start, ITE_887x_IOSIZE);
982 }
983 }
984
985 if (i == ARRAY_SIZE(inta_addr)) {
986 pci_err(dev, "could not find iobase\n");
987 return -ENODEV;
988 }
989
990 /* start of undocumented type checking (see parport_pc.c) */
991 type = inb(port: iobase->start + 0x18) & 0x0f;
992
993 switch (type) {
994 case 0x2: /* ITE8871 (1P) */
995 case 0xa: /* ITE8875 (1P) */
996 ret = 0;
997 break;
998 case 0xe: /* ITE8872 (2S1P) */
999 ret = 2;
1000 break;
1001 case 0x6: /* ITE8873 (1S) */
1002 ret = 1;
1003 break;
1004 case 0x8: /* ITE8874 (2S) */
1005 ret = 2;
1006 break;
1007 default:
1008 moan_device(str: "Unknown ITE887x", dev);
1009 ret = -ENODEV;
1010 }
1011
1012 /* configure all serial ports */
1013 for (i = 0; i < ret; i++) {
1014 /* read the I/O port from the device */
1015 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
1016 val: &ioport);
1017 ioport &= 0x0000FF00; /* the actual base address */
1018 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
1019 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1020 ITE_887x_POSIO_IOSIZE_8 | ioport);
1021
1022 /* write the ioport to the UARTBAR */
1023 pci_read_config_dword(dev, ITE_887x_UARTBAR, val: &uartbar);
1024 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
1025 uartbar |= (ioport << (16 * i)); /* set the ioport */
1026 pci_write_config_dword(dev, ITE_887x_UARTBAR, val: uartbar);
1027
1028 /* get current config */
1029 pci_read_config_dword(dev, ITE_887x_MISCR, val: &miscr);
1030 /* disable interrupts (UARTx_Routing[3:0]) */
1031 miscr &= ~(0xf << (12 - 4 * i));
1032 /* activate the UART (UARTx_En) */
1033 miscr |= 1 << (23 - i);
1034 /* write new config with activated UART */
1035 pci_write_config_dword(dev, ITE_887x_MISCR, val: miscr);
1036 }
1037
1038 if (ret <= 0) {
1039 /* the device has no UARTs if we get here */
1040 release_region(iobase->start, ITE_887x_IOSIZE);
1041 }
1042
1043 return ret;
1044}
1045
1046static void pci_ite887x_exit(struct pci_dev *dev)
1047{
1048 u32 ioport;
1049 /* the ioport is bit 0-15 in POSIO0R */
1050 pci_read_config_dword(dev, ITE_887x_POSIO0, val: &ioport);
1051 ioport &= 0xffff;
1052 release_region(ioport, ITE_887x_IOSIZE);
1053}
1054
1055/*
1056 * Oxford Semiconductor Inc.
1057 * Check if an OxSemi device is part of the Tornado range of devices.
1058 */
1059#define PCI_VENDOR_ID_ENDRUN 0x7401
1060#define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1061
1062static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1063{
1064 /* OxSemi Tornado devices are all 0xCxxx */
1065 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1066 (dev->device & 0xf000) != 0xc000)
1067 return false;
1068
1069 /* EndRun devices are all 0xExxx */
1070 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1071 (dev->device & 0xf000) != 0xe000)
1072 return false;
1073
1074 return true;
1075}
1076
1077/*
1078 * Determine the number of ports available on a Tornado device.
1079 */
1080static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1081{
1082 u8 __iomem *p;
1083 unsigned long deviceID;
1084 unsigned int number_uarts = 0;
1085
1086 if (!pci_oxsemi_tornado_p(dev))
1087 return 0;
1088
1089 p = pci_iomap(dev, bar: 0, max: 5);
1090 if (p == NULL)
1091 return -ENOMEM;
1092
1093 deviceID = ioread32(p);
1094 /* Tornado device */
1095 if (deviceID == 0x07000200) {
1096 number_uarts = ioread8(p + 4);
1097 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1098 number_uarts,
1099 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1100 "EndRun" : "Oxford");
1101 }
1102 pci_iounmap(dev, p);
1103 return number_uarts;
1104}
1105
1106/* Tornado-specific constants for the TCR and CPR registers; see below. */
1107#define OXSEMI_TORNADO_TCR_MASK 0xf
1108#define OXSEMI_TORNADO_CPR_MASK 0x1ff
1109#define OXSEMI_TORNADO_CPR_MIN 0x008
1110#define OXSEMI_TORNADO_CPR_DEF 0x10f
1111
1112/*
1113 * Determine the oversampling rate, the clock prescaler, and the clock
1114 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1115 * which is four times the baud base, and the prescaler increments in
1116 * steps of 1/8. Therefore to make calculations on integers we need
1117 * to use a scaled clock rate, which is the baud base multiplied by 32
1118 * (or our assumed UART clock rate multiplied by 2).
1119 *
1120 * The allowed oversampling rates are from 4 up to 16 inclusive (values
1121 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1122 * values between 1.000 and 63.875 inclusive (operation for values from
1123 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1124 * unsigned 16-bit integer.
1125 *
1126 * For the most accurate baud rate we use a table of predetermined
1127 * oversampling rates and clock prescalers that records all possible
1128 * products of the two parameters in the range from 4 up to 255 inclusive,
1129 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1130 * by 8. The table is sorted by the decreasing value of the oversampling
1131 * rate and ties are resolved by sorting by the decreasing value of the
1132 * product. This way preference is given to higher oversampling rates.
1133 *
1134 * We iterate over the table and choose the product of an oversampling
1135 * rate and a clock prescaler that gives the lowest integer division
1136 * result deviation, or if an exact integer divider is found we stop
1137 * looking for it right away. We do some fixup if the resulting clock
1138 * divisor required would be out of its unsigned 16-bit integer range.
1139 *
1140 * Finally we abuse the supposed fractional part returned to encode the
1141 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1142 * prescaler which will end up in the TCR and CPR/CPR2 registers.
1143 */
1144static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1145 unsigned int baud,
1146 unsigned int *frac)
1147{
1148 static u8 p[][2] = {
1149 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1150 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1151 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1152 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1153 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1154 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1155 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1156 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1157 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1158 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1159 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1160 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1161 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1162 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1163 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1164 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1165 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1166 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1167 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1168 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1169 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1170 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1171 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1172 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1173 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1174 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1175 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1176 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1177 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1178 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1179 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1180 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1181 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1182 { 4, 9, }, { 4, 8, },
1183 };
1184 /* Scale the quotient for comparison to get the fractional part. */
1185 const unsigned int quot_scale = 65536;
1186 unsigned int sclk = port->uartclk * 2;
1187 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1188 unsigned int best_squot;
1189 unsigned int squot;
1190 unsigned int quot;
1191 u16 cpr;
1192 u8 tcr;
1193 int i;
1194
1195 /* Old custom speed handling. */
1196 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
1197 unsigned int cust_div = port->custom_divisor;
1198
1199 quot = cust_div & UART_DIV_MAX;
1200 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
1201 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
1202 if (cpr < OXSEMI_TORNADO_CPR_MIN)
1203 cpr = OXSEMI_TORNADO_CPR_DEF;
1204 } else {
1205 best_squot = quot_scale;
1206 for (i = 0; i < ARRAY_SIZE(p); i++) {
1207 unsigned int spre;
1208 unsigned int srem;
1209 u8 cp;
1210 u8 tc;
1211
1212 tc = p[i][0];
1213 cp = p[i][1];
1214 spre = tc * cp;
1215
1216 srem = sdiv % spre;
1217 if (srem > spre / 2)
1218 srem = spre - srem;
1219 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1220
1221 if (srem == 0) {
1222 tcr = tc;
1223 cpr = cp;
1224 quot = sdiv / spre;
1225 break;
1226 } else if (squot < best_squot) {
1227 best_squot = squot;
1228 tcr = tc;
1229 cpr = cp;
1230 quot = DIV_ROUND_CLOSEST(sdiv, spre);
1231 }
1232 }
1233 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1234 quot % 2 == 0) {
1235 quot >>= 1;
1236 tcr <<= 1;
1237 }
1238 while (quot > UART_DIV_MAX) {
1239 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1240 quot >>= 1;
1241 tcr <<= 1;
1242 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1243 quot >>= 1;
1244 cpr <<= 1;
1245 } else {
1246 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1247 cpr = OXSEMI_TORNADO_CPR_MASK;
1248 }
1249 }
1250 }
1251
1252 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1253 return quot;
1254}
1255
1256/*
1257 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1258 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1259 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1260 * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1261 * has to be written first, followed by CPR2, which occupies the location
1262 * of CKS used with earlier UART designs.
1263 */
1264static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1265 unsigned int baud,
1266 unsigned int quot,
1267 unsigned int quot_frac)
1268{
1269 struct uart_8250_port *up = up_to_u8250p(up: port);
1270 u8 cpr2 = quot_frac >> 16;
1271 u8 cpr = quot_frac >> 8;
1272 u8 tcr = quot_frac;
1273
1274 serial_icr_write(up, UART_TCR, value: tcr);
1275 serial_icr_write(up, UART_CPR, value: cpr);
1276 serial_icr_write(up, UART_CKS, value: cpr2);
1277 serial8250_do_set_divisor(port, baud, quot);
1278}
1279
1280/*
1281 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1282 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1283 */
1284static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1285 unsigned int mctrl)
1286{
1287 struct uart_8250_port *up = up_to_u8250p(up: port);
1288
1289 up->mcr |= UART_MCR_CLKSEL;
1290 serial8250_do_set_mctrl(port, mctrl);
1291}
1292
1293/*
1294 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1295 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1296 */
1297static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1298 const struct pciserial_board *board,
1299 struct uart_8250_port *up, int idx)
1300{
1301 struct pci_dev *dev = priv->dev;
1302
1303 if (pci_oxsemi_tornado_p(dev)) {
1304 up->port.flags |= UPF_FULL_PROBE;
1305 up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1306 up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1307 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1308 }
1309
1310 return pci_default_setup(priv, board, up, idx);
1311}
1312
1313#define QPCR_TEST_FOR1 0x3F
1314#define QPCR_TEST_GET1 0x00
1315#define QPCR_TEST_FOR2 0x40
1316#define QPCR_TEST_GET2 0x40
1317#define QPCR_TEST_FOR3 0x80
1318#define QPCR_TEST_GET3 0x40
1319#define QPCR_TEST_FOR4 0xC0
1320#define QPCR_TEST_GET4 0x80
1321
1322#define QOPR_CLOCK_X1 0x0000
1323#define QOPR_CLOCK_X2 0x0001
1324#define QOPR_CLOCK_X4 0x0002
1325#define QOPR_CLOCK_X8 0x0003
1326#define QOPR_CLOCK_RATE_MASK 0x0003
1327
1328/* Quatech devices have their own extra interface features */
1329static struct pci_device_id quatech_cards[] = {
1330 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
1331 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
1332 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1333 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
1334 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1335 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
1336 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
1337 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
1338 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
1339 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
1340 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
1341 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1342 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1343 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1344 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1345 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1346 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1347 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1348 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1349 { 0, }
1350};
1351
1352static int pci_quatech_rqopr(struct uart_8250_port *port)
1353{
1354 unsigned long base = port->port.iobase;
1355 u8 LCR, val;
1356
1357 LCR = inb(port: base + UART_LCR);
1358 outb(value: 0xBF, port: base + UART_LCR);
1359 val = inb(port: base + UART_SCR);
1360 outb(value: LCR, port: base + UART_LCR);
1361 return val;
1362}
1363
1364static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1365{
1366 unsigned long base = port->port.iobase;
1367 u8 LCR;
1368
1369 LCR = inb(port: base + UART_LCR);
1370 outb(value: 0xBF, port: base + UART_LCR);
1371 inb(port: base + UART_SCR);
1372 outb(value: qopr, port: base + UART_SCR);
1373 outb(value: LCR, port: base + UART_LCR);
1374}
1375
1376static int pci_quatech_rqmcr(struct uart_8250_port *port)
1377{
1378 unsigned long base = port->port.iobase;
1379 u8 LCR, val, qmcr;
1380
1381 LCR = inb(port: base + UART_LCR);
1382 outb(value: 0xBF, port: base + UART_LCR);
1383 val = inb(port: base + UART_SCR);
1384 outb(value: val | 0x10, port: base + UART_SCR);
1385 qmcr = inb(port: base + UART_MCR);
1386 outb(value: val, port: base + UART_SCR);
1387 outb(value: LCR, port: base + UART_LCR);
1388
1389 return qmcr;
1390}
1391
1392static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1393{
1394 unsigned long base = port->port.iobase;
1395 u8 LCR, val;
1396
1397 LCR = inb(port: base + UART_LCR);
1398 outb(value: 0xBF, port: base + UART_LCR);
1399 val = inb(port: base + UART_SCR);
1400 outb(value: val | 0x10, port: base + UART_SCR);
1401 outb(value: qmcr, port: base + UART_MCR);
1402 outb(value: val, port: base + UART_SCR);
1403 outb(value: LCR, port: base + UART_LCR);
1404}
1405
1406static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1407{
1408 unsigned long base = port->port.iobase;
1409 u8 LCR, val;
1410
1411 LCR = inb(port: base + UART_LCR);
1412 outb(value: 0xBF, port: base + UART_LCR);
1413 val = inb(port: base + UART_SCR);
1414 if (val & 0x20) {
1415 outb(value: 0x80, UART_LCR);
1416 if (!(inb(UART_SCR) & 0x20)) {
1417 outb(value: LCR, port: base + UART_LCR);
1418 return 1;
1419 }
1420 }
1421 return 0;
1422}
1423
1424static int pci_quatech_test(struct uart_8250_port *port)
1425{
1426 u8 reg, qopr;
1427
1428 qopr = pci_quatech_rqopr(port);
1429 pci_quatech_wqopr(port, qopr: qopr & QPCR_TEST_FOR1);
1430 reg = pci_quatech_rqopr(port) & 0xC0;
1431 if (reg != QPCR_TEST_GET1)
1432 return -EINVAL;
1433 pci_quatech_wqopr(port, qopr: (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1434 reg = pci_quatech_rqopr(port) & 0xC0;
1435 if (reg != QPCR_TEST_GET2)
1436 return -EINVAL;
1437 pci_quatech_wqopr(port, qopr: (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1438 reg = pci_quatech_rqopr(port) & 0xC0;
1439 if (reg != QPCR_TEST_GET3)
1440 return -EINVAL;
1441 pci_quatech_wqopr(port, qopr: (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1442 reg = pci_quatech_rqopr(port) & 0xC0;
1443 if (reg != QPCR_TEST_GET4)
1444 return -EINVAL;
1445
1446 pci_quatech_wqopr(port, qopr);
1447 return 0;
1448}
1449
1450static int pci_quatech_clock(struct uart_8250_port *port)
1451{
1452 u8 qopr, reg, set;
1453 unsigned long clock;
1454
1455 if (pci_quatech_test(port) < 0)
1456 return 1843200;
1457
1458 qopr = pci_quatech_rqopr(port);
1459
1460 pci_quatech_wqopr(port, qopr: qopr & ~QOPR_CLOCK_X8);
1461 reg = pci_quatech_rqopr(port);
1462 if (reg & QOPR_CLOCK_X8) {
1463 clock = 1843200;
1464 goto out;
1465 }
1466 pci_quatech_wqopr(port, qopr: qopr | QOPR_CLOCK_X8);
1467 reg = pci_quatech_rqopr(port);
1468 if (!(reg & QOPR_CLOCK_X8)) {
1469 clock = 1843200;
1470 goto out;
1471 }
1472 reg &= QOPR_CLOCK_X8;
1473 if (reg == QOPR_CLOCK_X2) {
1474 clock = 3685400;
1475 set = QOPR_CLOCK_X2;
1476 } else if (reg == QOPR_CLOCK_X4) {
1477 clock = 7372800;
1478 set = QOPR_CLOCK_X4;
1479 } else if (reg == QOPR_CLOCK_X8) {
1480 clock = 14745600;
1481 set = QOPR_CLOCK_X8;
1482 } else {
1483 clock = 1843200;
1484 set = QOPR_CLOCK_X1;
1485 }
1486 qopr &= ~QOPR_CLOCK_RATE_MASK;
1487 qopr |= set;
1488
1489out:
1490 pci_quatech_wqopr(port, qopr);
1491 return clock;
1492}
1493
1494static int pci_quatech_rs422(struct uart_8250_port *port)
1495{
1496 u8 qmcr;
1497 int rs422 = 0;
1498
1499 if (!pci_quatech_has_qmcr(port))
1500 return 0;
1501 qmcr = pci_quatech_rqmcr(port);
1502 pci_quatech_wqmcr(port, qmcr: 0xFF);
1503 if (pci_quatech_rqmcr(port))
1504 rs422 = 1;
1505 pci_quatech_wqmcr(port, qmcr);
1506 return rs422;
1507}
1508
1509static int pci_quatech_init(struct pci_dev *dev)
1510{
1511 const struct pci_device_id *match;
1512 bool amcc = false;
1513
1514 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1515 return serial_8250_warn_need_ioport(dev);
1516
1517 match = pci_match_id(ids: quatech_cards, dev);
1518 if (match)
1519 amcc = match->driver_data;
1520 else
1521 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1522
1523 if (amcc) {
1524 unsigned long base = pci_resource_start(dev, 0);
1525 if (base) {
1526 u32 tmp;
1527
1528 outl(inl(port: base + 0x38) | 0x00002000, port: base + 0x38);
1529 tmp = inl(port: base + 0x3c);
1530 outl(value: tmp | 0x01000000, port: base + 0x3c);
1531 outl(value: tmp & ~0x01000000, port: base + 0x3c);
1532 }
1533 }
1534 return 0;
1535}
1536
1537static int pci_quatech_setup(struct serial_private *priv,
1538 const struct pciserial_board *board,
1539 struct uart_8250_port *port, int idx)
1540{
1541 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1542 return serial_8250_warn_need_ioport(dev: priv->dev);
1543
1544 /* Needed by pci_quatech calls below */
1545 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1546 /* Set up the clocking */
1547 port->port.uartclk = pci_quatech_clock(port);
1548 /* For now just warn about RS422 */
1549 if (pci_quatech_rs422(port))
1550 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1551 return pci_default_setup(priv, board, port, idx);
1552}
1553
1554static int pci_default_setup(struct serial_private *priv,
1555 const struct pciserial_board *board,
1556 struct uart_8250_port *port, int idx)
1557{
1558 unsigned int bar, offset = board->first_offset, maxnr;
1559
1560 bar = FL_GET_BASE(board->flags);
1561 if (board->flags & FL_BASE_BARS)
1562 bar += idx;
1563 else
1564 offset += idx * board->uart_offset;
1565
1566 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1567 (board->reg_shift + 3);
1568
1569 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1570 return 1;
1571
1572 return setup_port(priv, port, bar, offset, regshift: board->reg_shift);
1573}
1574
1575static int
1576ce4100_serial_setup(struct serial_private *priv,
1577 const struct pciserial_board *board,
1578 struct uart_8250_port *port, int idx)
1579{
1580 int ret;
1581
1582 ret = setup_port(priv, port, bar: idx, offset: 0, regshift: board->reg_shift);
1583 port->port.iotype = UPIO_MEM32;
1584 port->port.type = PORT_XSCALE;
1585 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1586 port->port.regshift = 2;
1587
1588 return ret;
1589}
1590
1591static int
1592pci_omegapci_setup(struct serial_private *priv,
1593 const struct pciserial_board *board,
1594 struct uart_8250_port *port, int idx)
1595{
1596 return setup_port(priv, port, bar: 2, offset: idx * 8, regshift: 0);
1597}
1598
1599static int
1600pci_brcm_trumanage_setup(struct serial_private *priv,
1601 const struct pciserial_board *board,
1602 struct uart_8250_port *port, int idx)
1603{
1604 int ret = pci_default_setup(priv, board, port, idx);
1605
1606 port->port.type = PORT_BRCM_TRUMANAGE;
1607 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1608 return ret;
1609}
1610
1611/* RTS will control by MCR if this bit is 0 */
1612#define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1613/* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1614#define FINTEK_RTS_INVERT BIT(5)
1615
1616/* We should do proper H/W transceiver setting before change to RS485 mode */
1617static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1618 struct serial_rs485 *rs485)
1619{
1620 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1621 u8 setting;
1622 u8 *index = (u8 *) port->private_data;
1623
1624 pci_read_config_byte(dev: pci_dev, where: 0x40 + 8 * *index + 7, val: &setting);
1625
1626 if (rs485->flags & SER_RS485_ENABLED) {
1627 /* Enable RTS H/W control mode */
1628 setting |= FINTEK_RTS_CONTROL_BY_HW;
1629
1630 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1631 /* RTS driving high on TX */
1632 setting &= ~FINTEK_RTS_INVERT;
1633 } else {
1634 /* RTS driving low on TX */
1635 setting |= FINTEK_RTS_INVERT;
1636 }
1637 } else {
1638 /* Disable RTS H/W control mode */
1639 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1640 }
1641
1642 pci_write_config_byte(dev: pci_dev, where: 0x40 + 8 * *index + 7, val: setting);
1643
1644 return 0;
1645}
1646
1647static const struct serial_rs485 pci_fintek_rs485_supported = {
1648 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
1649 /* F81504/508/512 does not support RTS delay before or after send */
1650};
1651
1652static int pci_fintek_setup(struct serial_private *priv,
1653 const struct pciserial_board *board,
1654 struct uart_8250_port *port, int idx)
1655{
1656 struct pci_dev *pdev = priv->dev;
1657 u8 *data;
1658 u8 config_base;
1659 u16 iobase;
1660
1661 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1662 return serial_8250_warn_need_ioport(dev: pdev);
1663
1664 config_base = 0x40 + 0x08 * idx;
1665
1666 /* Get the io address from configuration space */
1667 pci_read_config_word(dev: pdev, where: config_base + 4, val: &iobase);
1668
1669 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1670
1671 port->port.iotype = UPIO_PORT;
1672 port->port.iobase = iobase;
1673 port->port.rs485_config = pci_fintek_rs485_config;
1674 port->port.rs485_supported = pci_fintek_rs485_supported;
1675
1676 data = devm_kzalloc(dev: &pdev->dev, size: sizeof(u8), GFP_KERNEL);
1677 if (!data)
1678 return -ENOMEM;
1679
1680 /* preserve index in PCI configuration space */
1681 *data = idx;
1682 port->port.private_data = data;
1683
1684 return 0;
1685}
1686
1687static int pci_fintek_init(struct pci_dev *dev)
1688{
1689 unsigned long iobase;
1690 u32 max_port, i;
1691 resource_size_t bar_data[3];
1692 u8 config_base;
1693 struct serial_private *priv = pci_get_drvdata(pdev: dev);
1694
1695 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1696 return serial_8250_warn_need_ioport(dev);
1697
1698 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1699 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1700 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1701 return -ENODEV;
1702
1703 switch (dev->device) {
1704 case 0x1104: /* 4 ports */
1705 case 0x1108: /* 8 ports */
1706 max_port = dev->device & 0xff;
1707 break;
1708 case 0x1112: /* 12 ports */
1709 max_port = 12;
1710 break;
1711 default:
1712 return -EINVAL;
1713 }
1714
1715 /* Get the io address dispatch from the BIOS */
1716 bar_data[0] = pci_resource_start(dev, 5);
1717 bar_data[1] = pci_resource_start(dev, 4);
1718 bar_data[2] = pci_resource_start(dev, 3);
1719
1720 for (i = 0; i < max_port; ++i) {
1721 /* UART0 configuration offset start from 0x40 */
1722 config_base = 0x40 + 0x08 * i;
1723
1724 /* Calculate Real IO Port */
1725 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1726
1727 /* Enable UART I/O port */
1728 pci_write_config_byte(dev, where: config_base + 0x00, val: 0x01);
1729
1730 /* Select 128-byte FIFO and 8x FIFO threshold */
1731 pci_write_config_byte(dev, where: config_base + 0x01, val: 0x33);
1732
1733 /* LSB UART */
1734 pci_write_config_byte(dev, where: config_base + 0x04,
1735 val: (u8)(iobase & 0xff));
1736
1737 /* MSB UART */
1738 pci_write_config_byte(dev, where: config_base + 0x05,
1739 val: (u8)((iobase & 0xff00) >> 8));
1740
1741 pci_write_config_byte(dev, where: config_base + 0x06, val: dev->irq);
1742
1743 if (!priv) {
1744 /* First init without port data
1745 * force init to RS232 Mode
1746 */
1747 pci_write_config_byte(dev, where: config_base + 0x07, val: 0x01);
1748 }
1749 }
1750
1751 return max_port;
1752}
1753
1754static void f815xxa_mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)
1755{
1756 struct f815xxa_data *data = p->private_data;
1757 unsigned long flags;
1758
1759 spin_lock_irqsave(&data->lock, flags);
1760 writeb(val: value, addr: p->membase + offset);
1761 readb(addr: p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1762 spin_unlock_irqrestore(lock: &data->lock, flags);
1763}
1764
1765static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1766 const struct pciserial_board *board,
1767 struct uart_8250_port *port, int idx)
1768{
1769 struct pci_dev *pdev = priv->dev;
1770 struct f815xxa_data *data;
1771
1772 data = devm_kzalloc(dev: &pdev->dev, size: sizeof(*data), GFP_KERNEL);
1773 if (!data)
1774 return -ENOMEM;
1775
1776 data->idx = idx;
1777 spin_lock_init(&data->lock);
1778
1779 port->port.private_data = data;
1780 port->port.iotype = UPIO_MEM;
1781 port->port.flags |= UPF_IOREMAP;
1782 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1783 port->port.serial_out = f815xxa_mem_serial_out;
1784
1785 return 0;
1786}
1787
1788static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1789{
1790 u32 max_port, i;
1791 int config_base;
1792
1793 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1794 return -ENODEV;
1795
1796 switch (dev->device) {
1797 case 0x1204: /* 4 ports */
1798 case 0x1208: /* 8 ports */
1799 max_port = dev->device & 0xff;
1800 break;
1801 case 0x1212: /* 12 ports */
1802 max_port = 12;
1803 break;
1804 default:
1805 return -EINVAL;
1806 }
1807
1808 /* Set to mmio decode */
1809 pci_write_config_byte(dev, where: 0x209, val: 0x40);
1810
1811 for (i = 0; i < max_port; ++i) {
1812 /* UART0 configuration offset start from 0x2A0 */
1813 config_base = 0x2A0 + 0x08 * i;
1814
1815 /* Select 128-byte FIFO and 8x FIFO threshold */
1816 pci_write_config_byte(dev, where: config_base + 0x01, val: 0x33);
1817
1818 /* Enable UART I/O port */
1819 pci_write_config_byte(dev, where: config_base + 0, val: 0x01);
1820 }
1821
1822 return max_port;
1823}
1824
1825static int skip_tx_en_setup(struct serial_private *priv,
1826 const struct pciserial_board *board,
1827 struct uart_8250_port *port, int idx)
1828{
1829 port->port.quirks |= UPQ_NO_TXEN_TEST;
1830 pci_dbg(priv->dev,
1831 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1832 priv->dev->vendor, priv->dev->device,
1833 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1834
1835 return pci_default_setup(priv, board, port, idx);
1836}
1837
1838static void kt_handle_break(struct uart_port *p)
1839{
1840 struct uart_8250_port *up = up_to_u8250p(up: p);
1841 /*
1842 * On receipt of a BI, serial device in Intel ME (Intel
1843 * management engine) needs to have its fifos cleared for sane
1844 * SOL (Serial Over Lan) output.
1845 */
1846 serial8250_clear_and_reinit_fifos(p: up);
1847}
1848
1849static u32 kt_serial_in(struct uart_port *p, unsigned int offset)
1850{
1851 struct uart_8250_port *up = up_to_u8250p(up: p);
1852 u32 val;
1853
1854 /*
1855 * When the Intel ME (management engine) gets reset its serial
1856 * port registers could return 0 momentarily. Functions like
1857 * serial8250_console_write, read and save the IER, perform
1858 * some operation and then restore it. In order to avoid
1859 * setting IER register inadvertently to 0, if the value read
1860 * is 0, double check with ier value in uart_8250_port and use
1861 * that instead. up->ier should be the same value as what is
1862 * currently configured.
1863 */
1864 val = inb(port: p->iobase + offset);
1865 if (offset == UART_IER) {
1866 if (val == 0)
1867 val = up->ier;
1868 }
1869 return val;
1870}
1871
1872static int kt_serial_setup(struct serial_private *priv,
1873 const struct pciserial_board *board,
1874 struct uart_8250_port *port, int idx)
1875{
1876 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1877 return serial_8250_warn_need_ioport(dev: priv->dev);
1878
1879 port->port.flags |= UPF_BUG_THRE;
1880 port->port.serial_in = kt_serial_in;
1881 port->port.handle_break = kt_handle_break;
1882 return skip_tx_en_setup(priv, board, port, idx);
1883}
1884
1885static int pci_eg20t_init(struct pci_dev *dev)
1886{
1887#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1888 return -ENODEV;
1889#else
1890 return 0;
1891#endif
1892}
1893
1894static int
1895pci_wch_ch353_setup(struct serial_private *priv,
1896 const struct pciserial_board *board,
1897 struct uart_8250_port *port, int idx)
1898{
1899 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1900 return serial_8250_warn_need_ioport(dev: priv->dev);
1901
1902 port->port.flags |= UPF_FIXED_TYPE;
1903 port->port.type = PORT_16550A;
1904 return pci_default_setup(priv, board, port, idx);
1905}
1906
1907static int
1908pci_wch_ch355_setup(struct serial_private *priv,
1909 const struct pciserial_board *board,
1910 struct uart_8250_port *port, int idx)
1911{
1912 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1913 return serial_8250_warn_need_ioport(dev: priv->dev);
1914
1915 port->port.flags |= UPF_FIXED_TYPE;
1916 port->port.type = PORT_16550A;
1917 return pci_default_setup(priv, board, port, idx);
1918}
1919
1920static int
1921pci_wch_ch38x_setup(struct serial_private *priv,
1922 const struct pciserial_board *board,
1923 struct uart_8250_port *port, int idx)
1924{
1925 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1926 return serial_8250_warn_need_ioport(dev: priv->dev);
1927
1928 port->port.flags |= UPF_FIXED_TYPE;
1929 port->port.type = PORT_16850;
1930 return pci_default_setup(priv, board, port, idx);
1931}
1932
1933
1934#define CH384_XINT_ENABLE_REG 0xEB
1935#define CH384_XINT_ENABLE_BIT 0x02
1936
1937static int pci_wch_ch38x_init(struct pci_dev *dev)
1938{
1939 int max_port;
1940 unsigned long iobase;
1941
1942 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1943 return serial_8250_warn_need_ioport(dev);
1944
1945 switch (dev->device) {
1946 case 0x3853: /* 8 ports */
1947 max_port = 8;
1948 break;
1949 default:
1950 return -EINVAL;
1951 }
1952
1953 iobase = pci_resource_start(dev, 0);
1954 outb(CH384_XINT_ENABLE_BIT, port: iobase + CH384_XINT_ENABLE_REG);
1955
1956 return max_port;
1957}
1958
1959static void pci_wch_ch38x_exit(struct pci_dev *dev)
1960{
1961 unsigned long iobase;
1962
1963 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {
1964 serial_8250_warn_need_ioport(dev);
1965 return;
1966 }
1967
1968 iobase = pci_resource_start(dev, 0);
1969 outb(value: 0x0, port: iobase + CH384_XINT_ENABLE_REG);
1970}
1971
1972
1973static int
1974pci_sunix_setup(struct serial_private *priv,
1975 const struct pciserial_board *board,
1976 struct uart_8250_port *port, int idx)
1977{
1978 int bar;
1979 int offset;
1980
1981 port->port.flags |= UPF_FIXED_TYPE;
1982 port->port.type = PORT_SUNIX;
1983
1984 if (idx < 4) {
1985 bar = 0;
1986 offset = idx * board->uart_offset;
1987 } else {
1988 bar = 1;
1989 idx -= 4;
1990 idx = div_s64_rem(dividend: idx, divisor: 4, remainder: &offset);
1991 offset = idx * 64 + offset * board->uart_offset;
1992 }
1993
1994 return setup_port(priv, port, bar, offset, regshift: 0);
1995}
1996
1997#define MOXA_PUART_GPIO_EN 0x09
1998#define MOXA_PUART_GPIO_OUT 0x0A
1999
2000#define MOXA_GPIO_PIN2 BIT(2)
2001
2002#define MOXA_RS232 0x00
2003#define MOXA_RS422 0x01
2004#define MOXA_RS485_4W 0x0B
2005#define MOXA_RS485_2W 0x0F
2006#define MOXA_UIR_OFFSET 0x04
2007#define MOXA_EVEN_RS_MASK GENMASK(3, 0)
2008#define MOXA_ODD_RS_MASK GENMASK(7, 4)
2009
2010enum {
2011 MOXA_SUPP_RS232 = BIT(0),
2012 MOXA_SUPP_RS422 = BIT(1),
2013 MOXA_SUPP_RS485 = BIT(2),
2014};
2015
2016static unsigned short moxa_get_nports(unsigned short device)
2017{
2018 switch (device) {
2019 case PCI_DEVICE_ID_MOXA_CP116E_A_A:
2020 case PCI_DEVICE_ID_MOXA_CP116E_A_B:
2021 return 8;
2022 }
2023
2024 return FIELD_GET(0x00F0, device);
2025}
2026
2027static bool pci_moxa_is_mini_pcie(unsigned short device)
2028{
2029 if (device == PCI_DEVICE_ID_MOXA_CP102N ||
2030 device == PCI_DEVICE_ID_MOXA_CP104N ||
2031 device == PCI_DEVICE_ID_MOXA_CP112N ||
2032 device == PCI_DEVICE_ID_MOXA_CP114N ||
2033 device == PCI_DEVICE_ID_MOXA_CP132N ||
2034 device == PCI_DEVICE_ID_MOXA_CP134N)
2035 return true;
2036
2037 return false;
2038}
2039
2040static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)
2041{
2042 switch (dev->device & 0x0F00) {
2043 case 0x0000:
2044 case 0x0600:
2045 return MOXA_SUPP_RS232;
2046 case 0x0100:
2047 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2048 case 0x0300:
2049 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2050 }
2051 return 0;
2052}
2053
2054static int pci_moxa_set_interface(const struct pci_dev *dev,
2055 unsigned int port_idx,
2056 u8 mode)
2057{
2058 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2059 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
2060 u8 val;
2061
2062 val = inb(port: UIR_addr);
2063
2064 if (port_idx % 2) {
2065 val &= ~MOXA_ODD_RS_MASK;
2066 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
2067 } else {
2068 val &= ~MOXA_EVEN_RS_MASK;
2069 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
2070 }
2071 outb(value: val, port: UIR_addr);
2072
2073 return 0;
2074}
2075
2076static int pci_moxa_init(struct pci_dev *dev)
2077{
2078 unsigned short device = dev->device;
2079 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2080 unsigned int i, num_ports = moxa_get_nports(device);
2081 u8 val, init_mode = MOXA_RS232;
2082
2083 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2084 return serial_8250_warn_need_ioport(dev);
2085
2086 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {
2087 init_mode = MOXA_RS422;
2088 }
2089 for (i = 0; i < num_ports; ++i)
2090 pci_moxa_set_interface(dev, port_idx: i, mode: init_mode);
2091
2092 /*
2093 * Enable hardware buffer to prevent break signal output when system boots up.
2094 * This hardware buffer is only supported on Mini PCIe series.
2095 */
2096 if (pci_moxa_is_mini_pcie(device)) {
2097 /* Set GPIO direction */
2098 val = inb(port: iobar_addr + MOXA_PUART_GPIO_EN);
2099 val |= MOXA_GPIO_PIN2;
2100 outb(value: val, port: iobar_addr + MOXA_PUART_GPIO_EN);
2101 /* Enable low GPIO */
2102 val = inb(port: iobar_addr + MOXA_PUART_GPIO_OUT);
2103 val &= ~MOXA_GPIO_PIN2;
2104 outb(value: val, port: iobar_addr + MOXA_PUART_GPIO_OUT);
2105 }
2106
2107 return num_ports;
2108}
2109
2110static int
2111pci_moxa_setup(struct serial_private *priv,
2112 const struct pciserial_board *board,
2113 struct uart_8250_port *port, int idx)
2114{
2115 unsigned int bar = FL_GET_BASE(board->flags);
2116 int offset;
2117
2118 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2119 return serial_8250_warn_need_ioport(dev: priv->dev);
2120
2121 if (board->num_ports == 4 && idx == 3)
2122 offset = 7 * board->uart_offset;
2123 else
2124 offset = idx * board->uart_offset;
2125
2126 return setup_port(priv, port, bar, offset, regshift: 0);
2127}
2128
2129/*
2130 * Master list of serial port init/setup/exit quirks.
2131 * This does not describe the general nature of the port.
2132 * (ie, baud base, number and location of ports, etc)
2133 *
2134 * This list is ordered alphabetically by vendor then device.
2135 * Specific entries must come before more generic entries.
2136 */
2137static struct pci_serial_quirk pci_serial_quirks[] = {
2138 /*
2139 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2140 */
2141 {
2142 .vendor = PCI_VENDOR_ID_AMCC,
2143 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2144 .subvendor = PCI_ANY_ID,
2145 .subdevice = PCI_ANY_ID,
2146 .setup = addidata_apci7800_setup,
2147 },
2148 /*
2149 * AFAVLAB cards - these may be called via parport_serial
2150 * It is not clear whether this applies to all products.
2151 */
2152 {
2153 .vendor = PCI_VENDOR_ID_AFAVLAB,
2154 .device = PCI_ANY_ID,
2155 .subvendor = PCI_ANY_ID,
2156 .subdevice = PCI_ANY_ID,
2157 .setup = afavlab_setup,
2158 },
2159 /*
2160 * HP Diva
2161 */
2162 {
2163 .vendor = PCI_VENDOR_ID_HP,
2164 .device = PCI_DEVICE_ID_HP_DIVA,
2165 .subvendor = PCI_ANY_ID,
2166 .subdevice = PCI_ANY_ID,
2167 .init = pci_hp_diva_init,
2168 .setup = pci_hp_diva_setup,
2169 },
2170 /*
2171 * HPE PCI serial device
2172 */
2173 {
2174 .vendor = PCI_VENDOR_ID_HP_3PAR,
2175 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2176 .subvendor = PCI_ANY_ID,
2177 .subdevice = PCI_ANY_ID,
2178 .setup = pci_hp_diva_setup,
2179 },
2180 /*
2181 * Intel
2182 */
2183 {
2184 .vendor = PCI_VENDOR_ID_INTEL,
2185 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2186 .subvendor = 0xe4bf,
2187 .subdevice = PCI_ANY_ID,
2188 .init = pci_inteli960ni_init,
2189 .setup = pci_default_setup,
2190 },
2191 {
2192 .vendor = PCI_VENDOR_ID_INTEL,
2193 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .setup = skip_tx_en_setup,
2197 },
2198 {
2199 .vendor = PCI_VENDOR_ID_INTEL,
2200 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .setup = skip_tx_en_setup,
2204 },
2205 {
2206 .vendor = PCI_VENDOR_ID_INTEL,
2207 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2208 .subvendor = PCI_ANY_ID,
2209 .subdevice = PCI_ANY_ID,
2210 .setup = skip_tx_en_setup,
2211 },
2212 {
2213 .vendor = PCI_VENDOR_ID_INTEL,
2214 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2215 .subvendor = PCI_ANY_ID,
2216 .subdevice = PCI_ANY_ID,
2217 .setup = ce4100_serial_setup,
2218 },
2219 {
2220 .vendor = PCI_VENDOR_ID_INTEL,
2221 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2222 .subvendor = PCI_ANY_ID,
2223 .subdevice = PCI_ANY_ID,
2224 .setup = kt_serial_setup,
2225 },
2226 /*
2227 * ITE
2228 */
2229 {
2230 .vendor = PCI_VENDOR_ID_ITE,
2231 .device = PCI_DEVICE_ID_ITE_8872,
2232 .subvendor = PCI_ANY_ID,
2233 .subdevice = PCI_ANY_ID,
2234 .init = pci_ite887x_init,
2235 .setup = pci_default_setup,
2236 .exit = pci_ite887x_exit,
2237 },
2238 /*
2239 * National Instruments
2240 */
2241 {
2242 .vendor = PCI_VENDOR_ID_NI,
2243 .device = PCI_DEVICE_ID_NI_PCI23216,
2244 .subvendor = PCI_ANY_ID,
2245 .subdevice = PCI_ANY_ID,
2246 .init = pci_ni8420_init,
2247 .setup = pci_default_setup,
2248 .exit = pci_ni8420_exit,
2249 },
2250 {
2251 .vendor = PCI_VENDOR_ID_NI,
2252 .device = PCI_DEVICE_ID_NI_PCI2328,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .init = pci_ni8420_init,
2256 .setup = pci_default_setup,
2257 .exit = pci_ni8420_exit,
2258 },
2259 {
2260 .vendor = PCI_VENDOR_ID_NI,
2261 .device = PCI_DEVICE_ID_NI_PCI2324,
2262 .subvendor = PCI_ANY_ID,
2263 .subdevice = PCI_ANY_ID,
2264 .init = pci_ni8420_init,
2265 .setup = pci_default_setup,
2266 .exit = pci_ni8420_exit,
2267 },
2268 {
2269 .vendor = PCI_VENDOR_ID_NI,
2270 .device = PCI_DEVICE_ID_NI_PCI2322,
2271 .subvendor = PCI_ANY_ID,
2272 .subdevice = PCI_ANY_ID,
2273 .init = pci_ni8420_init,
2274 .setup = pci_default_setup,
2275 .exit = pci_ni8420_exit,
2276 },
2277 {
2278 .vendor = PCI_VENDOR_ID_NI,
2279 .device = PCI_DEVICE_ID_NI_PCI2324I,
2280 .subvendor = PCI_ANY_ID,
2281 .subdevice = PCI_ANY_ID,
2282 .init = pci_ni8420_init,
2283 .setup = pci_default_setup,
2284 .exit = pci_ni8420_exit,
2285 },
2286 {
2287 .vendor = PCI_VENDOR_ID_NI,
2288 .device = PCI_DEVICE_ID_NI_PCI2322I,
2289 .subvendor = PCI_ANY_ID,
2290 .subdevice = PCI_ANY_ID,
2291 .init = pci_ni8420_init,
2292 .setup = pci_default_setup,
2293 .exit = pci_ni8420_exit,
2294 },
2295 {
2296 .vendor = PCI_VENDOR_ID_NI,
2297 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2298 .subvendor = PCI_ANY_ID,
2299 .subdevice = PCI_ANY_ID,
2300 .init = pci_ni8420_init,
2301 .setup = pci_default_setup,
2302 .exit = pci_ni8420_exit,
2303 },
2304 {
2305 .vendor = PCI_VENDOR_ID_NI,
2306 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2307 .subvendor = PCI_ANY_ID,
2308 .subdevice = PCI_ANY_ID,
2309 .init = pci_ni8420_init,
2310 .setup = pci_default_setup,
2311 .exit = pci_ni8420_exit,
2312 },
2313 {
2314 .vendor = PCI_VENDOR_ID_NI,
2315 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2316 .subvendor = PCI_ANY_ID,
2317 .subdevice = PCI_ANY_ID,
2318 .init = pci_ni8420_init,
2319 .setup = pci_default_setup,
2320 .exit = pci_ni8420_exit,
2321 },
2322 {
2323 .vendor = PCI_VENDOR_ID_NI,
2324 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2325 .subvendor = PCI_ANY_ID,
2326 .subdevice = PCI_ANY_ID,
2327 .init = pci_ni8420_init,
2328 .setup = pci_default_setup,
2329 .exit = pci_ni8420_exit,
2330 },
2331 {
2332 .vendor = PCI_VENDOR_ID_NI,
2333 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2334 .subvendor = PCI_ANY_ID,
2335 .subdevice = PCI_ANY_ID,
2336 .init = pci_ni8420_init,
2337 .setup = pci_default_setup,
2338 .exit = pci_ni8420_exit,
2339 },
2340 {
2341 .vendor = PCI_VENDOR_ID_NI,
2342 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2343 .subvendor = PCI_ANY_ID,
2344 .subdevice = PCI_ANY_ID,
2345 .init = pci_ni8420_init,
2346 .setup = pci_default_setup,
2347 .exit = pci_ni8420_exit,
2348 },
2349 {
2350 .vendor = PCI_VENDOR_ID_NI,
2351 .device = PCI_ANY_ID,
2352 .subvendor = PCI_ANY_ID,
2353 .subdevice = PCI_ANY_ID,
2354 .init = pci_ni8430_init,
2355 .setup = pci_ni8430_setup,
2356 .exit = pci_ni8430_exit,
2357 },
2358 /* Quatech */
2359 {
2360 .vendor = PCI_VENDOR_ID_QUATECH,
2361 .device = PCI_ANY_ID,
2362 .subvendor = PCI_ANY_ID,
2363 .subdevice = PCI_ANY_ID,
2364 .init = pci_quatech_init,
2365 .setup = pci_quatech_setup,
2366 },
2367 /*
2368 * Panacom
2369 */
2370 {
2371 .vendor = PCI_VENDOR_ID_PANACOM,
2372 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2373 .subvendor = PCI_ANY_ID,
2374 .subdevice = PCI_ANY_ID,
2375 .init = pci_plx9050_init,
2376 .setup = pci_default_setup,
2377 .exit = pci_plx9050_exit,
2378 },
2379 {
2380 .vendor = PCI_VENDOR_ID_PANACOM,
2381 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2382 .subvendor = PCI_ANY_ID,
2383 .subdevice = PCI_ANY_ID,
2384 .init = pci_plx9050_init,
2385 .setup = pci_default_setup,
2386 .exit = pci_plx9050_exit,
2387 },
2388 /*
2389 * PLX
2390 */
2391 {
2392 .vendor = PCI_VENDOR_ID_PLX,
2393 .device = PCI_DEVICE_ID_PLX_9050,
2394 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2395 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2396 .init = pci_plx9050_init,
2397 .setup = pci_default_setup,
2398 .exit = pci_plx9050_exit,
2399 },
2400 {
2401 .vendor = PCI_VENDOR_ID_PLX,
2402 .device = PCI_DEVICE_ID_PLX_9050,
2403 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2404 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2405 .init = pci_plx9050_init,
2406 .setup = pci_default_setup,
2407 .exit = pci_plx9050_exit,
2408 },
2409 {
2410 .vendor = PCI_VENDOR_ID_PLX,
2411 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2412 .subvendor = PCI_VENDOR_ID_PLX,
2413 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2414 .init = pci_plx9050_init,
2415 .setup = pci_default_setup,
2416 .exit = pci_plx9050_exit,
2417 },
2418 /*
2419 * SBS Technologies, Inc., PMC-OCTALPRO 232
2420 */
2421 {
2422 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2423 .device = PCI_DEVICE_ID_OCTPRO,
2424 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2425 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2426 .init = sbs_init,
2427 .setup = sbs_setup,
2428 .exit = sbs_exit,
2429 },
2430 /*
2431 * SBS Technologies, Inc., PMC-OCTALPRO 422
2432 */
2433 {
2434 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2435 .device = PCI_DEVICE_ID_OCTPRO,
2436 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2437 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2438 .init = sbs_init,
2439 .setup = sbs_setup,
2440 .exit = sbs_exit,
2441 },
2442 /*
2443 * SBS Technologies, Inc., P-Octal 232
2444 */
2445 {
2446 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2447 .device = PCI_DEVICE_ID_OCTPRO,
2448 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2449 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2450 .init = sbs_init,
2451 .setup = sbs_setup,
2452 .exit = sbs_exit,
2453 },
2454 /*
2455 * SBS Technologies, Inc., P-Octal 422
2456 */
2457 {
2458 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2459 .device = PCI_DEVICE_ID_OCTPRO,
2460 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2461 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2462 .init = sbs_init,
2463 .setup = sbs_setup,
2464 .exit = sbs_exit,
2465 },
2466 /*
2467 * SIIG cards - these may be called via parport_serial
2468 */
2469 {
2470 .vendor = PCI_VENDOR_ID_SIIG,
2471 .device = PCI_ANY_ID,
2472 .subvendor = PCI_ANY_ID,
2473 .subdevice = PCI_ANY_ID,
2474 .init = pci_siig_init,
2475 .setup = pci_siig_setup,
2476 },
2477 /*
2478 * Titan cards
2479 */
2480 {
2481 .vendor = PCI_VENDOR_ID_TITAN,
2482 .device = PCI_DEVICE_ID_TITAN_400L,
2483 .subvendor = PCI_ANY_ID,
2484 .subdevice = PCI_ANY_ID,
2485 .setup = titan_400l_800l_setup,
2486 },
2487 {
2488 .vendor = PCI_VENDOR_ID_TITAN,
2489 .device = PCI_DEVICE_ID_TITAN_800L,
2490 .subvendor = PCI_ANY_ID,
2491 .subdevice = PCI_ANY_ID,
2492 .setup = titan_400l_800l_setup,
2493 },
2494 /*
2495 * Timedia cards
2496 */
2497 {
2498 .vendor = PCI_VENDOR_ID_TIMEDIA,
2499 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2500 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2501 .subdevice = PCI_ANY_ID,
2502 .probe = pci_timedia_probe,
2503 .init = pci_timedia_init,
2504 .setup = pci_timedia_setup,
2505 },
2506 {
2507 .vendor = PCI_VENDOR_ID_TIMEDIA,
2508 .device = PCI_ANY_ID,
2509 .subvendor = PCI_ANY_ID,
2510 .subdevice = PCI_ANY_ID,
2511 .setup = pci_timedia_setup,
2512 },
2513 /*
2514 * Sunix PCI serial boards
2515 */
2516 {
2517 .vendor = PCI_VENDOR_ID_SUNIX,
2518 .device = PCI_DEVICE_ID_SUNIX_1999,
2519 .subvendor = PCI_VENDOR_ID_SUNIX,
2520 .subdevice = PCI_ANY_ID,
2521 .setup = pci_sunix_setup,
2522 },
2523 /*
2524 * Xircom cards
2525 */
2526 {
2527 .vendor = PCI_VENDOR_ID_XIRCOM,
2528 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2529 .subvendor = PCI_ANY_ID,
2530 .subdevice = PCI_ANY_ID,
2531 .init = pci_xircom_init,
2532 .setup = pci_default_setup,
2533 },
2534 /*
2535 * Netmos cards - these may be called via parport_serial
2536 */
2537 {
2538 .vendor = PCI_VENDOR_ID_NETMOS,
2539 .device = PCI_ANY_ID,
2540 .subvendor = PCI_ANY_ID,
2541 .subdevice = PCI_ANY_ID,
2542 .init = pci_netmos_init,
2543 .setup = pci_netmos_9900_setup,
2544 },
2545 /*
2546 * EndRun Technologies
2547 */
2548 {
2549 .vendor = PCI_VENDOR_ID_ENDRUN,
2550 .device = PCI_ANY_ID,
2551 .subvendor = PCI_ANY_ID,
2552 .subdevice = PCI_ANY_ID,
2553 .init = pci_oxsemi_tornado_init,
2554 .setup = pci_default_setup,
2555 },
2556 /*
2557 * For Oxford Semiconductor Tornado based devices
2558 */
2559 {
2560 .vendor = PCI_VENDOR_ID_OXSEMI,
2561 .device = PCI_ANY_ID,
2562 .subvendor = PCI_ANY_ID,
2563 .subdevice = PCI_ANY_ID,
2564 .init = pci_oxsemi_tornado_init,
2565 .setup = pci_oxsemi_tornado_setup,
2566 },
2567 {
2568 .vendor = PCI_VENDOR_ID_MAINPINE,
2569 .device = PCI_ANY_ID,
2570 .subvendor = PCI_ANY_ID,
2571 .subdevice = PCI_ANY_ID,
2572 .init = pci_oxsemi_tornado_init,
2573 .setup = pci_oxsemi_tornado_setup,
2574 },
2575 {
2576 .vendor = PCI_VENDOR_ID_DIGI,
2577 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2578 .subvendor = PCI_SUBVENDOR_ID_IBM,
2579 .subdevice = PCI_ANY_ID,
2580 .init = pci_oxsemi_tornado_init,
2581 .setup = pci_oxsemi_tornado_setup,
2582 },
2583 /*
2584 * Brainboxes devices - all Oxsemi based
2585 */
2586 {
2587 .vendor = PCI_VENDOR_ID_INTASHIELD,
2588 .device = 0x4027,
2589 .subvendor = PCI_ANY_ID,
2590 .subdevice = PCI_ANY_ID,
2591 .init = pci_oxsemi_tornado_init,
2592 .setup = pci_oxsemi_tornado_setup,
2593 },
2594 {
2595 .vendor = PCI_VENDOR_ID_INTASHIELD,
2596 .device = 0x4028,
2597 .subvendor = PCI_ANY_ID,
2598 .subdevice = PCI_ANY_ID,
2599 .init = pci_oxsemi_tornado_init,
2600 .setup = pci_oxsemi_tornado_setup,
2601 },
2602 {
2603 .vendor = PCI_VENDOR_ID_INTASHIELD,
2604 .device = 0x4029,
2605 .subvendor = PCI_ANY_ID,
2606 .subdevice = PCI_ANY_ID,
2607 .init = pci_oxsemi_tornado_init,
2608 .setup = pci_oxsemi_tornado_setup,
2609 },
2610 {
2611 .vendor = PCI_VENDOR_ID_INTASHIELD,
2612 .device = 0x4019,
2613 .subvendor = PCI_ANY_ID,
2614 .subdevice = PCI_ANY_ID,
2615 .init = pci_oxsemi_tornado_init,
2616 .setup = pci_oxsemi_tornado_setup,
2617 },
2618 {
2619 .vendor = PCI_VENDOR_ID_INTASHIELD,
2620 .device = 0x4016,
2621 .subvendor = PCI_ANY_ID,
2622 .subdevice = PCI_ANY_ID,
2623 .init = pci_oxsemi_tornado_init,
2624 .setup = pci_oxsemi_tornado_setup,
2625 },
2626 {
2627 .vendor = PCI_VENDOR_ID_INTASHIELD,
2628 .device = 0x4015,
2629 .subvendor = PCI_ANY_ID,
2630 .subdevice = PCI_ANY_ID,
2631 .init = pci_oxsemi_tornado_init,
2632 .setup = pci_oxsemi_tornado_setup,
2633 },
2634 {
2635 .vendor = PCI_VENDOR_ID_INTASHIELD,
2636 .device = 0x400A,
2637 .subvendor = PCI_ANY_ID,
2638 .subdevice = PCI_ANY_ID,
2639 .init = pci_oxsemi_tornado_init,
2640 .setup = pci_oxsemi_tornado_setup,
2641 },
2642 {
2643 .vendor = PCI_VENDOR_ID_INTASHIELD,
2644 .device = 0x400E,
2645 .subvendor = PCI_ANY_ID,
2646 .subdevice = PCI_ANY_ID,
2647 .init = pci_oxsemi_tornado_init,
2648 .setup = pci_oxsemi_tornado_setup,
2649 },
2650 {
2651 .vendor = PCI_VENDOR_ID_INTASHIELD,
2652 .device = 0x400C,
2653 .subvendor = PCI_ANY_ID,
2654 .subdevice = PCI_ANY_ID,
2655 .init = pci_oxsemi_tornado_init,
2656 .setup = pci_oxsemi_tornado_setup,
2657 },
2658 {
2659 .vendor = PCI_VENDOR_ID_INTASHIELD,
2660 .device = 0x400B,
2661 .subvendor = PCI_ANY_ID,
2662 .subdevice = PCI_ANY_ID,
2663 .init = pci_oxsemi_tornado_init,
2664 .setup = pci_oxsemi_tornado_setup,
2665 },
2666 {
2667 .vendor = PCI_VENDOR_ID_INTASHIELD,
2668 .device = 0x400F,
2669 .subvendor = PCI_ANY_ID,
2670 .subdevice = PCI_ANY_ID,
2671 .init = pci_oxsemi_tornado_init,
2672 .setup = pci_oxsemi_tornado_setup,
2673 },
2674 {
2675 .vendor = PCI_VENDOR_ID_INTASHIELD,
2676 .device = 0x4010,
2677 .subvendor = PCI_ANY_ID,
2678 .subdevice = PCI_ANY_ID,
2679 .init = pci_oxsemi_tornado_init,
2680 .setup = pci_oxsemi_tornado_setup,
2681 },
2682 {
2683 .vendor = PCI_VENDOR_ID_INTASHIELD,
2684 .device = 0x4011,
2685 .subvendor = PCI_ANY_ID,
2686 .subdevice = PCI_ANY_ID,
2687 .init = pci_oxsemi_tornado_init,
2688 .setup = pci_oxsemi_tornado_setup,
2689 },
2690 {
2691 .vendor = PCI_VENDOR_ID_INTASHIELD,
2692 .device = 0x401D,
2693 .subvendor = PCI_ANY_ID,
2694 .subdevice = PCI_ANY_ID,
2695 .init = pci_oxsemi_tornado_init,
2696 .setup = pci_oxsemi_tornado_setup,
2697 },
2698 {
2699 .vendor = PCI_VENDOR_ID_INTASHIELD,
2700 .device = 0x401E,
2701 .subvendor = PCI_ANY_ID,
2702 .subdevice = PCI_ANY_ID,
2703 .init = pci_oxsemi_tornado_init,
2704 .setup = pci_oxsemi_tornado_setup,
2705 },
2706 {
2707 .vendor = PCI_VENDOR_ID_INTASHIELD,
2708 .device = 0x4013,
2709 .subvendor = PCI_ANY_ID,
2710 .subdevice = PCI_ANY_ID,
2711 .init = pci_oxsemi_tornado_init,
2712 .setup = pci_oxsemi_tornado_setup,
2713 },
2714 {
2715 .vendor = PCI_VENDOR_ID_INTASHIELD,
2716 .device = 0x4017,
2717 .subvendor = PCI_ANY_ID,
2718 .subdevice = PCI_ANY_ID,
2719 .init = pci_oxsemi_tornado_init,
2720 .setup = pci_oxsemi_tornado_setup,
2721 },
2722 {
2723 .vendor = PCI_VENDOR_ID_INTASHIELD,
2724 .device = 0x4018,
2725 .subvendor = PCI_ANY_ID,
2726 .subdevice = PCI_ANY_ID,
2727 .init = pci_oxsemi_tornado_init,
2728 .setup = pci_oxsemi_tornado_setup,
2729 },
2730 {
2731 .vendor = PCI_VENDOR_ID_INTASHIELD,
2732 .device = 0x4026,
2733 .subvendor = PCI_ANY_ID,
2734 .subdevice = PCI_ANY_ID,
2735 .init = pci_oxsemi_tornado_init,
2736 .setup = pci_oxsemi_tornado_setup,
2737 },
2738 {
2739 .vendor = PCI_VENDOR_ID_INTASHIELD,
2740 .device = 0x4021,
2741 .subvendor = PCI_ANY_ID,
2742 .subdevice = PCI_ANY_ID,
2743 .init = pci_oxsemi_tornado_init,
2744 .setup = pci_oxsemi_tornado_setup,
2745 },
2746 {
2747 .vendor = PCI_VENDOR_ID_INTEL,
2748 .device = 0x8811,
2749 .subvendor = PCI_ANY_ID,
2750 .subdevice = PCI_ANY_ID,
2751 .init = pci_eg20t_init,
2752 .setup = pci_default_setup,
2753 },
2754 {
2755 .vendor = PCI_VENDOR_ID_INTEL,
2756 .device = 0x8812,
2757 .subvendor = PCI_ANY_ID,
2758 .subdevice = PCI_ANY_ID,
2759 .init = pci_eg20t_init,
2760 .setup = pci_default_setup,
2761 },
2762 {
2763 .vendor = PCI_VENDOR_ID_INTEL,
2764 .device = 0x8813,
2765 .subvendor = PCI_ANY_ID,
2766 .subdevice = PCI_ANY_ID,
2767 .init = pci_eg20t_init,
2768 .setup = pci_default_setup,
2769 },
2770 {
2771 .vendor = PCI_VENDOR_ID_INTEL,
2772 .device = 0x8814,
2773 .subvendor = PCI_ANY_ID,
2774 .subdevice = PCI_ANY_ID,
2775 .init = pci_eg20t_init,
2776 .setup = pci_default_setup,
2777 },
2778 {
2779 .vendor = 0x10DB,
2780 .device = 0x8027,
2781 .subvendor = PCI_ANY_ID,
2782 .subdevice = PCI_ANY_ID,
2783 .init = pci_eg20t_init,
2784 .setup = pci_default_setup,
2785 },
2786 {
2787 .vendor = 0x10DB,
2788 .device = 0x8028,
2789 .subvendor = PCI_ANY_ID,
2790 .subdevice = PCI_ANY_ID,
2791 .init = pci_eg20t_init,
2792 .setup = pci_default_setup,
2793 },
2794 {
2795 .vendor = 0x10DB,
2796 .device = 0x8029,
2797 .subvendor = PCI_ANY_ID,
2798 .subdevice = PCI_ANY_ID,
2799 .init = pci_eg20t_init,
2800 .setup = pci_default_setup,
2801 },
2802 {
2803 .vendor = 0x10DB,
2804 .device = 0x800C,
2805 .subvendor = PCI_ANY_ID,
2806 .subdevice = PCI_ANY_ID,
2807 .init = pci_eg20t_init,
2808 .setup = pci_default_setup,
2809 },
2810 {
2811 .vendor = 0x10DB,
2812 .device = 0x800D,
2813 .subvendor = PCI_ANY_ID,
2814 .subdevice = PCI_ANY_ID,
2815 .init = pci_eg20t_init,
2816 .setup = pci_default_setup,
2817 },
2818 /*
2819 * Cronyx Omega PCI (PLX-chip based)
2820 */
2821 {
2822 .vendor = PCI_VENDOR_ID_PLX,
2823 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2824 .subvendor = PCI_ANY_ID,
2825 .subdevice = PCI_ANY_ID,
2826 .setup = pci_omegapci_setup,
2827 },
2828 /* WCH CH353 1S1P card (16550 clone) */
2829 {
2830 .vendor = PCI_VENDOR_ID_WCHCN,
2831 .device = PCI_DEVICE_ID_WCHCN_CH353_1S1P,
2832 .subvendor = PCI_ANY_ID,
2833 .subdevice = PCI_ANY_ID,
2834 .setup = pci_wch_ch353_setup,
2835 },
2836 /* WCH CH353 2S1P card (16550 clone) */
2837 {
2838 .vendor = PCI_VENDOR_ID_WCHCN,
2839 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1P,
2840 .subvendor = PCI_ANY_ID,
2841 .subdevice = PCI_ANY_ID,
2842 .setup = pci_wch_ch353_setup,
2843 },
2844 /* WCH CH353 4S card (16550 clone) */
2845 {
2846 .vendor = PCI_VENDOR_ID_WCHCN,
2847 .device = PCI_DEVICE_ID_WCHCN_CH353_4S,
2848 .subvendor = PCI_ANY_ID,
2849 .subdevice = PCI_ANY_ID,
2850 .setup = pci_wch_ch353_setup,
2851 },
2852 /* WCH CH353 2S1PF card (16550 clone) */
2853 {
2854 .vendor = PCI_VENDOR_ID_WCHCN,
2855 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
2856 .subvendor = PCI_ANY_ID,
2857 .subdevice = PCI_ANY_ID,
2858 .setup = pci_wch_ch353_setup,
2859 },
2860 /* WCH CH352 2S card (16550 clone) */
2861 {
2862 .vendor = PCI_VENDOR_ID_WCHCN,
2863 .device = PCI_DEVICE_ID_WCHCN_CH352_2S,
2864 .subvendor = PCI_ANY_ID,
2865 .subdevice = PCI_ANY_ID,
2866 .setup = pci_wch_ch353_setup,
2867 },
2868 /* WCH CH355 4S card (16550 clone) */
2869 {
2870 .vendor = PCI_VENDOR_ID_WCHCN,
2871 .device = PCI_DEVICE_ID_WCHCN_CH355_4S,
2872 .subvendor = PCI_ANY_ID,
2873 .subdevice = PCI_ANY_ID,
2874 .setup = pci_wch_ch355_setup,
2875 },
2876 /* WCH CH382 2S card (16850 clone) */
2877 {
2878 .vendor = PCI_VENDOR_ID_WCHIC,
2879 .device = PCI_DEVICE_ID_WCHIC_CH382_2S,
2880 .subvendor = PCI_ANY_ID,
2881 .subdevice = PCI_ANY_ID,
2882 .setup = pci_wch_ch38x_setup,
2883 },
2884 /* WCH CH382 2S1P card (16850 clone) */
2885 {
2886 .vendor = PCI_VENDOR_ID_WCHIC,
2887 .device = PCI_DEVICE_ID_WCHIC_CH382_2S1P,
2888 .subvendor = PCI_ANY_ID,
2889 .subdevice = PCI_ANY_ID,
2890 .setup = pci_wch_ch38x_setup,
2891 },
2892 /* WCH CH384 4S card (16850 clone) */
2893 {
2894 .vendor = PCI_VENDOR_ID_WCHIC,
2895 .device = PCI_DEVICE_ID_WCHIC_CH384_4S,
2896 .subvendor = PCI_ANY_ID,
2897 .subdevice = PCI_ANY_ID,
2898 .setup = pci_wch_ch38x_setup,
2899 },
2900 /* WCH CH384 8S card (16850 clone) */
2901 {
2902 .vendor = PCI_VENDOR_ID_WCHIC,
2903 .device = PCI_DEVICE_ID_WCHIC_CH384_8S,
2904 .subvendor = PCI_ANY_ID,
2905 .subdevice = PCI_ANY_ID,
2906 .init = pci_wch_ch38x_init,
2907 .exit = pci_wch_ch38x_exit,
2908 .setup = pci_wch_ch38x_setup,
2909 },
2910 /*
2911 * Broadcom TruManage (NetXtreme)
2912 */
2913 {
2914 .vendor = PCI_VENDOR_ID_BROADCOM,
2915 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2916 .subvendor = PCI_ANY_ID,
2917 .subdevice = PCI_ANY_ID,
2918 .setup = pci_brcm_trumanage_setup,
2919 },
2920 {
2921 .vendor = 0x1c29,
2922 .device = 0x1104,
2923 .subvendor = PCI_ANY_ID,
2924 .subdevice = PCI_ANY_ID,
2925 .setup = pci_fintek_setup,
2926 .init = pci_fintek_init,
2927 },
2928 {
2929 .vendor = 0x1c29,
2930 .device = 0x1108,
2931 .subvendor = PCI_ANY_ID,
2932 .subdevice = PCI_ANY_ID,
2933 .setup = pci_fintek_setup,
2934 .init = pci_fintek_init,
2935 },
2936 {
2937 .vendor = 0x1c29,
2938 .device = 0x1112,
2939 .subvendor = PCI_ANY_ID,
2940 .subdevice = PCI_ANY_ID,
2941 .setup = pci_fintek_setup,
2942 .init = pci_fintek_init,
2943 },
2944 /*
2945 * MOXA
2946 */
2947 {
2948 .vendor = PCI_VENDOR_ID_MOXA,
2949 .device = PCI_ANY_ID,
2950 .subvendor = PCI_ANY_ID,
2951 .subdevice = PCI_ANY_ID,
2952 .init = pci_moxa_init,
2953 .setup = pci_moxa_setup,
2954 },
2955 {
2956 .vendor = 0x1c29,
2957 .device = 0x1204,
2958 .subvendor = PCI_ANY_ID,
2959 .subdevice = PCI_ANY_ID,
2960 .setup = pci_fintek_f815xxa_setup,
2961 .init = pci_fintek_f815xxa_init,
2962 },
2963 {
2964 .vendor = 0x1c29,
2965 .device = 0x1208,
2966 .subvendor = PCI_ANY_ID,
2967 .subdevice = PCI_ANY_ID,
2968 .setup = pci_fintek_f815xxa_setup,
2969 .init = pci_fintek_f815xxa_init,
2970 },
2971 {
2972 .vendor = 0x1c29,
2973 .device = 0x1212,
2974 .subvendor = PCI_ANY_ID,
2975 .subdevice = PCI_ANY_ID,
2976 .setup = pci_fintek_f815xxa_setup,
2977 .init = pci_fintek_f815xxa_init,
2978 },
2979
2980 /*
2981 * Default "match everything" terminator entry
2982 */
2983 {
2984 .vendor = PCI_ANY_ID,
2985 .device = PCI_ANY_ID,
2986 .subvendor = PCI_ANY_ID,
2987 .subdevice = PCI_ANY_ID,
2988 .setup = pci_default_setup,
2989 }
2990};
2991
2992static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2993{
2994 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2995}
2996
2997static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2998{
2999 struct pci_serial_quirk *quirk;
3000
3001 for (quirk = pci_serial_quirks; ; quirk++)
3002 if (quirk_id_matches(quirk_id: quirk->vendor, dev_id: dev->vendor) &&
3003 quirk_id_matches(quirk_id: quirk->device, dev_id: dev->device) &&
3004 quirk_id_matches(quirk_id: quirk->subvendor, dev_id: dev->subsystem_vendor) &&
3005 quirk_id_matches(quirk_id: quirk->subdevice, dev_id: dev->subsystem_device))
3006 break;
3007 return quirk;
3008}
3009
3010/*
3011 * This is the configuration table for all of the PCI serial boards
3012 * which we support. It is directly indexed by the pci_board_num_t enum
3013 * value, which is encoded in the pci_device_id PCI probe table's
3014 * driver_data member.
3015 *
3016 * The makeup of these names are:
3017 * pbn_bn{_bt}_n_baud{_offsetinhex}
3018 *
3019 * bn = PCI BAR number
3020 * bt = Index using PCI BARs
3021 * n = number of serial ports
3022 * baud = baud rate
3023 * offsetinhex = offset for each sequential port (in hex)
3024 *
3025 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
3026 *
3027 * Please note: in theory if n = 1, _bt infix should make no difference.
3028 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
3029 */
3030enum pci_board_num_t {
3031 pbn_default = 0,
3032
3033 pbn_b0_1_115200,
3034 pbn_b0_2_115200,
3035 pbn_b0_4_115200,
3036 pbn_b0_5_115200,
3037 pbn_b0_8_115200,
3038
3039 pbn_b0_1_921600,
3040 pbn_b0_2_921600,
3041 pbn_b0_4_921600,
3042
3043 pbn_b0_2_1130000,
3044
3045 pbn_b0_4_1152000,
3046
3047 pbn_b0_4_1250000,
3048
3049 pbn_b0_2_1843200,
3050 pbn_b0_4_1843200,
3051
3052 pbn_b0_1_15625000,
3053
3054 pbn_b0_bt_1_115200,
3055 pbn_b0_bt_2_115200,
3056 pbn_b0_bt_4_115200,
3057 pbn_b0_bt_8_115200,
3058
3059 pbn_b0_bt_1_460800,
3060 pbn_b0_bt_2_460800,
3061 pbn_b0_bt_4_460800,
3062
3063 pbn_b0_bt_1_921600,
3064 pbn_b0_bt_2_921600,
3065 pbn_b0_bt_4_921600,
3066 pbn_b0_bt_8_921600,
3067
3068 pbn_b1_1_115200,
3069 pbn_b1_2_115200,
3070 pbn_b1_4_115200,
3071 pbn_b1_8_115200,
3072 pbn_b1_16_115200,
3073
3074 pbn_b1_1_921600,
3075 pbn_b1_2_921600,
3076 pbn_b1_4_921600,
3077 pbn_b1_8_921600,
3078
3079 pbn_b1_2_1250000,
3080
3081 pbn_b1_bt_1_115200,
3082 pbn_b1_bt_2_115200,
3083 pbn_b1_bt_4_115200,
3084
3085 pbn_b1_bt_2_921600,
3086
3087 pbn_b1_1_1382400,
3088 pbn_b1_2_1382400,
3089 pbn_b1_4_1382400,
3090 pbn_b1_8_1382400,
3091
3092 pbn_b2_1_115200,
3093 pbn_b2_2_115200,
3094 pbn_b2_4_115200,
3095 pbn_b2_8_115200,
3096
3097 pbn_b2_1_460800,
3098 pbn_b2_4_460800,
3099 pbn_b2_8_460800,
3100 pbn_b2_16_460800,
3101
3102 pbn_b2_1_921600,
3103 pbn_b2_4_921600,
3104 pbn_b2_8_921600,
3105
3106 pbn_b2_8_1152000,
3107
3108 pbn_b2_bt_1_115200,
3109 pbn_b2_bt_2_115200,
3110 pbn_b2_bt_4_115200,
3111
3112 pbn_b2_bt_2_921600,
3113 pbn_b2_bt_4_921600,
3114
3115 pbn_b3_2_115200,
3116 pbn_b3_4_115200,
3117 pbn_b3_8_115200,
3118
3119 pbn_b4_bt_2_921600,
3120 pbn_b4_bt_4_921600,
3121 pbn_b4_bt_8_921600,
3122
3123 /*
3124 * Board-specific versions.
3125 */
3126 pbn_panacom,
3127 pbn_panacom2,
3128 pbn_panacom4,
3129 pbn_plx_romulus,
3130 pbn_oxsemi,
3131 pbn_oxsemi_1_15625000,
3132 pbn_oxsemi_2_15625000,
3133 pbn_oxsemi_4_15625000,
3134 pbn_oxsemi_8_15625000,
3135 pbn_intel_i960,
3136 pbn_sgi_ioc3,
3137 pbn_computone_4,
3138 pbn_computone_6,
3139 pbn_computone_8,
3140 pbn_sbsxrsio,
3141 pbn_pasemi_1682M,
3142 pbn_ni8430_2,
3143 pbn_ni8430_4,
3144 pbn_ni8430_8,
3145 pbn_ni8430_16,
3146 pbn_ADDIDATA_PCIe_1_3906250,
3147 pbn_ADDIDATA_PCIe_2_3906250,
3148 pbn_ADDIDATA_PCIe_4_3906250,
3149 pbn_ADDIDATA_PCIe_8_3906250,
3150 pbn_ce4100_1_115200,
3151 pbn_omegapci,
3152 pbn_NETMOS9900_2s_115200,
3153 pbn_brcm_trumanage,
3154 pbn_fintek_4,
3155 pbn_fintek_8,
3156 pbn_fintek_12,
3157 pbn_fintek_F81504A,
3158 pbn_fintek_F81508A,
3159 pbn_fintek_F81512A,
3160 pbn_wch382_2,
3161 pbn_wch384_4,
3162 pbn_wch384_8,
3163 pbn_sunix_pci_1s,
3164 pbn_sunix_pci_2s,
3165 pbn_sunix_pci_4s,
3166 pbn_sunix_pci_8s,
3167 pbn_sunix_pci_16s,
3168 pbn_titan_1_4000000,
3169 pbn_titan_2_4000000,
3170 pbn_titan_4_4000000,
3171 pbn_titan_8_4000000,
3172 pbn_moxa_2,
3173 pbn_moxa_4,
3174 pbn_moxa_8,
3175};
3176
3177/*
3178 * uart_offset - the space between channels
3179 * reg_shift - describes how the UART registers are mapped
3180 * to PCI memory by the card.
3181 * For example IER register on SBS, Inc. PMC-OctPro is located at
3182 * offset 0x10 from the UART base, while UART_IER is defined as 1
3183 * in include/linux/serial_reg.h,
3184 * see first lines of serial_in() and serial_out() in 8250.c
3185*/
3186
3187static struct pciserial_board pci_boards[] = {
3188 [pbn_default] = {
3189 .flags = FL_BASE0,
3190 .num_ports = 1,
3191 .base_baud = 115200,
3192 .uart_offset = 8,
3193 },
3194 [pbn_b0_1_115200] = {
3195 .flags = FL_BASE0,
3196 .num_ports = 1,
3197 .base_baud = 115200,
3198 .uart_offset = 8,
3199 },
3200 [pbn_b0_2_115200] = {
3201 .flags = FL_BASE0,
3202 .num_ports = 2,
3203 .base_baud = 115200,
3204 .uart_offset = 8,
3205 },
3206 [pbn_b0_4_115200] = {
3207 .flags = FL_BASE0,
3208 .num_ports = 4,
3209 .base_baud = 115200,
3210 .uart_offset = 8,
3211 },
3212 [pbn_b0_5_115200] = {
3213 .flags = FL_BASE0,
3214 .num_ports = 5,
3215 .base_baud = 115200,
3216 .uart_offset = 8,
3217 },
3218 [pbn_b0_8_115200] = {
3219 .flags = FL_BASE0,
3220 .num_ports = 8,
3221 .base_baud = 115200,
3222 .uart_offset = 8,
3223 },
3224 [pbn_b0_1_921600] = {
3225 .flags = FL_BASE0,
3226 .num_ports = 1,
3227 .base_baud = 921600,
3228 .uart_offset = 8,
3229 },
3230 [pbn_b0_2_921600] = {
3231 .flags = FL_BASE0,
3232 .num_ports = 2,
3233 .base_baud = 921600,
3234 .uart_offset = 8,
3235 },
3236 [pbn_b0_4_921600] = {
3237 .flags = FL_BASE0,
3238 .num_ports = 4,
3239 .base_baud = 921600,
3240 .uart_offset = 8,
3241 },
3242
3243 [pbn_b0_2_1130000] = {
3244 .flags = FL_BASE0,
3245 .num_ports = 2,
3246 .base_baud = 1130000,
3247 .uart_offset = 8,
3248 },
3249
3250 [pbn_b0_4_1152000] = {
3251 .flags = FL_BASE0,
3252 .num_ports = 4,
3253 .base_baud = 1152000,
3254 .uart_offset = 8,
3255 },
3256
3257 [pbn_b0_4_1250000] = {
3258 .flags = FL_BASE0,
3259 .num_ports = 4,
3260 .base_baud = 1250000,
3261 .uart_offset = 8,
3262 },
3263
3264 [pbn_b0_2_1843200] = {
3265 .flags = FL_BASE0,
3266 .num_ports = 2,
3267 .base_baud = 1843200,
3268 .uart_offset = 8,
3269 },
3270 [pbn_b0_4_1843200] = {
3271 .flags = FL_BASE0,
3272 .num_ports = 4,
3273 .base_baud = 1843200,
3274 .uart_offset = 8,
3275 },
3276
3277 [pbn_b0_1_15625000] = {
3278 .flags = FL_BASE0,
3279 .num_ports = 1,
3280 .base_baud = 15625000,
3281 .uart_offset = 8,
3282 },
3283
3284 [pbn_b0_bt_1_115200] = {
3285 .flags = FL_BASE0|FL_BASE_BARS,
3286 .num_ports = 1,
3287 .base_baud = 115200,
3288 .uart_offset = 8,
3289 },
3290 [pbn_b0_bt_2_115200] = {
3291 .flags = FL_BASE0|FL_BASE_BARS,
3292 .num_ports = 2,
3293 .base_baud = 115200,
3294 .uart_offset = 8,
3295 },
3296 [pbn_b0_bt_4_115200] = {
3297 .flags = FL_BASE0|FL_BASE_BARS,
3298 .num_ports = 4,
3299 .base_baud = 115200,
3300 .uart_offset = 8,
3301 },
3302 [pbn_b0_bt_8_115200] = {
3303 .flags = FL_BASE0|FL_BASE_BARS,
3304 .num_ports = 8,
3305 .base_baud = 115200,
3306 .uart_offset = 8,
3307 },
3308
3309 [pbn_b0_bt_1_460800] = {
3310 .flags = FL_BASE0|FL_BASE_BARS,
3311 .num_ports = 1,
3312 .base_baud = 460800,
3313 .uart_offset = 8,
3314 },
3315 [pbn_b0_bt_2_460800] = {
3316 .flags = FL_BASE0|FL_BASE_BARS,
3317 .num_ports = 2,
3318 .base_baud = 460800,
3319 .uart_offset = 8,
3320 },
3321 [pbn_b0_bt_4_460800] = {
3322 .flags = FL_BASE0|FL_BASE_BARS,
3323 .num_ports = 4,
3324 .base_baud = 460800,
3325 .uart_offset = 8,
3326 },
3327
3328 [pbn_b0_bt_1_921600] = {
3329 .flags = FL_BASE0|FL_BASE_BARS,
3330 .num_ports = 1,
3331 .base_baud = 921600,
3332 .uart_offset = 8,
3333 },
3334 [pbn_b0_bt_2_921600] = {
3335 .flags = FL_BASE0|FL_BASE_BARS,
3336 .num_ports = 2,
3337 .base_baud = 921600,
3338 .uart_offset = 8,
3339 },
3340 [pbn_b0_bt_4_921600] = {
3341 .flags = FL_BASE0|FL_BASE_BARS,
3342 .num_ports = 4,
3343 .base_baud = 921600,
3344 .uart_offset = 8,
3345 },
3346 [pbn_b0_bt_8_921600] = {
3347 .flags = FL_BASE0|FL_BASE_BARS,
3348 .num_ports = 8,
3349 .base_baud = 921600,
3350 .uart_offset = 8,
3351 },
3352
3353 [pbn_b1_1_115200] = {
3354 .flags = FL_BASE1,
3355 .num_ports = 1,
3356 .base_baud = 115200,
3357 .uart_offset = 8,
3358 },
3359 [pbn_b1_2_115200] = {
3360 .flags = FL_BASE1,
3361 .num_ports = 2,
3362 .base_baud = 115200,
3363 .uart_offset = 8,
3364 },
3365 [pbn_b1_4_115200] = {
3366 .flags = FL_BASE1,
3367 .num_ports = 4,
3368 .base_baud = 115200,
3369 .uart_offset = 8,
3370 },
3371 [pbn_b1_8_115200] = {
3372 .flags = FL_BASE1,
3373 .num_ports = 8,
3374 .base_baud = 115200,
3375 .uart_offset = 8,
3376 },
3377 [pbn_b1_16_115200] = {
3378 .flags = FL_BASE1,
3379 .num_ports = 16,
3380 .base_baud = 115200,
3381 .uart_offset = 8,
3382 },
3383
3384 [pbn_b1_1_921600] = {
3385 .flags = FL_BASE1,
3386 .num_ports = 1,
3387 .base_baud = 921600,
3388 .uart_offset = 8,
3389 },
3390 [pbn_b1_2_921600] = {
3391 .flags = FL_BASE1,
3392 .num_ports = 2,
3393 .base_baud = 921600,
3394 .uart_offset = 8,
3395 },
3396 [pbn_b1_4_921600] = {
3397 .flags = FL_BASE1,
3398 .num_ports = 4,
3399 .base_baud = 921600,
3400 .uart_offset = 8,
3401 },
3402 [pbn_b1_8_921600] = {
3403 .flags = FL_BASE1,
3404 .num_ports = 8,
3405 .base_baud = 921600,
3406 .uart_offset = 8,
3407 },
3408 [pbn_b1_2_1250000] = {
3409 .flags = FL_BASE1,
3410 .num_ports = 2,
3411 .base_baud = 1250000,
3412 .uart_offset = 8,
3413 },
3414
3415 [pbn_b1_bt_1_115200] = {
3416 .flags = FL_BASE1|FL_BASE_BARS,
3417 .num_ports = 1,
3418 .base_baud = 115200,
3419 .uart_offset = 8,
3420 },
3421 [pbn_b1_bt_2_115200] = {
3422 .flags = FL_BASE1|FL_BASE_BARS,
3423 .num_ports = 2,
3424 .base_baud = 115200,
3425 .uart_offset = 8,
3426 },
3427 [pbn_b1_bt_4_115200] = {
3428 .flags = FL_BASE1|FL_BASE_BARS,
3429 .num_ports = 4,
3430 .base_baud = 115200,
3431 .uart_offset = 8,
3432 },
3433
3434 [pbn_b1_bt_2_921600] = {
3435 .flags = FL_BASE1|FL_BASE_BARS,
3436 .num_ports = 2,
3437 .base_baud = 921600,
3438 .uart_offset = 8,
3439 },
3440
3441 [pbn_b1_1_1382400] = {
3442 .flags = FL_BASE1,
3443 .num_ports = 1,
3444 .base_baud = 1382400,
3445 .uart_offset = 8,
3446 },
3447 [pbn_b1_2_1382400] = {
3448 .flags = FL_BASE1,
3449 .num_ports = 2,
3450 .base_baud = 1382400,
3451 .uart_offset = 8,
3452 },
3453 [pbn_b1_4_1382400] = {
3454 .flags = FL_BASE1,
3455 .num_ports = 4,
3456 .base_baud = 1382400,
3457 .uart_offset = 8,
3458 },
3459 [pbn_b1_8_1382400] = {
3460 .flags = FL_BASE1,
3461 .num_ports = 8,
3462 .base_baud = 1382400,
3463 .uart_offset = 8,
3464 },
3465
3466 [pbn_b2_1_115200] = {
3467 .flags = FL_BASE2,
3468 .num_ports = 1,
3469 .base_baud = 115200,
3470 .uart_offset = 8,
3471 },
3472 [pbn_b2_2_115200] = {
3473 .flags = FL_BASE2,
3474 .num_ports = 2,
3475 .base_baud = 115200,
3476 .uart_offset = 8,
3477 },
3478 [pbn_b2_4_115200] = {
3479 .flags = FL_BASE2,
3480 .num_ports = 4,
3481 .base_baud = 115200,
3482 .uart_offset = 8,
3483 },
3484 [pbn_b2_8_115200] = {
3485 .flags = FL_BASE2,
3486 .num_ports = 8,
3487 .base_baud = 115200,
3488 .uart_offset = 8,
3489 },
3490
3491 [pbn_b2_1_460800] = {
3492 .flags = FL_BASE2,
3493 .num_ports = 1,
3494 .base_baud = 460800,
3495 .uart_offset = 8,
3496 },
3497 [pbn_b2_4_460800] = {
3498 .flags = FL_BASE2,
3499 .num_ports = 4,
3500 .base_baud = 460800,
3501 .uart_offset = 8,
3502 },
3503 [pbn_b2_8_460800] = {
3504 .flags = FL_BASE2,
3505 .num_ports = 8,
3506 .base_baud = 460800,
3507 .uart_offset = 8,
3508 },
3509 [pbn_b2_16_460800] = {
3510 .flags = FL_BASE2,
3511 .num_ports = 16,
3512 .base_baud = 460800,
3513 .uart_offset = 8,
3514 },
3515
3516 [pbn_b2_1_921600] = {
3517 .flags = FL_BASE2,
3518 .num_ports = 1,
3519 .base_baud = 921600,
3520 .uart_offset = 8,
3521 },
3522 [pbn_b2_4_921600] = {
3523 .flags = FL_BASE2,
3524 .num_ports = 4,
3525 .base_baud = 921600,
3526 .uart_offset = 8,
3527 },
3528 [pbn_b2_8_921600] = {
3529 .flags = FL_BASE2,
3530 .num_ports = 8,
3531 .base_baud = 921600,
3532 .uart_offset = 8,
3533 },
3534
3535 [pbn_b2_8_1152000] = {
3536 .flags = FL_BASE2,
3537 .num_ports = 8,
3538 .base_baud = 1152000,
3539 .uart_offset = 8,
3540 },
3541
3542 [pbn_b2_bt_1_115200] = {
3543 .flags = FL_BASE2|FL_BASE_BARS,
3544 .num_ports = 1,
3545 .base_baud = 115200,
3546 .uart_offset = 8,
3547 },
3548 [pbn_b2_bt_2_115200] = {
3549 .flags = FL_BASE2|FL_BASE_BARS,
3550 .num_ports = 2,
3551 .base_baud = 115200,
3552 .uart_offset = 8,
3553 },
3554 [pbn_b2_bt_4_115200] = {
3555 .flags = FL_BASE2|FL_BASE_BARS,
3556 .num_ports = 4,
3557 .base_baud = 115200,
3558 .uart_offset = 8,
3559 },
3560
3561 [pbn_b2_bt_2_921600] = {
3562 .flags = FL_BASE2|FL_BASE_BARS,
3563 .num_ports = 2,
3564 .base_baud = 921600,
3565 .uart_offset = 8,
3566 },
3567 [pbn_b2_bt_4_921600] = {
3568 .flags = FL_BASE2|FL_BASE_BARS,
3569 .num_ports = 4,
3570 .base_baud = 921600,
3571 .uart_offset = 8,
3572 },
3573
3574 [pbn_b3_2_115200] = {
3575 .flags = FL_BASE3,
3576 .num_ports = 2,
3577 .base_baud = 115200,
3578 .uart_offset = 8,
3579 },
3580 [pbn_b3_4_115200] = {
3581 .flags = FL_BASE3,
3582 .num_ports = 4,
3583 .base_baud = 115200,
3584 .uart_offset = 8,
3585 },
3586 [pbn_b3_8_115200] = {
3587 .flags = FL_BASE3,
3588 .num_ports = 8,
3589 .base_baud = 115200,
3590 .uart_offset = 8,
3591 },
3592
3593 [pbn_b4_bt_2_921600] = {
3594 .flags = FL_BASE4,
3595 .num_ports = 2,
3596 .base_baud = 921600,
3597 .uart_offset = 8,
3598 },
3599 [pbn_b4_bt_4_921600] = {
3600 .flags = FL_BASE4,
3601 .num_ports = 4,
3602 .base_baud = 921600,
3603 .uart_offset = 8,
3604 },
3605 [pbn_b4_bt_8_921600] = {
3606 .flags = FL_BASE4,
3607 .num_ports = 8,
3608 .base_baud = 921600,
3609 .uart_offset = 8,
3610 },
3611
3612 /*
3613 * Entries following this are board-specific.
3614 */
3615
3616 /*
3617 * Panacom - IOMEM
3618 */
3619 [pbn_panacom] = {
3620 .flags = FL_BASE2,
3621 .num_ports = 2,
3622 .base_baud = 921600,
3623 .uart_offset = 0x400,
3624 .reg_shift = 7,
3625 },
3626 [pbn_panacom2] = {
3627 .flags = FL_BASE2|FL_BASE_BARS,
3628 .num_ports = 2,
3629 .base_baud = 921600,
3630 .uart_offset = 0x400,
3631 .reg_shift = 7,
3632 },
3633 [pbn_panacom4] = {
3634 .flags = FL_BASE2|FL_BASE_BARS,
3635 .num_ports = 4,
3636 .base_baud = 921600,
3637 .uart_offset = 0x400,
3638 .reg_shift = 7,
3639 },
3640
3641 /* I think this entry is broken - the first_offset looks wrong --rmk */
3642 [pbn_plx_romulus] = {
3643 .flags = FL_BASE2,
3644 .num_ports = 4,
3645 .base_baud = 921600,
3646 .uart_offset = 8 << 2,
3647 .reg_shift = 2,
3648 .first_offset = 0x03,
3649 },
3650
3651 /*
3652 * This board uses the size of PCI Base region 0 to
3653 * signal now many ports are available
3654 */
3655 [pbn_oxsemi] = {
3656 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3657 .num_ports = 32,
3658 .base_baud = 115200,
3659 .uart_offset = 8,
3660 },
3661 [pbn_oxsemi_1_15625000] = {
3662 .flags = FL_BASE0,
3663 .num_ports = 1,
3664 .base_baud = 15625000,
3665 .uart_offset = 0x200,
3666 .first_offset = 0x1000,
3667 },
3668 [pbn_oxsemi_2_15625000] = {
3669 .flags = FL_BASE0,
3670 .num_ports = 2,
3671 .base_baud = 15625000,
3672 .uart_offset = 0x200,
3673 .first_offset = 0x1000,
3674 },
3675 [pbn_oxsemi_4_15625000] = {
3676 .flags = FL_BASE0,
3677 .num_ports = 4,
3678 .base_baud = 15625000,
3679 .uart_offset = 0x200,
3680 .first_offset = 0x1000,
3681 },
3682 [pbn_oxsemi_8_15625000] = {
3683 .flags = FL_BASE0,
3684 .num_ports = 8,
3685 .base_baud = 15625000,
3686 .uart_offset = 0x200,
3687 .first_offset = 0x1000,
3688 },
3689
3690
3691 /*
3692 * EKF addition for i960 Boards form EKF with serial port.
3693 * Max 256 ports.
3694 */
3695 [pbn_intel_i960] = {
3696 .flags = FL_BASE0,
3697 .num_ports = 32,
3698 .base_baud = 921600,
3699 .uart_offset = 8 << 2,
3700 .reg_shift = 2,
3701 .first_offset = 0x10000,
3702 },
3703 [pbn_sgi_ioc3] = {
3704 .flags = FL_BASE0|FL_NOIRQ,
3705 .num_ports = 1,
3706 .base_baud = 458333,
3707 .uart_offset = 8,
3708 .reg_shift = 0,
3709 .first_offset = 0x20178,
3710 },
3711
3712 /*
3713 * Computone - uses IOMEM.
3714 */
3715 [pbn_computone_4] = {
3716 .flags = FL_BASE0,
3717 .num_ports = 4,
3718 .base_baud = 921600,
3719 .uart_offset = 0x40,
3720 .reg_shift = 2,
3721 .first_offset = 0x200,
3722 },
3723 [pbn_computone_6] = {
3724 .flags = FL_BASE0,
3725 .num_ports = 6,
3726 .base_baud = 921600,
3727 .uart_offset = 0x40,
3728 .reg_shift = 2,
3729 .first_offset = 0x200,
3730 },
3731 [pbn_computone_8] = {
3732 .flags = FL_BASE0,
3733 .num_ports = 8,
3734 .base_baud = 921600,
3735 .uart_offset = 0x40,
3736 .reg_shift = 2,
3737 .first_offset = 0x200,
3738 },
3739 [pbn_sbsxrsio] = {
3740 .flags = FL_BASE0,
3741 .num_ports = 8,
3742 .base_baud = 460800,
3743 .uart_offset = 256,
3744 .reg_shift = 4,
3745 },
3746 /*
3747 * PA Semi PWRficient PA6T-1682M on-chip UART
3748 */
3749 [pbn_pasemi_1682M] = {
3750 .flags = FL_BASE0,
3751 .num_ports = 1,
3752 .base_baud = 8333333,
3753 },
3754 /*
3755 * National Instruments 843x
3756 */
3757 [pbn_ni8430_16] = {
3758 .flags = FL_BASE0,
3759 .num_ports = 16,
3760 .base_baud = 3686400,
3761 .uart_offset = 0x10,
3762 .first_offset = 0x800,
3763 },
3764 [pbn_ni8430_8] = {
3765 .flags = FL_BASE0,
3766 .num_ports = 8,
3767 .base_baud = 3686400,
3768 .uart_offset = 0x10,
3769 .first_offset = 0x800,
3770 },
3771 [pbn_ni8430_4] = {
3772 .flags = FL_BASE0,
3773 .num_ports = 4,
3774 .base_baud = 3686400,
3775 .uart_offset = 0x10,
3776 .first_offset = 0x800,
3777 },
3778 [pbn_ni8430_2] = {
3779 .flags = FL_BASE0,
3780 .num_ports = 2,
3781 .base_baud = 3686400,
3782 .uart_offset = 0x10,
3783 .first_offset = 0x800,
3784 },
3785 /*
3786 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3787 */
3788 [pbn_ADDIDATA_PCIe_1_3906250] = {
3789 .flags = FL_BASE0,
3790 .num_ports = 1,
3791 .base_baud = 3906250,
3792 .uart_offset = 0x200,
3793 .first_offset = 0x1000,
3794 },
3795 [pbn_ADDIDATA_PCIe_2_3906250] = {
3796 .flags = FL_BASE0,
3797 .num_ports = 2,
3798 .base_baud = 3906250,
3799 .uart_offset = 0x200,
3800 .first_offset = 0x1000,
3801 },
3802 [pbn_ADDIDATA_PCIe_4_3906250] = {
3803 .flags = FL_BASE0,
3804 .num_ports = 4,
3805 .base_baud = 3906250,
3806 .uart_offset = 0x200,
3807 .first_offset = 0x1000,
3808 },
3809 [pbn_ADDIDATA_PCIe_8_3906250] = {
3810 .flags = FL_BASE0,
3811 .num_ports = 8,
3812 .base_baud = 3906250,
3813 .uart_offset = 0x200,
3814 .first_offset = 0x1000,
3815 },
3816 [pbn_ce4100_1_115200] = {
3817 .flags = FL_BASE_BARS,
3818 .num_ports = 2,
3819 .base_baud = 921600,
3820 .reg_shift = 2,
3821 },
3822 [pbn_omegapci] = {
3823 .flags = FL_BASE0,
3824 .num_ports = 8,
3825 .base_baud = 115200,
3826 .uart_offset = 0x200,
3827 },
3828 [pbn_NETMOS9900_2s_115200] = {
3829 .flags = FL_BASE0,
3830 .num_ports = 2,
3831 .base_baud = 115200,
3832 },
3833 [pbn_brcm_trumanage] = {
3834 .flags = FL_BASE0,
3835 .num_ports = 1,
3836 .reg_shift = 2,
3837 .base_baud = 115200,
3838 },
3839 [pbn_fintek_4] = {
3840 .num_ports = 4,
3841 .uart_offset = 8,
3842 .base_baud = 115200,
3843 .first_offset = 0x40,
3844 },
3845 [pbn_fintek_8] = {
3846 .num_ports = 8,
3847 .uart_offset = 8,
3848 .base_baud = 115200,
3849 .first_offset = 0x40,
3850 },
3851 [pbn_fintek_12] = {
3852 .num_ports = 12,
3853 .uart_offset = 8,
3854 .base_baud = 115200,
3855 .first_offset = 0x40,
3856 },
3857 [pbn_fintek_F81504A] = {
3858 .num_ports = 4,
3859 .uart_offset = 8,
3860 .base_baud = 115200,
3861 },
3862 [pbn_fintek_F81508A] = {
3863 .num_ports = 8,
3864 .uart_offset = 8,
3865 .base_baud = 115200,
3866 },
3867 [pbn_fintek_F81512A] = {
3868 .num_ports = 12,
3869 .uart_offset = 8,
3870 .base_baud = 115200,
3871 },
3872 [pbn_wch382_2] = {
3873 .flags = FL_BASE0,
3874 .num_ports = 2,
3875 .base_baud = 115200,
3876 .uart_offset = 8,
3877 .first_offset = 0xC0,
3878 },
3879 [pbn_wch384_4] = {
3880 .flags = FL_BASE0,
3881 .num_ports = 4,
3882 .base_baud = 115200,
3883 .uart_offset = 8,
3884 .first_offset = 0xC0,
3885 },
3886 [pbn_wch384_8] = {
3887 .flags = FL_BASE0,
3888 .num_ports = 8,
3889 .base_baud = 115200,
3890 .uart_offset = 8,
3891 .first_offset = 0x00,
3892 },
3893 [pbn_sunix_pci_1s] = {
3894 .num_ports = 1,
3895 .base_baud = 921600,
3896 .uart_offset = 0x8,
3897 },
3898 [pbn_sunix_pci_2s] = {
3899 .num_ports = 2,
3900 .base_baud = 921600,
3901 .uart_offset = 0x8,
3902 },
3903 [pbn_sunix_pci_4s] = {
3904 .num_ports = 4,
3905 .base_baud = 921600,
3906 .uart_offset = 0x8,
3907 },
3908 [pbn_sunix_pci_8s] = {
3909 .num_ports = 8,
3910 .base_baud = 921600,
3911 .uart_offset = 0x8,
3912 },
3913 [pbn_sunix_pci_16s] = {
3914 .num_ports = 16,
3915 .base_baud = 921600,
3916 .uart_offset = 0x8,
3917 },
3918 [pbn_titan_1_4000000] = {
3919 .flags = FL_BASE0,
3920 .num_ports = 1,
3921 .base_baud = 4000000,
3922 .uart_offset = 0x200,
3923 .first_offset = 0x1000,
3924 },
3925 [pbn_titan_2_4000000] = {
3926 .flags = FL_BASE0,
3927 .num_ports = 2,
3928 .base_baud = 4000000,
3929 .uart_offset = 0x200,
3930 .first_offset = 0x1000,
3931 },
3932 [pbn_titan_4_4000000] = {
3933 .flags = FL_BASE0,
3934 .num_ports = 4,
3935 .base_baud = 4000000,
3936 .uart_offset = 0x200,
3937 .first_offset = 0x1000,
3938 },
3939 [pbn_titan_8_4000000] = {
3940 .flags = FL_BASE0,
3941 .num_ports = 8,
3942 .base_baud = 4000000,
3943 .uart_offset = 0x200,
3944 .first_offset = 0x1000,
3945 },
3946 [pbn_moxa_2] = {
3947 .flags = FL_BASE1,
3948 .num_ports = 2,
3949 .base_baud = 921600,
3950 .uart_offset = 0x200,
3951 },
3952 [pbn_moxa_4] = {
3953 .flags = FL_BASE1,
3954 .num_ports = 4,
3955 .base_baud = 921600,
3956 .uart_offset = 0x200,
3957 },
3958 [pbn_moxa_8] = {
3959 .flags = FL_BASE1,
3960 .num_ports = 8,
3961 .base_baud = 921600,
3962 .uart_offset = 0x200,
3963 },
3964};
3965
3966#define REPORT_CONFIG(option) \
3967 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3968#define REPORT_8250_CONFIG(option) \
3969 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3970 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3971
3972static const struct pci_device_id blacklist[] = {
3973 /* softmodems */
3974 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3975 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3976 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3977
3978 /* multi-io cards handled by parport_serial */
3979 /* WCH CH353 2S1P */
3980 { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), },
3981 /* WCH CH353 1S1P */
3982 { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), },
3983 /* WCH CH382 2S1P */
3984 { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), },
3985
3986 /* Intel platforms with MID UART */
3987 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
3988 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
3989 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
3990 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
3991 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
3992 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
3993
3994 /* Intel platforms with DesignWare UART */
3995 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
3996 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
3997 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
3998 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
3999 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
4000 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
4001 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
4002 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
4003 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
4004 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
4005 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
4006 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
4007 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
4008
4009 /* Exar devices */
4010 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4011 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4012
4013 /* Pericom devices */
4014 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4015 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4016
4017 /* End of the black list */
4018 { }
4019};
4020
4021static int serial_pci_is_class_communication(struct pci_dev *dev)
4022{
4023 /*
4024 * If it is not a communications device or the programming
4025 * interface is greater than 6, give up.
4026 */
4027 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
4028 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
4029 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
4030 (dev->class & 0xff) > 6)
4031 return -ENODEV;
4032
4033 return 0;
4034}
4035
4036/*
4037 * Given a complete unknown PCI device, try to use some heuristics to
4038 * guess what the configuration might be, based on the pitiful PCI
4039 * serial specs. Returns 0 on success, -ENODEV on failure.
4040 */
4041static int
4042serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
4043{
4044 int num_iomem, num_port, first_port = -1, i;
4045 int rc;
4046
4047 rc = serial_pci_is_class_communication(dev);
4048 if (rc)
4049 return rc;
4050
4051 /*
4052 * Should we try to make guesses for multiport serial devices later?
4053 */
4054 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
4055 return -ENODEV;
4056
4057 num_iomem = num_port = 0;
4058 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4059 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4060 num_port++;
4061 if (first_port == -1)
4062 first_port = i;
4063 }
4064 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4065 num_iomem++;
4066 }
4067
4068 /*
4069 * If there is 1 or 0 iomem regions, and exactly one port,
4070 * use it. We guess the number of ports based on the IO
4071 * region size.
4072 */
4073 if (num_iomem <= 1 && num_port == 1) {
4074 board->flags = first_port;
4075 board->num_ports = pci_resource_len(dev, first_port) / 8;
4076 return 0;
4077 }
4078
4079 /*
4080 * Now guess if we've got a board which indexes by BARs.
4081 * Each IO BAR should be 8 bytes, and they should follow
4082 * consecutively.
4083 */
4084 first_port = -1;
4085 num_port = 0;
4086 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4087 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4088 pci_resource_len(dev, i) == 8 &&
4089 (first_port == -1 || (first_port + num_port) == i)) {
4090 num_port++;
4091 if (first_port == -1)
4092 first_port = i;
4093 }
4094 }
4095
4096 if (num_port > 1) {
4097 board->flags = first_port | FL_BASE_BARS;
4098 board->num_ports = num_port;
4099 return 0;
4100 }
4101
4102 return -ENODEV;
4103}
4104
4105static inline int
4106serial_pci_matches(const struct pciserial_board *board,
4107 const struct pciserial_board *guessed)
4108{
4109 return
4110 board->num_ports == guessed->num_ports &&
4111 board->base_baud == guessed->base_baud &&
4112 board->uart_offset == guessed->uart_offset &&
4113 board->reg_shift == guessed->reg_shift &&
4114 board->first_offset == guessed->first_offset;
4115}
4116
4117struct serial_private *
4118pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4119{
4120 struct uart_8250_port uart;
4121 struct serial_private *priv;
4122 struct pci_serial_quirk *quirk;
4123 int rc, nr_ports, i;
4124
4125 nr_ports = board->num_ports;
4126
4127 /*
4128 * Find an init and setup quirks.
4129 */
4130 quirk = find_quirk(dev);
4131
4132 /*
4133 * Run the new-style initialization function.
4134 * The initialization function returns:
4135 * <0 - error
4136 * 0 - use board->num_ports
4137 * >0 - number of ports
4138 */
4139 if (quirk->init) {
4140 rc = quirk->init(dev);
4141 if (rc < 0) {
4142 priv = ERR_PTR(error: rc);
4143 goto err_out;
4144 }
4145 if (rc)
4146 nr_ports = rc;
4147 }
4148
4149 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL);
4150 if (!priv) {
4151 priv = ERR_PTR(error: -ENOMEM);
4152 goto err_deinit;
4153 }
4154
4155 priv->dev = dev;
4156 priv->quirk = quirk;
4157
4158 memset(s: &uart, c: 0, n: sizeof(uart));
4159 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4160 uart.port.uartclk = board->base_baud * 16;
4161
4162 if (board->flags & FL_NOIRQ) {
4163 uart.port.irq = 0;
4164 } else {
4165 if (pci_match_id(ids: pci_use_msi, dev)) {
4166 pci_dbg(dev, "Using MSI(-X) interrupts\n");
4167 pci_set_master(dev);
4168 uart.port.flags &= ~UPF_SHARE_IRQ;
4169 rc = pci_alloc_irq_vectors(dev, min_vecs: 1, max_vecs: 1, PCI_IRQ_ALL_TYPES);
4170 } else {
4171 pci_dbg(dev, "Using legacy interrupts\n");
4172 rc = pci_alloc_irq_vectors(dev, min_vecs: 1, max_vecs: 1, PCI_IRQ_INTX);
4173 }
4174 if (rc < 0) {
4175 kfree(objp: priv);
4176 priv = ERR_PTR(error: rc);
4177 goto err_deinit;
4178 }
4179
4180 uart.port.irq = pci_irq_vector(dev, nr: 0);
4181 }
4182
4183 uart.port.dev = &dev->dev;
4184
4185 for (i = 0; i < nr_ports; i++) {
4186 if (quirk->setup(priv, board, &uart, i))
4187 break;
4188
4189 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4190 uart.port.iobase, uart.port.irq, uart.port.iotype);
4191
4192 priv->line[i] = serial8250_register_8250_port(&uart);
4193 if (priv->line[i] < 0) {
4194 pci_err(dev,
4195 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4196 uart.port.iobase, uart.port.irq,
4197 uart.port.iotype, priv->line[i]);
4198 break;
4199 }
4200 }
4201 priv->nr = i;
4202 priv->board = board;
4203 return priv;
4204
4205err_deinit:
4206 if (quirk->exit)
4207 quirk->exit(dev);
4208err_out:
4209 return priv;
4210}
4211EXPORT_SYMBOL_GPL(pciserial_init_ports);
4212
4213static void pciserial_detach_ports(struct serial_private *priv)
4214{
4215 struct pci_serial_quirk *quirk;
4216 int i;
4217
4218 for (i = 0; i < priv->nr; i++)
4219 serial8250_unregister_port(line: priv->line[i]);
4220
4221 /*
4222 * Find the exit quirks.
4223 */
4224 quirk = find_quirk(dev: priv->dev);
4225 if (quirk->exit)
4226 quirk->exit(priv->dev);
4227}
4228
4229void pciserial_remove_ports(struct serial_private *priv)
4230{
4231 pciserial_detach_ports(priv);
4232 kfree(objp: priv);
4233}
4234EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4235
4236void pciserial_suspend_ports(struct serial_private *priv)
4237{
4238 int i;
4239
4240 for (i = 0; i < priv->nr; i++)
4241 if (priv->line[i] >= 0)
4242 serial8250_suspend_port(line: priv->line[i]);
4243
4244 /*
4245 * Ensure that every init quirk is properly torn down
4246 */
4247 if (priv->quirk->exit)
4248 priv->quirk->exit(priv->dev);
4249}
4250EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4251
4252void pciserial_resume_ports(struct serial_private *priv)
4253{
4254 int i;
4255
4256 /*
4257 * Ensure that the board is correctly configured.
4258 */
4259 if (priv->quirk->init)
4260 priv->quirk->init(priv->dev);
4261
4262 for (i = 0; i < priv->nr; i++)
4263 if (priv->line[i] >= 0)
4264 serial8250_resume_port(line: priv->line[i]);
4265}
4266EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4267
4268/*
4269 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4270 * to the arrangement of serial ports on a PCI card.
4271 */
4272static int
4273pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4274{
4275 struct pci_serial_quirk *quirk;
4276 struct serial_private *priv;
4277 const struct pciserial_board *board;
4278 const struct pci_device_id *exclude;
4279 struct pciserial_board tmp;
4280 int rc;
4281
4282 quirk = find_quirk(dev);
4283 if (quirk->probe) {
4284 rc = quirk->probe(dev);
4285 if (rc)
4286 return rc;
4287 }
4288
4289 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4290 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4291 return -EINVAL;
4292 }
4293
4294 board = &pci_boards[ent->driver_data];
4295
4296 exclude = pci_match_id(ids: blacklist, dev);
4297 if (exclude) {
4298 if (exclude->driver_data)
4299 pci_warn(dev, "ignoring port, enable %s to handle\n",
4300 (const char *)exclude->driver_data);
4301 return -ENODEV;
4302 }
4303
4304 rc = pcim_enable_device(pdev: dev);
4305 pci_save_state(dev);
4306 if (rc)
4307 return rc;
4308
4309 if (ent->driver_data == pbn_default) {
4310 /*
4311 * Use a copy of the pci_board entry for this;
4312 * avoid changing entries in the table.
4313 */
4314 memcpy(to: &tmp, from: board, len: sizeof(struct pciserial_board));
4315 board = &tmp;
4316
4317 /*
4318 * We matched one of our class entries. Try to
4319 * determine the parameters of this board.
4320 */
4321 rc = serial_pci_guess_board(dev, board: &tmp);
4322 if (rc)
4323 return rc;
4324 } else {
4325 /*
4326 * We matched an explicit entry. If we are able to
4327 * detect this boards settings with our heuristic,
4328 * then we no longer need this entry.
4329 */
4330 memcpy(to: &tmp, from: &pci_boards[pbn_default],
4331 len: sizeof(struct pciserial_board));
4332 rc = serial_pci_guess_board(dev, board: &tmp);
4333 if (rc == 0 && serial_pci_matches(board, guessed: &tmp))
4334 moan_device(str: "Redundant entry in serial pci_table.",
4335 dev);
4336 }
4337
4338 priv = pciserial_init_ports(dev, board);
4339 if (IS_ERR(ptr: priv))
4340 return PTR_ERR(ptr: priv);
4341
4342 pci_set_drvdata(pdev: dev, data: priv);
4343 return 0;
4344}
4345
4346static void pciserial_remove_one(struct pci_dev *dev)
4347{
4348 struct serial_private *priv = pci_get_drvdata(pdev: dev);
4349
4350 pciserial_remove_ports(priv);
4351}
4352
4353#ifdef CONFIG_PM_SLEEP
4354static int pciserial_suspend_one(struct device *dev)
4355{
4356 struct serial_private *priv = dev_get_drvdata(dev);
4357
4358 if (priv)
4359 pciserial_suspend_ports(priv);
4360
4361 return 0;
4362}
4363
4364static int pciserial_resume_one(struct device *dev)
4365{
4366 struct pci_dev *pdev = to_pci_dev(dev);
4367 struct serial_private *priv = pci_get_drvdata(pdev);
4368 int err;
4369
4370 if (priv) {
4371 /*
4372 * The device may have been disabled. Re-enable it.
4373 */
4374 err = pci_enable_device(dev: pdev);
4375 /* FIXME: We cannot simply error out here */
4376 if (err)
4377 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4378 pciserial_resume_ports(priv);
4379 }
4380 return 0;
4381}
4382#endif
4383
4384static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4385 pciserial_resume_one);
4386
4387static const struct pci_device_id serial_pci_tbl[] = {
4388 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4389 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4390 pbn_b0_4_921600 },
4391 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4392 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4393 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4394 pbn_b2_8_921600 },
4395 /* Advantech also use 0x3618 and 0xf618 */
4396 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4397 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4398 pbn_b0_4_921600 },
4399 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4400 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4401 pbn_b0_4_921600 },
4402 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4403 PCI_SUBVENDOR_ID_CONNECT_TECH,
4404 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4405 pbn_b1_8_1382400 },
4406 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4407 PCI_SUBVENDOR_ID_CONNECT_TECH,
4408 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4409 pbn_b1_4_1382400 },
4410 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4411 PCI_SUBVENDOR_ID_CONNECT_TECH,
4412 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4413 pbn_b1_2_1382400 },
4414 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4415 PCI_SUBVENDOR_ID_CONNECT_TECH,
4416 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4417 pbn_b1_8_1382400 },
4418 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4419 PCI_SUBVENDOR_ID_CONNECT_TECH,
4420 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4421 pbn_b1_4_1382400 },
4422 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4423 PCI_SUBVENDOR_ID_CONNECT_TECH,
4424 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4425 pbn_b1_2_1382400 },
4426 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4427 PCI_SUBVENDOR_ID_CONNECT_TECH,
4428 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4429 pbn_b1_8_921600 },
4430 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4431 PCI_SUBVENDOR_ID_CONNECT_TECH,
4432 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4433 pbn_b1_8_921600 },
4434 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4435 PCI_SUBVENDOR_ID_CONNECT_TECH,
4436 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4437 pbn_b1_4_921600 },
4438 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4439 PCI_SUBVENDOR_ID_CONNECT_TECH,
4440 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4441 pbn_b1_4_921600 },
4442 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4443 PCI_SUBVENDOR_ID_CONNECT_TECH,
4444 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4445 pbn_b1_2_921600 },
4446 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4447 PCI_SUBVENDOR_ID_CONNECT_TECH,
4448 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4449 pbn_b1_8_921600 },
4450 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4451 PCI_SUBVENDOR_ID_CONNECT_TECH,
4452 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4453 pbn_b1_8_921600 },
4454 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4455 PCI_SUBVENDOR_ID_CONNECT_TECH,
4456 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4457 pbn_b1_4_921600 },
4458 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4459 PCI_SUBVENDOR_ID_CONNECT_TECH,
4460 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4461 pbn_b1_2_1250000 },
4462 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4463 PCI_SUBVENDOR_ID_CONNECT_TECH,
4464 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4465 pbn_b0_2_1843200 },
4466 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4467 PCI_SUBVENDOR_ID_CONNECT_TECH,
4468 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4469 pbn_b0_4_1843200 },
4470 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4471 PCI_VENDOR_ID_AFAVLAB,
4472 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4473 pbn_b0_4_1152000 },
4474 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4476 pbn_b2_bt_1_115200 },
4477 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479 pbn_b2_bt_2_115200 },
4480 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482 pbn_b2_bt_4_115200 },
4483 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485 pbn_b2_bt_2_115200 },
4486 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4488 pbn_b2_bt_4_115200 },
4489 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 pbn_b2_8_115200 },
4492 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_b2_8_460800 },
4495 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_b2_8_115200 },
4498
4499 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501 pbn_b2_bt_2_115200 },
4502 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 pbn_b2_bt_2_921600 },
4505 /*
4506 * VScom SPCOM800, from sl@s.pl
4507 */
4508 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_b2_8_921600 },
4511 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 pbn_b2_4_921600 },
4514 /* Unknown card - subdevice 0x1584 */
4515 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4516 PCI_VENDOR_ID_PLX,
4517 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4518 pbn_b2_4_115200 },
4519 /* Unknown card - subdevice 0x1588 */
4520 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4521 PCI_VENDOR_ID_PLX,
4522 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4523 pbn_b2_8_115200 },
4524 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4525 PCI_SUBVENDOR_ID_KEYSPAN,
4526 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4527 pbn_panacom },
4528 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 pbn_panacom4 },
4531 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_panacom2 },
4534 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4535 PCI_VENDOR_ID_ESDGMBH,
4536 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4537 pbn_b2_4_115200 },
4538 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4539 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4540 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4541 pbn_b2_4_460800 },
4542 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4543 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4544 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4545 pbn_b2_8_460800 },
4546 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4547 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4548 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4549 pbn_b2_16_460800 },
4550 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4551 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4552 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4553 pbn_b2_16_460800 },
4554 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4555 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4556 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4557 pbn_b2_4_460800 },
4558 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4559 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4560 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4561 pbn_b2_8_460800 },
4562 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4563 PCI_SUBVENDOR_ID_EXSYS,
4564 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4565 pbn_b2_4_115200 },
4566 /*
4567 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4568 * (Exoray@isys.ca)
4569 */
4570 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4571 0x10b5, 0x106a, 0, 0,
4572 pbn_plx_romulus },
4573 /*
4574 * Quatech cards. These actually have configurable clocks but for
4575 * now we just use the default.
4576 *
4577 * 100 series are RS232, 200 series RS422,
4578 */
4579 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_b1_4_115200 },
4582 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_b1_2_115200 },
4585 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_b2_2_115200 },
4588 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_b1_2_115200 },
4591 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b2_2_115200 },
4594 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b1_4_115200 },
4597 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_b1_8_115200 },
4600 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_b1_8_115200 },
4603 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b1_4_115200 },
4606 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b1_2_115200 },
4609 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_b1_4_115200 },
4612 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_b1_2_115200 },
4615 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b2_4_115200 },
4618 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_b2_2_115200 },
4621 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b2_1_115200 },
4624 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_b2_4_115200 },
4627 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_b2_2_115200 },
4630 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_b2_1_115200 },
4633 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_b0_8_115200 },
4636
4637 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4638 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4639 0, 0,
4640 pbn_b0_4_921600 },
4641 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4642 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4643 0, 0,
4644 pbn_b0_4_1152000 },
4645 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_b0_bt_2_921600 },
4648
4649 /*
4650 * The below card is a little controversial since it is the
4651 * subject of a PCI vendor/device ID clash. (See
4652 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4653 * For now just used the hex ID 0x950a.
4654 */
4655 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4656 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4657 0, 0, pbn_b0_2_115200 },
4658 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4659 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4660 0, 0, pbn_b0_2_115200 },
4661 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663 pbn_b0_2_1130000 },
4664 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4665 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4666 pbn_b0_1_921600 },
4667 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_b0_4_115200 },
4670 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_b0_bt_2_921600 },
4673 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_b2_8_1152000 },
4676
4677 /*
4678 * Oxford Semiconductor Inc. Tornado PCI express device range.
4679 */
4680 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682 pbn_b0_1_15625000 },
4683 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4685 pbn_b0_1_15625000 },
4686 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4688 pbn_oxsemi_1_15625000 },
4689 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691 pbn_oxsemi_1_15625000 },
4692 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694 pbn_b0_1_15625000 },
4695 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 pbn_b0_1_15625000 },
4698 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 pbn_oxsemi_1_15625000 },
4701 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 pbn_oxsemi_1_15625000 },
4704 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706 pbn_b0_1_15625000 },
4707 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 pbn_b0_1_15625000 },
4710 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712 pbn_b0_1_15625000 },
4713 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715 pbn_b0_1_15625000 },
4716 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718 pbn_oxsemi_2_15625000 },
4719 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721 pbn_oxsemi_2_15625000 },
4722 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724 pbn_oxsemi_4_15625000 },
4725 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727 pbn_oxsemi_4_15625000 },
4728 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 pbn_oxsemi_8_15625000 },
4731 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 pbn_oxsemi_8_15625000 },
4734 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 pbn_oxsemi_1_15625000 },
4737 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 pbn_oxsemi_1_15625000 },
4740 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742 pbn_oxsemi_1_15625000 },
4743 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_oxsemi_1_15625000 },
4746 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 pbn_oxsemi_1_15625000 },
4749 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751 pbn_oxsemi_1_15625000 },
4752 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_oxsemi_1_15625000 },
4755 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_oxsemi_1_15625000 },
4758 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_oxsemi_1_15625000 },
4761 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 pbn_oxsemi_1_15625000 },
4764 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_oxsemi_1_15625000 },
4767 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_oxsemi_1_15625000 },
4770 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772 pbn_oxsemi_1_15625000 },
4773 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_oxsemi_1_15625000 },
4776 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778 pbn_oxsemi_1_15625000 },
4779 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_oxsemi_1_15625000 },
4782 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_oxsemi_1_15625000 },
4785 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_oxsemi_1_15625000 },
4788 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_oxsemi_1_15625000 },
4791 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_oxsemi_1_15625000 },
4794 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_oxsemi_1_15625000 },
4797 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_oxsemi_1_15625000 },
4800 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_oxsemi_1_15625000 },
4803 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_oxsemi_1_15625000 },
4806 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808 pbn_oxsemi_1_15625000 },
4809 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_oxsemi_1_15625000 },
4812 /*
4813 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4814 */
4815 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4816 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4817 pbn_oxsemi_1_15625000 },
4818 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4819 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4820 pbn_oxsemi_2_15625000 },
4821 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4822 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4823 pbn_oxsemi_4_15625000 },
4824 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4825 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4826 pbn_oxsemi_8_15625000 },
4827
4828 /*
4829 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4830 */
4831 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4832 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4833 pbn_oxsemi_2_15625000 },
4834 /*
4835 * EndRun Technologies. PCI express device range.
4836 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4837 */
4838 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4840 pbn_oxsemi_2_15625000 },
4841
4842 /*
4843 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4844 * from skokodyn@yahoo.com
4845 */
4846 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4847 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4848 pbn_sbsxrsio },
4849 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4850 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4851 pbn_sbsxrsio },
4852 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4853 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4854 pbn_sbsxrsio },
4855 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4856 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4857 pbn_sbsxrsio },
4858
4859 /*
4860 * Digitan DS560-558, from jimd@esoft.com
4861 */
4862 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864 pbn_b1_1_115200 },
4865
4866 /*
4867 * Titan Electronic cards
4868 * The 400L and 800L have a custom setup quirk.
4869 */
4870 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872 pbn_b0_1_921600 },
4873 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875 pbn_b0_2_921600 },
4876 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878 pbn_b0_4_921600 },
4879 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4881 pbn_b0_4_921600 },
4882 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884 pbn_b1_1_921600 },
4885 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887 pbn_b1_bt_2_921600 },
4888 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890 pbn_b0_bt_4_921600 },
4891 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 pbn_b0_bt_8_921600 },
4894 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 pbn_b4_bt_2_921600 },
4897 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 pbn_b4_bt_4_921600 },
4900 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 pbn_b4_bt_8_921600 },
4903 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_b0_4_921600 },
4906 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_b0_4_921600 },
4909 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 pbn_b0_4_921600 },
4912 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914 pbn_titan_1_4000000 },
4915 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917 pbn_titan_2_4000000 },
4918 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920 pbn_titan_4_4000000 },
4921 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 pbn_titan_8_4000000 },
4924 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 pbn_titan_2_4000000 },
4927 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929 pbn_titan_2_4000000 },
4930 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 pbn_b0_bt_2_921600 },
4933 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935 pbn_b0_4_921600 },
4936 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_b0_4_921600 },
4939 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 pbn_b0_4_921600 },
4942 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_b0_4_921600 },
4945
4946 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4948 pbn_b2_1_460800 },
4949 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951 pbn_b2_1_460800 },
4952 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4954 pbn_b2_1_460800 },
4955 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957 pbn_b2_bt_2_921600 },
4958 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960 pbn_b2_bt_2_921600 },
4961 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963 pbn_b2_bt_2_921600 },
4964 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966 pbn_b2_bt_4_921600 },
4967 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4969 pbn_b2_bt_4_921600 },
4970 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4972 pbn_b2_bt_4_921600 },
4973 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 pbn_b0_1_921600 },
4976 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 pbn_b0_1_921600 },
4979 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981 pbn_b0_1_921600 },
4982 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 pbn_b0_bt_2_921600 },
4985 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4987 pbn_b0_bt_2_921600 },
4988 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990 pbn_b0_bt_2_921600 },
4991 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 pbn_b0_bt_4_921600 },
4994 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 pbn_b0_bt_4_921600 },
4997 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 pbn_b0_bt_4_921600 },
5000 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002 pbn_b0_bt_8_921600 },
5003 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005 pbn_b0_bt_8_921600 },
5006 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 pbn_b0_bt_8_921600 },
5009
5010 /*
5011 * Computone devices submitted by Doug McNash dmcnash@computone.com
5012 */
5013 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5014 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
5015 0, 0, pbn_computone_4 },
5016 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5017 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
5018 0, 0, pbn_computone_8 },
5019 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5020 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
5021 0, 0, pbn_computone_6 },
5022
5023 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5025 pbn_oxsemi },
5026 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5027 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5028 pbn_b0_bt_1_921600 },
5029
5030 /*
5031 * Sunix PCI serial boards
5032 */
5033 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5034 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
5035 pbn_sunix_pci_1s },
5036 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5037 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
5038 pbn_sunix_pci_2s },
5039 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5040 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
5041 pbn_sunix_pci_4s },
5042 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5043 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
5044 pbn_sunix_pci_4s },
5045 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5046 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
5047 pbn_sunix_pci_8s },
5048 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5049 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5050 pbn_sunix_pci_8s },
5051 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5052 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5053 pbn_sunix_pci_16s },
5054
5055 /*
5056 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5057 */
5058 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5060 pbn_b0_bt_8_115200 },
5061 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5063 pbn_b0_bt_8_115200 },
5064
5065 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5067 pbn_b0_bt_2_115200 },
5068 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5070 pbn_b0_bt_2_115200 },
5071 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5073 pbn_b0_bt_2_115200 },
5074 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5076 pbn_b0_bt_4_460800 },
5077 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5079 pbn_b0_bt_4_460800 },
5080 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5082 pbn_b0_bt_2_460800 },
5083 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5085 pbn_b0_bt_2_460800 },
5086 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5088 pbn_b0_bt_2_460800 },
5089 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5091 pbn_b0_bt_1_115200 },
5092 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5094 pbn_b0_bt_1_460800 },
5095
5096 /*
5097 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5098 * Cards are identified by their subsystem vendor IDs, which
5099 * (in hex) match the model number.
5100 *
5101 * Note that JC140x are RS422/485 cards which require ox950
5102 * ACR = 0x10, and as such are not currently fully supported.
5103 */
5104 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5105 0x1204, 0x0004, 0, 0,
5106 pbn_b0_4_921600 },
5107 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5108 0x1208, 0x0004, 0, 0,
5109 pbn_b0_4_921600 },
5110/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5111 0x1402, 0x0002, 0, 0,
5112 pbn_b0_2_921600 }, */
5113/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5114 0x1404, 0x0004, 0, 0,
5115 pbn_b0_4_921600 }, */
5116 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5117 0x1208, 0x0004, 0, 0,
5118 pbn_b0_4_921600 },
5119
5120 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5121 0x1204, 0x0004, 0, 0,
5122 pbn_b0_4_921600 },
5123 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5124 0x1208, 0x0004, 0, 0,
5125 pbn_b0_4_921600 },
5126 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5127 0x1208, 0x0004, 0, 0,
5128 pbn_b0_4_921600 },
5129 /*
5130 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5131 */
5132 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5134 pbn_b1_1_1382400 },
5135
5136 /*
5137 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5138 */
5139 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5141 pbn_b1_1_1382400 },
5142
5143 /*
5144 * RAStel 2 port modem, gerg@moreton.com.au
5145 */
5146 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5148 pbn_b2_bt_2_115200 },
5149
5150 /*
5151 * EKF addition for i960 Boards form EKF with serial port
5152 */
5153 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5154 0xE4BF, PCI_ANY_ID, 0, 0,
5155 pbn_intel_i960 },
5156
5157 /*
5158 * Xircom Cardbus/Ethernet combos
5159 */
5160 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5162 pbn_b0_1_115200 },
5163 /*
5164 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5165 */
5166 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5168 pbn_b0_1_115200 },
5169
5170 /*
5171 * Untested PCI modems, sent in from various folks...
5172 */
5173
5174 /*
5175 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5176 */
5177 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5178 0x1048, 0x1500, 0, 0,
5179 pbn_b1_1_115200 },
5180
5181 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5182 0xFF00, 0, 0, 0,
5183 pbn_sgi_ioc3 },
5184
5185 /*
5186 * HP Diva card
5187 */
5188 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5189 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5190 pbn_b1_1_115200 },
5191 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5193 pbn_b0_5_115200 },
5194 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5196 pbn_b2_1_115200 },
5197 /* HPE PCI serial device */
5198 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5200 pbn_b1_1_115200 },
5201
5202 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5204 pbn_b3_2_115200 },
5205 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5207 pbn_b3_4_115200 },
5208 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5210 pbn_b3_8_115200 },
5211 /*
5212 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5213 */
5214 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5216 pbn_b0_1_115200 },
5217 /*
5218 * ITE
5219 */
5220 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5221 PCI_ANY_ID, PCI_ANY_ID,
5222 0, 0,
5223 pbn_b1_bt_1_115200 },
5224
5225 /*
5226 * IntaShield IS-100
5227 */
5228 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5230 pbn_b2_1_115200 },
5231 /*
5232 * IntaShield IS-200
5233 */
5234 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5236 pbn_b2_2_115200 },
5237 /*
5238 * IntaShield IS-400
5239 */
5240 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5242 pbn_b2_4_115200 },
5243 /*
5244 * IntaShield IX-100
5245 */
5246 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5247 PCI_ANY_ID, PCI_ANY_ID,
5248 0, 0,
5249 pbn_oxsemi_1_15625000 },
5250 /*
5251 * IntaShield IX-200
5252 */
5253 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5254 PCI_ANY_ID, PCI_ANY_ID,
5255 0, 0,
5256 pbn_oxsemi_2_15625000 },
5257 /*
5258 * IntaShield IX-400
5259 */
5260 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5261 PCI_ANY_ID, PCI_ANY_ID,
5262 0, 0,
5263 pbn_oxsemi_4_15625000 },
5264 /* Brainboxes Devices */
5265 /*
5266 * Brainboxes UC-101
5267 */
5268 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5269 PCI_ANY_ID, PCI_ANY_ID,
5270 0, 0,
5271 pbn_b2_2_115200 },
5272 { PCI_VENDOR_ID_INTASHIELD, 0x0BA2,
5273 PCI_ANY_ID, PCI_ANY_ID,
5274 0, 0,
5275 pbn_b2_2_115200 },
5276 { PCI_VENDOR_ID_INTASHIELD, 0x0BA3,
5277 PCI_ANY_ID, PCI_ANY_ID,
5278 0, 0,
5279 pbn_b2_2_115200 },
5280 /*
5281 * Brainboxes UC-235/246
5282 */
5283 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5284 PCI_ANY_ID, PCI_ANY_ID,
5285 0, 0,
5286 pbn_b2_1_115200 },
5287 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5288 PCI_ANY_ID, PCI_ANY_ID,
5289 0, 0,
5290 pbn_b2_1_115200 },
5291 /*
5292 * Brainboxes UC-253/UC-734
5293 */
5294 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5295 PCI_ANY_ID, PCI_ANY_ID,
5296 0, 0,
5297 pbn_b2_2_115200 },
5298 /*
5299 * Brainboxes UC-260/271/701/756
5300 */
5301 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5302 PCI_ANY_ID, PCI_ANY_ID,
5303 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5304 pbn_b2_4_115200 },
5305 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5306 PCI_ANY_ID, PCI_ANY_ID,
5307 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5308 pbn_b2_4_115200 },
5309 /*
5310 * Brainboxes UC-268
5311 */
5312 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5313 PCI_ANY_ID, PCI_ANY_ID,
5314 0, 0,
5315 pbn_b2_4_115200 },
5316 /*
5317 * Brainboxes UC-275/279
5318 */
5319 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5320 PCI_ANY_ID, PCI_ANY_ID,
5321 0, 0,
5322 pbn_b2_8_115200 },
5323 /*
5324 * Brainboxes UC-302
5325 */
5326 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5327 PCI_ANY_ID, PCI_ANY_ID,
5328 0, 0,
5329 pbn_b2_2_115200 },
5330 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5331 PCI_ANY_ID, PCI_ANY_ID,
5332 0, 0,
5333 pbn_b2_2_115200 },
5334 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5335 PCI_ANY_ID, PCI_ANY_ID,
5336 0, 0,
5337 pbn_b2_2_115200 },
5338 /*
5339 * Brainboxes UC-310
5340 */
5341 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5342 PCI_ANY_ID, PCI_ANY_ID,
5343 0, 0,
5344 pbn_b2_2_115200 },
5345 /*
5346 * Brainboxes UC-313
5347 */
5348 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5349 PCI_ANY_ID, PCI_ANY_ID,
5350 0, 0,
5351 pbn_b2_2_115200 },
5352 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5353 PCI_ANY_ID, PCI_ANY_ID,
5354 0, 0,
5355 pbn_b2_2_115200 },
5356 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5357 PCI_ANY_ID, PCI_ANY_ID,
5358 0, 0,
5359 pbn_b2_2_115200 },
5360 /*
5361 * Brainboxes UC-320/324
5362 */
5363 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5364 PCI_ANY_ID, PCI_ANY_ID,
5365 0, 0,
5366 pbn_b2_1_115200 },
5367 /*
5368 * Brainboxes UC-346
5369 */
5370 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5371 PCI_ANY_ID, PCI_ANY_ID,
5372 0, 0,
5373 pbn_b2_4_115200 },
5374 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5375 PCI_ANY_ID, PCI_ANY_ID,
5376 0, 0,
5377 pbn_b2_4_115200 },
5378 /*
5379 * Brainboxes UC-357
5380 */
5381 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5382 PCI_ANY_ID, PCI_ANY_ID,
5383 0, 0,
5384 pbn_b2_2_115200 },
5385 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5386 PCI_ANY_ID, PCI_ANY_ID,
5387 0, 0,
5388 pbn_b2_2_115200 },
5389 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5390 PCI_ANY_ID, PCI_ANY_ID,
5391 0, 0,
5392 pbn_b2_2_115200 },
5393 /*
5394 * Brainboxes UC-368
5395 */
5396 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5397 PCI_ANY_ID, PCI_ANY_ID,
5398 0, 0,
5399 pbn_b2_4_115200 },
5400 { PCI_VENDOR_ID_INTASHIELD, 0x0C42,
5401 PCI_ANY_ID, PCI_ANY_ID,
5402 0, 0,
5403 pbn_b2_4_115200 },
5404 { PCI_VENDOR_ID_INTASHIELD, 0x0C43,
5405 PCI_ANY_ID, PCI_ANY_ID,
5406 0, 0,
5407 pbn_b2_4_115200 },
5408 /*
5409 * Brainboxes UC-420
5410 */
5411 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5412 PCI_ANY_ID, PCI_ANY_ID,
5413 0, 0,
5414 pbn_b2_4_115200 },
5415 /*
5416 * Brainboxes UC-607
5417 */
5418 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5419 PCI_ANY_ID, PCI_ANY_ID,
5420 0, 0,
5421 pbn_b2_2_115200 },
5422 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5423 PCI_ANY_ID, PCI_ANY_ID,
5424 0, 0,
5425 pbn_b2_2_115200 },
5426 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5427 PCI_ANY_ID, PCI_ANY_ID,
5428 0, 0,
5429 pbn_b2_2_115200 },
5430 /*
5431 * Brainboxes UC-836
5432 */
5433 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5434 PCI_ANY_ID, PCI_ANY_ID,
5435 0, 0,
5436 pbn_b2_4_115200 },
5437 /*
5438 * Brainboxes UP-189
5439 */
5440 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5441 PCI_ANY_ID, PCI_ANY_ID,
5442 0, 0,
5443 pbn_b2_2_115200 },
5444 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5445 PCI_ANY_ID, PCI_ANY_ID,
5446 0, 0,
5447 pbn_b2_2_115200 },
5448 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5449 PCI_ANY_ID, PCI_ANY_ID,
5450 0, 0,
5451 pbn_b2_2_115200 },
5452 /*
5453 * Brainboxes UP-200
5454 */
5455 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5456 PCI_ANY_ID, PCI_ANY_ID,
5457 0, 0,
5458 pbn_b2_2_115200 },
5459 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5460 PCI_ANY_ID, PCI_ANY_ID,
5461 0, 0,
5462 pbn_b2_2_115200 },
5463 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5464 PCI_ANY_ID, PCI_ANY_ID,
5465 0, 0,
5466 pbn_b2_2_115200 },
5467 /*
5468 * Brainboxes UP-869
5469 */
5470 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5471 PCI_ANY_ID, PCI_ANY_ID,
5472 0, 0,
5473 pbn_b2_2_115200 },
5474 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5475 PCI_ANY_ID, PCI_ANY_ID,
5476 0, 0,
5477 pbn_b2_2_115200 },
5478 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5479 PCI_ANY_ID, PCI_ANY_ID,
5480 0, 0,
5481 pbn_b2_2_115200 },
5482 /*
5483 * Brainboxes UP-880
5484 */
5485 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5486 PCI_ANY_ID, PCI_ANY_ID,
5487 0, 0,
5488 pbn_b2_2_115200 },
5489 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5490 PCI_ANY_ID, PCI_ANY_ID,
5491 0, 0,
5492 pbn_b2_2_115200 },
5493 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5494 PCI_ANY_ID, PCI_ANY_ID,
5495 0, 0,
5496 pbn_b2_2_115200 },
5497 /*
5498 * Brainboxes PX-101
5499 */
5500 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5501 PCI_ANY_ID, PCI_ANY_ID,
5502 0, 0,
5503 pbn_b0_2_115200 },
5504 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5505 PCI_ANY_ID, PCI_ANY_ID,
5506 0, 0,
5507 pbn_oxsemi_2_15625000 },
5508 /*
5509 * Brainboxes PX-235/246
5510 */
5511 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5512 PCI_ANY_ID, PCI_ANY_ID,
5513 0, 0,
5514 pbn_b0_1_115200 },
5515 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5516 PCI_ANY_ID, PCI_ANY_ID,
5517 0, 0,
5518 pbn_oxsemi_1_15625000 },
5519 /*
5520 * Brainboxes PX-203/PX-257
5521 */
5522 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5523 PCI_ANY_ID, PCI_ANY_ID,
5524 0, 0,
5525 pbn_b0_2_115200 },
5526 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5527 PCI_ANY_ID, PCI_ANY_ID,
5528 0, 0,
5529 pbn_oxsemi_2_15625000 },
5530 /*
5531 * Brainboxes PX-260/PX-701
5532 */
5533 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5534 PCI_ANY_ID, PCI_ANY_ID,
5535 0, 0,
5536 pbn_oxsemi_4_15625000 },
5537 /*
5538 * Brainboxes PX-275/279
5539 */
5540 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5541 PCI_ANY_ID, PCI_ANY_ID,
5542 0, 0,
5543 pbn_b2_8_115200 },
5544 /*
5545 * Brainboxes PX-310
5546 */
5547 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5548 PCI_ANY_ID, PCI_ANY_ID,
5549 0, 0,
5550 pbn_oxsemi_2_15625000 },
5551 /*
5552 * Brainboxes PX-313
5553 */
5554 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5555 PCI_ANY_ID, PCI_ANY_ID,
5556 0, 0,
5557 pbn_oxsemi_2_15625000 },
5558 /*
5559 * Brainboxes PX-320/324/PX-376/PX-387
5560 */
5561 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5562 PCI_ANY_ID, PCI_ANY_ID,
5563 0, 0,
5564 pbn_oxsemi_1_15625000 },
5565 /*
5566 * Brainboxes PX-335/346
5567 */
5568 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5569 PCI_ANY_ID, PCI_ANY_ID,
5570 0, 0,
5571 pbn_oxsemi_4_15625000 },
5572 /*
5573 * Brainboxes PX-368
5574 */
5575 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5576 PCI_ANY_ID, PCI_ANY_ID,
5577 0, 0,
5578 pbn_oxsemi_4_15625000 },
5579 /*
5580 * Brainboxes PX-420
5581 */
5582 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5583 PCI_ANY_ID, PCI_ANY_ID,
5584 0, 0,
5585 pbn_b0_4_115200 },
5586 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5587 PCI_ANY_ID, PCI_ANY_ID,
5588 0, 0,
5589 pbn_oxsemi_4_15625000 },
5590 /*
5591 * Brainboxes PX-475
5592 */
5593 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5594 PCI_ANY_ID, PCI_ANY_ID,
5595 0, 0,
5596 pbn_oxsemi_1_15625000 },
5597 /*
5598 * Brainboxes PX-803/PX-857
5599 */
5600 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5601 PCI_ANY_ID, PCI_ANY_ID,
5602 0, 0,
5603 pbn_b0_2_115200 },
5604 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5605 PCI_ANY_ID, PCI_ANY_ID,
5606 0, 0,
5607 pbn_oxsemi_2_15625000 },
5608 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5609 PCI_ANY_ID, PCI_ANY_ID,
5610 0, 0,
5611 pbn_oxsemi_2_15625000 },
5612 /*
5613 * Brainboxes PX-820
5614 */
5615 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5616 PCI_ANY_ID, PCI_ANY_ID,
5617 0, 0,
5618 pbn_b0_4_115200 },
5619 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5620 PCI_ANY_ID, PCI_ANY_ID,
5621 0, 0,
5622 pbn_oxsemi_4_15625000 },
5623 /*
5624 * Brainboxes PX-835/PX-846
5625 */
5626 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5627 PCI_ANY_ID, PCI_ANY_ID,
5628 0, 0,
5629 pbn_b0_1_115200 },
5630 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5631 PCI_ANY_ID, PCI_ANY_ID,
5632 0, 0,
5633 pbn_oxsemi_1_15625000 },
5634 /*
5635 * Brainboxes XC-235
5636 */
5637 { PCI_VENDOR_ID_INTASHIELD, 0x4026,
5638 PCI_ANY_ID, PCI_ANY_ID,
5639 0, 0,
5640 pbn_oxsemi_1_15625000 },
5641 /*
5642 * Brainboxes XC-475
5643 */
5644 { PCI_VENDOR_ID_INTASHIELD, 0x4021,
5645 PCI_ANY_ID, PCI_ANY_ID,
5646 0, 0,
5647 pbn_oxsemi_1_15625000 },
5648
5649 /*
5650 * Perle PCI-RAS cards
5651 */
5652 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5653 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5654 0, 0, pbn_b2_4_921600 },
5655 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5656 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5657 0, 0, pbn_b2_8_921600 },
5658
5659 /*
5660 * Mainpine series cards: Fairly standard layout but fools
5661 * parts of the autodetect in some cases and uses otherwise
5662 * unmatched communications subclasses in the PCI Express case
5663 */
5664
5665 { /* RockForceDUO */
5666 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5667 PCI_VENDOR_ID_MAINPINE, 0x0200,
5668 0, 0, pbn_b0_2_115200 },
5669 { /* RockForceQUATRO */
5670 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5671 PCI_VENDOR_ID_MAINPINE, 0x0300,
5672 0, 0, pbn_b0_4_115200 },
5673 { /* RockForceDUO+ */
5674 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5675 PCI_VENDOR_ID_MAINPINE, 0x0400,
5676 0, 0, pbn_b0_2_115200 },
5677 { /* RockForceQUATRO+ */
5678 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5679 PCI_VENDOR_ID_MAINPINE, 0x0500,
5680 0, 0, pbn_b0_4_115200 },
5681 { /* RockForce+ */
5682 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5683 PCI_VENDOR_ID_MAINPINE, 0x0600,
5684 0, 0, pbn_b0_2_115200 },
5685 { /* RockForce+ */
5686 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5687 PCI_VENDOR_ID_MAINPINE, 0x0700,
5688 0, 0, pbn_b0_4_115200 },
5689 { /* RockForceOCTO+ */
5690 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5691 PCI_VENDOR_ID_MAINPINE, 0x0800,
5692 0, 0, pbn_b0_8_115200 },
5693 { /* RockForceDUO+ */
5694 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5695 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5696 0, 0, pbn_b0_2_115200 },
5697 { /* RockForceQUARTRO+ */
5698 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5699 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5700 0, 0, pbn_b0_4_115200 },
5701 { /* RockForceOCTO+ */
5702 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5703 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5704 0, 0, pbn_b0_8_115200 },
5705 { /* RockForceD1 */
5706 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5707 PCI_VENDOR_ID_MAINPINE, 0x2000,
5708 0, 0, pbn_b0_1_115200 },
5709 { /* RockForceF1 */
5710 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5711 PCI_VENDOR_ID_MAINPINE, 0x2100,
5712 0, 0, pbn_b0_1_115200 },
5713 { /* RockForceD2 */
5714 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5715 PCI_VENDOR_ID_MAINPINE, 0x2200,
5716 0, 0, pbn_b0_2_115200 },
5717 { /* RockForceF2 */
5718 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5719 PCI_VENDOR_ID_MAINPINE, 0x2300,
5720 0, 0, pbn_b0_2_115200 },
5721 { /* RockForceD4 */
5722 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5723 PCI_VENDOR_ID_MAINPINE, 0x2400,
5724 0, 0, pbn_b0_4_115200 },
5725 { /* RockForceF4 */
5726 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5727 PCI_VENDOR_ID_MAINPINE, 0x2500,
5728 0, 0, pbn_b0_4_115200 },
5729 { /* RockForceD8 */
5730 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5731 PCI_VENDOR_ID_MAINPINE, 0x2600,
5732 0, 0, pbn_b0_8_115200 },
5733 { /* RockForceF8 */
5734 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5735 PCI_VENDOR_ID_MAINPINE, 0x2700,
5736 0, 0, pbn_b0_8_115200 },
5737 { /* IQ Express D1 */
5738 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5739 PCI_VENDOR_ID_MAINPINE, 0x3000,
5740 0, 0, pbn_b0_1_115200 },
5741 { /* IQ Express F1 */
5742 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5743 PCI_VENDOR_ID_MAINPINE, 0x3100,
5744 0, 0, pbn_b0_1_115200 },
5745 { /* IQ Express D2 */
5746 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5747 PCI_VENDOR_ID_MAINPINE, 0x3200,
5748 0, 0, pbn_b0_2_115200 },
5749 { /* IQ Express F2 */
5750 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5751 PCI_VENDOR_ID_MAINPINE, 0x3300,
5752 0, 0, pbn_b0_2_115200 },
5753 { /* IQ Express D4 */
5754 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5755 PCI_VENDOR_ID_MAINPINE, 0x3400,
5756 0, 0, pbn_b0_4_115200 },
5757 { /* IQ Express F4 */
5758 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5759 PCI_VENDOR_ID_MAINPINE, 0x3500,
5760 0, 0, pbn_b0_4_115200 },
5761 { /* IQ Express D8 */
5762 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5763 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5764 0, 0, pbn_b0_8_115200 },
5765 { /* IQ Express F8 */
5766 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5767 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5768 0, 0, pbn_b0_8_115200 },
5769
5770
5771 /*
5772 * PA Semi PA6T-1682M on-chip UART
5773 */
5774 { PCI_VENDOR_ID_PASEMI, 0xa004,
5775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5776 pbn_pasemi_1682M },
5777
5778 /*
5779 * National Instruments
5780 */
5781 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5783 pbn_b1_16_115200 },
5784 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5786 pbn_b1_8_115200 },
5787 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5789 pbn_b1_bt_4_115200 },
5790 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5792 pbn_b1_bt_2_115200 },
5793 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5795 pbn_b1_bt_4_115200 },
5796 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5798 pbn_b1_bt_2_115200 },
5799 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5801 pbn_b1_16_115200 },
5802 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5804 pbn_b1_8_115200 },
5805 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5807 pbn_b1_bt_4_115200 },
5808 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5810 pbn_b1_bt_2_115200 },
5811 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5813 pbn_b1_bt_4_115200 },
5814 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5816 pbn_b1_bt_2_115200 },
5817 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5819 pbn_ni8430_2 },
5820 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5822 pbn_ni8430_2 },
5823 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5825 pbn_ni8430_4 },
5826 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5828 pbn_ni8430_4 },
5829 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5831 pbn_ni8430_8 },
5832 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5834 pbn_ni8430_8 },
5835 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5837 pbn_ni8430_16 },
5838 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5840 pbn_ni8430_16 },
5841 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5843 pbn_ni8430_2 },
5844 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5846 pbn_ni8430_2 },
5847 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5849 pbn_ni8430_4 },
5850 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5852 pbn_ni8430_4 },
5853
5854 /*
5855 * MOXA
5856 */
5857 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
5858 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), .driver_data: pbn_moxa_2 },
5859 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), .driver_data: pbn_moxa_2 },
5860 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), .driver_data: pbn_moxa_4 },
5861 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), .driver_data: pbn_moxa_4 },
5862 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), .driver_data: pbn_moxa_2 },
5863 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), .driver_data: pbn_moxa_4 },
5864 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), .driver_data: pbn_moxa_4 },
5865 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), .driver_data: pbn_moxa_8 },
5866 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), .driver_data: pbn_moxa_8 },
5867 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), .driver_data: pbn_moxa_8 },
5868 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), .driver_data: pbn_moxa_8 },
5869 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), .driver_data: pbn_moxa_2 },
5870 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), .driver_data: pbn_moxa_2 },
5871 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), .driver_data: pbn_moxa_4 },
5872 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), .driver_data: pbn_moxa_4 },
5873 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), .driver_data: pbn_moxa_8 },
5874 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), .driver_data: pbn_moxa_8 },
5875
5876 /*
5877 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5878 */
5879 { PCI_VENDOR_ID_ADDIDATA,
5880 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5881 PCI_ANY_ID,
5882 PCI_ANY_ID,
5883 .class: 0,
5884 .class_mask: 0,
5885 .driver_data: pbn_b0_4_115200 },
5886
5887 { PCI_VENDOR_ID_ADDIDATA,
5888 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5889 PCI_ANY_ID,
5890 PCI_ANY_ID,
5891 0,
5892 0,
5893 pbn_b0_2_115200 },
5894
5895 { PCI_VENDOR_ID_ADDIDATA,
5896 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5897 PCI_ANY_ID,
5898 PCI_ANY_ID,
5899 0,
5900 0,
5901 pbn_b0_1_115200 },
5902
5903 { PCI_VENDOR_ID_AMCC,
5904 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5905 PCI_ANY_ID,
5906 PCI_ANY_ID,
5907 0,
5908 0,
5909 pbn_b1_8_115200 },
5910
5911 { PCI_VENDOR_ID_ADDIDATA,
5912 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5913 PCI_ANY_ID,
5914 PCI_ANY_ID,
5915 0,
5916 0,
5917 pbn_b0_4_115200 },
5918
5919 { PCI_VENDOR_ID_ADDIDATA,
5920 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5921 PCI_ANY_ID,
5922 PCI_ANY_ID,
5923 0,
5924 0,
5925 pbn_b0_2_115200 },
5926
5927 { PCI_VENDOR_ID_ADDIDATA,
5928 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5929 PCI_ANY_ID,
5930 PCI_ANY_ID,
5931 0,
5932 0,
5933 pbn_b0_1_115200 },
5934
5935 { PCI_VENDOR_ID_ADDIDATA,
5936 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5937 PCI_ANY_ID,
5938 PCI_ANY_ID,
5939 0,
5940 0,
5941 pbn_b0_4_115200 },
5942
5943 { PCI_VENDOR_ID_ADDIDATA,
5944 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5945 PCI_ANY_ID,
5946 PCI_ANY_ID,
5947 0,
5948 0,
5949 pbn_b0_2_115200 },
5950
5951 { PCI_VENDOR_ID_ADDIDATA,
5952 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5953 PCI_ANY_ID,
5954 PCI_ANY_ID,
5955 0,
5956 0,
5957 pbn_b0_1_115200 },
5958
5959 { PCI_VENDOR_ID_ADDIDATA,
5960 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5961 PCI_ANY_ID,
5962 PCI_ANY_ID,
5963 0,
5964 0,
5965 pbn_b0_8_115200 },
5966
5967 { PCI_VENDOR_ID_ADDIDATA,
5968 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5969 PCI_ANY_ID,
5970 PCI_ANY_ID,
5971 0,
5972 0,
5973 pbn_ADDIDATA_PCIe_4_3906250 },
5974
5975 { PCI_VENDOR_ID_ADDIDATA,
5976 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5977 PCI_ANY_ID,
5978 PCI_ANY_ID,
5979 0,
5980 0,
5981 pbn_ADDIDATA_PCIe_2_3906250 },
5982
5983 { PCI_VENDOR_ID_ADDIDATA,
5984 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5985 PCI_ANY_ID,
5986 PCI_ANY_ID,
5987 0,
5988 0,
5989 pbn_ADDIDATA_PCIe_1_3906250 },
5990
5991 { PCI_VENDOR_ID_ADDIDATA,
5992 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5993 PCI_ANY_ID,
5994 PCI_ANY_ID,
5995 0,
5996 0,
5997 pbn_ADDIDATA_PCIe_8_3906250 },
5998
5999 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
6000 PCI_VENDOR_ID_IBM, 0x0299,
6001 0, 0, pbn_b0_bt_2_115200 },
6002
6003 /*
6004 * other NetMos 9835 devices are most likely handled by the
6005 * parport_serial driver, check drivers/parport/parport_serial.c
6006 * before adding them here.
6007 */
6008
6009 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
6010 0xA000, 0x1000,
6011 0, 0, pbn_b0_1_115200 },
6012
6013 /* the 9901 is a rebranded 9912 */
6014 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
6015 0xA000, 0x1000,
6016 0, 0, pbn_b0_1_115200 },
6017
6018 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
6019 0xA000, 0x1000,
6020 0, 0, pbn_b0_1_115200 },
6021
6022 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
6023 0xA000, 0x1000,
6024 0, 0, pbn_b0_1_115200 },
6025
6026 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
6027 0xA000, 0x1000,
6028 0, 0, pbn_b0_1_115200 },
6029
6030 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
6031 0xA000, 0x3002,
6032 0, 0, pbn_NETMOS9900_2s_115200 },
6033
6034 /*
6035 * Best Connectivity and Rosewill PCI Multi I/O cards
6036 */
6037
6038 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6039 0xA000, 0x1000,
6040 0, 0, pbn_b0_1_115200 },
6041
6042 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6043 0xA000, 0x3002,
6044 0, 0, pbn_b0_bt_2_115200 },
6045
6046 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6047 0xA000, 0x3004,
6048 0, 0, pbn_b0_bt_4_115200 },
6049
6050 /*
6051 * ASIX AX99100 PCIe to Multi I/O Controller
6052 */
6053 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
6054 0xA000, 0x1000,
6055 0, 0, pbn_b0_1_115200 },
6056
6057 /* Intel CE4100 */
6058 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
6059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6060 pbn_ce4100_1_115200 },
6061
6062 /*
6063 * Cronyx Omega PCI
6064 */
6065 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
6066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6067 pbn_omegapci },
6068
6069 /*
6070 * Broadcom TruManage
6071 */
6072 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
6073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6074 pbn_brcm_trumanage },
6075
6076 /*
6077 * AgeStar as-prs2-009
6078 */
6079 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
6080 PCI_ANY_ID, PCI_ANY_ID,
6081 0, 0, pbn_b0_bt_2_115200 },
6082
6083 /*
6084 * WCH CH353 series devices: The 2S1P is handled by parport_serial
6085 * so not listed here.
6086 */
6087 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S,
6088 PCI_ANY_ID, PCI_ANY_ID,
6089 0, 0, pbn_b0_bt_4_115200 },
6090
6091 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
6092 PCI_ANY_ID, PCI_ANY_ID,
6093 0, 0, pbn_b0_bt_2_115200 },
6094
6095 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S,
6096 PCI_ANY_ID, PCI_ANY_ID,
6097 0, 0, pbn_b0_bt_4_115200 },
6098
6099 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S,
6100 PCI_ANY_ID, PCI_ANY_ID,
6101 0, 0, pbn_wch382_2 },
6102
6103 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S,
6104 PCI_ANY_ID, PCI_ANY_ID,
6105 0, 0, pbn_wch384_4 },
6106
6107 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S,
6108 PCI_ANY_ID, PCI_ANY_ID,
6109 0, 0, pbn_wch384_8 },
6110 /*
6111 * Realtek RealManage
6112 */
6113 { PCI_VENDOR_ID_REALTEK, 0x816a,
6114 PCI_ANY_ID, PCI_ANY_ID,
6115 0, 0, pbn_b0_1_115200 },
6116
6117 { PCI_VENDOR_ID_REALTEK, 0x816b,
6118 PCI_ANY_ID, PCI_ANY_ID,
6119 0, 0, pbn_b0_1_115200 },
6120
6121 /* Fintek PCI serial cards */
6122 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6123 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6124 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6125 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6126 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6127 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6128
6129 /* MKS Tenta SCOM-080x serial cards */
6130 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6131 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6132
6133 /* Amazon PCI serial device */
6134 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6135
6136 /*
6137 * These entries match devices with class COMMUNICATION_SERIAL,
6138 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
6139 */
6140 { PCI_ANY_ID, PCI_ANY_ID,
6141 PCI_ANY_ID, PCI_ANY_ID,
6142 PCI_CLASS_COMMUNICATION_SERIAL << 8,
6143 0xffff00, pbn_default },
6144 { PCI_ANY_ID, PCI_ANY_ID,
6145 PCI_ANY_ID, PCI_ANY_ID,
6146 PCI_CLASS_COMMUNICATION_MODEM << 8,
6147 0xffff00, pbn_default },
6148 { PCI_ANY_ID, PCI_ANY_ID,
6149 PCI_ANY_ID, PCI_ANY_ID,
6150 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
6151 0xffff00, pbn_default },
6152 { 0, }
6153};
6154
6155static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
6156 pci_channel_state_t state)
6157{
6158 struct serial_private *priv = pci_get_drvdata(pdev: dev);
6159
6160 if (state == pci_channel_io_perm_failure)
6161 return PCI_ERS_RESULT_DISCONNECT;
6162
6163 if (priv)
6164 pciserial_detach_ports(priv);
6165
6166 pci_disable_device(dev);
6167
6168 return PCI_ERS_RESULT_NEED_RESET;
6169}
6170
6171static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
6172{
6173 int rc;
6174
6175 rc = pci_enable_device(dev);
6176
6177 if (rc)
6178 return PCI_ERS_RESULT_DISCONNECT;
6179
6180 pci_restore_state(dev);
6181 pci_save_state(dev);
6182
6183 return PCI_ERS_RESULT_RECOVERED;
6184}
6185
6186static void serial8250_io_resume(struct pci_dev *dev)
6187{
6188 struct serial_private *priv = pci_get_drvdata(pdev: dev);
6189 struct serial_private *new;
6190
6191 if (!priv)
6192 return;
6193
6194 new = pciserial_init_ports(dev, priv->board);
6195 if (!IS_ERR(ptr: new)) {
6196 pci_set_drvdata(pdev: dev, data: new);
6197 kfree(objp: priv);
6198 }
6199}
6200
6201static const struct pci_error_handlers serial8250_err_handler = {
6202 .error_detected = serial8250_io_error_detected,
6203 .slot_reset = serial8250_io_slot_reset,
6204 .resume = serial8250_io_resume,
6205};
6206
6207static struct pci_driver serial_pci_driver = {
6208 .name = "serial",
6209 .probe = pciserial_init_one,
6210 .remove = pciserial_remove_one,
6211 .driver = {
6212 .pm = &pciserial_pm_ops,
6213 },
6214 .id_table = serial_pci_tbl,
6215 .err_handler = &serial8250_err_handler,
6216};
6217
6218module_pci_driver(serial_pci_driver);
6219
6220MODULE_LICENSE("GPL");
6221MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6222MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
6223MODULE_IMPORT_NS("SERIAL_8250_PCI");
6224