1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2021 Intel Corporation
4 */
5
6#include <linux/dma-fence.h>
7#include <linux/dma-resv.h>
8
9#include <drm/drm_blend.h>
10#include <drm/drm_gem.h>
11#include <drm/drm_modeset_helper.h>
12
13#include "i915_drv.h"
14#include "i915_utils.h"
15#include "intel_bo.h"
16#include "intel_display.h"
17#include "intel_display_core.h"
18#include "intel_display_types.h"
19#include "intel_dpt.h"
20#include "intel_fb.h"
21#include "intel_fb_bo.h"
22#include "intel_frontbuffer.h"
23#include "intel_panic.h"
24#include "intel_plane.h"
25
26#define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
27
28/*
29 * From the Sky Lake PRM:
30 * "The Color Control Surface (CCS) contains the compression status of
31 * the cache-line pairs. The compression state of the cache-line pair
32 * is specified by 2 bits in the CCS. Each CCS cache-line represents
33 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
34 * cache-line-pairs. CCS is always Y tiled."
35 *
36 * Since cache line pairs refers to horizontally adjacent cache lines,
37 * each cache line in the CCS corresponds to an area of 32x16 cache
38 * lines on the main surface. Since each pixel is 4 bytes, this gives
39 * us a ratio of one byte in the CCS for each 8x16 pixels in the
40 * main surface.
41 */
42static const struct drm_format_info skl_ccs_formats[] = {
43 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
44 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
45 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
46 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
47 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
48 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
49 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
50 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
51 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
52 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
53 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
54 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
55 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
56 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
57 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
58 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
59};
60
61/*
62 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
63 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
64 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
65 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
66 * the main surface.
67 */
68static const struct drm_format_info gen12_ccs_formats[] = {
69 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
70 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
71 .hsub = 1, .vsub = 1, },
72 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
73 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
74 .hsub = 1, .vsub = 1, },
75 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
76 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
77 .hsub = 1, .vsub = 1, .has_alpha = true },
78 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
79 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
80 .hsub = 1, .vsub = 1, .has_alpha = true },
81 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
82 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
83 .hsub = 1, .vsub = 1, },
84 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
85 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
86 .hsub = 1, .vsub = 1, },
87 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
88 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
89 .hsub = 1, .vsub = 1, .has_alpha = true },
90 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
91 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
92 .hsub = 1, .vsub = 1, .has_alpha = true },
93 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2,
94 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
95 .hsub = 1, .vsub = 1, },
96 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2,
97 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
98 .hsub = 1, .vsub = 1, },
99 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2,
100 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
101 .hsub = 1, .vsub = 1, .has_alpha = true },
102 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2,
103 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
104 .hsub = 1, .vsub = 1, .has_alpha = true },
105 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
106 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
107 .hsub = 2, .vsub = 1, .is_yuv = true },
108 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
109 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
110 .hsub = 2, .vsub = 1, .is_yuv = true },
111 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
112 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
113 .hsub = 2, .vsub = 1, .is_yuv = true },
114 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
115 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
116 .hsub = 2, .vsub = 1, .is_yuv = true },
117 { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
118 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
119 .hsub = 1, .vsub = 1, .is_yuv = true },
120 { .format = DRM_FORMAT_NV12, .num_planes = 4,
121 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
122 .hsub = 2, .vsub = 2, .is_yuv = true },
123 { .format = DRM_FORMAT_P010, .num_planes = 4,
124 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
125 .hsub = 2, .vsub = 2, .is_yuv = true },
126 { .format = DRM_FORMAT_P012, .num_planes = 4,
127 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
128 .hsub = 2, .vsub = 2, .is_yuv = true },
129 { .format = DRM_FORMAT_P016, .num_planes = 4,
130 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
131 .hsub = 2, .vsub = 2, .is_yuv = true },
132};
133
134/*
135 * Same as gen12_ccs_formats[] above, but with additional surface used
136 * to pass Clear Color information in plane 2 with 64 bits of data.
137 */
138static const struct drm_format_info gen12_ccs_cc_formats[] = {
139 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
140 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 },
141 .hsub = 1, .vsub = 1, },
142 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
143 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 },
144 .hsub = 1, .vsub = 1, },
145 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
146 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 },
147 .hsub = 1, .vsub = 1, .has_alpha = true },
148 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
149 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 },
150 .hsub = 1, .vsub = 1, .has_alpha = true },
151 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
152 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 },
153 .hsub = 1, .vsub = 1, },
154 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
155 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 },
156 .hsub = 1, .vsub = 1, },
157 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
158 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 },
159 .hsub = 1, .vsub = 1, .has_alpha = true },
160 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
161 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 },
162 .hsub = 1, .vsub = 1, .has_alpha = true },
163 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 3,
164 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
165 .hsub = 1, .vsub = 1, },
166 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 3,
167 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
168 .hsub = 1, .vsub = 1, },
169 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 3,
170 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
171 .hsub = 1, .vsub = 1, .has_alpha = true },
172 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 3,
173 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
174 .hsub = 1, .vsub = 1, .has_alpha = true },
175};
176
177static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
178 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
179 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
180 .hsub = 1, .vsub = 1, },
181 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
182 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
183 .hsub = 1, .vsub = 1, },
184 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
185 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
186 .hsub = 1, .vsub = 1, .has_alpha = true },
187 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
188 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
189 .hsub = 1, .vsub = 1, .has_alpha = true },
190 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
191 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
192 .hsub = 1, .vsub = 1, },
193 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
194 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
195 .hsub = 1, .vsub = 1, },
196 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
197 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
198 .hsub = 1, .vsub = 1, .has_alpha = true },
199 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
200 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
201 .hsub = 1, .vsub = 1, .has_alpha = true },
202 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2,
203 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
204 .hsub = 1, .vsub = 1, },
205 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2,
206 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
207 .hsub = 1, .vsub = 1, },
208 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2,
209 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
210 .hsub = 1, .vsub = 1, .has_alpha = true },
211 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2,
212 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
213 .hsub = 1, .vsub = 1, .has_alpha = true },
214};
215
216struct intel_modifier_desc {
217 u64 modifier;
218 struct {
219 u8 from;
220 u8 until;
221 } display_ver;
222#define DISPLAY_VER_ALL { 0, -1 }
223
224 const struct drm_format_info *formats;
225 int format_count;
226#define FORMAT_OVERRIDE(format_list) \
227 .formats = format_list, \
228 .format_count = ARRAY_SIZE(format_list)
229
230 u8 plane_caps;
231
232 struct {
233 u8 cc_planes:3;
234 u8 packed_aux_planes:4;
235 u8 planar_aux_planes:4;
236 } ccs;
237};
238
239#define INTEL_PLANE_CAP_CCS_MASK (INTEL_PLANE_CAP_CCS_RC | \
240 INTEL_PLANE_CAP_CCS_RC_CC | \
241 INTEL_PLANE_CAP_CCS_MC)
242#define INTEL_PLANE_CAP_TILING_MASK (INTEL_PLANE_CAP_TILING_X | \
243 INTEL_PLANE_CAP_TILING_Y | \
244 INTEL_PLANE_CAP_TILING_Yf | \
245 INTEL_PLANE_CAP_TILING_4)
246#define INTEL_PLANE_CAP_TILING_NONE 0
247
248static const struct intel_modifier_desc intel_modifiers[] = {
249 {
250 .modifier = I915_FORMAT_MOD_4_TILED_LNL_CCS,
251 .display_ver = { 20, -1 },
252 .plane_caps = INTEL_PLANE_CAP_TILING_4,
253 }, {
254 .modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS,
255 .display_ver = { 14, -1 },
256 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS,
257 }, {
258 .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
259 .display_ver = { 14, 14 },
260 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
261
262 .ccs.packed_aux_planes = BIT(1),
263 .ccs.planar_aux_planes = BIT(2) | BIT(3),
264
265 FORMAT_OVERRIDE(gen12_ccs_formats),
266 }, {
267 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS,
268 .display_ver = { 14, 14 },
269 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
270
271 .ccs.packed_aux_planes = BIT(1),
272
273 FORMAT_OVERRIDE(gen12_ccs_formats),
274 }, {
275 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC,
276 .display_ver = { 14, 14 },
277 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
278
279 .ccs.cc_planes = BIT(2),
280 .ccs.packed_aux_planes = BIT(1),
281
282 FORMAT_OVERRIDE(gen12_ccs_cc_formats),
283 }, {
284 .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
285 .display_ver = { 13, 13 },
286 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
287 }, {
288 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
289 .display_ver = { 13, 13 },
290 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
291
292 .ccs.cc_planes = BIT(1),
293
294 FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
295 }, {
296 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
297 .display_ver = { 13, 13 },
298 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
299 }, {
300 .modifier = I915_FORMAT_MOD_4_TILED,
301 .display_ver = { 13, -1 },
302 .plane_caps = INTEL_PLANE_CAP_TILING_4,
303 }, {
304 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
305 .display_ver = { 12, 13 },
306 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
307
308 .ccs.packed_aux_planes = BIT(1),
309 .ccs.planar_aux_planes = BIT(2) | BIT(3),
310
311 FORMAT_OVERRIDE(gen12_ccs_formats),
312 }, {
313 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
314 .display_ver = { 12, 13 },
315 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,
316
317 .ccs.packed_aux_planes = BIT(1),
318
319 FORMAT_OVERRIDE(gen12_ccs_formats),
320 }, {
321 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
322 .display_ver = { 12, 13 },
323 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC_CC,
324
325 .ccs.cc_planes = BIT(2),
326 .ccs.packed_aux_planes = BIT(1),
327
328 FORMAT_OVERRIDE(gen12_ccs_cc_formats),
329 }, {
330 .modifier = I915_FORMAT_MOD_Yf_TILED_CCS,
331 .display_ver = { 9, 11 },
332 .plane_caps = INTEL_PLANE_CAP_TILING_Yf | INTEL_PLANE_CAP_CCS_RC,
333
334 .ccs.packed_aux_planes = BIT(1),
335
336 FORMAT_OVERRIDE(skl_ccs_formats),
337 }, {
338 .modifier = I915_FORMAT_MOD_Y_TILED_CCS,
339 .display_ver = { 9, 11 },
340 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,
341
342 .ccs.packed_aux_planes = BIT(1),
343
344 FORMAT_OVERRIDE(skl_ccs_formats),
345 }, {
346 .modifier = I915_FORMAT_MOD_Yf_TILED,
347 .display_ver = { 9, 11 },
348 .plane_caps = INTEL_PLANE_CAP_TILING_Yf,
349 }, {
350 .modifier = I915_FORMAT_MOD_Y_TILED,
351 .display_ver = { 9, 13 },
352 .plane_caps = INTEL_PLANE_CAP_TILING_Y,
353 }, {
354 .modifier = I915_FORMAT_MOD_X_TILED,
355 .display_ver = { 0, 29 },
356 .plane_caps = INTEL_PLANE_CAP_TILING_X,
357 }, {
358 .modifier = DRM_FORMAT_MOD_LINEAR,
359 .display_ver = DISPLAY_VER_ALL,
360 },
361};
362
363static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier)
364{
365 int i;
366
367 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++)
368 if (intel_modifiers[i].modifier == modifier)
369 return &intel_modifiers[i];
370
371 return NULL;
372}
373
374static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
375{
376 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
377
378 if (WARN_ON(!md))
379 return &intel_modifiers[0];
380
381 return md;
382}
383
384static const struct drm_format_info *
385lookup_format_info(const struct drm_format_info formats[],
386 int num_formats, u32 format)
387{
388 int i;
389
390 for (i = 0; i < num_formats; i++) {
391 if (formats[i].format == format)
392 return &formats[i];
393 }
394
395 return NULL;
396}
397
398unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
399{
400 const struct intel_modifier_desc *md;
401 u8 tiling_caps;
402
403 md = lookup_modifier_or_null(modifier: fb_modifier);
404 if (!md)
405 return I915_TILING_NONE;
406
407 tiling_caps = lookup_modifier_or_null(modifier: fb_modifier)->plane_caps &
408 INTEL_PLANE_CAP_TILING_MASK;
409
410 switch (tiling_caps) {
411 case INTEL_PLANE_CAP_TILING_Y:
412 return I915_TILING_Y;
413 case INTEL_PLANE_CAP_TILING_X:
414 return I915_TILING_X;
415 case INTEL_PLANE_CAP_TILING_4:
416 case INTEL_PLANE_CAP_TILING_Yf:
417 case INTEL_PLANE_CAP_TILING_NONE:
418 return I915_TILING_NONE;
419 default:
420 MISSING_CASE(tiling_caps);
421 return I915_TILING_NONE;
422 }
423}
424
425/**
426 * intel_fb_get_format_info: Get a modifier specific format information
427 * @pixel_format: pixel format
428 * @modifier: modifier
429 *
430 * Returns:
431 * Returns the format information for @pixel_format specific to @modifier,
432 * or %NULL if the modifier doesn't override the format.
433 */
434const struct drm_format_info *
435intel_fb_get_format_info(u32 pixel_format, u64 modifier)
436{
437 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
438
439 if (!md || !md->formats)
440 return NULL;
441
442 return lookup_format_info(formats: md->formats, num_formats: md->format_count, format: pixel_format);
443}
444
445static bool plane_caps_contain_any(u8 caps, u8 mask)
446{
447 return caps & mask;
448}
449
450static bool plane_caps_contain_all(u8 caps, u8 mask)
451{
452 return (caps & mask) == mask;
453}
454
455/**
456 * intel_fb_is_tiled_modifier: Check if a modifier is a tiled modifier type
457 * @modifier: Modifier to check
458 *
459 * Returns:
460 * Returns %true if @modifier is a tiled modifier.
461 */
462bool intel_fb_is_tiled_modifier(u64 modifier)
463{
464 return plane_caps_contain_any(caps: lookup_modifier(modifier)->plane_caps,
465 INTEL_PLANE_CAP_TILING_MASK);
466}
467
468/**
469 * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
470 * @modifier: Modifier to check
471 *
472 * Returns:
473 * Returns %true if @modifier is a render, render with color clear or
474 * media compression modifier.
475 */
476bool intel_fb_is_ccs_modifier(u64 modifier)
477{
478 return plane_caps_contain_any(caps: lookup_modifier(modifier)->plane_caps,
479 INTEL_PLANE_CAP_CCS_MASK);
480}
481
482/**
483 * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type
484 * @modifier: Modifier to check
485 *
486 * Returns:
487 * Returns %true if @modifier is a render with color clear modifier.
488 */
489bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
490{
491 return plane_caps_contain_any(caps: lookup_modifier(modifier)->plane_caps,
492 INTEL_PLANE_CAP_CCS_RC_CC);
493}
494
495/**
496 * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
497 * @modifier: Modifier to check
498 *
499 * Returns:
500 * Returns %true if @modifier is a media compression modifier.
501 */
502bool intel_fb_is_mc_ccs_modifier(u64 modifier)
503{
504 return plane_caps_contain_any(caps: lookup_modifier(modifier)->plane_caps,
505 INTEL_PLANE_CAP_CCS_MC);
506}
507
508/**
509 * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement.
510 * @modifier: Modifier to check
511 *
512 * Returns:
513 * Returns %true if @modifier requires 64k aligned physical pages.
514 */
515bool intel_fb_needs_64k_phys(u64 modifier)
516{
517 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
518
519 if (!md)
520 return false;
521
522 return plane_caps_contain_any(caps: md->plane_caps,
523 INTEL_PLANE_CAP_NEED64K_PHYS);
524}
525
526/**
527 * intel_fb_is_tile4_modifier: Check if a modifier is a tile4 modifier type
528 * @modifier: Modifier to check
529 *
530 * Returns:
531 * Returns %true if @modifier is a tile4 modifier.
532 */
533bool intel_fb_is_tile4_modifier(u64 modifier)
534{
535 return plane_caps_contain_any(caps: lookup_modifier(modifier)->plane_caps,
536 INTEL_PLANE_CAP_TILING_4);
537}
538
539static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
540 u8 display_ver_from, u8 display_ver_until)
541{
542 return md->display_ver.from <= display_ver_until &&
543 display_ver_from <= md->display_ver.until;
544}
545
546static bool plane_has_modifier(struct intel_display *display,
547 u8 plane_caps,
548 const struct intel_modifier_desc *md)
549{
550 struct drm_i915_private *i915 = to_i915(dev: display->drm);
551
552 if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until))
553 return false;
554
555 if (!plane_caps_contain_all(caps: plane_caps, mask: md->plane_caps))
556 return false;
557
558 /*
559 * Separate AuxCCS and Flat CCS modifiers to be run only on platforms
560 * where supported.
561 */
562 if (intel_fb_is_ccs_modifier(modifier: md->modifier) &&
563 HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
564 return false;
565
566 if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&
567 (GRAPHICS_VER(i915) < 20 || !display->platform.dgfx))
568 return false;
569
570 if (md->modifier == I915_FORMAT_MOD_4_TILED_LNL_CCS &&
571 (GRAPHICS_VER(i915) < 20 || display->platform.dgfx))
572 return false;
573
574 return true;
575}
576
577/**
578 * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities
579 * @display: display instance
580 * @plane_caps: capabilities for the plane the modifiers are queried for
581 *
582 * Returns:
583 * Returns the list of modifiers allowed by the @display platform and @plane_caps.
584 * The caller must free the returned buffer.
585 */
586u64 *intel_fb_plane_get_modifiers(struct intel_display *display,
587 u8 plane_caps)
588{
589 u64 *list, *p;
590 int count = 1; /* +1 for invalid modifier terminator */
591 int i;
592
593 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
594 if (plane_has_modifier(display, plane_caps, md: &intel_modifiers[i]))
595 count++;
596 }
597
598 list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);
599 if (drm_WARN_ON(display->drm, !list))
600 return NULL;
601
602 p = list;
603 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
604 if (plane_has_modifier(display, plane_caps, md: &intel_modifiers[i]))
605 *p++ = intel_modifiers[i].modifier;
606 }
607 *p++ = DRM_FORMAT_MOD_INVALID;
608
609 return list;
610}
611
612/**
613 * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane
614 * @plane: Plane to check the modifier support for
615 * @modifier: The modifier to check the support for
616 *
617 * Returns:
618 * %true if the @modifier is supported on @plane.
619 */
620bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
621{
622 int i;
623
624 for (i = 0; i < plane->base.modifier_count; i++)
625 if (plane->base.modifiers[i] == modifier)
626 return true;
627
628 return false;
629}
630
631static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
632 const struct drm_format_info *info)
633{
634 if (!info->is_yuv)
635 return false;
636
637 if (hweight8(md->ccs.planar_aux_planes) == 2)
638 return info->num_planes == 4;
639 else
640 return info->num_planes == 2;
641}
642
643/**
644 * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar
645 * @info: format to check
646 * @modifier: modifier used with the format
647 *
648 * Returns:
649 * %true if @info / @modifier is YUV semiplanar.
650 */
651bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
652 u64 modifier)
653{
654 return format_is_yuv_semiplanar(md: lookup_modifier(modifier), info);
655}
656
657static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md,
658 const struct drm_format_info *format)
659{
660 if (format_is_yuv_semiplanar(md, info: format))
661 return md->ccs.planar_aux_planes;
662 else
663 return md->ccs.packed_aux_planes;
664}
665
666/**
667 * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane
668 * @fb: Framebuffer
669 * @color_plane: color plane index to check
670 *
671 * Returns:
672 * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane.
673 */
674bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
675{
676 const struct intel_modifier_desc *md = lookup_modifier(modifier: fb->modifier);
677
678 return ccs_aux_plane_mask(md, format: fb->format) & BIT(color_plane);
679}
680
681/**
682 * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane
683 * @fb: Framebuffer
684 * @color_plane: color plane index to check
685 *
686 * Returns:
687 * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane.
688 */
689static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
690{
691 const struct intel_modifier_desc *md = lookup_modifier(modifier: fb->modifier);
692
693 return check_modifier_display_ver_range(md, display_ver_from: 12, display_ver_until: 14) &&
694 ccs_aux_plane_mask(md, format: fb->format) & BIT(color_plane);
695}
696
697/**
698 * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
699 * @fb: Framebuffer
700 *
701 * Returns:
702 * Returns the index of the color clear plane for @fb, or -1 if @fb is not a
703 * framebuffer using a render compression/color clear modifier.
704 */
705int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
706{
707 const struct intel_modifier_desc *md = lookup_modifier(modifier: fb->modifier);
708
709 if (!md->ccs.cc_planes)
710 return -1;
711
712 drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
713
714 return ilog2((int)md->ccs.cc_planes);
715}
716
717static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane)
718{
719 return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
720}
721
722bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
723{
724 return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
725 intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) ||
726 is_gen12_ccs_cc_plane(fb, color_plane);
727}
728
729int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
730{
731 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
732 (main_plane && main_plane >= fb->format->num_planes / 2));
733
734 return fb->format->num_planes / 2 + main_plane;
735}
736
737int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
738{
739 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
740 ccs_plane < fb->format->num_planes / 2);
741
742 if (is_gen12_ccs_cc_plane(fb, color_plane: ccs_plane))
743 return 0;
744
745 return ccs_plane - fb->format->num_planes / 2;
746}
747
748static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane)
749{
750 int main_plane = skl_ccs_to_main_plane(fb: &fb->base, ccs_plane);
751 unsigned int main_stride = fb->base.pitches[main_plane];
752 unsigned int main_tile_width = intel_tile_width_bytes(fb: &fb->base, color_plane: main_plane);
753
754 return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64;
755}
756
757int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
758{
759 const struct intel_modifier_desc *md = lookup_modifier(modifier: fb->modifier);
760 struct intel_display *display = to_intel_display(fb->dev);
761
762 if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)
763 return main_to_ccs_plane(fb, main_plane);
764 else if (DISPLAY_VER(display) < 11 &&
765 format_is_yuv_semiplanar(md, info: fb->format))
766 return 1;
767 else
768 return 0;
769}
770
771unsigned int intel_tile_size(struct intel_display *display)
772{
773 return DISPLAY_VER(display) == 2 ? 2048 : 4096;
774}
775
776unsigned int
777intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
778{
779 struct intel_display *display = to_intel_display(fb->dev);
780 struct drm_i915_private *i915 = to_i915(dev: display->drm);
781 unsigned int cpp = fb->format->cpp[color_plane];
782
783 switch (fb->modifier) {
784 case DRM_FORMAT_MOD_LINEAR:
785 return intel_tile_size(display);
786 case I915_FORMAT_MOD_X_TILED:
787 if (DISPLAY_VER(display) == 2)
788 return 128;
789 else
790 return 512;
791 case I915_FORMAT_MOD_4_TILED_BMG_CCS:
792 case I915_FORMAT_MOD_4_TILED_LNL_CCS:
793 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
794 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
795 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
796 case I915_FORMAT_MOD_4_TILED:
797 /*
798 * Each 4K tile consists of 64B(8*8) subtiles, with
799 * same shape as Y Tile(i.e 4*16B OWords)
800 */
801 return 128;
802 case I915_FORMAT_MOD_Y_TILED_CCS:
803 if (intel_fb_is_ccs_aux_plane(fb, color_plane))
804 return 128;
805 fallthrough;
806 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
807 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
808 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
809 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
810 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
811 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
812 if (intel_fb_is_ccs_aux_plane(fb, color_plane) ||
813 is_gen12_ccs_cc_plane(fb, color_plane))
814 return 64;
815 fallthrough;
816 case I915_FORMAT_MOD_Y_TILED:
817 if (DISPLAY_VER(display) == 2 || HAS_128_BYTE_Y_TILING(i915))
818 return 128;
819 else
820 return 512;
821 case I915_FORMAT_MOD_Yf_TILED_CCS:
822 if (intel_fb_is_ccs_aux_plane(fb, color_plane))
823 return 128;
824 fallthrough;
825 case I915_FORMAT_MOD_Yf_TILED:
826 switch (cpp) {
827 case 1:
828 return 64;
829 case 2:
830 case 4:
831 return 128;
832 case 8:
833 case 16:
834 return 256;
835 default:
836 MISSING_CASE(cpp);
837 return cpp;
838 }
839 break;
840 default:
841 MISSING_CASE(fb->modifier);
842 return cpp;
843 }
844}
845
846unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
847{
848 struct intel_display *display = to_intel_display(fb->dev);
849
850 return intel_tile_size(display) /
851 intel_tile_width_bytes(fb, color_plane);
852}
853
854/*
855 * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT
856 * page tile size.
857 */
858static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
859 unsigned int *tile_width,
860 unsigned int *tile_height)
861{
862 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
863 unsigned int cpp = fb->format->cpp[color_plane];
864
865 *tile_width = tile_width_bytes / cpp;
866 *tile_height = intel_tile_height(fb, color_plane);
867}
868
869/*
870 * Return the tile dimensions in pixel units, based on the tile block size.
871 * The block covers the full GTT page sized tile on all tiled surfaces and
872 * it's a 64 byte portion of the tile on TGL+ CCS surfaces.
873 */
874static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane,
875 unsigned int *tile_width,
876 unsigned int *tile_height)
877{
878 intel_tile_dims(fb, color_plane, tile_width, tile_height);
879
880 if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane))
881 *tile_height = 1;
882}
883
884unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane)
885{
886 unsigned int tile_width, tile_height;
887
888 intel_tile_dims(fb, color_plane, tile_width: &tile_width, tile_height: &tile_height);
889
890 return fb->pitches[color_plane] * tile_height;
891}
892
893unsigned int
894intel_fb_align_height(const struct drm_framebuffer *fb,
895 int color_plane, unsigned int height)
896{
897 unsigned int tile_height = intel_tile_height(fb, color_plane);
898
899 return ALIGN(height, tile_height);
900}
901
902bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier)
903{
904 return HAS_DPT(display) && modifier != DRM_FORMAT_MOD_LINEAR;
905}
906
907bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
908{
909 struct intel_display *display = to_intel_display(fb->dev);
910
911 return display->params.enable_dpt &&
912 intel_fb_modifier_uses_dpt(display, modifier: fb->modifier);
913}
914
915void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
916 const struct drm_framebuffer *fb,
917 int color_plane)
918{
919 int main_plane;
920
921 if (color_plane == 0) {
922 *hsub = 1;
923 *vsub = 1;
924
925 return;
926 }
927
928 /*
929 * TODO: Deduct the subsampling from the char block for all CCS
930 * formats and planes.
931 */
932 if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) {
933 *hsub = fb->format->hsub;
934 *vsub = fb->format->vsub;
935
936 return;
937 }
938
939 main_plane = skl_ccs_to_main_plane(fb, ccs_plane: color_plane);
940 *hsub = drm_format_info_block_width(info: fb->format, plane: color_plane) /
941 drm_format_info_block_width(info: fb->format, plane: main_plane);
942
943 /*
944 * The min stride check in the core framebuffer_check() function
945 * assumes that format->hsub applies to every plane except for the
946 * first plane. That's incorrect for the CCS AUX plane of the first
947 * plane, but for the above check to pass we must define the block
948 * width with that subsampling applied to it. Adjust the width here
949 * accordingly, so we can calculate the actual subsampling factor.
950 */
951 if (main_plane == 0)
952 *hsub *= fb->format->hsub;
953
954 *vsub = 32;
955}
956
957static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h)
958{
959 int main_plane = intel_fb_is_ccs_aux_plane(fb: &fb->base, color_plane) ?
960 skl_ccs_to_main_plane(fb: &fb->base, ccs_plane: color_plane) : 0;
961 unsigned int main_width = fb->base.width;
962 unsigned int main_height = fb->base.height;
963 int main_hsub, main_vsub;
964 int hsub, vsub;
965
966 intel_fb_plane_get_subsampling(hsub: &main_hsub, vsub: &main_vsub, fb: &fb->base, color_plane: main_plane);
967 intel_fb_plane_get_subsampling(hsub: &hsub, vsub: &vsub, fb: &fb->base, color_plane);
968
969 *w = DIV_ROUND_UP(main_width, main_hsub * hsub);
970 *h = DIV_ROUND_UP(main_height, main_vsub * vsub);
971}
972
973static u32 intel_adjust_tile_offset(int *x, int *y,
974 unsigned int tile_width,
975 unsigned int tile_height,
976 unsigned int tile_size,
977 unsigned int pitch_tiles,
978 u32 old_offset,
979 u32 new_offset)
980{
981 unsigned int pitch_pixels = pitch_tiles * tile_width;
982 unsigned int tiles;
983
984 WARN_ON(old_offset & (tile_size - 1));
985 WARN_ON(new_offset & (tile_size - 1));
986 WARN_ON(new_offset > old_offset);
987
988 tiles = (old_offset - new_offset) / tile_size;
989
990 *y += tiles / pitch_tiles * tile_height;
991 *x += tiles % pitch_tiles * tile_width;
992
993 /* minimize x in case it got needlessly big */
994 *y += *x / pitch_pixels * tile_height;
995 *x %= pitch_pixels;
996
997 return new_offset;
998}
999
1000static u32 intel_adjust_linear_offset(int *x, int *y,
1001 unsigned int cpp,
1002 unsigned int pitch,
1003 u32 old_offset,
1004 u32 new_offset)
1005{
1006 old_offset += *y * pitch + *x * cpp;
1007
1008 *y = (old_offset - new_offset) / pitch;
1009 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
1010
1011 return new_offset;
1012}
1013
1014static u32 intel_adjust_aligned_offset(int *x, int *y,
1015 const struct drm_framebuffer *fb,
1016 int color_plane,
1017 unsigned int rotation,
1018 unsigned int pitch,
1019 u32 old_offset, u32 new_offset)
1020{
1021 struct intel_display *display = to_intel_display(fb->dev);
1022 unsigned int cpp = fb->format->cpp[color_plane];
1023
1024 drm_WARN_ON(display->drm, new_offset > old_offset);
1025
1026 if (!is_surface_linear(fb, color_plane)) {
1027 unsigned int tile_size, tile_width, tile_height;
1028 unsigned int pitch_tiles;
1029
1030 tile_size = intel_tile_size(display);
1031 intel_tile_dims(fb, color_plane, tile_width: &tile_width, tile_height: &tile_height);
1032
1033 if (drm_rotation_90_or_270(rotation)) {
1034 pitch_tiles = pitch / tile_height;
1035 swap(tile_width, tile_height);
1036 } else {
1037 pitch_tiles = pitch / (tile_width * cpp);
1038 }
1039
1040 intel_adjust_tile_offset(x, y, tile_width, tile_height,
1041 tile_size, pitch_tiles,
1042 old_offset, new_offset);
1043 } else {
1044 intel_adjust_linear_offset(x, y, cpp, pitch,
1045 old_offset, new_offset);
1046 }
1047
1048 return new_offset;
1049}
1050
1051/*
1052 * Adjust the tile offset by moving the difference into
1053 * the x/y offsets.
1054 */
1055u32 intel_plane_adjust_aligned_offset(int *x, int *y,
1056 const struct intel_plane_state *plane_state,
1057 int color_plane,
1058 u32 old_offset, u32 new_offset)
1059{
1060 return intel_adjust_aligned_offset(x, y, fb: plane_state->hw.fb, color_plane,
1061 rotation: plane_state->hw.rotation,
1062 pitch: plane_state->view.color_plane[color_plane].mapping_stride,
1063 old_offset, new_offset);
1064}
1065
1066/*
1067 * Computes the aligned offset to the base tile and adjusts
1068 * x, y. bytes per pixel is assumed to be a power-of-two.
1069 *
1070 * In the 90/270 rotated case, x and y are assumed
1071 * to be already rotated to match the rotated GTT view, and
1072 * pitch is the tile_height aligned framebuffer height.
1073 *
1074 * This function is used when computing the derived information
1075 * under intel_framebuffer, so using any of that information
1076 * here is not allowed. Anything under drm_framebuffer can be
1077 * used. This is why the user has to pass in the pitch since it
1078 * is specified in the rotated orientation.
1079 */
1080static u32 intel_compute_aligned_offset(struct intel_display *display,
1081 int *x, int *y,
1082 const struct drm_framebuffer *fb,
1083 int color_plane,
1084 unsigned int pitch,
1085 unsigned int rotation,
1086 unsigned int alignment)
1087{
1088 unsigned int cpp = fb->format->cpp[color_plane];
1089 u32 offset, offset_aligned;
1090
1091 if (!is_surface_linear(fb, color_plane)) {
1092 unsigned int tile_size, tile_width, tile_height;
1093 unsigned int tile_rows, tiles, pitch_tiles;
1094
1095 tile_size = intel_tile_size(display);
1096 intel_tile_dims(fb, color_plane, tile_width: &tile_width, tile_height: &tile_height);
1097
1098 if (drm_rotation_90_or_270(rotation)) {
1099 pitch_tiles = pitch / tile_height;
1100 swap(tile_width, tile_height);
1101 } else {
1102 pitch_tiles = pitch / (tile_width * cpp);
1103 }
1104
1105 tile_rows = *y / tile_height;
1106 *y %= tile_height;
1107
1108 tiles = *x / tile_width;
1109 *x %= tile_width;
1110
1111 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
1112
1113 offset_aligned = offset;
1114 if (alignment)
1115 offset_aligned = rounddown(offset_aligned, alignment);
1116
1117 intel_adjust_tile_offset(x, y, tile_width, tile_height,
1118 tile_size, pitch_tiles,
1119 old_offset: offset, new_offset: offset_aligned);
1120 } else {
1121 offset = *y * pitch + *x * cpp;
1122 offset_aligned = offset;
1123 if (alignment) {
1124 offset_aligned = rounddown(offset_aligned, alignment);
1125 *y = (offset % alignment) / pitch;
1126 *x = ((offset % alignment) - *y * pitch) / cpp;
1127 } else {
1128 *y = *x = 0;
1129 }
1130 }
1131
1132 return offset_aligned;
1133}
1134
1135u32 intel_plane_compute_aligned_offset(int *x, int *y,
1136 const struct intel_plane_state *plane_state,
1137 int color_plane)
1138{
1139 struct intel_display *display = to_intel_display(plane_state);
1140 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1141 const struct drm_framebuffer *fb = plane_state->hw.fb;
1142 unsigned int rotation = plane_state->hw.rotation;
1143 unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride;
1144 unsigned int alignment = plane->min_alignment(plane, fb, color_plane);
1145
1146 return intel_compute_aligned_offset(display, x, y, fb, color_plane,
1147 pitch, rotation, alignment);
1148}
1149
1150/* Convert the fb->offset[] into x/y offsets */
1151static int intel_fb_offset_to_xy(int *x, int *y,
1152 const struct drm_framebuffer *fb,
1153 int color_plane)
1154{
1155 struct intel_display *display = to_intel_display(fb->dev);
1156 unsigned int height, alignment, unused;
1157
1158 if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
1159 alignment = intel_tile_size(display);
1160 else
1161 alignment = 0;
1162
1163 if (alignment != 0 && fb->offsets[color_plane] % alignment) {
1164 drm_dbg_kms(display->drm,
1165 "Misaligned offset 0x%08x for color plane %d\n",
1166 fb->offsets[color_plane], color_plane);
1167 return -EINVAL;
1168 }
1169
1170 height = drm_format_info_plane_height(info: fb->format, height: fb->height, plane: color_plane);
1171 height = ALIGN(height, intel_tile_height(fb, color_plane));
1172
1173 /* Catch potential overflows early */
1174 if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]),
1175 fb->offsets[color_plane], &unused)) {
1176 drm_dbg_kms(display->drm,
1177 "Bad offset 0x%08x or pitch %d for color plane %d\n",
1178 fb->offsets[color_plane], fb->pitches[color_plane],
1179 color_plane);
1180 return -ERANGE;
1181 }
1182
1183 *x = 0;
1184 *y = 0;
1185
1186 intel_adjust_aligned_offset(x, y,
1187 fb, color_plane, DRM_MODE_ROTATE_0,
1188 pitch: fb->pitches[color_plane],
1189 old_offset: fb->offsets[color_plane], new_offset: 0);
1190
1191 return 0;
1192}
1193
1194static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y)
1195{
1196 struct intel_display *display = to_intel_display(fb->dev);
1197 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1198 int main_plane;
1199 int hsub, vsub;
1200 int tile_width, tile_height;
1201 int ccs_x, ccs_y;
1202 int main_x, main_y;
1203
1204 if (!intel_fb_is_ccs_aux_plane(fb, color_plane: ccs_plane))
1205 return 0;
1206
1207 /*
1208 * While all the tile dimensions are based on a 2k or 4k GTT page size
1209 * here the main and CCS coordinates must match only within a (64 byte
1210 * on TGL+) block inside the tile.
1211 */
1212 intel_tile_block_dims(fb, color_plane: ccs_plane, tile_width: &tile_width, tile_height: &tile_height);
1213 intel_fb_plane_get_subsampling(hsub: &hsub, vsub: &vsub, fb, color_plane: ccs_plane);
1214
1215 tile_width *= hsub;
1216 tile_height *= vsub;
1217
1218 ccs_x = (x * hsub) % tile_width;
1219 ccs_y = (y * vsub) % tile_height;
1220
1221 main_plane = skl_ccs_to_main_plane(fb, ccs_plane);
1222 main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width;
1223 main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height;
1224
1225 /*
1226 * CCS doesn't have its own x/y offset register, so the intra CCS tile
1227 * x/y offsets must match between CCS and the main surface.
1228 */
1229 if (main_x != ccs_x || main_y != ccs_y) {
1230 drm_dbg_kms(display->drm,
1231 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
1232 main_x, main_y, ccs_x, ccs_y,
1233 intel_fb->normal_view.color_plane[main_plane].x,
1234 intel_fb->normal_view.color_plane[main_plane].y,
1235 x, y);
1236 return -EINVAL;
1237 }
1238
1239 return 0;
1240}
1241
1242static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
1243{
1244 struct intel_display *display = to_intel_display(plane_state);
1245 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1246 const struct drm_framebuffer *fb = plane_state->hw.fb;
1247 int i;
1248
1249 /* We don't want to deal with remapping with cursors */
1250 if (plane->id == PLANE_CURSOR)
1251 return false;
1252
1253 /*
1254 * The display engine limits already match/exceed the
1255 * render engine limits, so not much point in remapping.
1256 * Would also need to deal with the fence POT alignment
1257 * and gen2 2KiB GTT tile size.
1258 */
1259 if (DISPLAY_VER(display) < 4)
1260 return false;
1261
1262 /*
1263 * The new CCS hash mode isn't compatible with remapping as
1264 * the virtual address of the pages affects the compressed data.
1265 */
1266 if (intel_fb_is_ccs_modifier(modifier: fb->modifier))
1267 return false;
1268
1269 /* Linear needs a page aligned stride for remapping */
1270 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1271 unsigned int alignment = intel_tile_size(display) - 1;
1272
1273 for (i = 0; i < fb->format->num_planes; i++) {
1274 if (fb->pitches[i] & alignment)
1275 return false;
1276 }
1277 }
1278
1279 return true;
1280}
1281
1282bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
1283{
1284 struct intel_display *display = to_intel_display(fb->base.dev);
1285
1286 return (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) &&
1287 intel_fb_uses_dpt(fb: &fb->base);
1288}
1289
1290bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
1291{
1292 struct intel_display *display = to_intel_display(plane_state);
1293 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1294
1295 return DISPLAY_VER(display) < 4 ||
1296 (plane->fbc && !plane_state->no_fbc_reason &&
1297 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
1298}
1299
1300static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
1301{
1302 if (drm_rotation_90_or_270(rotation))
1303 return fb->rotated_view.color_plane[color_plane].mapping_stride;
1304 else if (intel_fb_needs_pot_stride_remap(fb))
1305 return fb->remapped_view.color_plane[color_plane].mapping_stride;
1306 else
1307 return fb->normal_view.color_plane[color_plane].mapping_stride;
1308}
1309
1310static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
1311{
1312 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1313 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);
1314 unsigned int rotation = plane_state->hw.rotation;
1315 u32 stride, max_stride;
1316
1317 /*
1318 * No remapping for invisible planes since we don't have
1319 * an actual source viewport to remap.
1320 */
1321 if (!plane_state->uapi.visible)
1322 return false;
1323
1324 if (!intel_plane_can_remap(plane_state))
1325 return false;
1326
1327 /*
1328 * FIXME: aux plane limits on gen9+ are
1329 * unclear in Bspec, for now no checking.
1330 */
1331 stride = intel_fb_pitch(fb, color_plane: 0, rotation);
1332 max_stride = plane->max_stride(plane, fb->base.format->format,
1333 fb->base.modifier, rotation);
1334
1335 return stride > max_stride;
1336}
1337
1338static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane,
1339 int plane_width, int *x, int *y)
1340{
1341 struct intel_display *display = to_intel_display(fb->base.dev);
1342 struct drm_gem_object *obj = intel_fb_bo(fb: &fb->base);
1343 int ret;
1344
1345 ret = intel_fb_offset_to_xy(x, y, fb: &fb->base, color_plane);
1346 if (ret) {
1347 drm_dbg_kms(display->drm,
1348 "bad fb plane %d offset: 0x%x\n",
1349 color_plane, fb->base.offsets[color_plane]);
1350 return ret;
1351 }
1352
1353 ret = intel_fb_check_ccs_xy(fb: &fb->base, ccs_plane: color_plane, x: *x, y: *y);
1354 if (ret)
1355 return ret;
1356
1357 /*
1358 * The fence (if used) is aligned to the start of the object
1359 * so having the framebuffer wrap around across the edge of the
1360 * fenced region doesn't really work. We have no API to configure
1361 * the fence start offset within the object (nor could we probably
1362 * on gen2/3). So it's just easier if we just require that the
1363 * fb layout agrees with the fence layout. We already check that the
1364 * fb stride matches the fence stride elsewhere.
1365 */
1366 if (color_plane == 0 && intel_bo_is_tiled(obj) &&
1367 (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) {
1368 drm_dbg_kms(display->drm,
1369 "bad fb plane %d offset: 0x%x\n",
1370 color_plane, fb->base.offsets[color_plane]);
1371 return -EINVAL;
1372 }
1373
1374 return 0;
1375}
1376
1377static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y)
1378{
1379 struct intel_display *display = to_intel_display(fb->base.dev);
1380 unsigned int tile_size = intel_tile_size(display);
1381 u32 offset;
1382
1383 offset = intel_compute_aligned_offset(display, x, y, fb: &fb->base, color_plane,
1384 pitch: fb->base.pitches[color_plane],
1385 DRM_MODE_ROTATE_0,
1386 alignment: tile_size);
1387
1388 return offset / tile_size;
1389}
1390
1391struct fb_plane_view_dims {
1392 unsigned int width, height;
1393 unsigned int tile_width, tile_height;
1394};
1395
1396static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane,
1397 unsigned int width, unsigned int height,
1398 struct fb_plane_view_dims *dims)
1399{
1400 dims->width = width;
1401 dims->height = height;
1402
1403 intel_tile_dims(fb: &fb->base, color_plane, tile_width: &dims->tile_width, tile_height: &dims->tile_height);
1404}
1405
1406static unsigned int
1407plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
1408 const struct fb_plane_view_dims *dims)
1409{
1410 return DIV_ROUND_UP(fb->base.pitches[color_plane],
1411 dims->tile_width * fb->base.format->cpp[color_plane]);
1412}
1413
1414static unsigned int
1415plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
1416 unsigned int pitch_tiles)
1417{
1418 if (intel_fb_needs_pot_stride_remap(fb)) {
1419 /*
1420 * ADL_P, the only platform needing a POT stride has a minimum
1421 * of 8 main surface tiles.
1422 */
1423 return roundup_pow_of_two(max(pitch_tiles, 8u));
1424 } else {
1425 return pitch_tiles;
1426 }
1427}
1428
1429static unsigned int
1430plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane,
1431 unsigned int tile_width,
1432 unsigned int src_stride_tiles, unsigned int dst_stride_tiles)
1433{
1434 struct intel_display *display = to_intel_display(fb->base.dev);
1435 unsigned int stride_tiles;
1436
1437 if ((display->platform.alderlake_p || DISPLAY_VER(display) >= 14) &&
1438 src_stride_tiles < dst_stride_tiles)
1439 stride_tiles = src_stride_tiles;
1440 else
1441 stride_tiles = dst_stride_tiles;
1442
1443 return stride_tiles * tile_width * fb->base.format->cpp[color_plane];
1444}
1445
1446static unsigned int
1447plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane,
1448 const struct fb_plane_view_dims *dims,
1449 int x)
1450{
1451 return DIV_ROUND_UP(x + dims->width, dims->tile_width);
1452}
1453
1454static unsigned int
1455plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane,
1456 const struct fb_plane_view_dims *dims,
1457 int y)
1458{
1459 return DIV_ROUND_UP(y + dims->height, dims->tile_height);
1460}
1461
1462static unsigned int
1463plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane,
1464 const struct fb_plane_view_dims *dims,
1465 int x, int y)
1466{
1467 struct intel_display *display = to_intel_display(fb->base.dev);
1468 unsigned int size;
1469
1470 size = (y + dims->height) * fb->base.pitches[color_plane] +
1471 x * fb->base.format->cpp[color_plane];
1472
1473 return DIV_ROUND_UP(size, intel_tile_size(display));
1474}
1475
1476#define assign_chk_ovf(display, var, val) ({ \
1477 drm_WARN_ON((display)->drm, overflows_type(val, var)); \
1478 (var) = (val); \
1479})
1480
1481#define assign_bfld_chk_ovf(display, var, val) ({ \
1482 (var) = (val); \
1483 drm_WARN_ON((display)->drm, (var) != (val)); \
1484 (var); \
1485})
1486
1487static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane,
1488 const struct fb_plane_view_dims *dims,
1489 u32 obj_offset, u32 gtt_offset, int x, int y,
1490 struct intel_fb_view *view)
1491{
1492 struct intel_display *display = to_intel_display(fb->base.dev);
1493 struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane];
1494 struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane];
1495 unsigned int tile_width = dims->tile_width;
1496 unsigned int tile_height = dims->tile_height;
1497 unsigned int tile_size = intel_tile_size(display);
1498 struct drm_rect r;
1499 u32 size = 0;
1500
1501 assign_bfld_chk_ovf(display, remap_info->offset, obj_offset);
1502
1503 if (intel_fb_is_gen12_ccs_aux_plane(fb: &fb->base, color_plane)) {
1504 remap_info->linear = 1;
1505
1506 assign_chk_ovf(display, remap_info->size,
1507 plane_view_linear_tiles(fb, color_plane, dims, x, y));
1508 } else {
1509 remap_info->linear = 0;
1510
1511 assign_chk_ovf(display, remap_info->src_stride,
1512 plane_view_src_stride_tiles(fb, color_plane, dims));
1513 assign_chk_ovf(display, remap_info->width,
1514 plane_view_width_tiles(fb, color_plane, dims, x));
1515 assign_chk_ovf(display, remap_info->height,
1516 plane_view_height_tiles(fb, color_plane, dims, y));
1517 }
1518
1519 if (view->gtt.type == I915_GTT_VIEW_ROTATED) {
1520 drm_WARN_ON(display->drm, remap_info->linear);
1521 check_array_bounds(display, view->gtt.rotated.plane, color_plane);
1522
1523 assign_chk_ovf(display, remap_info->dst_stride,
1524 plane_view_dst_stride_tiles(fb, color_plane, remap_info->height));
1525
1526 /* rotate the x/y offsets to match the GTT view */
1527 drm_rect_init(r: &r, x, y, width: dims->width, height: dims->height);
1528 drm_rect_rotate(r: &r,
1529 width: remap_info->width * tile_width,
1530 height: remap_info->height * tile_height,
1531 DRM_MODE_ROTATE_270);
1532
1533 color_plane_info->x = r.x1;
1534 color_plane_info->y = r.y1;
1535
1536 color_plane_info->mapping_stride = remap_info->dst_stride * tile_height;
1537 color_plane_info->scanout_stride = color_plane_info->mapping_stride;
1538
1539 size += remap_info->dst_stride * remap_info->width;
1540
1541 /* rotate the tile dimensions to match the GTT view */
1542 swap(tile_width, tile_height);
1543 } else {
1544 drm_WARN_ON(display->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED);
1545
1546 check_array_bounds(display, view->gtt.remapped.plane, color_plane);
1547
1548 if (view->gtt.remapped.plane_alignment) {
1549 u32 aligned_offset = ALIGN(gtt_offset,
1550 view->gtt.remapped.plane_alignment);
1551
1552 size += aligned_offset - gtt_offset;
1553 gtt_offset = aligned_offset;
1554 }
1555
1556 color_plane_info->x = x;
1557 color_plane_info->y = y;
1558
1559 if (remap_info->linear) {
1560 color_plane_info->mapping_stride = fb->base.pitches[color_plane];
1561 color_plane_info->scanout_stride = color_plane_info->mapping_stride;
1562
1563 size += remap_info->size;
1564 } else {
1565 unsigned int dst_stride;
1566
1567 /*
1568 * The hardware automagically calculates the CCS AUX surface
1569 * stride from the main surface stride so can't really remap a
1570 * smaller subset (unless we'd remap in whole AUX page units).
1571 */
1572 if (intel_fb_needs_pot_stride_remap(fb) &&
1573 intel_fb_is_ccs_modifier(modifier: fb->base.modifier))
1574 dst_stride = remap_info->src_stride;
1575 else
1576 dst_stride = remap_info->width;
1577
1578 dst_stride = plane_view_dst_stride_tiles(fb, color_plane, pitch_tiles: dst_stride);
1579
1580 assign_chk_ovf(display, remap_info->dst_stride, dst_stride);
1581 color_plane_info->mapping_stride = dst_stride *
1582 tile_width *
1583 fb->base.format->cpp[color_plane];
1584 color_plane_info->scanout_stride =
1585 plane_view_scanout_stride(fb, color_plane, tile_width,
1586 src_stride_tiles: remap_info->src_stride,
1587 dst_stride_tiles: dst_stride);
1588
1589 size += dst_stride * remap_info->height;
1590 }
1591 }
1592
1593 /*
1594 * We only keep the x/y offsets, so push all of the gtt offset into
1595 * the x/y offsets. x,y will hold the first pixel of the framebuffer
1596 * plane from the start of the remapped/rotated gtt mapping.
1597 */
1598 if (remap_info->linear)
1599 intel_adjust_linear_offset(x: &color_plane_info->x, y: &color_plane_info->y,
1600 cpp: fb->base.format->cpp[color_plane],
1601 pitch: color_plane_info->mapping_stride,
1602 old_offset: gtt_offset * tile_size, new_offset: 0);
1603 else
1604 intel_adjust_tile_offset(x: &color_plane_info->x, y: &color_plane_info->y,
1605 tile_width, tile_height,
1606 tile_size, pitch_tiles: remap_info->dst_stride,
1607 old_offset: gtt_offset * tile_size, new_offset: 0);
1608
1609 return size;
1610}
1611
1612#undef assign_chk_ovf
1613
1614/* Return number of tiles @color_plane needs. */
1615static unsigned int
1616calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane,
1617 const struct fb_plane_view_dims *dims,
1618 int x, int y)
1619{
1620 unsigned int tiles;
1621
1622 if (is_surface_linear(fb: &fb->base, color_plane)) {
1623 tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y);
1624 } else {
1625 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) *
1626 plane_view_height_tiles(fb, color_plane, dims, y);
1627 /*
1628 * If the plane isn't horizontally tile aligned,
1629 * we need one more tile.
1630 */
1631 if (x != 0)
1632 tiles++;
1633 }
1634
1635 return tiles;
1636}
1637
1638static void intel_fb_view_init(struct intel_display *display,
1639 struct intel_fb_view *view,
1640 enum i915_gtt_view_type view_type)
1641{
1642 memset(s: view, c: 0, n: sizeof(*view));
1643 view->gtt.type = view_type;
1644
1645 if (view_type == I915_GTT_VIEW_REMAPPED &&
1646 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14))
1647 view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE;
1648}
1649
1650bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb)
1651{
1652 struct intel_display *display = to_intel_display(fb->base.dev);
1653
1654 if (DISPLAY_VER(display) >= 13)
1655 return false;
1656
1657 return fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||
1658 fb->base.modifier == I915_FORMAT_MOD_Yf_TILED;
1659}
1660
1661static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb)
1662{
1663 struct intel_display *display = to_intel_display(fb->dev);
1664 struct intel_plane *plane;
1665 unsigned int min_alignment = 0;
1666
1667 for_each_intel_plane(display->drm, plane) {
1668 unsigned int plane_min_alignment;
1669
1670 if (!drm_plane_has_format(plane: &plane->base, format: fb->format->format, modifier: fb->modifier))
1671 continue;
1672
1673 plane_min_alignment = plane->min_alignment(plane, fb, 0);
1674
1675 drm_WARN_ON(display->drm, plane_min_alignment &&
1676 !is_power_of_2(plane_min_alignment));
1677
1678 if (intel_plane_needs_physical(plane))
1679 continue;
1680
1681 min_alignment = max(min_alignment, plane_min_alignment);
1682 }
1683
1684 return min_alignment;
1685}
1686
1687static unsigned int intel_fb_vtd_guard(const struct drm_framebuffer *fb)
1688{
1689 struct intel_display *display = to_intel_display(fb->dev);
1690 struct intel_plane *plane;
1691 unsigned int vtd_guard = 0;
1692
1693 for_each_intel_plane(display->drm, plane) {
1694 if (!drm_plane_has_format(plane: &plane->base, format: fb->format->format, modifier: fb->modifier))
1695 continue;
1696
1697 vtd_guard = max_t(unsigned int, vtd_guard, plane->vtd_guard);
1698 }
1699
1700 return vtd_guard;
1701}
1702
1703int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb)
1704{
1705 struct drm_gem_object *obj = intel_fb_bo(fb: &fb->base);
1706 u32 gtt_offset_rotated = 0;
1707 u32 gtt_offset_remapped = 0;
1708 unsigned int max_size = 0;
1709 int i, num_planes = fb->base.format->num_planes;
1710 unsigned int tile_size = intel_tile_size(display);
1711
1712 intel_fb_view_init(display, view: &fb->normal_view, view_type: I915_GTT_VIEW_NORMAL);
1713
1714 drm_WARN_ON(display->drm,
1715 intel_fb_supports_90_270_rotation(fb) &&
1716 intel_fb_needs_pot_stride_remap(fb));
1717
1718 if (intel_fb_supports_90_270_rotation(fb))
1719 intel_fb_view_init(display, view: &fb->rotated_view, view_type: I915_GTT_VIEW_ROTATED);
1720 if (intel_fb_needs_pot_stride_remap(fb))
1721 intel_fb_view_init(display, view: &fb->remapped_view, view_type: I915_GTT_VIEW_REMAPPED);
1722
1723 for (i = 0; i < num_planes; i++) {
1724 struct fb_plane_view_dims view_dims;
1725 unsigned int width, height;
1726 unsigned int size;
1727 u32 offset;
1728 int x, y;
1729 int ret;
1730
1731 /*
1732 * Plane 2 of Render Compression with Clear Color fb modifier
1733 * is consumed by the driver and not passed to DE. Skip the
1734 * arithmetic related to alignment and offset calculation.
1735 */
1736 if (is_gen12_ccs_cc_plane(fb: &fb->base, color_plane: i)) {
1737 unsigned int end;
1738
1739 if (!IS_ALIGNED(fb->base.offsets[i], 64)) {
1740 drm_dbg_kms(display->drm,
1741 "fb misaligned clear color plane %d offset (0x%x)\n",
1742 i, fb->base.offsets[i]);
1743 return -EINVAL;
1744 }
1745
1746 if (check_add_overflow(fb->base.offsets[i], 64, &end)) {
1747 drm_dbg_kms(display->drm,
1748 "fb bad clear color plane %d offset (0x%x)\n",
1749 i, fb->base.offsets[i]);
1750 return -EINVAL;
1751 }
1752
1753 max_size = max(max_size, DIV_ROUND_UP(end, tile_size));
1754 continue;
1755 }
1756
1757 intel_fb_plane_dims(fb, color_plane: i, w: &width, h: &height);
1758
1759 ret = convert_plane_offset_to_xy(fb, color_plane: i, plane_width: width, x: &x, y: &y);
1760 if (ret)
1761 return ret;
1762
1763 init_plane_view_dims(fb, color_plane: i, width, height, dims: &view_dims);
1764
1765 /*
1766 * First pixel of the framebuffer from
1767 * the start of the normal gtt mapping.
1768 */
1769 fb->normal_view.color_plane[i].x = x;
1770 fb->normal_view.color_plane[i].y = y;
1771 fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i];
1772 fb->normal_view.color_plane[i].scanout_stride =
1773 fb->normal_view.color_plane[i].mapping_stride;
1774
1775 offset = calc_plane_aligned_offset(fb, color_plane: i, x: &x, y: &y);
1776
1777 if (intel_fb_supports_90_270_rotation(fb))
1778 gtt_offset_rotated += calc_plane_remap_info(fb, color_plane: i, dims: &view_dims,
1779 obj_offset: offset, gtt_offset: gtt_offset_rotated, x, y,
1780 view: &fb->rotated_view);
1781
1782 if (intel_fb_needs_pot_stride_remap(fb))
1783 gtt_offset_remapped += calc_plane_remap_info(fb, color_plane: i, dims: &view_dims,
1784 obj_offset: offset, gtt_offset: gtt_offset_remapped, x, y,
1785 view: &fb->remapped_view);
1786
1787 size = calc_plane_normal_size(fb, color_plane: i, dims: &view_dims, x, y);
1788 /* how many tiles in total needed in the bo */
1789 max_size = max(max_size, offset + size);
1790 }
1791
1792 if (mul_u32_u32(a: max_size, b: tile_size) > obj->size) {
1793 drm_dbg_kms(display->drm,
1794 "fb too big for bo (need %llu bytes, have %zu bytes)\n",
1795 mul_u32_u32(max_size, tile_size), obj->size);
1796 return -EINVAL;
1797 }
1798
1799 fb->min_alignment = intel_fb_min_alignment(fb: &fb->base);
1800 fb->vtd_guard = intel_fb_vtd_guard(fb: &fb->base);
1801
1802 return 0;
1803}
1804
1805unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb,
1806 const struct intel_fb_view *view,
1807 unsigned int rotation)
1808{
1809 unsigned int vtd_guard;
1810 int color_plane;
1811
1812 vtd_guard = to_intel_framebuffer(fb)->vtd_guard;
1813 if (!vtd_guard)
1814 return 0;
1815
1816 for (color_plane = 0; color_plane < fb->format->num_planes; color_plane++) {
1817 unsigned int stride, tile;
1818
1819 if (intel_fb_is_ccs_aux_plane(fb, color_plane) ||
1820 is_gen12_ccs_cc_plane(fb, color_plane))
1821 continue;
1822
1823 stride = view->color_plane[color_plane].mapping_stride;
1824
1825 if (drm_rotation_90_or_270(rotation))
1826 tile = intel_tile_height(fb, color_plane);
1827 else
1828 tile = intel_tile_width_bytes(fb, color_plane);
1829
1830 vtd_guard = max(vtd_guard, DIV_ROUND_UP(stride, tile));
1831 }
1832
1833 return vtd_guard;
1834}
1835
1836static void intel_plane_remap_gtt(struct intel_plane_state *plane_state)
1837{
1838 struct intel_display *display = to_intel_display(plane_state);
1839 struct drm_framebuffer *fb = plane_state->hw.fb;
1840 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1841 unsigned int rotation = plane_state->hw.rotation;
1842 int i, num_planes = fb->format->num_planes;
1843 unsigned int src_x, src_y;
1844 unsigned int src_w, src_h;
1845 u32 gtt_offset = 0;
1846
1847 intel_fb_view_init(display, view: &plane_state->view,
1848 view_type: drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED :
1849 I915_GTT_VIEW_REMAPPED);
1850
1851 src_x = plane_state->uapi.src.x1 >> 16;
1852 src_y = plane_state->uapi.src.y1 >> 16;
1853 src_w = drm_rect_width(r: &plane_state->uapi.src) >> 16;
1854 src_h = drm_rect_height(r: &plane_state->uapi.src) >> 16;
1855
1856 drm_WARN_ON(display->drm, intel_fb_is_ccs_modifier(fb->modifier));
1857
1858 /* Make src coordinates relative to the viewport */
1859 drm_rect_translate(r: &plane_state->uapi.src,
1860 dx: -(src_x << 16), dy: -(src_y << 16));
1861
1862 /* Rotate src coordinates to match rotated GTT view */
1863 if (drm_rotation_90_or_270(rotation))
1864 drm_rect_rotate(r: &plane_state->uapi.src,
1865 width: src_w << 16, height: src_h << 16,
1866 DRM_MODE_ROTATE_270);
1867
1868 for (i = 0; i < num_planes; i++) {
1869 unsigned int hsub = i ? fb->format->hsub : 1;
1870 unsigned int vsub = i ? fb->format->vsub : 1;
1871 struct fb_plane_view_dims view_dims;
1872 unsigned int width, height;
1873 unsigned int x, y;
1874 u32 offset;
1875
1876 x = src_x / hsub;
1877 y = src_y / vsub;
1878 width = src_w / hsub;
1879 height = src_h / vsub;
1880
1881 init_plane_view_dims(fb: intel_fb, color_plane: i, width, height, dims: &view_dims);
1882
1883 /*
1884 * First pixel of the src viewport from the
1885 * start of the normal gtt mapping.
1886 */
1887 x += intel_fb->normal_view.color_plane[i].x;
1888 y += intel_fb->normal_view.color_plane[i].y;
1889
1890 offset = calc_plane_aligned_offset(fb: intel_fb, color_plane: i, x: &x, y: &y);
1891
1892 gtt_offset += calc_plane_remap_info(fb: intel_fb, color_plane: i, dims: &view_dims,
1893 obj_offset: offset, gtt_offset, x, y,
1894 view: &plane_state->view);
1895 }
1896}
1897
1898unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1899{
1900 unsigned int size = 0;
1901 int i;
1902
1903 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
1904 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
1905
1906 return size;
1907}
1908
1909unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
1910{
1911 unsigned int size = 0;
1912 int i;
1913
1914 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
1915 unsigned int plane_size;
1916
1917 if (rem_info->plane[i].linear)
1918 plane_size = rem_info->plane[i].size;
1919 else
1920 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
1921
1922 if (plane_size == 0)
1923 continue;
1924
1925 if (rem_info->plane_alignment)
1926 size = ALIGN(size, rem_info->plane_alignment);
1927
1928 size += plane_size;
1929 }
1930
1931 return size;
1932}
1933
1934void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation,
1935 struct intel_fb_view *view)
1936{
1937 if (drm_rotation_90_or_270(rotation))
1938 *view = fb->rotated_view;
1939 else if (intel_fb_needs_pot_stride_remap(fb))
1940 *view = fb->remapped_view;
1941 else
1942 *view = fb->normal_view;
1943}
1944
1945/*
1946 * Convert the x/y offsets into a linear offset.
1947 * Only valid with 0/180 degree rotation, which is fine since linear
1948 * offset is only used with linear buffers on pre-hsw and tiled buffers
1949 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
1950 */
1951u32 intel_fb_xy_to_linear(int x, int y,
1952 const struct intel_plane_state *plane_state,
1953 int color_plane)
1954{
1955 const struct drm_framebuffer *fb = plane_state->hw.fb;
1956 unsigned int cpp = fb->format->cpp[color_plane];
1957 unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride;
1958
1959 return y * pitch + x * cpp;
1960}
1961
1962/*
1963 * Add the x/y offsets derived from fb->offsets[] to the user
1964 * specified plane src x/y offsets. The resulting x/y offsets
1965 * specify the start of scanout from the beginning of the gtt mapping.
1966 */
1967void intel_add_fb_offsets(int *x, int *y,
1968 const struct intel_plane_state *plane_state,
1969 int color_plane)
1970
1971{
1972 *x += plane_state->view.color_plane[color_plane].x;
1973 *y += plane_state->view.color_plane[color_plane].y;
1974}
1975
1976static
1977u32 intel_fb_max_stride(struct intel_display *display,
1978 u32 pixel_format, u64 modifier)
1979{
1980 /*
1981 * Arbitrary limit for gen4+ chosen to match the
1982 * render engine max stride.
1983 *
1984 * The new CCS hash mode makes remapping impossible
1985 */
1986 if (DISPLAY_VER(display) < 4 || intel_fb_is_ccs_modifier(modifier) ||
1987 intel_fb_modifier_uses_dpt(display, modifier))
1988 return intel_plane_fb_max_stride(drm: display->drm, pixel_format, modifier);
1989 else if (DISPLAY_VER(display) >= 7)
1990 return 256 * 1024;
1991 else
1992 return 128 * 1024;
1993}
1994
1995static unsigned int
1996intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1997{
1998 struct intel_display *display = to_intel_display(fb->dev);
1999 unsigned int tile_width;
2000
2001 if (is_surface_linear(fb, color_plane)) {
2002 unsigned int max_stride = intel_plane_fb_max_stride(drm: display->drm,
2003 pixel_format: fb->format->format,
2004 modifier: fb->modifier);
2005
2006 /*
2007 * To make remapping with linear generally feasible
2008 * we need the stride to be page aligned.
2009 */
2010 if (fb->pitches[color_plane] > max_stride &&
2011 !intel_fb_is_ccs_modifier(modifier: fb->modifier))
2012 return intel_tile_size(display);
2013 else
2014 return 64;
2015 }
2016
2017 tile_width = intel_tile_width_bytes(fb, color_plane);
2018 if (intel_fb_is_ccs_modifier(modifier: fb->modifier)) {
2019 /*
2020 * On TGL the surface stride must be 4 tile aligned, mapped by
2021 * one 64 byte cacheline on the CCS AUX surface.
2022 */
2023 if (DISPLAY_VER(display) >= 12)
2024 tile_width *= 4;
2025 /*
2026 * Display WA #0531: skl,bxt,kbl,glk
2027 *
2028 * Render decompression and plane width > 3840
2029 * combined with horizontal panning requires the
2030 * plane stride to be a multiple of 4. We'll just
2031 * require the entire fb to accommodate that to avoid
2032 * potential runtime errors at plane configuration time.
2033 */
2034 else if ((DISPLAY_VER(display) == 9 || display->platform.geminilake) &&
2035 color_plane == 0 && fb->width > 3840)
2036 tile_width *= 4;
2037 }
2038 return tile_width;
2039}
2040
2041static int intel_plane_check_stride(const struct intel_plane_state *plane_state)
2042{
2043 struct intel_display *display = to_intel_display(plane_state);
2044 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2045 const struct drm_framebuffer *fb = plane_state->hw.fb;
2046 unsigned int rotation = plane_state->hw.rotation;
2047 u32 stride, max_stride;
2048
2049 /*
2050 * We ignore stride for all invisible planes that
2051 * can be remapped. Otherwise we could end up
2052 * with a false positive when the remapping didn't
2053 * kick in due the plane being invisible.
2054 */
2055 if (intel_plane_can_remap(plane_state) &&
2056 !plane_state->uapi.visible)
2057 return 0;
2058
2059 /* FIXME other color planes? */
2060 stride = plane_state->view.color_plane[0].mapping_stride;
2061 max_stride = plane->max_stride(plane, fb->format->format,
2062 fb->modifier, rotation);
2063
2064 if (stride > max_stride) {
2065 drm_dbg_kms(display->drm,
2066 "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
2067 fb->base.id, stride,
2068 plane->base.base.id, plane->base.name, max_stride);
2069 return -EINVAL;
2070 }
2071
2072 return 0;
2073}
2074
2075int intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2076{
2077 const struct intel_framebuffer *fb =
2078 to_intel_framebuffer(plane_state->hw.fb);
2079 unsigned int rotation = plane_state->hw.rotation;
2080
2081 if (!fb)
2082 return 0;
2083
2084 if (intel_plane_needs_remap(plane_state)) {
2085 intel_plane_remap_gtt(plane_state);
2086
2087 /*
2088 * Sometimes even remapping can't overcome
2089 * the stride limitations :( Can happen with
2090 * big plane sizes and suitably misaligned
2091 * offsets.
2092 */
2093 return intel_plane_check_stride(plane_state);
2094 }
2095
2096 intel_fb_fill_view(fb, rotation, view: &plane_state->view);
2097
2098 /* Rotate src coordinates to match rotated GTT view */
2099 if (drm_rotation_90_or_270(rotation))
2100 drm_rect_rotate(r: &plane_state->uapi.src,
2101 width: fb->base.width << 16, height: fb->base.height << 16,
2102 DRM_MODE_ROTATE_270);
2103
2104 return intel_plane_check_stride(plane_state);
2105}
2106
2107static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
2108{
2109 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2110
2111 drm_framebuffer_cleanup(fb);
2112
2113 if (intel_fb_uses_dpt(fb))
2114 intel_dpt_destroy(vm: intel_fb->dpt_vm);
2115
2116 intel_frontbuffer_put(front: intel_fb->frontbuffer);
2117
2118 intel_fb_bo_framebuffer_fini(obj: intel_fb_bo(fb));
2119
2120 kfree(objp: intel_fb);
2121}
2122
2123static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
2124 struct drm_file *file,
2125 unsigned int *handle)
2126{
2127 struct drm_gem_object *obj = intel_fb_bo(fb);
2128 struct intel_display *display = to_intel_display(obj->dev);
2129
2130 if (intel_bo_is_userptr(obj)) {
2131 drm_dbg(display->drm,
2132 "attempting to use a userptr for a framebuffer, denied\n");
2133 return -EINVAL;
2134 }
2135
2136 return drm_gem_handle_create(file_priv: file, obj, handlep: handle);
2137}
2138
2139struct frontbuffer_fence_cb {
2140 struct dma_fence_cb base;
2141 struct intel_frontbuffer *front;
2142};
2143
2144static void intel_user_framebuffer_fence_wake(struct dma_fence *dma,
2145 struct dma_fence_cb *data)
2146{
2147 struct frontbuffer_fence_cb *cb = container_of(data, typeof(*cb), base);
2148
2149 intel_frontbuffer_queue_flush(front: cb->front);
2150 kfree(objp: cb);
2151 dma_fence_put(fence: dma);
2152}
2153
2154static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
2155 struct drm_file *file,
2156 unsigned int flags, unsigned int color,
2157 struct drm_clip_rect *clips,
2158 unsigned int num_clips)
2159{
2160 struct drm_gem_object *obj = intel_fb_bo(fb);
2161 struct intel_frontbuffer *front = to_intel_frontbuffer(fb);
2162 struct dma_fence *fence;
2163 struct frontbuffer_fence_cb *cb;
2164 int ret = 0;
2165
2166 if (!atomic_read(v: &front->bits))
2167 return 0;
2168
2169 if (dma_resv_test_signaled(obj: obj->resv, usage: dma_resv_usage_rw(write: false)))
2170 goto flush;
2171
2172 ret = dma_resv_get_singleton(obj: obj->resv, usage: dma_resv_usage_rw(write: false),
2173 fence: &fence);
2174 if (ret || !fence)
2175 goto flush;
2176
2177 cb = kmalloc(sizeof(*cb), GFP_KERNEL);
2178 if (!cb) {
2179 dma_fence_put(fence);
2180 ret = -ENOMEM;
2181 goto flush;
2182 }
2183
2184 cb->front = front;
2185
2186 intel_frontbuffer_invalidate(front, origin: ORIGIN_DIRTYFB);
2187
2188 ret = dma_fence_add_callback(fence, cb: &cb->base,
2189 func: intel_user_framebuffer_fence_wake);
2190 if (ret) {
2191 intel_user_framebuffer_fence_wake(dma: fence, data: &cb->base);
2192 if (ret == -ENOENT)
2193 ret = 0;
2194 }
2195
2196 return ret;
2197
2198flush:
2199 intel_bo_flush_if_display(obj);
2200 intel_frontbuffer_flush(front, origin: ORIGIN_DIRTYFB);
2201 return ret;
2202}
2203
2204static const struct drm_framebuffer_funcs intel_fb_funcs = {
2205 .destroy = intel_user_framebuffer_destroy,
2206 .create_handle = intel_user_framebuffer_create_handle,
2207 .dirty = intel_user_framebuffer_dirty,
2208};
2209
2210int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
2211 struct drm_gem_object *obj,
2212 const struct drm_format_info *info,
2213 struct drm_mode_fb_cmd2 *mode_cmd)
2214{
2215 struct intel_display *display = to_intel_display(obj->dev);
2216 struct drm_framebuffer *fb = &intel_fb->base;
2217 u32 max_stride;
2218 int ret = -EINVAL;
2219 int i;
2220
2221 ret = intel_fb_bo_framebuffer_init(fb, obj, mode_cmd);
2222 if (ret)
2223 return ret;
2224
2225 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
2226 if (!intel_fb->frontbuffer) {
2227 ret = -ENOMEM;
2228 goto err;
2229 }
2230
2231 ret = -EINVAL;
2232 if (!drm_any_plane_has_format(dev: display->drm,
2233 format: mode_cmd->pixel_format,
2234 modifier: mode_cmd->modifier[0])) {
2235 drm_dbg_kms(display->drm,
2236 "unsupported pixel format %p4cc / modifier 0x%llx\n",
2237 &mode_cmd->pixel_format, mode_cmd->modifier[0]);
2238 goto err_frontbuffer_put;
2239 }
2240
2241 max_stride = intel_fb_max_stride(display, pixel_format: mode_cmd->pixel_format,
2242 modifier: mode_cmd->modifier[0]);
2243 if (mode_cmd->pitches[0] > max_stride) {
2244 drm_dbg_kms(display->drm,
2245 "%s pitch (%u) must be at most %d\n",
2246 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
2247 "tiled" : "linear",
2248 mode_cmd->pitches[0], max_stride);
2249 goto err_frontbuffer_put;
2250 }
2251
2252 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
2253 if (mode_cmd->offsets[0] != 0) {
2254 drm_dbg_kms(display->drm,
2255 "plane 0 offset (0x%08x) must be 0\n",
2256 mode_cmd->offsets[0]);
2257 goto err_frontbuffer_put;
2258 }
2259
2260 drm_helper_mode_fill_fb_struct(dev: display->drm, fb, info, mode_cmd);
2261
2262 for (i = 0; i < fb->format->num_planes; i++) {
2263 unsigned int stride_alignment;
2264
2265 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
2266 drm_dbg_kms(display->drm, "bad plane %d handle\n", i);
2267 goto err_frontbuffer_put;
2268 }
2269
2270 stride_alignment = intel_fb_stride_alignment(fb, color_plane: i);
2271 if (fb->pitches[i] & (stride_alignment - 1)) {
2272 drm_dbg_kms(display->drm,
2273 "plane %d pitch (%d) must be at least %u byte aligned\n",
2274 i, fb->pitches[i], stride_alignment);
2275 goto err_frontbuffer_put;
2276 }
2277
2278 if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane: i)) {
2279 unsigned int ccs_aux_stride = gen12_ccs_aux_stride(fb: intel_fb, ccs_plane: i);
2280
2281 if (fb->pitches[i] != ccs_aux_stride) {
2282 drm_dbg_kms(display->drm,
2283 "ccs aux plane %d pitch (%d) must be %d\n",
2284 i, fb->pitches[i], ccs_aux_stride);
2285 goto err_frontbuffer_put;
2286 }
2287 }
2288
2289 fb->obj[i] = obj;
2290 }
2291
2292 ret = intel_fill_fb_info(display, fb: intel_fb);
2293 if (ret)
2294 goto err_frontbuffer_put;
2295
2296 if (intel_fb_uses_dpt(fb)) {
2297 struct i915_address_space *vm;
2298
2299 vm = intel_dpt_create(fb: intel_fb);
2300 if (IS_ERR(ptr: vm)) {
2301 drm_dbg_kms(display->drm, "failed to create DPT\n");
2302 ret = PTR_ERR(ptr: vm);
2303 goto err_frontbuffer_put;
2304 }
2305
2306 intel_fb->dpt_vm = vm;
2307 }
2308
2309 ret = drm_framebuffer_init(dev: display->drm, fb, funcs: &intel_fb_funcs);
2310 if (ret) {
2311 drm_err(display->drm, "framebuffer init failed %d\n", ret);
2312 goto err_free_dpt;
2313 }
2314
2315 return 0;
2316
2317err_free_dpt:
2318 if (intel_fb_uses_dpt(fb))
2319 intel_dpt_destroy(vm: intel_fb->dpt_vm);
2320err_frontbuffer_put:
2321 intel_frontbuffer_put(front: intel_fb->frontbuffer);
2322err:
2323 intel_fb_bo_framebuffer_fini(obj);
2324 return ret;
2325}
2326
2327struct drm_framebuffer *
2328intel_user_framebuffer_create(struct drm_device *dev,
2329 struct drm_file *filp,
2330 const struct drm_format_info *info,
2331 const struct drm_mode_fb_cmd2 *user_mode_cmd)
2332{
2333 struct drm_framebuffer *fb;
2334 struct drm_gem_object *obj;
2335 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
2336
2337 obj = intel_fb_bo_lookup_valid_bo(drm: dev, filp, user_mode_cmd: &mode_cmd);
2338 if (IS_ERR(ptr: obj))
2339 return ERR_CAST(ptr: obj);
2340
2341 fb = intel_framebuffer_create(obj, info, mode_cmd: &mode_cmd);
2342 drm_gem_object_put(obj);
2343
2344 return fb;
2345}
2346
2347struct intel_framebuffer *intel_framebuffer_alloc(void)
2348{
2349 struct intel_framebuffer *intel_fb;
2350 struct intel_panic *panic;
2351
2352 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2353 if (!intel_fb)
2354 return NULL;
2355
2356 panic = intel_panic_alloc();
2357 if (!panic) {
2358 kfree(objp: intel_fb);
2359 return NULL;
2360 }
2361
2362 intel_fb->panic = panic;
2363
2364 return intel_fb;
2365}
2366
2367struct drm_framebuffer *
2368intel_framebuffer_create(struct drm_gem_object *obj,
2369 const struct drm_format_info *info,
2370 struct drm_mode_fb_cmd2 *mode_cmd)
2371{
2372 struct intel_framebuffer *intel_fb;
2373 int ret;
2374
2375 intel_fb = intel_framebuffer_alloc();
2376 if (!intel_fb)
2377 return ERR_PTR(error: -ENOMEM);
2378
2379 ret = intel_framebuffer_init(intel_fb, obj, info, mode_cmd);
2380 if (ret)
2381 goto err;
2382
2383 return &intel_fb->base;
2384
2385err:
2386 kfree(objp: intel_fb);
2387 return ERR_PTR(error: ret);
2388}
2389
2390struct drm_gem_object *intel_fb_bo(const struct drm_framebuffer *fb)
2391{
2392 return fb ? fb->obj[0] : NULL;
2393}
2394