1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29
30#include <linux/export.h>
31#include <linux/i2c-algo-bit.h>
32#include <linux/i2c.h>
33#include <linux/iopoll.h>
34
35#include <drm/display/drm_hdcp_helper.h>
36
37#include "i915_drv.h"
38#include "i915_irq.h"
39#include "i915_reg.h"
40#include "intel_de.h"
41#include "intel_display_regs.h"
42#include "intel_display_types.h"
43#include "intel_display_wa.h"
44#include "intel_gmbus.h"
45#include "intel_gmbus_regs.h"
46
47struct intel_gmbus {
48 struct i2c_adapter adapter;
49#define GMBUS_FORCE_BIT_RETRY (1U << 31)
50 u32 force_bit;
51 u32 reg0;
52 i915_reg_t gpio_reg;
53 struct i2c_algo_bit_data bit_algo;
54 struct intel_display *display;
55};
56
57enum gmbus_gpio {
58 GPIOA,
59 GPIOB,
60 GPIOC,
61 GPIOD,
62 GPIOE,
63 GPIOF,
64 GPIOG,
65 GPIOH,
66 __GPIOI_UNUSED,
67 GPIOJ,
68 GPIOK,
69 GPIOL,
70 GPIOM,
71 GPION,
72 GPIOO,
73};
74
75struct gmbus_pin {
76 const char *name;
77 enum gmbus_gpio gpio;
78};
79
80/* Map gmbus pin pairs to names and registers. */
81static const struct gmbus_pin gmbus_pins[] = {
82 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
83 [GMBUS_PIN_VGADDC] = { .name: "vga", .gpio: GPIOA },
84 [GMBUS_PIN_PANEL] = { .name: "panel", .gpio: GPIOC },
85 [GMBUS_PIN_DPC] = { .name: "dpc", .gpio: GPIOD },
86 [GMBUS_PIN_DPB] = { .name: "dpb", .gpio: GPIOE },
87 [GMBUS_PIN_DPD] = { .name: "dpd", .gpio: GPIOF },
88};
89
90static const struct gmbus_pin gmbus_pins_bdw[] = {
91 [GMBUS_PIN_VGADDC] = { .name: "vga", .gpio: GPIOA },
92 [GMBUS_PIN_DPC] = { .name: "dpc", .gpio: GPIOD },
93 [GMBUS_PIN_DPB] = { .name: "dpb", .gpio: GPIOE },
94 [GMBUS_PIN_DPD] = { .name: "dpd", .gpio: GPIOF },
95};
96
97static const struct gmbus_pin gmbus_pins_skl[] = {
98 [GMBUS_PIN_DPC] = { .name: "dpc", .gpio: GPIOD },
99 [GMBUS_PIN_DPB] = { .name: "dpb", .gpio: GPIOE },
100 [GMBUS_PIN_DPD] = { .name: "dpd", .gpio: GPIOF },
101};
102
103static const struct gmbus_pin gmbus_pins_bxt[] = {
104 [GMBUS_PIN_1_BXT] = { .name: "dpb", .gpio: GPIOB },
105 [GMBUS_PIN_2_BXT] = { .name: "dpc", .gpio: GPIOC },
106 [GMBUS_PIN_3_BXT] = { .name: "misc", .gpio: GPIOD },
107};
108
109static const struct gmbus_pin gmbus_pins_cnp[] = {
110 [GMBUS_PIN_1_BXT] = { .name: "dpb", .gpio: GPIOB },
111 [GMBUS_PIN_2_BXT] = { .name: "dpc", .gpio: GPIOC },
112 [GMBUS_PIN_3_BXT] = { .name: "misc", .gpio: GPIOD },
113 [GMBUS_PIN_4_CNP] = { .name: "dpd", .gpio: GPIOE },
114};
115
116static const struct gmbus_pin gmbus_pins_icp[] = {
117 [GMBUS_PIN_1_BXT] = { .name: "dpa", .gpio: GPIOB },
118 [GMBUS_PIN_2_BXT] = { .name: "dpb", .gpio: GPIOC },
119 [GMBUS_PIN_3_BXT] = { .name: "dpc", .gpio: GPIOD },
120 [GMBUS_PIN_9_TC1_ICP] = { .name: "tc1", .gpio: GPIOJ },
121 [GMBUS_PIN_10_TC2_ICP] = { .name: "tc2", .gpio: GPIOK },
122 [GMBUS_PIN_11_TC3_ICP] = { .name: "tc3", .gpio: GPIOL },
123 [GMBUS_PIN_12_TC4_ICP] = { .name: "tc4", .gpio: GPIOM },
124 [GMBUS_PIN_13_TC5_TGP] = { .name: "tc5", .gpio: GPION },
125 [GMBUS_PIN_14_TC6_TGP] = { .name: "tc6", .gpio: GPIOO },
126};
127
128static const struct gmbus_pin gmbus_pins_dg1[] = {
129 [GMBUS_PIN_1_BXT] = { .name: "dpa", .gpio: GPIOB },
130 [GMBUS_PIN_2_BXT] = { .name: "dpb", .gpio: GPIOC },
131 [GMBUS_PIN_3_BXT] = { .name: "dpc", .gpio: GPIOD },
132 [GMBUS_PIN_4_CNP] = { .name: "dpd", .gpio: GPIOE },
133};
134
135static const struct gmbus_pin gmbus_pins_dg2[] = {
136 [GMBUS_PIN_1_BXT] = { .name: "dpa", .gpio: GPIOB },
137 [GMBUS_PIN_2_BXT] = { .name: "dpb", .gpio: GPIOC },
138 [GMBUS_PIN_3_BXT] = { .name: "dpc", .gpio: GPIOD },
139 [GMBUS_PIN_4_CNP] = { .name: "dpd", .gpio: GPIOE },
140 [GMBUS_PIN_9_TC1_ICP] = { .name: "tc1", .gpio: GPIOJ },
141};
142
143static const struct gmbus_pin gmbus_pins_mtp[] = {
144 [GMBUS_PIN_1_BXT] = { .name: "dpa", .gpio: GPIOB },
145 [GMBUS_PIN_2_BXT] = { .name: "dpb", .gpio: GPIOC },
146 [GMBUS_PIN_3_BXT] = { .name: "dpc", .gpio: GPIOD },
147 [GMBUS_PIN_4_CNP] = { .name: "dpd", .gpio: GPIOE },
148 [GMBUS_PIN_5_MTP] = { .name: "dpe", .gpio: GPIOF },
149 [GMBUS_PIN_9_TC1_ICP] = { .name: "tc1", .gpio: GPIOJ },
150 [GMBUS_PIN_10_TC2_ICP] = { .name: "tc2", .gpio: GPIOK },
151 [GMBUS_PIN_11_TC3_ICP] = { .name: "tc3", .gpio: GPIOL },
152 [GMBUS_PIN_12_TC4_ICP] = { .name: "tc4", .gpio: GPIOM },
153};
154
155static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,
156 unsigned int pin)
157{
158 const struct gmbus_pin *pins;
159 size_t size;
160
161 if (INTEL_PCH_TYPE(display) >= PCH_MTL) {
162 pins = gmbus_pins_mtp;
163 size = ARRAY_SIZE(gmbus_pins_mtp);
164 } else if (INTEL_PCH_TYPE(display) >= PCH_DG2) {
165 pins = gmbus_pins_dg2;
166 size = ARRAY_SIZE(gmbus_pins_dg2);
167 } else if (INTEL_PCH_TYPE(display) >= PCH_DG1) {
168 pins = gmbus_pins_dg1;
169 size = ARRAY_SIZE(gmbus_pins_dg1);
170 } else if (INTEL_PCH_TYPE(display) >= PCH_ICP) {
171 pins = gmbus_pins_icp;
172 size = ARRAY_SIZE(gmbus_pins_icp);
173 } else if (HAS_PCH_CNP(display)) {
174 pins = gmbus_pins_cnp;
175 size = ARRAY_SIZE(gmbus_pins_cnp);
176 } else if (display->platform.geminilake || display->platform.broxton) {
177 pins = gmbus_pins_bxt;
178 size = ARRAY_SIZE(gmbus_pins_bxt);
179 } else if (DISPLAY_VER(display) == 9) {
180 pins = gmbus_pins_skl;
181 size = ARRAY_SIZE(gmbus_pins_skl);
182 } else if (display->platform.broadwell) {
183 pins = gmbus_pins_bdw;
184 size = ARRAY_SIZE(gmbus_pins_bdw);
185 } else {
186 pins = gmbus_pins;
187 size = ARRAY_SIZE(gmbus_pins);
188 }
189
190 if (pin >= size || !pins[pin].name)
191 return NULL;
192
193 return &pins[pin];
194}
195
196bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)
197{
198 return get_gmbus_pin(display, pin);
199}
200
201/* Intel GPIO access functions */
202
203#define I2C_RISEFALL_TIME 10
204
205static inline struct intel_gmbus *
206to_intel_gmbus(struct i2c_adapter *i2c)
207{
208 return container_of(i2c, struct intel_gmbus, adapter);
209}
210
211void
212intel_gmbus_reset(struct intel_display *display)
213{
214 intel_de_write(display, GMBUS0(display), val: 0);
215 intel_de_write(display, GMBUS4(display), val: 0);
216}
217
218static void pnv_gmbus_clock_gating(struct intel_display *display,
219 bool enable)
220{
221 /* When using bit bashing for I2C, this bit needs to be set to 1 */
222 intel_de_rmw(display, DSPCLK_GATE_D,
223 PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
224 set: !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
225}
226
227static void pch_gmbus_clock_gating(struct intel_display *display,
228 bool enable)
229{
230 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
231 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
232 set: !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
233}
234
235static void bxt_gmbus_clock_gating(struct intel_display *display,
236 bool enable)
237{
238 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
239 set: !enable ? BXT_GMBUS_GATING_DIS : 0);
240}
241
242static u32 get_reserved(struct intel_gmbus *bus)
243{
244 struct intel_display *display = bus->display;
245 u32 preserve_bits = 0;
246
247 if (display->platform.i830 || display->platform.i845g)
248 return 0;
249
250 /* On most chips, these bits must be preserved in software. */
251 preserve_bits |= GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE;
252
253 /* Wa_16025573575: the masks bits need to be preserved through out */
254 if (intel_display_wa(display, 16025573575))
255 preserve_bits |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK |
256 GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK;
257
258 return intel_de_read_notrace(display, reg: bus->gpio_reg) & preserve_bits;
259}
260
261static int get_clock(void *data)
262{
263 struct intel_gmbus *bus = data;
264 struct intel_display *display = bus->display;
265 u32 reserved = get_reserved(bus);
266
267 intel_de_write_notrace(display, reg: bus->gpio_reg, val: reserved | GPIO_CLOCK_DIR_MASK);
268 intel_de_write_notrace(display, reg: bus->gpio_reg, val: reserved);
269
270 return (intel_de_read_notrace(display, reg: bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
271}
272
273static int get_data(void *data)
274{
275 struct intel_gmbus *bus = data;
276 struct intel_display *display = bus->display;
277 u32 reserved = get_reserved(bus);
278
279 intel_de_write_notrace(display, reg: bus->gpio_reg, val: reserved | GPIO_DATA_DIR_MASK);
280 intel_de_write_notrace(display, reg: bus->gpio_reg, val: reserved);
281
282 return (intel_de_read_notrace(display, reg: bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
283}
284
285static void set_clock(void *data, int state_high)
286{
287 struct intel_gmbus *bus = data;
288 struct intel_display *display = bus->display;
289 u32 reserved = get_reserved(bus);
290 u32 clock_bits;
291
292 if (state_high)
293 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
294 else
295 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
296 GPIO_CLOCK_VAL_MASK;
297
298 intel_de_write_notrace(display, reg: bus->gpio_reg, val: reserved | clock_bits);
299 intel_de_posting_read(display, reg: bus->gpio_reg);
300}
301
302static void set_data(void *data, int state_high)
303{
304 struct intel_gmbus *bus = data;
305 struct intel_display *display = bus->display;
306 u32 reserved = get_reserved(bus);
307 u32 data_bits;
308
309 if (state_high)
310 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
311 else
312 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
313 GPIO_DATA_VAL_MASK;
314
315 intel_de_write_notrace(display, reg: bus->gpio_reg, val: reserved | data_bits);
316 intel_de_posting_read(display, reg: bus->gpio_reg);
317}
318
319static void
320ptl_handle_mask_bits(struct intel_gmbus *bus, bool set)
321{
322 struct intel_display *display = bus->display;
323 u32 reg_val = intel_de_read_notrace(display, reg: bus->gpio_reg);
324 u32 mask_bits = GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK |
325 GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK;
326 if (set)
327 reg_val |= mask_bits;
328 else
329 reg_val &= ~mask_bits;
330
331 intel_de_write_notrace(display, reg: bus->gpio_reg, val: reg_val);
332 intel_de_posting_read(display, reg: bus->gpio_reg);
333}
334
335static int
336intel_gpio_pre_xfer(struct i2c_adapter *adapter)
337{
338 struct intel_gmbus *bus = to_intel_gmbus(i2c: adapter);
339 struct intel_display *display = bus->display;
340
341 intel_gmbus_reset(display);
342
343 if (display->platform.pineview)
344 pnv_gmbus_clock_gating(display, enable: false);
345
346 if (intel_display_wa(display, 16025573575))
347 ptl_handle_mask_bits(bus, set: true);
348
349 set_data(data: bus, state_high: 1);
350 set_clock(data: bus, state_high: 1);
351 udelay(I2C_RISEFALL_TIME);
352 return 0;
353}
354
355static void
356intel_gpio_post_xfer(struct i2c_adapter *adapter)
357{
358 struct intel_gmbus *bus = to_intel_gmbus(i2c: adapter);
359 struct intel_display *display = bus->display;
360
361 set_data(data: bus, state_high: 1);
362 set_clock(data: bus, state_high: 1);
363
364 if (display->platform.pineview)
365 pnv_gmbus_clock_gating(display, enable: true);
366
367 if (intel_display_wa(display, 16025573575))
368 ptl_handle_mask_bits(bus, set: false);
369}
370
371static void
372intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
373{
374 struct i2c_algo_bit_data *algo;
375
376 algo = &bus->bit_algo;
377
378 bus->gpio_reg = gpio_reg;
379 bus->adapter.algo_data = algo;
380 algo->setsda = set_data;
381 algo->setscl = set_clock;
382 algo->getsda = get_data;
383 algo->getscl = get_clock;
384 algo->pre_xfer = intel_gpio_pre_xfer;
385 algo->post_xfer = intel_gpio_post_xfer;
386 algo->udelay = I2C_RISEFALL_TIME;
387 algo->timeout = usecs_to_jiffies(u: 2200);
388 algo->data = bus;
389}
390
391static bool has_gmbus_irq(struct intel_display *display)
392{
393 struct drm_i915_private *i915 = to_i915(dev: display->drm);
394 /*
395 * encoder->shutdown() may want to use GMBUS
396 * after irqs have already been disabled.
397 */
398 return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(dev_priv: i915);
399}
400
401static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)
402{
403 DEFINE_WAIT(wait);
404 u32 gmbus2;
405 int ret;
406
407 /* Important: The hw handles only the first bit, so set only one! Since
408 * we also need to check for NAKs besides the hw ready/idle signal, we
409 * need to wake up periodically and check that ourselves.
410 */
411 if (!has_gmbus_irq(display))
412 irq_en = 0;
413
414 add_wait_queue(wq_head: &display->gmbus.wait_queue, wq_entry: &wait);
415 intel_de_write_fw(display, GMBUS4(display), val: irq_en);
416
417 status |= GMBUS_SATOER;
418
419 ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
420 gmbus2 & status,
421 0, 2, false);
422 if (ret)
423 ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
424 gmbus2 & status,
425 500, 50 * 1000, false);
426
427 intel_de_write_fw(display, GMBUS4(display), val: 0);
428 remove_wait_queue(wq_head: &display->gmbus.wait_queue, wq_entry: &wait);
429
430 if (gmbus2 & GMBUS_SATOER)
431 return -ENXIO;
432
433 return ret;
434}
435
436static int
437gmbus_wait_idle(struct intel_display *display)
438{
439 DEFINE_WAIT(wait);
440 u32 irq_enable;
441 int ret;
442
443 /* Important: The hw handles only the first bit, so set only one! */
444 irq_enable = 0;
445 if (has_gmbus_irq(display))
446 irq_enable = GMBUS_IDLE_EN;
447
448 add_wait_queue(wq_head: &display->gmbus.wait_queue, wq_entry: &wait);
449 intel_de_write_fw(display, GMBUS4(display), val: irq_enable);
450
451 ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, value: 0, timeout_ms: 10, NULL);
452
453 intel_de_write_fw(display, GMBUS4(display), val: 0);
454 remove_wait_queue(wq_head: &display->gmbus.wait_queue, wq_entry: &wait);
455
456 return ret;
457}
458
459static unsigned int gmbus_max_xfer_size(struct intel_display *display)
460{
461 return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
462 GMBUS_BYTE_COUNT_MAX;
463}
464
465static int
466gmbus_xfer_read_chunk(struct intel_display *display,
467 unsigned short addr, u8 *buf, unsigned int len,
468 u32 gmbus0_reg, u32 gmbus1_index)
469{
470 unsigned int size = len;
471 bool burst_read = len > gmbus_max_xfer_size(display);
472 bool extra_byte_added = false;
473
474 if (burst_read) {
475 /*
476 * As per HW Spec, for 512Bytes need to read extra Byte and
477 * Ignore the extra byte read.
478 */
479 if (len == 512) {
480 extra_byte_added = true;
481 len++;
482 }
483 size = len % 256 + 256;
484 intel_de_write_fw(display, GMBUS0(display),
485 val: gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
486 }
487
488 intel_de_write_fw(display, GMBUS1(display),
489 val: gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
490 while (len) {
491 int ret;
492 u32 val, loop = 0;
493
494 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
495 if (ret)
496 return ret;
497
498 val = intel_de_read_fw(display, GMBUS3(display));
499 do {
500 if (extra_byte_added && len == 1)
501 break;
502
503 *buf++ = val & 0xff;
504 val >>= 8;
505 } while (--len && ++loop < 4);
506
507 if (burst_read && len == size - 4)
508 /* Reset the override bit */
509 intel_de_write_fw(display, GMBUS0(display), val: gmbus0_reg);
510 }
511
512 return 0;
513}
514
515/*
516 * HW spec says that 512Bytes in Burst read need special treatment.
517 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
518 * an I2C target, which supports such a lengthy burst read too for experiments.
519 *
520 * So until things get clarified on HW support, to avoid the burst read length
521 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
522 */
523#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
524
525static int
526gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg,
527 u32 gmbus0_reg, u32 gmbus1_index)
528{
529 u8 *buf = msg->buf;
530 unsigned int rx_size = msg->len;
531 unsigned int len;
532 int ret;
533
534 do {
535 if (HAS_GMBUS_BURST_READ(display))
536 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
537 else
538 len = min(rx_size, gmbus_max_xfer_size(display));
539
540 ret = gmbus_xfer_read_chunk(display, addr: msg->addr, buf, len,
541 gmbus0_reg, gmbus1_index);
542 if (ret)
543 return ret;
544
545 rx_size -= len;
546 buf += len;
547 } while (rx_size != 0);
548
549 return 0;
550}
551
552static int
553gmbus_xfer_write_chunk(struct intel_display *display,
554 unsigned short addr, u8 *buf, unsigned int len,
555 u32 gmbus1_index)
556{
557 unsigned int chunk_size = len;
558 u32 val, loop;
559
560 val = loop = 0;
561 while (len && loop < 4) {
562 val |= *buf++ << (8 * loop++);
563 len -= 1;
564 }
565
566 intel_de_write_fw(display, GMBUS3(display), val);
567 intel_de_write_fw(display, GMBUS1(display),
568 val: gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
569 while (len) {
570 int ret;
571
572 val = loop = 0;
573 do {
574 val |= *buf++ << (8 * loop);
575 } while (--len && ++loop < 4);
576
577 intel_de_write_fw(display, GMBUS3(display), val);
578
579 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
580 if (ret)
581 return ret;
582 }
583
584 return 0;
585}
586
587static int
588gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg,
589 u32 gmbus1_index)
590{
591 u8 *buf = msg->buf;
592 unsigned int tx_size = msg->len;
593 unsigned int len;
594 int ret;
595
596 do {
597 len = min(tx_size, gmbus_max_xfer_size(display));
598
599 ret = gmbus_xfer_write_chunk(display, addr: msg->addr, buf, len,
600 gmbus1_index);
601 if (ret)
602 return ret;
603
604 buf += len;
605 tx_size -= len;
606 } while (tx_size != 0);
607
608 return 0;
609}
610
611/*
612 * The gmbus controller can combine a 1 or 2 byte write with another read/write
613 * that immediately follows it by using an "INDEX" cycle.
614 */
615static bool
616gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
617{
618 return (i + 1 < num &&
619 msgs[i].addr == msgs[i + 1].addr &&
620 !(msgs[i].flags & I2C_M_RD) &&
621 (msgs[i].len == 1 || msgs[i].len == 2) &&
622 msgs[i + 1].len > 0);
623}
624
625static int
626gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs,
627 u32 gmbus0_reg)
628{
629 u32 gmbus1_index = 0;
630 u32 gmbus5 = 0;
631 int ret;
632
633 if (msgs[0].len == 2)
634 gmbus5 = GMBUS_2BYTE_INDEX_EN |
635 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
636 if (msgs[0].len == 1)
637 gmbus1_index = GMBUS_CYCLE_INDEX |
638 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
639
640 /* GMBUS5 holds 16-bit index */
641 if (gmbus5)
642 intel_de_write_fw(display, GMBUS5(display), val: gmbus5);
643
644 if (msgs[1].flags & I2C_M_RD)
645 ret = gmbus_xfer_read(display, msg: &msgs[1], gmbus0_reg,
646 gmbus1_index);
647 else
648 ret = gmbus_xfer_write(display, msg: &msgs[1], gmbus1_index);
649
650 /* Clear GMBUS5 after each index transfer */
651 if (gmbus5)
652 intel_de_write_fw(display, GMBUS5(display), val: 0);
653
654 return ret;
655}
656
657static int
658do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
659 u32 gmbus0_source)
660{
661 struct intel_gmbus *bus = to_intel_gmbus(i2c: adapter);
662 struct intel_display *display = bus->display;
663 int i = 0, inc, try = 0;
664 int ret = 0;
665
666 /* Display WA #0868: skl,bxt,kbl,cfl,glk */
667 if (display->platform.geminilake || display->platform.broxton)
668 bxt_gmbus_clock_gating(display, enable: false);
669 else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display))
670 pch_gmbus_clock_gating(display, enable: false);
671
672retry:
673 intel_de_write_fw(display, GMBUS0(display), val: gmbus0_source | bus->reg0);
674
675 for (; i < num; i += inc) {
676 inc = 1;
677 if (gmbus_is_index_xfer(msgs, i, num)) {
678 ret = gmbus_index_xfer(display, msgs: &msgs[i],
679 gmbus0_reg: gmbus0_source | bus->reg0);
680 inc = 2; /* an index transmission is two msgs */
681 } else if (msgs[i].flags & I2C_M_RD) {
682 ret = gmbus_xfer_read(display, msg: &msgs[i],
683 gmbus0_reg: gmbus0_source | bus->reg0, gmbus1_index: 0);
684 } else {
685 ret = gmbus_xfer_write(display, msg: &msgs[i], gmbus1_index: 0);
686 }
687
688 if (!ret)
689 ret = gmbus_wait(display,
690 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
691 if (ret == -ETIMEDOUT)
692 goto timeout;
693 else if (ret)
694 goto clear_err;
695 }
696
697 /* Generate a STOP condition on the bus. Note that gmbus can't generata
698 * a STOP on the very first cycle. To simplify the code we
699 * unconditionally generate the STOP condition with an additional gmbus
700 * cycle. */
701 intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
702
703 /* Mark the GMBUS interface as disabled after waiting for idle.
704 * We will re-enable it at the start of the next xfer,
705 * till then let it sleep.
706 */
707 if (gmbus_wait_idle(display)) {
708 drm_dbg_kms(display->drm,
709 "GMBUS [%s] timed out waiting for idle\n",
710 adapter->name);
711 ret = -ETIMEDOUT;
712 }
713 intel_de_write_fw(display, GMBUS0(display), val: 0);
714 ret = ret ?: i;
715 goto out;
716
717clear_err:
718 /*
719 * Wait for bus to IDLE before clearing NAK.
720 * If we clear the NAK while bus is still active, then it will stay
721 * active and the next transaction may fail.
722 *
723 * If no ACK is received during the address phase of a transaction, the
724 * adapter must report -ENXIO. It is not clear what to return if no ACK
725 * is received at other times. But we have to be careful to not return
726 * spurious -ENXIO because that will prevent i2c and drm edid functions
727 * from retrying. So return -ENXIO only when gmbus properly quiescents -
728 * timing out seems to happen when there _is_ a ddc chip present, but
729 * it's slow responding and only answers on the 2nd retry.
730 */
731 ret = -ENXIO;
732 if (gmbus_wait_idle(display)) {
733 drm_dbg_kms(display->drm,
734 "GMBUS [%s] timed out after NAK\n",
735 adapter->name);
736 ret = -ETIMEDOUT;
737 }
738
739 /* Toggle the Software Clear Interrupt bit. This has the effect
740 * of resetting the GMBUS controller and so clearing the
741 * BUS_ERROR raised by the target's NAK.
742 */
743 intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT);
744 intel_de_write_fw(display, GMBUS1(display), val: 0);
745 intel_de_write_fw(display, GMBUS0(display), val: 0);
746
747 drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
748 adapter->name, msgs[i].addr,
749 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
750
751 /*
752 * Passive adapters sometimes NAK the first probe. Retry the first
753 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
754 * has retries internally. See also the retry loop in
755 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
756 */
757 if (ret == -ENXIO && i == 0 && try++ == 0) {
758 drm_dbg_kms(display->drm,
759 "GMBUS [%s] NAK on first message, retry\n",
760 adapter->name);
761 goto retry;
762 }
763
764 goto out;
765
766timeout:
767 drm_dbg_kms(display->drm,
768 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
769 bus->adapter.name, bus->reg0 & 0xff);
770 intel_de_write_fw(display, GMBUS0(display), val: 0);
771
772 /*
773 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
774 * instead. Use EAGAIN to have i2c core retry.
775 */
776 ret = -EAGAIN;
777
778out:
779 /* Display WA #0868: skl,bxt,kbl,cfl,glk */
780 if (display->platform.geminilake || display->platform.broxton)
781 bxt_gmbus_clock_gating(display, enable: true);
782 else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display))
783 pch_gmbus_clock_gating(display, enable: true);
784
785 return ret;
786}
787
788static int
789gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
790{
791 struct intel_gmbus *bus = to_intel_gmbus(i2c: adapter);
792 struct intel_display *display = bus->display;
793 intel_wakeref_t wakeref;
794 int ret;
795
796 wakeref = intel_display_power_get(display, domain: POWER_DOMAIN_GMBUS);
797
798 if (bus->force_bit) {
799 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
800 if (ret < 0)
801 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
802 } else {
803 ret = do_gmbus_xfer(adapter, msgs, num, gmbus0_source: 0);
804 if (ret == -EAGAIN)
805 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
806 }
807
808 intel_display_power_put(display, domain: POWER_DOMAIN_GMBUS, wakeref);
809
810 return ret;
811}
812
813int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
814{
815 struct intel_gmbus *bus = to_intel_gmbus(i2c: adapter);
816 struct intel_display *display = bus->display;
817 u8 cmd = DRM_HDCP_DDC_AKSV;
818 u8 buf[DRM_HDCP_KSV_LEN] = {};
819 struct i2c_msg msgs[] = {
820 {
821 .addr = DRM_HDCP_DDC_ADDR,
822 .flags = 0,
823 .len = sizeof(cmd),
824 .buf = &cmd,
825 },
826 {
827 .addr = DRM_HDCP_DDC_ADDR,
828 .flags = 0,
829 .len = sizeof(buf),
830 .buf = buf,
831 }
832 };
833 intel_wakeref_t wakeref;
834 int ret;
835
836 wakeref = intel_display_power_get(display, domain: POWER_DOMAIN_GMBUS);
837 mutex_lock(lock: &display->gmbus.mutex);
838
839 /*
840 * In order to output Aksv to the receiver, use an indexed write to
841 * pass the i2c command, and tell GMBUS to use the HW-provided value
842 * instead of sourcing GMBUS3 for the data.
843 */
844 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
845
846 mutex_unlock(lock: &display->gmbus.mutex);
847 intel_display_power_put(display, domain: POWER_DOMAIN_GMBUS, wakeref);
848
849 return ret;
850}
851
852static u32 gmbus_func(struct i2c_adapter *adapter)
853{
854 return i2c_bit_algo.functionality(adapter) &
855 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
856 /* I2C_FUNC_10BIT_ADDR | */
857 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
858 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
859}
860
861static const struct i2c_algorithm gmbus_algorithm = {
862 .master_xfer = gmbus_xfer,
863 .functionality = gmbus_func
864};
865
866static void gmbus_lock_bus(struct i2c_adapter *adapter,
867 unsigned int flags)
868{
869 struct intel_gmbus *bus = to_intel_gmbus(i2c: adapter);
870 struct intel_display *display = bus->display;
871
872 mutex_lock(lock: &display->gmbus.mutex);
873}
874
875static int gmbus_trylock_bus(struct i2c_adapter *adapter,
876 unsigned int flags)
877{
878 struct intel_gmbus *bus = to_intel_gmbus(i2c: adapter);
879 struct intel_display *display = bus->display;
880
881 return mutex_trylock(lock: &display->gmbus.mutex);
882}
883
884static void gmbus_unlock_bus(struct i2c_adapter *adapter,
885 unsigned int flags)
886{
887 struct intel_gmbus *bus = to_intel_gmbus(i2c: adapter);
888 struct intel_display *display = bus->display;
889
890 mutex_unlock(lock: &display->gmbus.mutex);
891}
892
893static const struct i2c_lock_operations gmbus_lock_ops = {
894 .lock_bus = gmbus_lock_bus,
895 .trylock_bus = gmbus_trylock_bus,
896 .unlock_bus = gmbus_unlock_bus,
897};
898
899/**
900 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
901 * @display: display device
902 */
903int intel_gmbus_setup(struct intel_display *display)
904{
905 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
906 unsigned int pin;
907 int ret;
908
909 if (display->platform.valleyview || display->platform.cherryview)
910 display->gmbus.mmio_base = VLV_DISPLAY_BASE;
911 else if (!HAS_GMCH(display))
912 /*
913 * Broxton uses the same PCH offsets for South Display Engine,
914 * even though it doesn't have a PCH.
915 */
916 display->gmbus.mmio_base = PCH_DISPLAY_BASE;
917
918 mutex_init(&display->gmbus.mutex);
919 init_waitqueue_head(&display->gmbus.wait_queue);
920
921 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
922 const struct gmbus_pin *gmbus_pin;
923 struct intel_gmbus *bus;
924
925 gmbus_pin = get_gmbus_pin(display, pin);
926 if (!gmbus_pin)
927 continue;
928
929 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
930 if (!bus) {
931 ret = -ENOMEM;
932 goto err;
933 }
934
935 bus->adapter.owner = THIS_MODULE;
936 snprintf(buf: bus->adapter.name,
937 size: sizeof(bus->adapter.name),
938 fmt: "i915 gmbus %s", gmbus_pin->name);
939
940 bus->adapter.dev.parent = &pdev->dev;
941 bus->display = display;
942
943 bus->adapter.algo = &gmbus_algorithm;
944 bus->adapter.lock_ops = &gmbus_lock_ops;
945
946 /*
947 * We wish to retry with bit banging
948 * after a timed out GMBUS attempt.
949 */
950 bus->adapter.retries = 1;
951
952 /* By default use a conservative clock rate */
953 bus->reg0 = pin | GMBUS_RATE_100KHZ;
954
955 /* gmbus seems to be broken on i830 */
956 if (display->platform.i830)
957 bus->force_bit = 1;
958
959 intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio));
960
961 ret = i2c_add_adapter(adap: &bus->adapter);
962 if (ret) {
963 kfree(objp: bus);
964 goto err;
965 }
966
967 display->gmbus.bus[pin] = bus;
968 }
969
970 intel_gmbus_reset(display);
971
972 return 0;
973
974err:
975 intel_gmbus_teardown(display);
976
977 return ret;
978}
979
980struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display,
981 unsigned int pin)
982{
983 if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) ||
984 !display->gmbus.bus[pin]))
985 return NULL;
986
987 return &display->gmbus.bus[pin]->adapter;
988}
989
990void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
991{
992 struct intel_gmbus *bus = to_intel_gmbus(i2c: adapter);
993 struct intel_display *display = bus->display;
994
995 mutex_lock(lock: &display->gmbus.mutex);
996
997 bus->force_bit += force_bit ? 1 : -1;
998 drm_dbg_kms(display->drm,
999 "%sabling bit-banging on %s. force bit now %d\n",
1000 force_bit ? "en" : "dis", adapter->name,
1001 bus->force_bit);
1002
1003 mutex_unlock(lock: &display->gmbus.mutex);
1004}
1005
1006bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1007{
1008 struct intel_gmbus *bus = to_intel_gmbus(i2c: adapter);
1009
1010 return bus->force_bit;
1011}
1012
1013void intel_gmbus_teardown(struct intel_display *display)
1014{
1015 unsigned int pin;
1016
1017 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
1018 struct intel_gmbus *bus;
1019
1020 bus = display->gmbus.bus[pin];
1021 if (!bus)
1022 continue;
1023
1024 i2c_del_adapter(adap: &bus->adapter);
1025
1026 kfree(objp: bus);
1027 display->gmbus.bus[pin] = NULL;
1028 }
1029}
1030
1031void intel_gmbus_irq_handler(struct intel_display *display)
1032{
1033 wake_up_all(&display->gmbus.wait_queue);
1034}
1035