| 1 | // SPDX-License-Identifier: MIT | 
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| 2 | /* | 
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| 3 | * Copyright © 2021 Intel Corporation | 
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| 4 | */ | 
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| 5 |  | 
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| 6 | #include "gem/i915_gem_lmem.h" | 
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| 7 | #include "gem/i915_gem_region.h" | 
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| 8 | #include "i915_drv.h" | 
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| 9 | #include "intel_crtc.h" | 
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| 10 | #include "intel_display.h" | 
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| 11 | #include "intel_display_core.h" | 
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| 12 | #include "intel_display_types.h" | 
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| 13 | #include "intel_fb.h" | 
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| 14 | #include "intel_frontbuffer.h" | 
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| 15 | #include "intel_plane.h" | 
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| 16 | #include "intel_plane_initial.h" | 
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| 17 |  | 
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| 18 | void intel_plane_initial_vblank_wait(struct intel_crtc *crtc) | 
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| 19 | { | 
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| 20 | intel_crtc_wait_for_next_vblank(crtc); | 
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| 21 | } | 
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| 22 |  | 
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| 23 | static bool | 
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| 24 | intel_reuse_initial_plane_obj(struct intel_crtc *this, | 
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| 25 | const struct intel_initial_plane_config plane_configs[], | 
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| 26 | struct drm_framebuffer **fb, | 
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| 27 | struct i915_vma **vma) | 
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| 28 | { | 
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| 29 | struct intel_display *display = to_intel_display(this); | 
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| 30 | struct intel_crtc *crtc; | 
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| 31 |  | 
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| 32 | for_each_intel_crtc(display->drm, crtc) { | 
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| 33 | struct intel_plane *plane = | 
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| 34 | to_intel_plane(crtc->base.primary); | 
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| 35 | const struct intel_plane_state *plane_state = | 
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| 36 | to_intel_plane_state(plane->base.state); | 
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| 37 | const struct intel_crtc_state *crtc_state = | 
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| 38 | to_intel_crtc_state(crtc->base.state); | 
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| 39 |  | 
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| 40 | if (!crtc_state->uapi.active) | 
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| 41 | continue; | 
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| 42 |  | 
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| 43 | if (!plane_state->ggtt_vma) | 
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| 44 | continue; | 
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| 45 |  | 
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| 46 | if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) { | 
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| 47 | *fb = plane_state->hw.fb; | 
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| 48 | *vma = plane_state->ggtt_vma; | 
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| 49 | return true; | 
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| 50 | } | 
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| 51 | } | 
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| 52 |  | 
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| 53 | return false; | 
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| 54 | } | 
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| 55 |  | 
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| 56 | static enum intel_memory_type | 
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| 57 | initial_plane_memory_type(struct intel_display *display) | 
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| 58 | { | 
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| 59 | struct drm_i915_private *i915 = to_i915(dev: display->drm); | 
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| 60 |  | 
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| 61 | if (display->platform.dgfx) | 
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| 62 | return INTEL_MEMORY_LOCAL; | 
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| 63 | else if (HAS_LMEMBAR_SMEM_STOLEN(i915)) | 
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| 64 | return INTEL_MEMORY_STOLEN_LOCAL; | 
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| 65 | else | 
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| 66 | return INTEL_MEMORY_STOLEN_SYSTEM; | 
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| 67 | } | 
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| 68 |  | 
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| 69 | static bool | 
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| 70 | initial_plane_phys(struct intel_display *display, | 
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| 71 | struct intel_initial_plane_config *plane_config) | 
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| 72 | { | 
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| 73 | struct drm_i915_private *i915 = to_i915(dev: display->drm); | 
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| 74 | struct i915_ggtt *ggtt = to_gt(i915)->ggtt; | 
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| 75 | struct intel_memory_region *mem; | 
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| 76 | enum intel_memory_type mem_type; | 
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| 77 | bool is_present, is_local; | 
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| 78 | dma_addr_t dma_addr; | 
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| 79 | u32 base; | 
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| 80 |  | 
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| 81 | mem_type = initial_plane_memory_type(display); | 
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| 82 | mem = intel_memory_region_by_type(i915, mem_type); | 
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| 83 | if (!mem) { | 
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| 84 | drm_dbg_kms(display->drm, | 
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| 85 | "Initial plane memory region (type %s) not initialized\n", | 
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| 86 | intel_memory_type_str(mem_type)); | 
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| 87 | return false; | 
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| 88 | } | 
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| 89 |  | 
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| 90 | base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); | 
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| 91 |  | 
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| 92 | dma_addr = intel_ggtt_read_entry(vm: &ggtt->vm, offset: base, is_present: &is_present, is_local: &is_local); | 
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| 93 |  | 
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| 94 | if (!is_present) { | 
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| 95 | drm_err(display->drm, | 
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| 96 | "Initial plane FB PTE not present\n"); | 
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| 97 | return false; | 
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| 98 | } | 
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| 99 |  | 
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| 100 | if (intel_memory_type_is_local(mem_type: mem->type) != is_local) { | 
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| 101 | drm_err(display->drm, | 
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| 102 | "Initial plane FB PTE unsuitable for %s\n", | 
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| 103 | mem->region.name); | 
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| 104 | return false; | 
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| 105 | } | 
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| 106 |  | 
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| 107 | if (dma_addr < mem->region.start || dma_addr > mem->region.end) { | 
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| 108 | drm_err(display->drm, | 
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| 109 | "Initial plane programming using invalid range, dma_addr=%pa (%s [%pa-%pa])\n", | 
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| 110 | &dma_addr, mem->region.name, &mem->region.start, &mem->region.end); | 
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| 111 | return false; | 
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| 112 | } | 
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| 113 |  | 
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| 114 | drm_dbg(display->drm, | 
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| 115 | "Using dma_addr=%pa, based on initial plane programming\n", | 
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| 116 | &dma_addr); | 
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| 117 |  | 
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| 118 | plane_config->phys_base = dma_addr - mem->region.start; | 
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| 119 | plane_config->mem = mem; | 
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| 120 |  | 
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| 121 | return true; | 
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| 122 | } | 
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| 123 |  | 
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| 124 | static struct i915_vma * | 
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| 125 | initial_plane_vma(struct intel_display *display, | 
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| 126 | struct intel_initial_plane_config *plane_config) | 
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| 127 | { | 
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| 128 | struct drm_i915_private *i915 = to_i915(dev: display->drm); | 
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| 129 | struct intel_memory_region *mem; | 
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| 130 | struct drm_i915_gem_object *obj; | 
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| 131 | struct drm_mm_node orig_mm = {}; | 
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| 132 | struct i915_vma *vma; | 
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| 133 | resource_size_t phys_base; | 
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| 134 | u32 base, size; | 
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| 135 | u64 pinctl; | 
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| 136 |  | 
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| 137 | if (plane_config->size == 0) | 
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| 138 | return NULL; | 
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| 139 |  | 
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| 140 | if (!initial_plane_phys(display, plane_config)) | 
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| 141 | return NULL; | 
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| 142 |  | 
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| 143 | phys_base = plane_config->phys_base; | 
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| 144 | mem = plane_config->mem; | 
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| 145 |  | 
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| 146 | base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); | 
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| 147 | size = round_up(plane_config->base + plane_config->size, | 
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| 148 | mem->min_page_size); | 
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| 149 | size -= base; | 
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| 150 |  | 
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| 151 | /* | 
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| 152 | * If the FB is too big, just don't use it since fbdev is not very | 
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| 153 | * important and we should probably use that space with FBC or other | 
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| 154 | * features. | 
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| 155 | */ | 
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| 156 | if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) && | 
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| 157 | mem == i915->mm.stolen_region && | 
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| 158 | size * 2 > i915->dsm.usable_size) { | 
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| 159 | drm_dbg_kms(display->drm, "Initial FB size exceeds half of stolen, discarding\n"); | 
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| 160 | return NULL; | 
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| 161 | } | 
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| 162 |  | 
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| 163 | obj = i915_gem_object_create_region_at(mem, offset: phys_base, size, | 
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| 164 | I915_BO_ALLOC_USER | | 
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| 165 | I915_BO_PREALLOC); | 
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| 166 | if (IS_ERR(ptr: obj)) { | 
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| 167 | drm_dbg_kms(display->drm, "Failed to preallocate initial FB in %s\n", | 
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| 168 | mem->region.name); | 
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| 169 | return NULL; | 
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| 170 | } | 
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| 171 |  | 
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| 172 | /* | 
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| 173 | * Mark it WT ahead of time to avoid changing the | 
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| 174 | * cache_level during fbdev initialization. The | 
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| 175 | * unbind there would get stuck waiting for rcu. | 
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| 176 | */ | 
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| 177 | i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ? | 
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| 178 | I915_CACHE_WT : I915_CACHE_NONE); | 
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| 179 |  | 
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| 180 | switch (plane_config->tiling) { | 
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| 181 | case I915_TILING_NONE: | 
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| 182 | break; | 
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| 183 | case I915_TILING_X: | 
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| 184 | case I915_TILING_Y: | 
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| 185 | obj->tiling_and_stride = | 
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| 186 | plane_config->fb->base.pitches[0] | | 
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| 187 | plane_config->tiling; | 
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| 188 | break; | 
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| 189 | default: | 
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| 190 | MISSING_CASE(plane_config->tiling); | 
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| 191 | goto err_obj; | 
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| 192 | } | 
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| 193 |  | 
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| 194 | /* | 
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| 195 | * MTL GOP likes to place the framebuffer high up in ggtt, | 
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| 196 | * which can cause problems for ggtt_reserve_guc_top(). | 
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| 197 | * Try to pin it to a low ggtt address instead to avoid that. | 
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| 198 | */ | 
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| 199 | base = 0; | 
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| 200 |  | 
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| 201 | if (base != plane_config->base) { | 
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| 202 | struct i915_ggtt *ggtt = to_gt(i915)->ggtt; | 
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| 203 | int ret; | 
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| 204 |  | 
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| 205 | /* | 
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| 206 | * Make sure the original and new locations | 
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| 207 | * can't overlap. That would corrupt the original | 
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| 208 | * PTEs which are still being used for scanout. | 
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| 209 | */ | 
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| 210 | ret = i915_gem_gtt_reserve(vm: &ggtt->vm, NULL, node: &orig_mm, | 
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| 211 | size, offset: plane_config->base, | 
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| 212 | I915_COLOR_UNEVICTABLE, PIN_NOEVICT); | 
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| 213 | if (ret) | 
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| 214 | goto err_obj; | 
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| 215 | } | 
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| 216 |  | 
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| 217 | vma = i915_vma_instance(obj, vm: &to_gt(i915)->ggtt->vm, NULL); | 
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| 218 | if (IS_ERR(ptr: vma)) | 
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| 219 | goto err_obj; | 
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| 220 |  | 
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| 221 | retry: | 
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| 222 | pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base; | 
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| 223 | if (!i915_gem_object_is_lmem(obj)) | 
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| 224 | pinctl |= PIN_MAPPABLE; | 
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| 225 | if (i915_vma_pin(vma, size: 0, alignment: 0, flags: pinctl)) { | 
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| 226 | if (drm_mm_node_allocated(node: &orig_mm)) { | 
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| 227 | drm_mm_remove_node(node: &orig_mm); | 
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| 228 | /* | 
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| 229 | * Try again, but this time pin | 
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| 230 | * it to its original location. | 
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| 231 | */ | 
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| 232 | base = plane_config->base; | 
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| 233 | goto retry; | 
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| 234 | } | 
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| 235 | goto err_obj; | 
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| 236 | } | 
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| 237 |  | 
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| 238 | if (i915_gem_object_is_tiled(obj) && | 
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| 239 | !i915_vma_is_map_and_fenceable(vma)) | 
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| 240 | goto err_obj; | 
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| 241 |  | 
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| 242 | if (drm_mm_node_allocated(node: &orig_mm)) | 
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| 243 | drm_mm_remove_node(node: &orig_mm); | 
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| 244 |  | 
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| 245 | drm_dbg_kms(display->drm, | 
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| 246 | "Initial plane fb bound to 0x%x in the ggtt (original 0x%x)\n", | 
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| 247 | i915_ggtt_offset(vma), plane_config->base); | 
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| 248 |  | 
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| 249 | return vma; | 
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| 250 |  | 
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| 251 | err_obj: | 
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| 252 | if (drm_mm_node_allocated(node: &orig_mm)) | 
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| 253 | drm_mm_remove_node(node: &orig_mm); | 
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| 254 | i915_gem_object_put(obj); | 
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| 255 | return NULL; | 
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| 256 | } | 
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| 257 |  | 
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| 258 | static bool | 
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| 259 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, | 
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| 260 | struct intel_initial_plane_config *plane_config) | 
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| 261 | { | 
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| 262 | struct intel_display *display = to_intel_display(crtc); | 
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| 263 | struct drm_mode_fb_cmd2 mode_cmd = {}; | 
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| 264 | struct drm_framebuffer *fb = &plane_config->fb->base; | 
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| 265 | struct i915_vma *vma; | 
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| 266 |  | 
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| 267 | switch (fb->modifier) { | 
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| 268 | case DRM_FORMAT_MOD_LINEAR: | 
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| 269 | case I915_FORMAT_MOD_X_TILED: | 
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| 270 | case I915_FORMAT_MOD_Y_TILED: | 
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| 271 | case I915_FORMAT_MOD_4_TILED: | 
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| 272 | break; | 
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| 273 | default: | 
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| 274 | drm_dbg(display->drm, | 
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| 275 | "Unsupported modifier for initial FB: 0x%llx\n", | 
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| 276 | fb->modifier); | 
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| 277 | return false; | 
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| 278 | } | 
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| 279 |  | 
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| 280 | vma = initial_plane_vma(display, plane_config); | 
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| 281 | if (!vma) | 
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| 282 | return false; | 
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| 283 |  | 
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| 284 | mode_cmd.pixel_format = fb->format->format; | 
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| 285 | mode_cmd.width = fb->width; | 
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| 286 | mode_cmd.height = fb->height; | 
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| 287 | mode_cmd.pitches[0] = fb->pitches[0]; | 
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| 288 | mode_cmd.modifier[0] = fb->modifier; | 
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| 289 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | 
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| 290 |  | 
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| 291 | if (intel_framebuffer_init(to_intel_framebuffer(fb), | 
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| 292 | intel_bo_to_drm_bo(vma->obj), | 
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| 293 | info: fb->format, mode_cmd: &mode_cmd)) { | 
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| 294 | drm_dbg_kms(display->drm, "intel fb init failed\n"); | 
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| 295 | goto err_vma; | 
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| 296 | } | 
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| 297 |  | 
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| 298 | plane_config->vma = vma; | 
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| 299 | return true; | 
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| 300 |  | 
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| 301 | err_vma: | 
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| 302 | i915_vma_put(vma); | 
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| 303 | return false; | 
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| 304 | } | 
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| 305 |  | 
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| 306 | static void | 
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| 307 | intel_find_initial_plane_obj(struct intel_crtc *crtc, | 
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| 308 | struct intel_initial_plane_config plane_configs[]) | 
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| 309 | { | 
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| 310 | struct drm_i915_private *dev_priv = to_i915(dev: crtc->base.dev); | 
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| 311 | struct intel_initial_plane_config *plane_config = | 
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| 312 | &plane_configs[crtc->pipe]; | 
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| 313 | struct intel_plane *plane = | 
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| 314 | to_intel_plane(crtc->base.primary); | 
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| 315 | struct intel_plane_state *plane_state = | 
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| 316 | to_intel_plane_state(plane->base.state); | 
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| 317 | struct drm_framebuffer *fb; | 
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| 318 | struct i915_vma *vma; | 
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| 319 |  | 
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| 320 | /* | 
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| 321 | * TODO: | 
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| 322 | *   Disable planes if get_initial_plane_config() failed. | 
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| 323 | *   Make sure things work if the surface base is not page aligned. | 
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| 324 | */ | 
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| 325 | if (!plane_config->fb) | 
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| 326 | return; | 
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| 327 |  | 
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| 328 | if (intel_alloc_initial_plane_obj(crtc, plane_config)) { | 
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| 329 | fb = &plane_config->fb->base; | 
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| 330 | vma = plane_config->vma; | 
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| 331 | goto valid_fb; | 
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| 332 | } | 
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| 333 |  | 
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| 334 | /* | 
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| 335 | * Failed to alloc the obj, check to see if we should share | 
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| 336 | * an fb with another CRTC instead | 
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| 337 | */ | 
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| 338 | if (intel_reuse_initial_plane_obj(this: crtc, plane_configs, fb: &fb, vma: &vma)) | 
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| 339 | goto valid_fb; | 
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| 340 |  | 
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| 341 | /* | 
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| 342 | * We've failed to reconstruct the BIOS FB.  Current display state | 
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| 343 | * indicates that the primary plane is visible, but has a NULL FB, | 
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| 344 | * which will lead to problems later if we don't fix it up.  The | 
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| 345 | * simplest solution is to just disable the primary plane now and | 
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| 346 | * pretend the BIOS never had it enabled. | 
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| 347 | */ | 
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| 348 | intel_plane_disable_noatomic(crtc, plane); | 
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| 349 |  | 
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| 350 | return; | 
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| 351 |  | 
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| 352 | valid_fb: | 
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| 353 | plane_state->uapi.rotation = plane_config->rotation; | 
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| 354 | intel_fb_fill_view(to_intel_framebuffer(fb), | 
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| 355 | rotation: plane_state->uapi.rotation, view: &plane_state->view); | 
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| 356 |  | 
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| 357 | __i915_vma_pin(vma); | 
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| 358 | plane_state->ggtt_vma = i915_vma_get(vma); | 
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| 359 | if (intel_plane_uses_fence(plane_state) && | 
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| 360 | i915_vma_pin_fence(vma) == 0 && vma->fence) | 
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| 361 | plane_state->flags |= PLANE_HAS_FENCE; | 
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| 362 |  | 
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| 363 | plane_state->surf = i915_ggtt_offset(vma: plane_state->ggtt_vma); | 
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| 364 |  | 
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| 365 | plane_state->uapi.src_x = 0; | 
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| 366 | plane_state->uapi.src_y = 0; | 
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| 367 | plane_state->uapi.src_w = fb->width << 16; | 
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| 368 | plane_state->uapi.src_h = fb->height << 16; | 
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| 369 |  | 
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| 370 | plane_state->uapi.crtc_x = 0; | 
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| 371 | plane_state->uapi.crtc_y = 0; | 
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| 372 | plane_state->uapi.crtc_w = fb->width; | 
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| 373 | plane_state->uapi.crtc_h = fb->height; | 
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| 374 |  | 
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| 375 | if (plane_config->tiling) | 
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| 376 | dev_priv->preserve_bios_swizzle = true; | 
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| 377 |  | 
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| 378 | plane_state->uapi.fb = fb; | 
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| 379 | drm_framebuffer_get(fb); | 
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| 380 |  | 
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| 381 | plane_state->uapi.crtc = &crtc->base; | 
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| 382 | intel_plane_copy_uapi_to_hw_state(plane_state, from_plane_state: plane_state, crtc); | 
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| 383 |  | 
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| 384 | atomic_or(i: plane->frontbuffer_bit, v: &to_intel_frontbuffer(fb)->bits); | 
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| 385 | } | 
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| 386 |  | 
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| 387 | static void plane_config_fini(struct intel_initial_plane_config *plane_config) | 
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| 388 | { | 
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| 389 | if (plane_config->fb) { | 
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| 390 | struct drm_framebuffer *fb = &plane_config->fb->base; | 
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| 391 |  | 
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| 392 | /* We may only have the stub and not a full framebuffer */ | 
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| 393 | if (drm_framebuffer_read_refcount(fb)) | 
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| 394 | drm_framebuffer_put(fb); | 
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| 395 | else | 
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| 396 | kfree(objp: fb); | 
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| 397 | } | 
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| 398 |  | 
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| 399 | if (plane_config->vma) | 
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| 400 | i915_vma_put(vma: plane_config->vma); | 
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| 401 | } | 
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| 402 |  | 
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| 403 | void intel_initial_plane_config(struct intel_display *display) | 
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| 404 | { | 
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| 405 | struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; | 
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| 406 | struct intel_crtc *crtc; | 
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| 407 |  | 
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| 408 | for_each_intel_crtc(display->drm, crtc) { | 
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| 409 | struct intel_initial_plane_config *plane_config = | 
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| 410 | &plane_configs[crtc->pipe]; | 
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| 411 |  | 
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| 412 | if (!to_intel_crtc_state(crtc->base.state)->uapi.active) | 
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| 413 | continue; | 
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| 414 |  | 
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| 415 | /* | 
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| 416 | * Note that reserving the BIOS fb up front prevents us | 
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| 417 | * from stuffing other stolen allocations like the ring | 
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| 418 | * on top.  This prevents some ugliness at boot time, and | 
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| 419 | * can even allow for smooth boot transitions if the BIOS | 
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| 420 | * fb is large enough for the active pipe configuration. | 
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| 421 | */ | 
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| 422 | display->funcs.display->get_initial_plane_config(crtc, plane_config); | 
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| 423 |  | 
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| 424 | /* | 
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| 425 | * If the fb is shared between multiple heads, we'll | 
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| 426 | * just get the first one. | 
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| 427 | */ | 
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| 428 | intel_find_initial_plane_obj(crtc, plane_configs); | 
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| 429 |  | 
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| 430 | if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config)) | 
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| 431 | intel_plane_initial_vblank_wait(crtc); | 
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| 432 |  | 
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| 433 | plane_config_fini(plane_config); | 
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| 434 | } | 
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| 435 | } | 
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| 436 |  | 
|---|