1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/ethtool.h>
19#include <linux/phy.h>
20#include <linux/if_vlan.h>
21#include <linux/in.h>
22#include <linux/io.h>
23#include <linux/ip.h>
24#include <linux/tcp.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
27#include <linux/pm_runtime.h>
28#include <linux/bitfield.h>
29#include <linux/prefetch.h>
30#include <linux/ipv6.h>
31#include <linux/unaligned.h>
32#include <net/ip6_checksum.h>
33#include <net/netdev_queues.h>
34
35#include "r8169.h"
36#include "r8169_firmware.h"
37
38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
55#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
56#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
57#define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
58#define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw"
59#define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw"
60#define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw"
61#define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw"
62#define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw"
63#define FIRMWARE_8127A_1 "rtl_nic/rtl8127a-1.fw"
64
65#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
66#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
67
68#define R8169_REGS_SIZE 256
69#define R8169_RX_BUF_SIZE (SZ_16K - 1)
70#define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
71#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
72#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
73#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
74#define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1)
75#define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS)
76
77#define OCP_STD_PHY_BASE 0xa400
78
79#define RTL_CFG_NO_GBIT 1
80
81/* write/read MMIO register */
82#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
83#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
84#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
85#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
86#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
87#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
88
89#define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
90#define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
91#define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
92#define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
93#define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN)
94
95static const struct rtl_chip_info {
96 u16 mask;
97 u16 val;
98 enum mac_version mac_version;
99 const char *name;
100 const char *fw_name;
101} rtl_chip_infos[] = {
102 /* 8127A family. */
103 { 0x7cf, 0x6c9, RTL_GIGA_MAC_VER_80, "RTL8127A", FIRMWARE_8127A_1 },
104
105 /* 8126A family. */
106 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 },
107 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 },
108
109 /* 8125BP family. */
110 { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 },
111
112 /* 8125D family. */
113 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 },
114 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 },
115
116 /* 8125B family. */
117 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63, "RTL8125B", FIRMWARE_8125B_2 },
118
119 /* 8125A family. */
120 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 },
121
122 /* RTL8117 */
123 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117" },
124 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117",
125 FIRMWARE_8168FP_3 },
126
127 /* 8168EP family. */
128 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51, "RTL8168ep/8111ep" },
129
130 /* 8168H family. */
131 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46, "RTL8168h/8111h",
132 FIRMWARE_8168H_2 },
133 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */
134 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46, "RTL8168M", FIRMWARE_8168H_2 },
135
136 /* 8168G family. */
137 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44, "RTL8411b", FIRMWARE_8411_2 },
138 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42, "RTL8168gu/8111gu",
139 FIRMWARE_8168G_3 },
140 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40, "RTL8168g/8111g",
141 FIRMWARE_8168G_2 },
142
143 /* 8168F family. */
144 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38, "RTL8411", FIRMWARE_8411_1 },
145 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36, "RTL8168f/8111f",
146 FIRMWARE_8168F_2 },
147 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35, "RTL8168f/8111f",
148 FIRMWARE_8168F_1 },
149
150 /* 8168E family. */
151 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34, "RTL8168evl/8111evl",
152 FIRMWARE_8168E_3 },
153 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32, "RTL8168e/8111e",
154 FIRMWARE_8168E_1 },
155 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33, "RTL8168e/8111e",
156 FIRMWARE_8168E_2 },
157
158 /* 8168D family. */
159 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25, "RTL8168d/8111d",
160 FIRMWARE_8168D_1 },
161 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26, "RTL8168d/8111d",
162 FIRMWARE_8168D_2 },
163
164 /* 8168DP family. */
165 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28, "RTL8168dp/8111dp" },
166 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31, "RTL8168dp/8111dp" },
167
168 /* 8168C family. */
169 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23, "RTL8168cp/8111cp" },
170 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18, "RTL8168cp/8111cp" },
171 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24, "RTL8168cp/8111cp" },
172 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19, "RTL8168c/8111c" },
173 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20, "RTL8168c/8111c" },
174 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21, "RTL8168c/8111c" },
175 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22, "RTL8168c/8111c" },
176
177 /* 8168B family. */
178 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17, "RTL8168b/8111b" },
179 /* This one is very old and rare, support has been removed.
180 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" },
181 */
182
183 /* 8101 family. */
184 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39, "RTL8106e", FIRMWARE_8106E_1 },
185 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37, "RTL8402", FIRMWARE_8402_1 },
186 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29, "RTL8105e", FIRMWARE_8105E_1 },
187 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30, "RTL8105e", FIRMWARE_8105E_1 },
188 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08, "RTL8102e" },
189 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08, "RTL8102e" },
190 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07, "RTL8102e" },
191 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07, "RTL8102e" },
192 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14, "RTL8401" },
193 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" },
194 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" },
195 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10, "RTL8101e/RTL8100e" },
196
197 /* 8110 family. */
198 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06, "RTL8169sc/8110sc" },
199 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05, "RTL8169sc/8110sc" },
200 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04, "RTL8169sb/8110sb" },
201 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" },
202 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" },
203
204 /* Catch-all */
205 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
206};
207
208static const struct pci_device_id rtl8169_pci_tbl[] = {
209 { PCI_VDEVICE(REALTEK, 0x2502) },
210 { PCI_VDEVICE(REALTEK, 0x2600) },
211 { PCI_VDEVICE(REALTEK, 0x8129) },
212 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
213 { PCI_VDEVICE(REALTEK, 0x8161) },
214 { PCI_VDEVICE(REALTEK, 0x8162) },
215 { PCI_VDEVICE(REALTEK, 0x8167) },
216 { PCI_VDEVICE(REALTEK, 0x8168) },
217 { PCI_VDEVICE(NCUBE, 0x8168) },
218 { PCI_VDEVICE(REALTEK, 0x8169) },
219 { PCI_VDEVICE(DLINK, 0x4300) },
220 { PCI_VDEVICE(DLINK, 0x4302) },
221 { PCI_VDEVICE(AT, 0xc107) },
222 { PCI_VDEVICE(USR, 0x0116) },
223 { PCI_VENDOR_ID_LINKSYS, .device: 0x1032, PCI_ANY_ID, .subdevice: 0x0024 },
224 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
225 { PCI_VDEVICE(REALTEK, 0x8125) },
226 { PCI_VDEVICE(REALTEK, 0x8126) },
227 { PCI_VDEVICE(REALTEK, 0x8127) },
228 { PCI_VDEVICE(REALTEK, 0x3000) },
229 { PCI_VDEVICE(REALTEK, 0x5000) },
230 { PCI_VDEVICE(REALTEK, 0x0e10) },
231 {}
232};
233
234MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
235
236enum rtl_registers {
237 MAC0 = 0, /* Ethernet hardware address. */
238 MAC4 = 4,
239 MAR0 = 8, /* Multicast filter. */
240 CounterAddrLow = 0x10,
241 CounterAddrHigh = 0x14,
242 TxDescStartAddrLow = 0x20,
243 TxDescStartAddrHigh = 0x24,
244 TxHDescStartAddrLow = 0x28,
245 TxHDescStartAddrHigh = 0x2c,
246 FLASH = 0x30,
247 ERSR = 0x36,
248 ChipCmd = 0x37,
249 TxPoll = 0x38,
250 IntrMask = 0x3c,
251 IntrStatus = 0x3e,
252
253 TxConfig = 0x40,
254#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
255#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
256
257 RxConfig = 0x44,
258#define RX128_INT_EN (1 << 15) /* 8111c and later */
259#define RX_MULTI_EN (1 << 14) /* 8111c only */
260#define RXCFG_FIFO_SHIFT 13
261 /* No threshold before first PCI xfer */
262#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
263#define RX_EARLY_OFF (1 << 11)
264#define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */
265#define RXCFG_DMA_SHIFT 8
266 /* Unlimited maximum PCI burst. */
267#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
268
269 Cfg9346 = 0x50,
270 Config0 = 0x51,
271 Config1 = 0x52,
272 Config2 = 0x53,
273#define PME_SIGNAL (1 << 5) /* 8168c and later */
274
275 Config3 = 0x54,
276 Config4 = 0x55,
277 Config5 = 0x56,
278 PHYAR = 0x60,
279 PHYstatus = 0x6c,
280 RxMaxSize = 0xda,
281 CPlusCmd = 0xe0,
282 IntrMitigate = 0xe2,
283
284#define RTL_COALESCE_TX_USECS GENMASK(15, 12)
285#define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
286#define RTL_COALESCE_RX_USECS GENMASK(7, 4)
287#define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
288
289#define RTL_COALESCE_T_MAX 0x0fU
290#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
291
292 RxDescAddrLow = 0xe4,
293 RxDescAddrHigh = 0xe8,
294 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
295
296#define NoEarlyTx 0x3f /* Max value : no early transmit. */
297
298 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
299
300#define TxPacketMax (8064 >> 7)
301#define EarlySize 0x27
302
303 FuncEvent = 0xf0,
304 FuncEventMask = 0xf4,
305 FuncPresetState = 0xf8,
306 IBCR0 = 0xf8,
307 IBCR2 = 0xf9,
308 IBIMR0 = 0xfa,
309 IBISR0 = 0xfb,
310 FuncForceEvent = 0xfc,
311};
312
313enum rtl8168_8101_registers {
314 CSIDR = 0x64,
315 CSIAR = 0x68,
316#define CSIAR_FLAG 0x80000000
317#define CSIAR_WRITE_CMD 0x80000000
318#define CSIAR_BYTE_ENABLE 0x0000f000
319#define CSIAR_ADDR_MASK 0x00000fff
320 PMCH = 0x6f,
321#define D3COLD_NO_PLL_DOWN BIT(7)
322#define D3HOT_NO_PLL_DOWN BIT(6)
323#define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
324 EPHYAR = 0x80,
325#define EPHYAR_FLAG 0x80000000
326#define EPHYAR_WRITE_CMD 0x80000000
327#define EPHYAR_REG_MASK 0x1f
328#define EPHYAR_REG_SHIFT 16
329#define EPHYAR_DATA_MASK 0xffff
330 DLLPR = 0xd0,
331#define PFM_EN (1 << 6)
332#define TX_10M_PS_EN (1 << 7)
333 DBG_REG = 0xd1,
334#define FIX_NAK_1 (1 << 4)
335#define FIX_NAK_2 (1 << 3)
336 TWSI = 0xd2,
337 MCU = 0xd3,
338#define NOW_IS_OOB (1 << 7)
339#define TX_EMPTY (1 << 5)
340#define RX_EMPTY (1 << 4)
341#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
342#define EN_NDP (1 << 3)
343#define EN_OOB_RESET (1 << 2)
344#define LINK_LIST_RDY (1 << 1)
345 EFUSEAR = 0xdc,
346#define EFUSEAR_FLAG 0x80000000
347#define EFUSEAR_WRITE_CMD 0x80000000
348#define EFUSEAR_READ_CMD 0x00000000
349#define EFUSEAR_REG_MASK 0x03ff
350#define EFUSEAR_REG_SHIFT 8
351#define EFUSEAR_DATA_MASK 0xff
352 MISC_1 = 0xf2,
353#define PFM_D3COLD_EN (1 << 6)
354};
355
356enum rtl8168_registers {
357 LED_CTRL = 0x18,
358 LED_FREQ = 0x1a,
359 EEE_LED = 0x1b,
360 ERIDR = 0x70,
361 ERIAR = 0x74,
362#define ERIAR_FLAG 0x80000000
363#define ERIAR_WRITE_CMD 0x80000000
364#define ERIAR_READ_CMD 0x00000000
365#define ERIAR_ADDR_BYTE_ALIGN 4
366#define ERIAR_TYPE_SHIFT 16
367#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
368#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
369#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
370#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
371#define ERIAR_MASK_SHIFT 12
372#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
373#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
374#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
375#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
376#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
377 EPHY_RXER_NUM = 0x7c,
378 OCPDR = 0xb0, /* OCP GPHY access */
379#define OCPDR_WRITE_CMD 0x80000000
380#define OCPDR_READ_CMD 0x00000000
381#define OCPDR_REG_MASK 0x7f
382#define OCPDR_GPHY_REG_SHIFT 16
383#define OCPDR_DATA_MASK 0xffff
384 OCPAR = 0xb4,
385#define OCPAR_FLAG 0x80000000
386#define OCPAR_GPHY_WRITE_CMD 0x8000f060
387#define OCPAR_GPHY_READ_CMD 0x0000f060
388 GPHY_OCP = 0xb8,
389 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC = 0xf0, /* 8168e only. */
391#define TXPLA_RST (1 << 29)
392#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
393#define PWM_EN (1 << 22)
394#define RXDV_GATED_EN (1 << 19)
395#define EARLY_TALLY_EN (1 << 16)
396};
397
398enum rtl8125_registers {
399 LEDSEL0 = 0x18,
400 INT_CFG0_8125 = 0x34,
401#define INT_CFG0_ENABLE_8125 BIT(0)
402#define INT_CFG0_CLKREQEN BIT(3)
403 IntrMask_8125 = 0x38,
404 IntrStatus_8125 = 0x3c,
405 INT_CFG1_8125 = 0x7a,
406 LEDSEL2 = 0x84,
407 LEDSEL1 = 0x86,
408 TxPoll_8125 = 0x90,
409 LEDSEL3 = 0x96,
410 MAC0_BKP = 0x19e0,
411 RSS_CTRL_8125 = 0x4500,
412 Q_NUM_CTRL_8125 = 0x4800,
413 EEE_TXIDLE_TIMER_8125 = 0x6048,
414};
415
416#define LEDSEL_MASK_8125 0x23f
417
418#define RX_VLAN_INNER_8125 BIT(22)
419#define RX_VLAN_OUTER_8125 BIT(23)
420#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
421
422#define RX_FETCH_DFLT_8125 (8 << 27)
423
424enum rtl_register_content {
425 /* InterruptStatusBits */
426 SYSErr = 0x8000,
427 PCSTimeout = 0x4000,
428 SWInt = 0x0100,
429 TxDescUnavail = 0x0080,
430 RxFIFOOver = 0x0040,
431 LinkChg = 0x0020,
432 RxOverflow = 0x0010,
433 TxErr = 0x0008,
434 TxOK = 0x0004,
435 RxErr = 0x0002,
436 RxOK = 0x0001,
437
438 /* RxStatusDesc */
439 RxRWT = (1 << 22),
440 RxRES = (1 << 21),
441 RxRUNT = (1 << 20),
442 RxCRC = (1 << 19),
443
444 /* ChipCmdBits */
445 StopReq = 0x80,
446 CmdReset = 0x10,
447 CmdRxEnb = 0x08,
448 CmdTxEnb = 0x04,
449 RxBufEmpty = 0x01,
450
451 /* TXPoll register p.5 */
452 HPQ = 0x80, /* Poll cmd on the high prio queue */
453 NPQ = 0x40, /* Poll cmd on the low prio queue */
454 FSWInt = 0x01, /* Forced software interrupt */
455
456 /* Cfg9346Bits */
457 Cfg9346_Lock = 0x00,
458 Cfg9346_Unlock = 0xc0,
459
460 /* rx_mode_bits */
461 AcceptErr = 0x20,
462 AcceptRunt = 0x10,
463#define RX_CONFIG_ACCEPT_ERR_MASK 0x30
464 AcceptBroadcast = 0x08,
465 AcceptMulticast = 0x04,
466 AcceptMyPhys = 0x02,
467 AcceptAllPhys = 0x01,
468#define RX_CONFIG_ACCEPT_OK_MASK 0x0f
469#define RX_CONFIG_ACCEPT_MASK 0x3f
470
471 /* TxConfigBits */
472 TxInterFrameGapShift = 24,
473 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
474
475 /* Config1 register p.24 */
476 LEDS1 = (1 << 7),
477 LEDS0 = (1 << 6),
478 Speed_down = (1 << 4),
479 MEMMAP = (1 << 3),
480 IOMAP = (1 << 2),
481 VPD = (1 << 1),
482 PMEnable = (1 << 0), /* Power Management Enable */
483
484 /* Config2 register p. 25 */
485 ClkReqEn = (1 << 7), /* Clock Request Enable */
486 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
487 PCI_Clock_66MHz = 0x01,
488 PCI_Clock_33MHz = 0x00,
489
490 /* Config3 register p.25 */
491 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
492 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
493 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
494 Rdy_to_L23 = (1 << 1), /* L23 Enable */
495 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
496
497 /* Config4 register */
498 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
499
500 /* Config5 register p.27 */
501 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
502 MWF = (1 << 5), /* Accept Multicast wakeup frame */
503 UWF = (1 << 4), /* Accept Unicast wakeup frame */
504 Spi_en = (1 << 3),
505 LanWake = (1 << 1), /* LanWake enable/disable */
506 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
507 ASPM_en = (1 << 0), /* ASPM enable */
508
509 /* CPlusCmd p.31 */
510 EnableBist = (1 << 15), // 8168 8101
511 Mac_dbgo_oe = (1 << 14), // 8168 8101
512 EnAnaPLL = (1 << 14), // 8169
513 Normal_mode = (1 << 13), // unused
514 Force_half_dup = (1 << 12), // 8168 8101
515 Force_rxflow_en = (1 << 11), // 8168 8101
516 Force_txflow_en = (1 << 10), // 8168 8101
517 Cxpl_dbg_sel = (1 << 9), // 8168 8101
518 ASF = (1 << 8), // 8168 8101
519 PktCntrDisable = (1 << 7), // 8168 8101
520 Mac_dbgo_sel = 0x001c, // 8168
521 RxVlan = (1 << 6),
522 RxChkSum = (1 << 5),
523 PCIDAC = (1 << 4),
524 PCIMulRW = (1 << 3),
525#define INTT_MASK GENMASK(1, 0)
526#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
527
528 /* rtl8169_PHYstatus */
529 TBI_Enable = 0x80,
530 TxFlowCtrl = 0x40,
531 RxFlowCtrl = 0x20,
532 _1000bpsF = 0x10,
533 _100bps = 0x08,
534 _10bps = 0x04,
535 LinkStatus = 0x02,
536 FullDup = 0x01,
537
538 /* ResetCounterCommand */
539 CounterReset = 0x1,
540
541 /* DumpCounterCommand */
542 CounterDump = 0x8,
543
544 /* magic enable v2 */
545 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
546};
547
548enum rtl_desc_bit {
549 /* First doubleword. */
550 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
551 RingEnd = (1 << 30), /* End of descriptor ring */
552 FirstFrag = (1 << 29), /* First segment of a packet */
553 LastFrag = (1 << 28), /* Final segment of a packet */
554};
555
556/* Generic case. */
557enum rtl_tx_desc_bit {
558 /* First doubleword. */
559 TD_LSO = (1 << 27), /* Large Send Offload */
560#define TD_MSS_MAX 0x07ffu /* MSS value */
561
562 /* Second doubleword. */
563 TxVlanTag = (1 << 17), /* Add VLAN tag */
564};
565
566/* 8169, 8168b and 810x except 8102e. */
567enum rtl_tx_desc_bit_0 {
568 /* First doubleword. */
569#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
570 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
571 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
572 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
573};
574
575/* 8102e, 8168c and beyond. */
576enum rtl_tx_desc_bit_1 {
577 /* First doubleword. */
578 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
579 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
580#define GTTCPHO_SHIFT 18
581#define GTTCPHO_MAX 0x7f
582
583 /* Second doubleword. */
584#define TCPHO_SHIFT 18
585#define TCPHO_MAX 0x3ff
586#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
587 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
588 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
589 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
590 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
591};
592
593enum rtl_rx_desc_bit {
594 /* Rx private */
595 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
596 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
597
598#define RxProtoUDP (PID1)
599#define RxProtoTCP (PID0)
600#define RxProtoIP (PID1 | PID0)
601#define RxProtoMask RxProtoIP
602
603 IPFail = (1 << 16), /* IP checksum failed */
604 UDPFail = (1 << 15), /* UDP/IP checksum failed */
605 TCPFail = (1 << 14), /* TCP/IP checksum failed */
606
607#define RxCSFailMask (IPFail | UDPFail | TCPFail)
608
609 RxVlanTag = (1 << 16), /* VLAN tag available */
610};
611
612#define RTL_GSO_MAX_SIZE_V1 32000
613#define RTL_GSO_MAX_SEGS_V1 24
614#define RTL_GSO_MAX_SIZE_V2 64000
615#define RTL_GSO_MAX_SEGS_V2 64
616
617struct TxDesc {
618 __le32 opts1;
619 __le32 opts2;
620 __le64 addr;
621};
622
623struct RxDesc {
624 __le32 opts1;
625 __le32 opts2;
626 __le64 addr;
627};
628
629struct ring_info {
630 struct sk_buff *skb;
631 u32 len;
632};
633
634struct rtl8169_counters {
635 __le64 tx_packets;
636 __le64 rx_packets;
637 __le64 tx_errors;
638 __le32 rx_errors;
639 __le16 rx_missed;
640 __le16 align_errors;
641 __le32 tx_one_collision;
642 __le32 tx_multi_collision;
643 __le64 rx_unicast;
644 __le64 rx_broadcast;
645 __le32 rx_multicast;
646 __le16 tx_aborted;
647 __le16 tx_underrun;
648 /* new since RTL8125 */
649 __le64 tx_octets;
650 __le64 rx_octets;
651 __le64 rx_multicast64;
652 __le64 tx_unicast64;
653 __le64 tx_broadcast64;
654 __le64 tx_multicast64;
655 __le32 tx_pause_on;
656 __le32 tx_pause_off;
657 __le32 tx_pause_all;
658 __le32 tx_deferred;
659 __le32 tx_late_collision;
660 __le32 tx_all_collision;
661 __le32 tx_aborted32;
662 __le32 align_errors32;
663 __le32 rx_frame_too_long;
664 __le32 rx_runt;
665 __le32 rx_pause_on;
666 __le32 rx_pause_off;
667 __le32 rx_pause_all;
668 __le32 rx_unknown_opcode;
669 __le32 rx_mac_error;
670 __le32 tx_underrun32;
671 __le32 rx_mac_missed;
672 __le32 rx_tcam_dropped;
673 __le32 tdu;
674 __le32 rdu;
675};
676
677struct rtl8169_tc_offsets {
678 bool inited;
679 __le64 tx_errors;
680 __le32 tx_multi_collision;
681 __le16 tx_aborted;
682 __le16 rx_missed;
683};
684
685enum rtl_flag {
686 RTL_FLAG_TASK_RESET_PENDING,
687 RTL_FLAG_TASK_TX_TIMEOUT,
688 RTL_FLAG_MAX
689};
690
691enum rtl_dash_type {
692 RTL_DASH_NONE,
693 RTL_DASH_DP,
694 RTL_DASH_EP,
695 RTL_DASH_25_BP,
696};
697
698struct rtl8169_private {
699 void __iomem *mmio_addr; /* memory map physical address */
700 struct pci_dev *pci_dev;
701 struct net_device *dev;
702 struct phy_device *phydev;
703 struct napi_struct napi;
704 enum mac_version mac_version;
705 enum rtl_dash_type dash_type;
706 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
707 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
708 u32 dirty_tx;
709 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
710 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
711 dma_addr_t TxPhyAddr;
712 dma_addr_t RxPhyAddr;
713 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
714 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
715 u16 cp_cmd;
716 u16 tx_lpi_timer;
717 u32 irq_mask;
718 int irq;
719 struct clk *clk;
720
721 struct {
722 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
723 struct work_struct work;
724 } wk;
725
726 raw_spinlock_t mac_ocp_lock;
727 struct mutex led_lock; /* serialize LED ctrl RMW access */
728
729 unsigned supports_gmii:1;
730 unsigned aspm_manageable:1;
731 unsigned dash_enabled:1;
732 dma_addr_t counters_phys_addr;
733 struct rtl8169_counters *counters;
734 struct rtl8169_tc_offsets tc_offset;
735 u32 saved_wolopts;
736
737 const char *fw_name;
738 struct rtl_fw *rtl_fw;
739
740 struct r8169_led_classdev *leds;
741
742 u32 ocp_base;
743};
744
745typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
746
747MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
748MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
749MODULE_SOFTDEP("pre: realtek");
750MODULE_LICENSE("GPL");
751MODULE_FIRMWARE(FIRMWARE_8168D_1);
752MODULE_FIRMWARE(FIRMWARE_8168D_2);
753MODULE_FIRMWARE(FIRMWARE_8168E_1);
754MODULE_FIRMWARE(FIRMWARE_8168E_2);
755MODULE_FIRMWARE(FIRMWARE_8168E_3);
756MODULE_FIRMWARE(FIRMWARE_8105E_1);
757MODULE_FIRMWARE(FIRMWARE_8168F_1);
758MODULE_FIRMWARE(FIRMWARE_8168F_2);
759MODULE_FIRMWARE(FIRMWARE_8402_1);
760MODULE_FIRMWARE(FIRMWARE_8411_1);
761MODULE_FIRMWARE(FIRMWARE_8411_2);
762MODULE_FIRMWARE(FIRMWARE_8106E_1);
763MODULE_FIRMWARE(FIRMWARE_8106E_2);
764MODULE_FIRMWARE(FIRMWARE_8168G_2);
765MODULE_FIRMWARE(FIRMWARE_8168G_3);
766MODULE_FIRMWARE(FIRMWARE_8168H_2);
767MODULE_FIRMWARE(FIRMWARE_8168FP_3);
768MODULE_FIRMWARE(FIRMWARE_8107E_2);
769MODULE_FIRMWARE(FIRMWARE_8125A_3);
770MODULE_FIRMWARE(FIRMWARE_8125B_2);
771MODULE_FIRMWARE(FIRMWARE_8125D_1);
772MODULE_FIRMWARE(FIRMWARE_8125D_2);
773MODULE_FIRMWARE(FIRMWARE_8125BP_2);
774MODULE_FIRMWARE(FIRMWARE_8126A_2);
775MODULE_FIRMWARE(FIRMWARE_8126A_3);
776MODULE_FIRMWARE(FIRMWARE_8127A_1);
777
778static inline struct device *tp_to_dev(struct rtl8169_private *tp)
779{
780 return &tp->pci_dev->dev;
781}
782
783static void rtl_lock_config_regs(struct rtl8169_private *tp)
784{
785 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
786}
787
788static void rtl_unlock_config_regs(struct rtl8169_private *tp)
789{
790 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
791}
792
793static void rtl_pci_commit(struct rtl8169_private *tp)
794{
795 /* Read an arbitrary register to commit a preceding PCI write */
796 RTL_R8(tp, ChipCmd);
797}
798
799static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
800{
801 u8 val;
802
803 val = RTL_R8(tp, Config2);
804 RTL_W8(tp, Config2, (val & ~clear) | set);
805}
806
807static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
808{
809 u8 val;
810
811 val = RTL_R8(tp, Config5);
812 RTL_W8(tp, Config5, (val & ~clear) | set);
813}
814
815static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg,
816 u8 bits, bool cond)
817{
818 u8 val, old_val;
819
820 old_val = RTL_R8(tp, reg);
821 if (cond)
822 val = old_val | bits;
823 else
824 val = old_val & ~bits;
825 if (val != old_val)
826 RTL_W8(tp, reg, val);
827}
828
829static bool rtl_is_8125(struct rtl8169_private *tp)
830{
831 return tp->mac_version >= RTL_GIGA_MAC_VER_61;
832}
833
834static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
835{
836 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
837 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
838 tp->mac_version <= RTL_GIGA_MAC_VER_52;
839}
840
841static bool rtl_supports_eee(struct rtl8169_private *tp)
842{
843 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
844 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
845 tp->mac_version != RTL_GIGA_MAC_VER_39;
846}
847
848static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
849{
850 int i;
851
852 for (i = 0; i < ETH_ALEN; i++)
853 mac[i] = RTL_R8(tp, reg + i);
854}
855
856struct rtl_cond {
857 bool (*check)(struct rtl8169_private *);
858 const char *msg;
859};
860
861static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
862 unsigned long usecs, int n, bool high)
863{
864 int i;
865
866 for (i = 0; i < n; i++) {
867 if (c->check(tp) == high)
868 return true;
869 fsleep(usecs);
870 }
871
872 if (net_ratelimit())
873 netdev_err(dev: tp->dev, format: "%s == %d (loop: %d, delay: %lu).\n",
874 c->msg, !high, n, usecs);
875 return false;
876}
877
878static bool rtl_loop_wait_high(struct rtl8169_private *tp,
879 const struct rtl_cond *c,
880 unsigned long d, int n)
881{
882 return rtl_loop_wait(tp, c, usecs: d, n, high: true);
883}
884
885static bool rtl_loop_wait_low(struct rtl8169_private *tp,
886 const struct rtl_cond *c,
887 unsigned long d, int n)
888{
889 return rtl_loop_wait(tp, c, usecs: d, n, high: false);
890}
891
892#define DECLARE_RTL_COND(name) \
893static bool name ## _check(struct rtl8169_private *); \
894 \
895static const struct rtl_cond name = { \
896 .check = name ## _check, \
897 .msg = #name \
898}; \
899 \
900static bool name ## _check(struct rtl8169_private *tp)
901
902int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val)
903{
904 struct device *dev = tp_to_dev(tp);
905 int ret;
906
907 ret = pm_runtime_resume_and_get(dev);
908 if (ret < 0)
909 return ret;
910
911 mutex_lock(lock: &tp->led_lock);
912 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val);
913 mutex_unlock(lock: &tp->led_lock);
914
915 pm_runtime_put_sync(dev);
916
917 return 0;
918}
919
920int rtl8168_get_led_mode(struct rtl8169_private *tp)
921{
922 struct device *dev = tp_to_dev(tp);
923 int ret;
924
925 ret = pm_runtime_resume_and_get(dev);
926 if (ret < 0)
927 return ret;
928
929 ret = RTL_R16(tp, LED_CTRL);
930
931 pm_runtime_put_sync(dev);
932
933 return ret;
934}
935
936static int rtl8125_get_led_reg(int index)
937{
938 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 };
939
940 return led_regs[index];
941}
942
943int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode)
944{
945 int reg = rtl8125_get_led_reg(index);
946 struct device *dev = tp_to_dev(tp);
947 int ret;
948 u16 val;
949
950 ret = pm_runtime_resume_and_get(dev);
951 if (ret < 0)
952 return ret;
953
954 mutex_lock(lock: &tp->led_lock);
955 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125;
956 RTL_W16(tp, reg, val | mode);
957 mutex_unlock(lock: &tp->led_lock);
958
959 pm_runtime_put_sync(dev);
960
961 return 0;
962}
963
964int rtl8125_get_led_mode(struct rtl8169_private *tp, int index)
965{
966 int reg = rtl8125_get_led_reg(index);
967 struct device *dev = tp_to_dev(tp);
968 int ret;
969
970 ret = pm_runtime_resume_and_get(dev);
971 if (ret < 0)
972 return ret;
973
974 ret = RTL_R16(tp, reg);
975
976 pm_runtime_put_sync(dev);
977
978 return ret;
979}
980
981void r8169_get_led_name(struct rtl8169_private *tp, int idx,
982 char *buf, int buf_len)
983{
984 struct pci_dev *pdev = tp->pci_dev;
985 char pdom[8], pfun[8];
986 int domain;
987
988 domain = pci_domain_nr(bus: pdev->bus);
989 if (domain)
990 snprintf(buf: pdom, size: sizeof(pdom), fmt: "P%d", domain);
991 else
992 pdom[0] = '\0';
993
994 if (pdev->multifunction)
995 snprintf(buf: pfun, size: sizeof(pfun), fmt: "f%d", PCI_FUNC(pdev->devfn));
996 else
997 pfun[0] = '\0';
998
999 snprintf(buf, size: buf_len, fmt: "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number,
1000 PCI_SLOT(pdev->devfn), pfun, idx);
1001}
1002
1003static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1004{
1005 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
1006 if (type == ERIAR_OOB && tp->mac_version == RTL_GIGA_MAC_VER_52)
1007 *cmd |= 0xf70 << 18;
1008}
1009
1010DECLARE_RTL_COND(rtl_eriar_cond)
1011{
1012 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1013}
1014
1015static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1016 u32 val, int type)
1017{
1018 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1019
1020 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
1021 return;
1022
1023 RTL_W32(tp, ERIDR, val);
1024 r8168fp_adjust_ocp_cmd(tp, cmd: &cmd, type);
1025 RTL_W32(tp, ERIAR, cmd);
1026
1027 rtl_loop_wait_low(tp, c: &rtl_eriar_cond, d: 100, n: 100);
1028}
1029
1030static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1031 u32 val)
1032{
1033 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1034}
1035
1036static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1037{
1038 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1039
1040 r8168fp_adjust_ocp_cmd(tp, cmd: &cmd, type);
1041 RTL_W32(tp, ERIAR, cmd);
1042
1043 return rtl_loop_wait_high(tp, c: &rtl_eriar_cond, d: 100, n: 100) ?
1044 RTL_R32(tp, ERIDR) : ~0;
1045}
1046
1047static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1048{
1049 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1050}
1051
1052static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
1053{
1054 u32 val = rtl_eri_read(tp, addr);
1055
1056 rtl_eri_write(tp, addr, ERIAR_MASK_1111, val: (val & ~m) | p);
1057}
1058
1059static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1060{
1061 rtl_w0w1_eri(tp, addr, p, m: 0);
1062}
1063
1064static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1065{
1066 rtl_w0w1_eri(tp, addr, p: 0, m);
1067}
1068
1069static bool rtl_ocp_reg_failure(u32 reg)
1070{
1071 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
1072}
1073
1074DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1075{
1076 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
1077}
1078
1079static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1080{
1081 if (rtl_ocp_reg_failure(reg))
1082 return;
1083
1084 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1085
1086 rtl_loop_wait_low(tp, c: &rtl_ocp_gphy_cond, d: 25, n: 10);
1087}
1088
1089static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1090{
1091 if (rtl_ocp_reg_failure(reg))
1092 return 0;
1093
1094 RTL_W32(tp, GPHY_OCP, reg << 15);
1095
1096 return rtl_loop_wait_high(tp, c: &rtl_ocp_gphy_cond, d: 25, n: 10) ?
1097 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
1098}
1099
1100static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1101{
1102 if (rtl_ocp_reg_failure(reg))
1103 return;
1104
1105 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
1106}
1107
1108static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1109{
1110 unsigned long flags;
1111
1112 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1113 __r8168_mac_ocp_write(tp, reg, data);
1114 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1115}
1116
1117static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1118{
1119 if (rtl_ocp_reg_failure(reg))
1120 return 0;
1121
1122 RTL_W32(tp, OCPDR, reg << 15);
1123
1124 return RTL_R32(tp, OCPDR);
1125}
1126
1127static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1128{
1129 unsigned long flags;
1130 u16 val;
1131
1132 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1133 val = __r8168_mac_ocp_read(tp, reg);
1134 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1135
1136 return val;
1137}
1138
1139static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
1140 u16 set)
1141{
1142 unsigned long flags;
1143 u16 data;
1144
1145 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1146 data = __r8168_mac_ocp_read(tp, reg);
1147 __r8168_mac_ocp_write(tp, reg, data: (data & ~mask) | set);
1148 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1149}
1150
1151/* Work around a hw issue with RTL8168g PHY, the quirk disables
1152 * PHY MCU interrupts before PHY power-down.
1153 */
1154static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
1155{
1156 switch (tp->mac_version) {
1157 case RTL_GIGA_MAC_VER_40:
1158 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
1159 rtl_eri_set_bits(tp, addr: 0x1a8, p: 0xfc000000);
1160 else
1161 rtl_eri_clear_bits(tp, addr: 0x1a8, m: 0xfc000000);
1162 break;
1163 default:
1164 break;
1165 }
1166};
1167
1168static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1169{
1170 if (reg == 0x1f) {
1171 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1172 return;
1173 }
1174
1175 if (tp->ocp_base != OCP_STD_PHY_BASE)
1176 reg -= 0x10;
1177
1178 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
1179 rtl8168g_phy_suspend_quirk(tp, value);
1180
1181 r8168_phy_ocp_write(tp, reg: tp->ocp_base + reg * 2, data: value);
1182}
1183
1184static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1185{
1186 if (reg == 0x1f)
1187 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
1188
1189 if (tp->ocp_base != OCP_STD_PHY_BASE)
1190 reg -= 0x10;
1191
1192 return r8168_phy_ocp_read(tp, reg: tp->ocp_base + reg * 2);
1193}
1194
1195static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1196{
1197 if (reg == 0x1f) {
1198 tp->ocp_base = value << 4;
1199 return;
1200 }
1201
1202 r8168_mac_ocp_write(tp, reg: tp->ocp_base + reg, data: value);
1203}
1204
1205static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1206{
1207 return r8168_mac_ocp_read(tp, reg: tp->ocp_base + reg);
1208}
1209
1210DECLARE_RTL_COND(rtl_phyar_cond)
1211{
1212 return RTL_R32(tp, PHYAR) & 0x80000000;
1213}
1214
1215static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1216{
1217 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1218
1219 rtl_loop_wait_low(tp, c: &rtl_phyar_cond, d: 25, n: 20);
1220 /*
1221 * According to hardware specs a 20us delay is required after write
1222 * complete indication, but before sending next command.
1223 */
1224 udelay(usec: 20);
1225}
1226
1227static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1228{
1229 int value;
1230
1231 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1232
1233 value = rtl_loop_wait_high(tp, c: &rtl_phyar_cond, d: 25, n: 20) ?
1234 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1235
1236 /*
1237 * According to hardware specs a 20us delay is required after read
1238 * complete indication, but before sending next command.
1239 */
1240 udelay(usec: 20);
1241
1242 return value;
1243}
1244
1245DECLARE_RTL_COND(rtl_ocpar_cond)
1246{
1247 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1248}
1249
1250#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1251
1252static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1253{
1254 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1255}
1256
1257static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1258{
1259 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1260}
1261
1262static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1263{
1264 r8168dp_2_mdio_start(tp);
1265
1266 r8169_mdio_write(tp, reg, value);
1267
1268 r8168dp_2_mdio_stop(tp);
1269}
1270
1271static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1272{
1273 int value;
1274
1275 /* Work around issue with chip reporting wrong PHY ID */
1276 if (reg == MII_PHYSID2)
1277 return 0xc912;
1278
1279 r8168dp_2_mdio_start(tp);
1280
1281 value = r8169_mdio_read(tp, reg);
1282
1283 r8168dp_2_mdio_stop(tp);
1284
1285 return value;
1286}
1287
1288static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1289{
1290 switch (tp->mac_version) {
1291 case RTL_GIGA_MAC_VER_28:
1292 case RTL_GIGA_MAC_VER_31:
1293 r8168dp_2_mdio_write(tp, reg: location, value: val);
1294 break;
1295 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
1296 r8168g_mdio_write(tp, reg: location, value: val);
1297 break;
1298 default:
1299 r8169_mdio_write(tp, reg: location, value: val);
1300 break;
1301 }
1302}
1303
1304static int rtl_readphy(struct rtl8169_private *tp, int location)
1305{
1306 switch (tp->mac_version) {
1307 case RTL_GIGA_MAC_VER_28:
1308 case RTL_GIGA_MAC_VER_31:
1309 return r8168dp_2_mdio_read(tp, reg: location);
1310 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
1311 return r8168g_mdio_read(tp, reg: location);
1312 default:
1313 return r8169_mdio_read(tp, reg: location);
1314 }
1315}
1316
1317DECLARE_RTL_COND(rtl_ephyar_cond)
1318{
1319 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1320}
1321
1322static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1323{
1324 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1325 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1326
1327 rtl_loop_wait_low(tp, c: &rtl_ephyar_cond, d: 10, n: 100);
1328
1329 udelay(usec: 10);
1330}
1331
1332static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1333{
1334 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1335
1336 return rtl_loop_wait_high(tp, c: &rtl_ephyar_cond, d: 10, n: 100) ?
1337 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1338}
1339
1340static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1341{
1342 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1343 return rtl_loop_wait_high(tp, c: &rtl_ocpar_cond, d: 100, n: 20) ?
1344 RTL_R32(tp, OCPDR) : ~0;
1345}
1346
1347static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1348{
1349 return _rtl_eri_read(tp, addr: reg, ERIAR_OOB);
1350}
1351
1352static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1353 u32 data)
1354{
1355 RTL_W32(tp, OCPDR, data);
1356 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1357 rtl_loop_wait_low(tp, c: &rtl_ocpar_cond, d: 100, n: 20);
1358}
1359
1360static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1361 u32 data)
1362{
1363 _rtl_eri_write(tp, addr: reg, mask: ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1364 val: data, ERIAR_OOB);
1365}
1366
1367static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1368{
1369 rtl_eri_write(tp, addr: 0xe8, ERIAR_MASK_0001, val: cmd);
1370
1371 r8168dp_ocp_write(tp, mask: 0x1, reg: 0x30, data: 0x00000001);
1372}
1373
1374#define OOB_CMD_RESET 0x00
1375#define OOB_CMD_DRIVER_START 0x05
1376#define OOB_CMD_DRIVER_STOP 0x06
1377
1378static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1379{
1380 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1381}
1382
1383DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1384{
1385 u16 reg;
1386
1387 reg = rtl8168_get_ocp_reg(tp);
1388
1389 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1390}
1391
1392DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1393{
1394 return r8168ep_ocp_read(tp, reg: 0x124) & 0x00000001;
1395}
1396
1397DECLARE_RTL_COND(rtl_ocp_tx_cond)
1398{
1399 return RTL_R8(tp, IBISR0) & 0x20;
1400}
1401
1402static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1403{
1404 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1405 rtl_loop_wait_high(tp, c: &rtl_ocp_tx_cond, d: 50000, n: 2000);
1406 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1407 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1408}
1409
1410static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1411{
1412 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1413 if (tp->dash_enabled)
1414 rtl_loop_wait_high(tp, c: &rtl_dp_ocp_read_cond, d: 10000, n: 10);
1415}
1416
1417static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1418{
1419 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x180, OOB_CMD_DRIVER_START);
1420 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x30, data: r8168ep_ocp_read(tp, reg: 0x30) | 0x01);
1421 if (tp->dash_enabled)
1422 rtl_loop_wait_high(tp, c: &rtl_ep_ocp_read_cond, d: 10000, n: 30);
1423}
1424
1425static void rtl8125bp_driver_start(struct rtl8169_private *tp)
1426{
1427 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x14, OOB_CMD_DRIVER_START);
1428 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x18, data: 0x00);
1429 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x10, data: 0x01);
1430}
1431
1432static void rtl8168_driver_start(struct rtl8169_private *tp)
1433{
1434 if (tp->dash_type == RTL_DASH_DP)
1435 rtl8168dp_driver_start(tp);
1436 else if (tp->dash_type == RTL_DASH_25_BP)
1437 rtl8125bp_driver_start(tp);
1438 else
1439 rtl8168ep_driver_start(tp);
1440}
1441
1442static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1443{
1444 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1445 if (tp->dash_enabled)
1446 rtl_loop_wait_low(tp, c: &rtl_dp_ocp_read_cond, d: 10000, n: 10);
1447}
1448
1449static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1450{
1451 rtl8168ep_stop_cmac(tp);
1452 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x180, OOB_CMD_DRIVER_STOP);
1453 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x30, data: r8168ep_ocp_read(tp, reg: 0x30) | 0x01);
1454 if (tp->dash_enabled)
1455 rtl_loop_wait_low(tp, c: &rtl_ep_ocp_read_cond, d: 10000, n: 10);
1456}
1457
1458static void rtl8125bp_driver_stop(struct rtl8169_private *tp)
1459{
1460 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x14, OOB_CMD_DRIVER_STOP);
1461 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x18, data: 0x00);
1462 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x10, data: 0x01);
1463}
1464
1465static void rtl8168_driver_stop(struct rtl8169_private *tp)
1466{
1467 if (tp->dash_type == RTL_DASH_DP)
1468 rtl8168dp_driver_stop(tp);
1469 else if (tp->dash_type == RTL_DASH_25_BP)
1470 rtl8125bp_driver_stop(tp);
1471 else
1472 rtl8168ep_driver_stop(tp);
1473}
1474
1475static bool r8168dp_check_dash(struct rtl8169_private *tp)
1476{
1477 u16 reg = rtl8168_get_ocp_reg(tp);
1478
1479 return r8168dp_ocp_read(tp, reg) & BIT(15);
1480}
1481
1482static bool r8168ep_check_dash(struct rtl8169_private *tp)
1483{
1484 return r8168ep_ocp_read(tp, reg: 0x128) & BIT(0);
1485}
1486
1487static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1488{
1489 switch (tp->dash_type) {
1490 case RTL_DASH_DP:
1491 return r8168dp_check_dash(tp);
1492 case RTL_DASH_EP:
1493 case RTL_DASH_25_BP:
1494 return r8168ep_check_dash(tp);
1495 default:
1496 return false;
1497 }
1498}
1499
1500static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
1501{
1502 switch (tp->mac_version) {
1503 case RTL_GIGA_MAC_VER_28:
1504 case RTL_GIGA_MAC_VER_31:
1505 return RTL_DASH_DP;
1506 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52:
1507 return RTL_DASH_EP;
1508 case RTL_GIGA_MAC_VER_66:
1509 return RTL_DASH_25_BP;
1510 default:
1511 return RTL_DASH_NONE;
1512 }
1513}
1514
1515static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1516{
1517 if (tp->mac_version >= RTL_GIGA_MAC_VER_25 &&
1518 tp->mac_version != RTL_GIGA_MAC_VER_28 &&
1519 tp->mac_version != RTL_GIGA_MAC_VER_31 &&
1520 tp->mac_version != RTL_GIGA_MAC_VER_38)
1521 r8169_mod_reg8_cond(tp, reg: PMCH, D3_NO_PLL_DOWN, cond: !enable);
1522}
1523
1524static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1525{
1526 rtl_eri_clear_bits(tp, addr: 0xdc, BIT(0));
1527 rtl_eri_set_bits(tp, addr: 0xdc, BIT(0));
1528}
1529
1530DECLARE_RTL_COND(rtl_efusear_cond)
1531{
1532 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1533}
1534
1535u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1536{
1537 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1538
1539 return rtl_loop_wait_high(tp, c: &rtl_efusear_cond, d: 100, n: 300) ?
1540 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1541}
1542
1543static u32 rtl_get_events(struct rtl8169_private *tp)
1544{
1545 if (rtl_is_8125(tp))
1546 return RTL_R32(tp, IntrStatus_8125);
1547 else
1548 return RTL_R16(tp, IntrStatus);
1549}
1550
1551static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1552{
1553 if (rtl_is_8125(tp))
1554 RTL_W32(tp, IntrStatus_8125, bits);
1555 else
1556 RTL_W16(tp, IntrStatus, bits);
1557}
1558
1559static void rtl_irq_disable(struct rtl8169_private *tp)
1560{
1561 if (rtl_is_8125(tp))
1562 RTL_W32(tp, IntrMask_8125, 0);
1563 else
1564 RTL_W16(tp, IntrMask, 0);
1565}
1566
1567static void rtl_irq_enable(struct rtl8169_private *tp)
1568{
1569 if (rtl_is_8125(tp))
1570 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1571 else
1572 RTL_W16(tp, IntrMask, tp->irq_mask);
1573}
1574
1575static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1576{
1577 rtl_irq_disable(tp);
1578 rtl_ack_events(tp, bits: 0xffffffff);
1579 rtl_pci_commit(tp);
1580}
1581
1582static void rtl_link_chg_patch(struct rtl8169_private *tp)
1583{
1584 struct phy_device *phydev = tp->phydev;
1585
1586 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1587 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1588 if (phydev->speed == SPEED_1000) {
1589 rtl_eri_write(tp, addr: 0x1bc, ERIAR_MASK_1111, val: 0x00000011);
1590 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_1111, val: 0x00000005);
1591 } else if (phydev->speed == SPEED_100) {
1592 rtl_eri_write(tp, addr: 0x1bc, ERIAR_MASK_1111, val: 0x0000001f);
1593 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_1111, val: 0x00000005);
1594 } else {
1595 rtl_eri_write(tp, addr: 0x1bc, ERIAR_MASK_1111, val: 0x0000001f);
1596 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_1111, val: 0x0000003f);
1597 }
1598 rtl_reset_packet_filter(tp);
1599 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1600 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1601 if (phydev->speed == SPEED_1000) {
1602 rtl_eri_write(tp, addr: 0x1bc, ERIAR_MASK_1111, val: 0x00000011);
1603 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_1111, val: 0x00000005);
1604 } else {
1605 rtl_eri_write(tp, addr: 0x1bc, ERIAR_MASK_1111, val: 0x0000001f);
1606 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_1111, val: 0x0000003f);
1607 }
1608 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1609 if (phydev->speed == SPEED_10) {
1610 rtl_eri_write(tp, addr: 0x1d0, ERIAR_MASK_0011, val: 0x4d02);
1611 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_0011, val: 0x0060a);
1612 } else {
1613 rtl_eri_write(tp, addr: 0x1d0, ERIAR_MASK_0011, val: 0x0000);
1614 }
1615 }
1616}
1617
1618#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1619
1620static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1621{
1622 struct rtl8169_private *tp = netdev_priv(dev);
1623
1624 wol->supported = WAKE_ANY;
1625 wol->wolopts = tp->saved_wolopts;
1626}
1627
1628static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1629{
1630 rtl_unlock_config_regs(tp);
1631
1632 if (rtl_is_8168evl_up(tp)) {
1633 if (wolopts & WAKE_MAGIC)
1634 rtl_eri_set_bits(tp, addr: 0x0dc, p: MagicPacket_v2);
1635 else
1636 rtl_eri_clear_bits(tp, addr: 0x0dc, m: MagicPacket_v2);
1637 } else if (rtl_is_8125(tp)) {
1638 if (wolopts & WAKE_MAGIC)
1639 r8168_mac_ocp_modify(tp, reg: 0xc0b6, mask: 0, BIT(0));
1640 else
1641 r8168_mac_ocp_modify(tp, reg: 0xc0b6, BIT(0), set: 0);
1642 } else {
1643 r8169_mod_reg8_cond(tp, reg: Config3, bits: MagicPacket,
1644 cond: wolopts & WAKE_MAGIC);
1645 }
1646
1647 r8169_mod_reg8_cond(tp, reg: Config3, bits: LinkUp, cond: wolopts & WAKE_PHY);
1648 if (rtl_is_8125(tp))
1649 r8168_mac_ocp_modify(tp, reg: 0xe0c6, mask: 0x3f,
1650 set: wolopts & WAKE_PHY ? 0x13 : 0);
1651 r8169_mod_reg8_cond(tp, reg: Config5, bits: UWF, cond: wolopts & WAKE_UCAST);
1652 r8169_mod_reg8_cond(tp, reg: Config5, bits: BWF, cond: wolopts & WAKE_BCAST);
1653 r8169_mod_reg8_cond(tp, reg: Config5, bits: MWF, cond: wolopts & WAKE_MCAST);
1654 r8169_mod_reg8_cond(tp, reg: Config5, bits: LanWake, cond: wolopts);
1655
1656 switch (tp->mac_version) {
1657 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1658 r8169_mod_reg8_cond(tp, reg: Config1, bits: PMEnable, cond: wolopts);
1659 break;
1660 case RTL_GIGA_MAC_VER_34:
1661 case RTL_GIGA_MAC_VER_37:
1662 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST:
1663 r8169_mod_reg8_cond(tp, reg: Config2, PME_SIGNAL, cond: wolopts);
1664 break;
1665 default:
1666 break;
1667 }
1668
1669 rtl_lock_config_regs(tp);
1670
1671 device_set_wakeup_enable(dev: tp_to_dev(tp), enable: wolopts);
1672
1673 if (!tp->dash_enabled) {
1674 rtl_set_d3_pll_down(tp, enable: !wolopts);
1675 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0;
1676 }
1677}
1678
1679static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1680{
1681 struct rtl8169_private *tp = netdev_priv(dev);
1682
1683 if (wol->wolopts & ~WAKE_ANY)
1684 return -EINVAL;
1685
1686 tp->saved_wolopts = wol->wolopts;
1687 __rtl8169_set_wol(tp, wolopts: tp->saved_wolopts);
1688
1689 return 0;
1690}
1691
1692static void rtl8169_get_drvinfo(struct net_device *dev,
1693 struct ethtool_drvinfo *info)
1694{
1695 struct rtl8169_private *tp = netdev_priv(dev);
1696 struct rtl_fw *rtl_fw = tp->rtl_fw;
1697
1698 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1699 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1700 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1701 if (rtl_fw)
1702 strscpy(info->fw_version, rtl_fw->version,
1703 sizeof(info->fw_version));
1704}
1705
1706static int rtl8169_get_regs_len(struct net_device *dev)
1707{
1708 return R8169_REGS_SIZE;
1709}
1710
1711static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1712 netdev_features_t features)
1713{
1714 struct rtl8169_private *tp = netdev_priv(dev);
1715
1716 if (dev->mtu > TD_MSS_MAX)
1717 features &= ~NETIF_F_ALL_TSO;
1718
1719 if (dev->mtu > ETH_DATA_LEN &&
1720 tp->mac_version > RTL_GIGA_MAC_VER_06)
1721 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1722
1723 return features;
1724}
1725
1726static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1727 netdev_features_t features)
1728{
1729 u32 rx_config = RTL_R32(tp, RxConfig);
1730
1731 if (features & NETIF_F_RXALL)
1732 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1733 else
1734 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1735
1736 if (rtl_is_8125(tp)) {
1737 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1738 rx_config |= RX_VLAN_8125;
1739 else
1740 rx_config &= ~RX_VLAN_8125;
1741 }
1742
1743 RTL_W32(tp, RxConfig, rx_config);
1744}
1745
1746static int rtl8169_set_features(struct net_device *dev,
1747 netdev_features_t features)
1748{
1749 struct rtl8169_private *tp = netdev_priv(dev);
1750
1751 rtl_set_rx_config_features(tp, features);
1752
1753 if (features & NETIF_F_RXCSUM)
1754 tp->cp_cmd |= RxChkSum;
1755 else
1756 tp->cp_cmd &= ~RxChkSum;
1757
1758 if (!rtl_is_8125(tp)) {
1759 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1760 tp->cp_cmd |= RxVlan;
1761 else
1762 tp->cp_cmd &= ~RxVlan;
1763 }
1764
1765 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1766 rtl_pci_commit(tp);
1767
1768 return 0;
1769}
1770
1771static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1772{
1773 return (skb_vlan_tag_present(skb)) ?
1774 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1775}
1776
1777static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1778{
1779 u32 opts2 = le32_to_cpu(desc->opts2);
1780
1781 if (opts2 & RxVlanTag)
1782 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1783}
1784
1785static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1786 void *p)
1787{
1788 struct rtl8169_private *tp = netdev_priv(dev);
1789 u32 __iomem *data = tp->mmio_addr;
1790 u32 *dw = p;
1791 int i;
1792
1793 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1794 memcpy_fromio(dw++, data++, 4);
1795}
1796
1797static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1798 "tx_packets",
1799 "rx_packets",
1800 "tx_errors",
1801 "rx_errors",
1802 "rx_missed",
1803 "align_errors",
1804 "tx_single_collisions",
1805 "tx_multi_collisions",
1806 "unicast",
1807 "broadcast",
1808 "multicast",
1809 "tx_aborted",
1810 "tx_underrun",
1811};
1812
1813static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1814{
1815 switch (sset) {
1816 case ETH_SS_STATS:
1817 return ARRAY_SIZE(rtl8169_gstrings);
1818 default:
1819 return -EOPNOTSUPP;
1820 }
1821}
1822
1823DECLARE_RTL_COND(rtl_counters_cond)
1824{
1825 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1826}
1827
1828static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1829{
1830 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1831
1832 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1833 rtl_pci_commit(tp);
1834 RTL_W32(tp, CounterAddrLow, cmd);
1835 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1836
1837 rtl_loop_wait_low(tp, c: &rtl_counters_cond, d: 10, n: 1000);
1838}
1839
1840static void rtl8169_update_counters(struct rtl8169_private *tp)
1841{
1842 u8 val = RTL_R8(tp, ChipCmd);
1843
1844 /*
1845 * Some chips are unable to dump tally counters when the receiver
1846 * is disabled. If 0xff chip may be in a PCI power-save state.
1847 */
1848 if (val & CmdRxEnb && val != 0xff)
1849 rtl8169_do_counters(tp, counter_cmd: CounterDump);
1850}
1851
1852static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1853{
1854 struct rtl8169_counters *counters = tp->counters;
1855
1856 /*
1857 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1858 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1859 * reset by a power cycle, while the counter values collected by the
1860 * driver are reset at every driver unload/load cycle.
1861 *
1862 * To make sure the HW values returned by @get_stats64 match the SW
1863 * values, we collect the initial values at first open(*) and use them
1864 * as offsets to normalize the values returned by @get_stats64.
1865 *
1866 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1867 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1868 * set at open time by rtl_hw_start.
1869 */
1870
1871 if (tp->tc_offset.inited)
1872 return;
1873
1874 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1875 rtl8169_do_counters(tp, counter_cmd: CounterReset);
1876 } else {
1877 rtl8169_update_counters(tp);
1878 tp->tc_offset.tx_errors = counters->tx_errors;
1879 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1880 tp->tc_offset.tx_aborted = counters->tx_aborted;
1881 tp->tc_offset.rx_missed = counters->rx_missed;
1882 }
1883
1884 tp->tc_offset.inited = true;
1885}
1886
1887static void rtl8169_get_ethtool_stats(struct net_device *dev,
1888 struct ethtool_stats *stats, u64 *data)
1889{
1890 struct rtl8169_private *tp = netdev_priv(dev);
1891 struct rtl8169_counters *counters;
1892
1893 counters = tp->counters;
1894 rtl8169_update_counters(tp);
1895
1896 data[0] = le64_to_cpu(counters->tx_packets);
1897 data[1] = le64_to_cpu(counters->rx_packets);
1898 data[2] = le64_to_cpu(counters->tx_errors);
1899 data[3] = le32_to_cpu(counters->rx_errors);
1900 data[4] = le16_to_cpu(counters->rx_missed);
1901 data[5] = le16_to_cpu(counters->align_errors);
1902 data[6] = le32_to_cpu(counters->tx_one_collision);
1903 data[7] = le32_to_cpu(counters->tx_multi_collision);
1904 data[8] = le64_to_cpu(counters->rx_unicast);
1905 data[9] = le64_to_cpu(counters->rx_broadcast);
1906 data[10] = le32_to_cpu(counters->rx_multicast);
1907 data[11] = le16_to_cpu(counters->tx_aborted);
1908 data[12] = le16_to_cpu(counters->tx_underrun);
1909}
1910
1911static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1912{
1913 switch(stringset) {
1914 case ETH_SS_STATS:
1915 memcpy(to: data, from: rtl8169_gstrings, len: sizeof(rtl8169_gstrings));
1916 break;
1917 }
1918}
1919
1920/*
1921 * Interrupt coalescing
1922 *
1923 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1924 * > 8169, 8168 and 810x line of chipsets
1925 *
1926 * 8169, 8168, and 8136(810x) serial chipsets support it.
1927 *
1928 * > 2 - the Tx timer unit at gigabit speed
1929 *
1930 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1931 * (0xe0) bit 1 and bit 0.
1932 *
1933 * For 8169
1934 * bit[1:0] \ speed 1000M 100M 10M
1935 * 0 0 320ns 2.56us 40.96us
1936 * 0 1 2.56us 20.48us 327.7us
1937 * 1 0 5.12us 40.96us 655.4us
1938 * 1 1 10.24us 81.92us 1.31ms
1939 *
1940 * For the other
1941 * bit[1:0] \ speed 1000M 100M 10M
1942 * 0 0 5us 2.56us 40.96us
1943 * 0 1 40us 20.48us 327.7us
1944 * 1 0 80us 40.96us 655.4us
1945 * 1 1 160us 81.92us 1.31ms
1946 */
1947
1948/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1949struct rtl_coalesce_info {
1950 u32 speed;
1951 u32 scale_nsecs[4];
1952};
1953
1954/* produce array with base delay *1, *8, *8*2, *8*2*2 */
1955#define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1956
1957static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1958 { SPEED_1000, COALESCE_DELAY(320) },
1959 { SPEED_100, COALESCE_DELAY(2560) },
1960 { SPEED_10, COALESCE_DELAY(40960) },
1961 { 0 },
1962};
1963
1964static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1965 { SPEED_1000, COALESCE_DELAY(5000) },
1966 { SPEED_100, COALESCE_DELAY(2560) },
1967 { SPEED_10, COALESCE_DELAY(40960) },
1968 { 0 },
1969};
1970#undef COALESCE_DELAY
1971
1972/* get rx/tx scale vector corresponding to current speed */
1973static const struct rtl_coalesce_info *
1974rtl_coalesce_info(struct rtl8169_private *tp)
1975{
1976 const struct rtl_coalesce_info *ci;
1977
1978 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1979 ci = rtl_coalesce_info_8169;
1980 else
1981 ci = rtl_coalesce_info_8168_8136;
1982
1983 /* if speed is unknown assume highest one */
1984 if (tp->phydev->speed == SPEED_UNKNOWN)
1985 return ci;
1986
1987 for (; ci->speed; ci++) {
1988 if (tp->phydev->speed == ci->speed)
1989 return ci;
1990 }
1991
1992 return ERR_PTR(error: -ELNRNG);
1993}
1994
1995static int rtl_get_coalesce(struct net_device *dev,
1996 struct ethtool_coalesce *ec,
1997 struct kernel_ethtool_coalesce *kernel_coal,
1998 struct netlink_ext_ack *extack)
1999{
2000 struct rtl8169_private *tp = netdev_priv(dev);
2001 const struct rtl_coalesce_info *ci;
2002 u32 scale, c_us, c_fr;
2003 u16 intrmit;
2004
2005 if (rtl_is_8125(tp))
2006 return -EOPNOTSUPP;
2007
2008 memset(s: ec, c: 0, n: sizeof(*ec));
2009
2010 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2011 ci = rtl_coalesce_info(tp);
2012 if (IS_ERR(ptr: ci))
2013 return PTR_ERR(ptr: ci);
2014
2015 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
2016
2017 intrmit = RTL_R16(tp, IntrMitigate);
2018
2019 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
2020 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
2021
2022 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
2023 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
2024 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
2025
2026 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
2027 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
2028
2029 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
2030 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
2031
2032 return 0;
2033}
2034
2035/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
2036static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
2037 u16 *cp01)
2038{
2039 const struct rtl_coalesce_info *ci;
2040 u16 i;
2041
2042 ci = rtl_coalesce_info(tp);
2043 if (IS_ERR(ptr: ci))
2044 return PTR_ERR(ptr: ci);
2045
2046 for (i = 0; i < 4; i++) {
2047 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
2048 *cp01 = i;
2049 return ci->scale_nsecs[i];
2050 }
2051 }
2052
2053 return -ERANGE;
2054}
2055
2056static int rtl_set_coalesce(struct net_device *dev,
2057 struct ethtool_coalesce *ec,
2058 struct kernel_ethtool_coalesce *kernel_coal,
2059 struct netlink_ext_ack *extack)
2060{
2061 struct rtl8169_private *tp = netdev_priv(dev);
2062 u32 tx_fr = ec->tx_max_coalesced_frames;
2063 u32 rx_fr = ec->rx_max_coalesced_frames;
2064 u32 coal_usec_max, units;
2065 u16 w = 0, cp01 = 0;
2066 int scale;
2067
2068 if (rtl_is_8125(tp))
2069 return -EOPNOTSUPP;
2070
2071 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
2072 return -ERANGE;
2073
2074 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
2075 scale = rtl_coalesce_choose_scale(tp, usec: coal_usec_max, cp01: &cp01);
2076 if (scale < 0)
2077 return scale;
2078
2079 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
2080 * not only when usecs=0 because of e.g. the following scenario:
2081 *
2082 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2083 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2084 * - then user does `ethtool -C eth0 rx-usecs 100`
2085 *
2086 * Since ethtool sends to kernel whole ethtool_coalesce settings,
2087 * if we want to ignore rx_frames then it has to be set to 0.
2088 */
2089 if (rx_fr == 1)
2090 rx_fr = 0;
2091 if (tx_fr == 1)
2092 tx_fr = 0;
2093
2094 /* HW requires time limit to be set if frame limit is set */
2095 if ((tx_fr && !ec->tx_coalesce_usecs) ||
2096 (rx_fr && !ec->rx_coalesce_usecs))
2097 return -EINVAL;
2098
2099 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
2100 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
2101
2102 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
2103 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
2104 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
2105 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
2106
2107 RTL_W16(tp, IntrMitigate, w);
2108
2109 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
2110 if (rtl_is_8168evl_up(tp)) {
2111 if (!rx_fr && !tx_fr)
2112 /* disable packet counter */
2113 tp->cp_cmd |= PktCntrDisable;
2114 else
2115 tp->cp_cmd &= ~PktCntrDisable;
2116 }
2117
2118 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2119 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2120 rtl_pci_commit(tp);
2121
2122 return 0;
2123}
2124
2125static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp)
2126{
2127 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20;
2128
2129 switch (tp->mac_version) {
2130 case RTL_GIGA_MAC_VER_46:
2131 case RTL_GIGA_MAC_VER_48:
2132 tp->tx_lpi_timer = timer_val;
2133 r8168_mac_ocp_write(tp, reg: 0xe048, data: timer_val);
2134 break;
2135 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
2136 tp->tx_lpi_timer = timer_val;
2137 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
2138 break;
2139 default:
2140 break;
2141 }
2142}
2143
2144static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp)
2145{
2146 unsigned int speed = tp->phydev->speed;
2147 unsigned int timer = tp->tx_lpi_timer;
2148
2149 if (!timer || speed == SPEED_UNKNOWN)
2150 return 0;
2151
2152 /* tx_lpi_timer value is in bytes */
2153 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed);
2154}
2155
2156static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data)
2157{
2158 struct rtl8169_private *tp = netdev_priv(dev);
2159 int ret;
2160
2161 if (!rtl_supports_eee(tp))
2162 return -EOPNOTSUPP;
2163
2164 ret = phy_ethtool_get_eee(phydev: tp->phydev, data);
2165 if (ret)
2166 return ret;
2167
2168 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp);
2169
2170 return 0;
2171}
2172
2173static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data)
2174{
2175 struct rtl8169_private *tp = netdev_priv(dev);
2176
2177 if (!rtl_supports_eee(tp))
2178 return -EOPNOTSUPP;
2179
2180 return phy_ethtool_set_eee(phydev: tp->phydev, data);
2181}
2182
2183static void rtl8169_get_ringparam(struct net_device *dev,
2184 struct ethtool_ringparam *data,
2185 struct kernel_ethtool_ringparam *kernel_data,
2186 struct netlink_ext_ack *extack)
2187{
2188 data->rx_max_pending = NUM_RX_DESC;
2189 data->rx_pending = NUM_RX_DESC;
2190 data->tx_max_pending = NUM_TX_DESC;
2191 data->tx_pending = NUM_TX_DESC;
2192}
2193
2194static void rtl8169_get_pause_stats(struct net_device *dev,
2195 struct ethtool_pause_stats *pause_stats)
2196{
2197 struct rtl8169_private *tp = netdev_priv(dev);
2198
2199 if (!rtl_is_8125(tp))
2200 return;
2201
2202 rtl8169_update_counters(tp);
2203 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on);
2204 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on);
2205}
2206
2207static void rtl8169_get_pauseparam(struct net_device *dev,
2208 struct ethtool_pauseparam *data)
2209{
2210 struct rtl8169_private *tp = netdev_priv(dev);
2211 bool tx_pause, rx_pause;
2212
2213 phy_get_pause(phydev: tp->phydev, tx_pause: &tx_pause, rx_pause: &rx_pause);
2214
2215 data->autoneg = tp->phydev->autoneg;
2216 data->tx_pause = tx_pause ? 1 : 0;
2217 data->rx_pause = rx_pause ? 1 : 0;
2218}
2219
2220static int rtl8169_set_pauseparam(struct net_device *dev,
2221 struct ethtool_pauseparam *data)
2222{
2223 struct rtl8169_private *tp = netdev_priv(dev);
2224
2225 if (dev->mtu > ETH_DATA_LEN)
2226 return -EOPNOTSUPP;
2227
2228 phy_set_asym_pause(phydev: tp->phydev, rx: data->rx_pause, tx: data->tx_pause);
2229
2230 return 0;
2231}
2232
2233static void rtl8169_get_eth_mac_stats(struct net_device *dev,
2234 struct ethtool_eth_mac_stats *mac_stats)
2235{
2236 struct rtl8169_private *tp = netdev_priv(dev);
2237
2238 rtl8169_update_counters(tp);
2239
2240 mac_stats->FramesTransmittedOK =
2241 le64_to_cpu(tp->counters->tx_packets);
2242 mac_stats->SingleCollisionFrames =
2243 le32_to_cpu(tp->counters->tx_one_collision);
2244 mac_stats->MultipleCollisionFrames =
2245 le32_to_cpu(tp->counters->tx_multi_collision);
2246 mac_stats->FramesReceivedOK =
2247 le64_to_cpu(tp->counters->rx_packets);
2248 mac_stats->AlignmentErrors =
2249 le16_to_cpu(tp->counters->align_errors);
2250 mac_stats->FramesLostDueToIntMACXmitError =
2251 le64_to_cpu(tp->counters->tx_errors);
2252 mac_stats->BroadcastFramesReceivedOK =
2253 le64_to_cpu(tp->counters->rx_broadcast);
2254 mac_stats->MulticastFramesReceivedOK =
2255 le32_to_cpu(tp->counters->rx_multicast);
2256
2257 if (!rtl_is_8125(tp))
2258 return;
2259
2260 mac_stats->AlignmentErrors =
2261 le32_to_cpu(tp->counters->align_errors32);
2262 mac_stats->OctetsTransmittedOK =
2263 le64_to_cpu(tp->counters->tx_octets);
2264 mac_stats->LateCollisions =
2265 le32_to_cpu(tp->counters->tx_late_collision);
2266 mac_stats->FramesAbortedDueToXSColls =
2267 le32_to_cpu(tp->counters->tx_aborted32);
2268 mac_stats->OctetsReceivedOK =
2269 le64_to_cpu(tp->counters->rx_octets);
2270 mac_stats->FramesLostDueToIntMACRcvError =
2271 le32_to_cpu(tp->counters->rx_mac_error);
2272 mac_stats->MulticastFramesXmittedOK =
2273 le64_to_cpu(tp->counters->tx_multicast64);
2274 mac_stats->BroadcastFramesXmittedOK =
2275 le64_to_cpu(tp->counters->tx_broadcast64);
2276 mac_stats->MulticastFramesReceivedOK =
2277 le64_to_cpu(tp->counters->rx_multicast64);
2278 mac_stats->FrameTooLongErrors =
2279 le32_to_cpu(tp->counters->rx_frame_too_long);
2280}
2281
2282static void rtl8169_get_eth_ctrl_stats(struct net_device *dev,
2283 struct ethtool_eth_ctrl_stats *ctrl_stats)
2284{
2285 struct rtl8169_private *tp = netdev_priv(dev);
2286
2287 if (!rtl_is_8125(tp))
2288 return;
2289
2290 rtl8169_update_counters(tp);
2291
2292 ctrl_stats->UnsupportedOpcodesReceived =
2293 le32_to_cpu(tp->counters->rx_unknown_opcode);
2294}
2295
2296static const struct ethtool_ops rtl8169_ethtool_ops = {
2297 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2298 ETHTOOL_COALESCE_MAX_FRAMES,
2299 .get_drvinfo = rtl8169_get_drvinfo,
2300 .get_regs_len = rtl8169_get_regs_len,
2301 .get_link = ethtool_op_get_link,
2302 .get_coalesce = rtl_get_coalesce,
2303 .set_coalesce = rtl_set_coalesce,
2304 .get_regs = rtl8169_get_regs,
2305 .get_wol = rtl8169_get_wol,
2306 .set_wol = rtl8169_set_wol,
2307 .get_strings = rtl8169_get_strings,
2308 .get_sset_count = rtl8169_get_sset_count,
2309 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2310 .get_ts_info = ethtool_op_get_ts_info,
2311 .nway_reset = phy_ethtool_nway_reset,
2312 .get_eee = rtl8169_get_eee,
2313 .set_eee = rtl8169_set_eee,
2314 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2315 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2316 .get_ringparam = rtl8169_get_ringparam,
2317 .get_pause_stats = rtl8169_get_pause_stats,
2318 .get_pauseparam = rtl8169_get_pauseparam,
2319 .set_pauseparam = rtl8169_set_pauseparam,
2320 .get_eth_mac_stats = rtl8169_get_eth_mac_stats,
2321 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats,
2322};
2323
2324static const struct rtl_chip_info *rtl8169_get_chip_version(u16 xid, bool gmii)
2325{
2326 /* Chips combining a 1Gbps MAC with a 100Mbps PHY */
2327 static const struct rtl_chip_info rtl8106eus_info = {
2328 .mac_version = RTL_GIGA_MAC_VER_43,
2329 .name = "RTL8106eus",
2330 .fw_name = FIRMWARE_8106E_2,
2331 };
2332 static const struct rtl_chip_info rtl8107e_info = {
2333 .mac_version = RTL_GIGA_MAC_VER_48,
2334 .name = "RTL8107e",
2335 .fw_name = FIRMWARE_8107E_2,
2336 };
2337 const struct rtl_chip_info *p = rtl_chip_infos;
2338
2339 while ((xid & p->mask) != p->val)
2340 p++;
2341
2342 if (p->mac_version == RTL_GIGA_MAC_VER_42 && !gmii)
2343 return &rtl8106eus_info;
2344 if (p->mac_version == RTL_GIGA_MAC_VER_46 && !gmii)
2345 return &rtl8107e_info;
2346
2347 return p;
2348}
2349
2350static void rtl_release_firmware(struct rtl8169_private *tp)
2351{
2352 if (tp->rtl_fw) {
2353 rtl_fw_release_firmware(rtl_fw: tp->rtl_fw);
2354 kfree(objp: tp->rtl_fw);
2355 tp->rtl_fw = NULL;
2356 }
2357}
2358
2359void r8169_apply_firmware(struct rtl8169_private *tp)
2360{
2361 int val;
2362
2363 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2364 if (tp->rtl_fw) {
2365 rtl_fw_write_firmware(tp, rtl_fw: tp->rtl_fw);
2366 /* At least one firmware doesn't reset tp->ocp_base. */
2367 tp->ocp_base = OCP_STD_PHY_BASE;
2368
2369 /* PHY soft reset may still be in progress */
2370 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2371 !(val & BMCR_RESET),
2372 50000, 600000, true);
2373 }
2374}
2375
2376static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2377{
2378 /* Adjust EEE LED frequency */
2379 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2380 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2381
2382 rtl_eri_set_bits(tp, addr: 0x1b0, p: 0x0003);
2383}
2384
2385static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2386{
2387 r8168_mac_ocp_modify(tp, reg: 0xe040, mask: 0, BIT(1) | BIT(0));
2388 r8168_mac_ocp_modify(tp, reg: 0xeb62, mask: 0, BIT(2) | BIT(1));
2389}
2390
2391static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2392{
2393 r8168_mac_ocp_modify(tp, reg: 0xe040, mask: 0, BIT(1) | BIT(0));
2394}
2395
2396static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2397{
2398 rtl_eri_write(tp, addr: 0xe0, ERIAR_MASK_1111, val: get_unaligned_le32(p: addr));
2399 rtl_eri_write(tp, addr: 0xe4, ERIAR_MASK_1111, val: get_unaligned_le16(p: addr + 4));
2400 rtl_eri_write(tp, addr: 0xf0, ERIAR_MASK_1111, val: get_unaligned_le16(p: addr) << 16);
2401 rtl_eri_write(tp, addr: 0xf4, ERIAR_MASK_1111, val: get_unaligned_le32(p: addr + 2));
2402}
2403
2404u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2405{
2406 u16 data1, data2, ioffset;
2407
2408 r8168_mac_ocp_write(tp, reg: 0xdd02, data: 0x807d);
2409 data1 = r8168_mac_ocp_read(tp, reg: 0xdd02);
2410 data2 = r8168_mac_ocp_read(tp, reg: 0xdd00);
2411
2412 ioffset = (data2 >> 1) & 0x7ff8;
2413 ioffset |= data2 & 0x0007;
2414 if (data1 & BIT(7))
2415 ioffset |= BIT(15);
2416
2417 return ioffset;
2418}
2419
2420static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2421{
2422 set_bit(nr: flag, addr: tp->wk.flags);
2423 if (!schedule_work(work: &tp->wk.work))
2424 clear_bit(nr: flag, addr: tp->wk.flags);
2425}
2426
2427static void rtl8169_init_phy(struct rtl8169_private *tp)
2428{
2429 r8169_hw_phy_config(tp, phydev: tp->phydev, ver: tp->mac_version);
2430
2431 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2432 pci_write_config_byte(dev: tp->pci_dev, PCI_LATENCY_TIMER, val: 0x40);
2433 pci_write_config_byte(dev: tp->pci_dev, PCI_CACHE_LINE_SIZE, val: 0x08);
2434 /* set undocumented MAC Reg C+CR Offset 0x82h */
2435 RTL_W8(tp, 0x82, 0x01);
2436 }
2437
2438 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2439 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2440 tp->pci_dev->subsystem_device == 0xe000)
2441 phy_write_paged(phydev: tp->phydev, page: 0x0001, regnum: 0x10, val: 0xf01b);
2442
2443 /* We may have called phy_speed_down before */
2444 phy_speed_up(phydev: tp->phydev);
2445
2446 genphy_soft_reset(phydev: tp->phydev);
2447}
2448
2449static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2450{
2451 rtl_unlock_config_regs(tp);
2452
2453 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2454 rtl_pci_commit(tp);
2455
2456 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2457 rtl_pci_commit(tp);
2458
2459 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2460 rtl_rar_exgmac_set(tp, addr);
2461
2462 rtl_lock_config_regs(tp);
2463}
2464
2465static int rtl_set_mac_address(struct net_device *dev, void *p)
2466{
2467 struct rtl8169_private *tp = netdev_priv(dev);
2468 int ret;
2469
2470 ret = eth_mac_addr(dev, p);
2471 if (ret)
2472 return ret;
2473
2474 rtl_rar_set(tp, addr: dev->dev_addr);
2475
2476 return 0;
2477}
2478
2479static void rtl_init_rxcfg(struct rtl8169_private *tp)
2480{
2481 switch (tp->mac_version) {
2482 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2483 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2484 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2485 break;
2486 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2487 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2488 case RTL_GIGA_MAC_VER_38:
2489 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2490 break;
2491 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2492 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2493 break;
2494 case RTL_GIGA_MAC_VER_61:
2495 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2496 break;
2497 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST:
2498 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2499 RX_PAUSE_SLOT_ON);
2500 break;
2501 default:
2502 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2503 break;
2504 }
2505}
2506
2507static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2508{
2509 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2510}
2511
2512static void rtl_jumbo_config(struct rtl8169_private *tp)
2513{
2514 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2515 int readrq = 4096;
2516
2517 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 &&
2518 tp->mac_version <= RTL_GIGA_MAC_VER_26)
2519 readrq = 512;
2520
2521 rtl_unlock_config_regs(tp);
2522 switch (tp->mac_version) {
2523 case RTL_GIGA_MAC_VER_17:
2524 r8169_mod_reg8_cond(tp, reg: Config4, BIT(0), cond: jumbo);
2525 break;
2526 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2527 r8169_mod_reg8_cond(tp, reg: Config3, bits: Jumbo_En0, cond: jumbo);
2528 r8169_mod_reg8_cond(tp, reg: Config4, bits: Jumbo_En1, cond: jumbo);
2529 break;
2530 case RTL_GIGA_MAC_VER_28:
2531 r8169_mod_reg8_cond(tp, reg: Config3, bits: Jumbo_En0, cond: jumbo);
2532 break;
2533 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2534 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f);
2535 r8169_mod_reg8_cond(tp, reg: Config3, bits: Jumbo_En0, cond: jumbo);
2536 r8169_mod_reg8_cond(tp, reg: Config4, BIT(0), cond: jumbo);
2537 break;
2538 default:
2539 break;
2540 }
2541 rtl_lock_config_regs(tp);
2542
2543 if (pci_is_pcie(dev: tp->pci_dev) && tp->supports_gmii)
2544 pcie_set_readrq(dev: tp->pci_dev, rq: readrq);
2545
2546 /* Chip doesn't support pause in jumbo mode */
2547 if (jumbo) {
2548 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2549 tp->phydev->advertising);
2550 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2551 tp->phydev->advertising);
2552 phy_start_aneg(phydev: tp->phydev);
2553 }
2554}
2555
2556DECLARE_RTL_COND(rtl_chipcmd_cond)
2557{
2558 return RTL_R8(tp, ChipCmd) & CmdReset;
2559}
2560
2561static void rtl_hw_reset(struct rtl8169_private *tp)
2562{
2563 RTL_W8(tp, ChipCmd, CmdReset);
2564
2565 rtl_loop_wait_low(tp, c: &rtl_chipcmd_cond, d: 100, n: 100);
2566}
2567
2568static void rtl_request_firmware(struct rtl8169_private *tp)
2569{
2570 struct rtl_fw *rtl_fw;
2571
2572 /* firmware loaded already or no firmware available */
2573 if (tp->rtl_fw || !tp->fw_name)
2574 return;
2575
2576 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2577 if (!rtl_fw)
2578 return;
2579
2580 rtl_fw->phy_write = rtl_writephy;
2581 rtl_fw->phy_read = rtl_readphy;
2582 rtl_fw->mac_mcu_write = mac_mcu_write;
2583 rtl_fw->mac_mcu_read = mac_mcu_read;
2584 rtl_fw->fw_name = tp->fw_name;
2585 rtl_fw->dev = tp_to_dev(tp);
2586
2587 if (rtl_fw_request_firmware(rtl_fw))
2588 kfree(objp: rtl_fw);
2589 else
2590 tp->rtl_fw = rtl_fw;
2591}
2592
2593static void rtl_rx_close(struct rtl8169_private *tp)
2594{
2595 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2596}
2597
2598DECLARE_RTL_COND(rtl_npq_cond)
2599{
2600 return RTL_R8(tp, TxPoll) & NPQ;
2601}
2602
2603DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2604{
2605 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2606}
2607
2608DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2609{
2610 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2611}
2612
2613DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2614{
2615 /* IntrMitigate has new functionality on RTL8125 */
2616 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2617}
2618
2619static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2620{
2621 switch (tp->mac_version) {
2622 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2623 rtl_loop_wait_high(tp, c: &rtl_txcfg_empty_cond, d: 100, n: 42);
2624 rtl_loop_wait_high(tp, c: &rtl_rxtx_empty_cond, d: 100, n: 42);
2625 break;
2626 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2627 rtl_loop_wait_high(tp, c: &rtl_rxtx_empty_cond, d: 100, n: 42);
2628 break;
2629 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST:
2630 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2631 rtl_loop_wait_high(tp, c: &rtl_rxtx_empty_cond, d: 100, n: 42);
2632 rtl_loop_wait_high(tp, c: &rtl_rxtx_empty_cond_2, d: 100, n: 42);
2633 break;
2634 default:
2635 break;
2636 }
2637}
2638
2639static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2640{
2641 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2642}
2643
2644static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2645{
2646 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2647 fsleep(usecs: 2000);
2648 rtl_wait_txrx_fifo_empty(tp);
2649}
2650
2651static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2652{
2653 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2654 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2655 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2656
2657 if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2658 rtl_disable_rxdvgate(tp);
2659}
2660
2661static void rtl_prepare_power_down(struct rtl8169_private *tp)
2662{
2663 if (tp->dash_enabled)
2664 return;
2665
2666 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2667 tp->mac_version == RTL_GIGA_MAC_VER_33)
2668 rtl_ephy_write(tp, reg_addr: 0x19, value: 0xff64);
2669
2670 if (device_may_wakeup(dev: tp_to_dev(tp))) {
2671 phy_speed_down(phydev: tp->phydev, sync: false);
2672 rtl_wol_enable_rx(tp);
2673 }
2674}
2675
2676static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2677{
2678 u32 val = TX_DMA_BURST << TxDMAShift |
2679 InterFrameGap << TxInterFrameGapShift;
2680
2681 if (rtl_is_8168evl_up(tp))
2682 val |= TXCFG_AUTO_FIFO;
2683
2684 RTL_W32(tp, TxConfig, val);
2685}
2686
2687static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2688{
2689 /* Low hurts. Let's disable the filtering. */
2690 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2691}
2692
2693static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2694{
2695 /*
2696 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2697 * register to be written before TxDescAddrLow to work.
2698 * Switching from MMIO to I/O access fixes the issue as well.
2699 */
2700 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2701 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2702 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2703 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2704}
2705
2706static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2707{
2708 u32 val;
2709
2710 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2711 val = 0x000fff00;
2712 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2713 val = 0x00ffff00;
2714 else
2715 return;
2716
2717 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2718 val |= 0xff;
2719
2720 RTL_W32(tp, 0x7c, val);
2721}
2722
2723static void rtl_set_rx_mode(struct net_device *dev)
2724{
2725 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2726 /* Multicast hash filter */
2727 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2728 struct rtl8169_private *tp = netdev_priv(dev);
2729 u32 tmp;
2730
2731 if (dev->flags & IFF_PROMISC) {
2732 rx_mode |= AcceptAllPhys;
2733 } else if (!(dev->flags & IFF_MULTICAST)) {
2734 rx_mode &= ~AcceptMulticast;
2735 } else if (dev->flags & IFF_ALLMULTI ||
2736 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2737 /* accept all multicasts */
2738 } else if (netdev_mc_empty(dev)) {
2739 rx_mode &= ~AcceptMulticast;
2740 } else {
2741 struct netdev_hw_addr *ha;
2742
2743 mc_filter[1] = mc_filter[0] = 0;
2744 netdev_for_each_mc_addr(ha, dev) {
2745 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2746 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2747 }
2748
2749 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2750 tmp = mc_filter[0];
2751 mc_filter[0] = swab32(mc_filter[1]);
2752 mc_filter[1] = swab32(tmp);
2753 }
2754 }
2755
2756 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2757 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2758
2759 tmp = RTL_R32(tp, RxConfig);
2760 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2761}
2762
2763DECLARE_RTL_COND(rtl_csiar_cond)
2764{
2765 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2766}
2767
2768static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2769{
2770 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2771
2772 RTL_W32(tp, CSIDR, value);
2773 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2774 CSIAR_BYTE_ENABLE | func << 16);
2775
2776 rtl_loop_wait_low(tp, c: &rtl_csiar_cond, d: 10, n: 100);
2777}
2778
2779static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2780{
2781 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2782
2783 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2784 CSIAR_BYTE_ENABLE);
2785
2786 return rtl_loop_wait_high(tp, c: &rtl_csiar_cond, d: 10, n: 100) ?
2787 RTL_R32(tp, CSIDR) : ~0;
2788}
2789
2790static void rtl_csi_mod(struct rtl8169_private *tp, int addr,
2791 u32 mask, u32 set)
2792{
2793 u32 val;
2794
2795 WARN(addr % 4, "Invalid CSI address %#x\n", addr);
2796
2797 netdev_notice_once(tp->dev,
2798 "No native access to PCI extended config space, falling back to CSI\n");
2799
2800 val = rtl_csi_read(tp, addr);
2801 rtl_csi_write(tp, addr, value: (val & ~mask) | set);
2802}
2803
2804static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp)
2805{
2806 struct pci_dev *pdev = tp->pci_dev;
2807 int rc;
2808 u8 val;
2809
2810#define RTL_GEN3_RELATED_OFF 0x0890
2811#define RTL_GEN3_ZRXDC_NONCOMPL 0x1
2812 if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) {
2813 rc = pci_read_config_byte(dev: pdev, RTL_GEN3_RELATED_OFF, val: &val);
2814 if (rc == PCIBIOS_SUCCESSFUL) {
2815 val &= ~RTL_GEN3_ZRXDC_NONCOMPL;
2816 rc = pci_write_config_byte(dev: pdev, RTL_GEN3_RELATED_OFF,
2817 val);
2818 if (rc == PCIBIOS_SUCCESSFUL)
2819 return;
2820 }
2821 }
2822
2823 rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, set: 0);
2824}
2825
2826static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2827{
2828 struct pci_dev *pdev = tp->pci_dev;
2829
2830 /* According to Realtek the value at config space address 0x070f
2831 * controls the L0s/L1 entrance latency. We try standard ECAM access
2832 * first and if it fails fall back to CSI.
2833 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2834 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2835 */
2836 if (pdev->cfg_size > 0x070f &&
2837 pci_write_config_byte(dev: pdev, where: 0x070f, val) == PCIBIOS_SUCCESSFUL)
2838 return;
2839
2840 rtl_csi_mod(tp, addr: 0x070c, mask: 0xff000000, set: val << 24);
2841}
2842
2843static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2844{
2845 /* L0 7us, L1 16us */
2846 rtl_set_aspm_entry_latency(tp, val: 0x27);
2847}
2848
2849struct ephy_info {
2850 unsigned int offset;
2851 u16 mask;
2852 u16 bits;
2853};
2854
2855static void __rtl_ephy_init(struct rtl8169_private *tp,
2856 const struct ephy_info *e, int len)
2857{
2858 u16 w;
2859
2860 while (len-- > 0) {
2861 w = (rtl_ephy_read(tp, reg_addr: e->offset) & ~e->mask) | e->bits;
2862 rtl_ephy_write(tp, reg_addr: e->offset, value: w);
2863 e++;
2864 }
2865}
2866
2867#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2868
2869static void rtl_disable_clock_request(struct rtl8169_private *tp)
2870{
2871 pcie_capability_clear_word(dev: tp->pci_dev, PCI_EXP_LNKCTL,
2872 PCI_EXP_LNKCTL_CLKREQ_EN);
2873}
2874
2875static void rtl_enable_clock_request(struct rtl8169_private *tp)
2876{
2877 pcie_capability_set_word(dev: tp->pci_dev, PCI_EXP_LNKCTL,
2878 PCI_EXP_LNKCTL_CLKREQ_EN);
2879}
2880
2881static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2882{
2883 /* work around an issue when PCI reset occurs during L2/L3 state */
2884 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2885}
2886
2887static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2888{
2889 /* Bits control which events trigger ASPM L1 exit:
2890 * Bit 12: rxdv
2891 * Bit 11: ltr_msg
2892 * Bit 10: txdma_poll
2893 * Bit 9: xadm
2894 * Bit 8: pktavi
2895 * Bit 7: txpla
2896 */
2897 switch (tp->mac_version) {
2898 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2899 rtl_eri_set_bits(tp, addr: 0xd4, p: 0x1f00);
2900 break;
2901 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2902 rtl_eri_set_bits(tp, addr: 0xd4, p: 0x0c00);
2903 break;
2904 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
2905 r8168_mac_ocp_modify(tp, reg: 0xc0ac, mask: 0, set: 0x1f80);
2906 break;
2907 default:
2908 break;
2909 }
2910}
2911
2912static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2913{
2914 switch (tp->mac_version) {
2915 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2916 rtl_eri_clear_bits(tp, addr: 0xd4, m: 0x1f00);
2917 break;
2918 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
2919 r8168_mac_ocp_modify(tp, reg: 0xc0ac, mask: 0x1f80, set: 0);
2920 break;
2921 default:
2922 break;
2923 }
2924}
2925
2926static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2927{
2928 u8 val8;
2929
2930 if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2931 return;
2932
2933 /* Don't enable ASPM in the chip if OS can't control ASPM */
2934 if (enable && tp->aspm_manageable) {
2935 /* On these chip versions ASPM can even harm
2936 * bus communication of other PCI devices.
2937 */
2938 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2939 tp->mac_version == RTL_GIGA_MAC_VER_43)
2940 return;
2941
2942 rtl_mod_config5(tp, clear: 0, set: ASPM_en);
2943 switch (tp->mac_version) {
2944 case RTL_GIGA_MAC_VER_70:
2945 case RTL_GIGA_MAC_VER_80:
2946 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;
2947 RTL_W8(tp, INT_CFG0_8125, val8);
2948 break;
2949 default:
2950 rtl_mod_config2(tp, clear: 0, set: ClkReqEn);
2951 break;
2952 }
2953
2954 switch (tp->mac_version) {
2955 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2956 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
2957 /* reset ephy tx/rx disable timer */
2958 r8168_mac_ocp_modify(tp, reg: 0xe094, mask: 0xff00, set: 0);
2959 /* chip can trigger L1.2 */
2960 r8168_mac_ocp_modify(tp, reg: 0xe092, mask: 0x00ff, BIT(2));
2961 break;
2962 default:
2963 break;
2964 }
2965 } else {
2966 switch (tp->mac_version) {
2967 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2968 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
2969 r8168_mac_ocp_modify(tp, reg: 0xe092, mask: 0x00ff, set: 0);
2970 break;
2971 default:
2972 break;
2973 }
2974
2975 switch (tp->mac_version) {
2976 case RTL_GIGA_MAC_VER_70:
2977 case RTL_GIGA_MAC_VER_80:
2978 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;
2979 RTL_W8(tp, INT_CFG0_8125, val8);
2980 break;
2981 default:
2982 rtl_mod_config2(tp, clear: ClkReqEn, set: 0);
2983 break;
2984 }
2985 rtl_mod_config5(tp, clear: ASPM_en, set: 0);
2986 }
2987}
2988
2989static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2990 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2991{
2992 /* Usage of dynamic vs. static FIFO is controlled by bit
2993 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2994 */
2995 rtl_eri_write(tp, addr: 0xc8, ERIAR_MASK_1111, val: (rx_stat << 16) | rx_dyn);
2996 rtl_eri_write(tp, addr: 0xe8, ERIAR_MASK_1111, val: (tx_stat << 16) | tx_dyn);
2997}
2998
2999static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
3000 u8 low, u8 high)
3001{
3002 /* FIFO thresholds for pause flow control */
3003 rtl_eri_write(tp, addr: 0xcc, ERIAR_MASK_0001, val: low);
3004 rtl_eri_write(tp, addr: 0xd0, ERIAR_MASK_0001, val: high);
3005}
3006
3007static void rtl_hw_start_8168b(struct rtl8169_private *tp)
3008{
3009 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3010}
3011
3012static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
3013{
3014 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
3015
3016 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3017
3018 rtl_disable_clock_request(tp);
3019}
3020
3021static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
3022{
3023 static const struct ephy_info e_info_8168cp[] = {
3024 { 0x01, 0, 0x0001 },
3025 { 0x02, 0x0800, 0x1000 },
3026 { 0x03, 0, 0x0042 },
3027 { 0x06, 0x0080, 0x0000 },
3028 { 0x07, 0, 0x2000 }
3029 };
3030
3031 rtl_set_def_aspm_entry_latency(tp);
3032
3033 rtl_ephy_init(tp, e_info_8168cp);
3034
3035 __rtl_hw_start_8168cp(tp);
3036}
3037
3038static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
3039{
3040 rtl_set_def_aspm_entry_latency(tp);
3041
3042 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3043}
3044
3045static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
3046{
3047 rtl_set_def_aspm_entry_latency(tp);
3048
3049 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3050
3051 /* Magic. */
3052 RTL_W8(tp, DBG_REG, 0x20);
3053}
3054
3055static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
3056{
3057 static const struct ephy_info e_info_8168c_1[] = {
3058 { 0x02, 0x0800, 0x1000 },
3059 { 0x03, 0, 0x0002 },
3060 { 0x06, 0x0080, 0x0000 }
3061 };
3062
3063 rtl_set_def_aspm_entry_latency(tp);
3064
3065 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3066
3067 rtl_ephy_init(tp, e_info_8168c_1);
3068
3069 __rtl_hw_start_8168cp(tp);
3070}
3071
3072static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
3073{
3074 static const struct ephy_info e_info_8168c_2[] = {
3075 { 0x01, 0, 0x0001 },
3076 { 0x03, 0x0400, 0x0020 }
3077 };
3078
3079 rtl_set_def_aspm_entry_latency(tp);
3080
3081 rtl_ephy_init(tp, e_info_8168c_2);
3082
3083 __rtl_hw_start_8168cp(tp);
3084}
3085
3086static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
3087{
3088 rtl_set_def_aspm_entry_latency(tp);
3089
3090 __rtl_hw_start_8168cp(tp);
3091}
3092
3093static void rtl_hw_start_8168d(struct rtl8169_private *tp)
3094{
3095 rtl_set_def_aspm_entry_latency(tp);
3096
3097 rtl_disable_clock_request(tp);
3098}
3099
3100static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
3101{
3102 static const struct ephy_info e_info_8168d_4[] = {
3103 { 0x0b, 0x0000, 0x0048 },
3104 { 0x19, 0x0020, 0x0050 },
3105 { 0x0c, 0x0100, 0x0020 },
3106 { 0x10, 0x0004, 0x0000 },
3107 };
3108
3109 rtl_set_def_aspm_entry_latency(tp);
3110
3111 rtl_ephy_init(tp, e_info_8168d_4);
3112
3113 rtl_enable_clock_request(tp);
3114}
3115
3116static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
3117{
3118 static const struct ephy_info e_info_8168e_1[] = {
3119 { 0x00, 0x0200, 0x0100 },
3120 { 0x00, 0x0000, 0x0004 },
3121 { 0x06, 0x0002, 0x0001 },
3122 { 0x06, 0x0000, 0x0030 },
3123 { 0x07, 0x0000, 0x2000 },
3124 { 0x00, 0x0000, 0x0020 },
3125 { 0x03, 0x5800, 0x2000 },
3126 { 0x03, 0x0000, 0x0001 },
3127 { 0x01, 0x0800, 0x1000 },
3128 { 0x07, 0x0000, 0x4000 },
3129 { 0x1e, 0x0000, 0x2000 },
3130 { 0x19, 0xffff, 0xfe6c },
3131 { 0x0a, 0x0000, 0x0040 }
3132 };
3133
3134 rtl_set_def_aspm_entry_latency(tp);
3135
3136 rtl_ephy_init(tp, e_info_8168e_1);
3137
3138 rtl_disable_clock_request(tp);
3139
3140 /* Reset tx FIFO pointer */
3141 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
3142 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
3143
3144 rtl_mod_config5(tp, clear: Spi_en, set: 0);
3145}
3146
3147static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
3148{
3149 static const struct ephy_info e_info_8168e_2[] = {
3150 { 0x09, 0x0000, 0x0080 },
3151 { 0x19, 0x0000, 0x0224 },
3152 { 0x00, 0x0000, 0x0004 },
3153 { 0x0c, 0x3df0, 0x0200 },
3154 };
3155
3156 rtl_set_def_aspm_entry_latency(tp);
3157
3158 rtl_ephy_init(tp, e_info_8168e_2);
3159
3160 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3161 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_1111, val: 0x0000);
3162 rtl_set_fifo_size(tp, rx_stat: 0x10, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3163 rtl_eri_set_bits(tp, addr: 0x1d0, BIT(1));
3164 rtl_reset_packet_filter(tp);
3165 rtl_eri_set_bits(tp, addr: 0x1b0, BIT(4));
3166 rtl_eri_write(tp, addr: 0xcc, ERIAR_MASK_1111, val: 0x00000050);
3167 rtl_eri_write(tp, addr: 0xd0, ERIAR_MASK_1111, val: 0x07ff0060);
3168
3169 rtl_disable_clock_request(tp);
3170
3171 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3172
3173 rtl8168_config_eee_mac(tp);
3174
3175 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3176 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3177 rtl_mod_config5(tp, clear: Spi_en, set: 0);
3178}
3179
3180static void rtl_hw_start_8168f(struct rtl8169_private *tp)
3181{
3182 rtl_set_def_aspm_entry_latency(tp);
3183
3184 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3185 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_1111, val: 0x0000);
3186 rtl_set_fifo_size(tp, rx_stat: 0x10, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3187 rtl_reset_packet_filter(tp);
3188 rtl_eri_set_bits(tp, addr: 0x1b0, BIT(4));
3189 rtl_eri_set_bits(tp, addr: 0x1d0, BIT(4) | BIT(1));
3190 rtl_eri_write(tp, addr: 0xcc, ERIAR_MASK_1111, val: 0x00000050);
3191 rtl_eri_write(tp, addr: 0xd0, ERIAR_MASK_1111, val: 0x00000060);
3192
3193 rtl_disable_clock_request(tp);
3194
3195 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3196 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3197 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3198 rtl_mod_config5(tp, clear: Spi_en, set: 0);
3199
3200 rtl8168_config_eee_mac(tp);
3201}
3202
3203static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3204{
3205 static const struct ephy_info e_info_8168f_1[] = {
3206 { 0x06, 0x00c0, 0x0020 },
3207 { 0x08, 0x0001, 0x0002 },
3208 { 0x09, 0x0000, 0x0080 },
3209 { 0x19, 0x0000, 0x0224 },
3210 { 0x00, 0x0000, 0x0008 },
3211 { 0x0c, 0x3df0, 0x0200 },
3212 };
3213
3214 rtl_hw_start_8168f(tp);
3215
3216 rtl_ephy_init(tp, e_info_8168f_1);
3217}
3218
3219static void rtl_hw_start_8411(struct rtl8169_private *tp)
3220{
3221 static const struct ephy_info e_info_8168f_1[] = {
3222 { 0x06, 0x00c0, 0x0020 },
3223 { 0x0f, 0xffff, 0x5200 },
3224 { 0x19, 0x0000, 0x0224 },
3225 { 0x00, 0x0000, 0x0008 },
3226 { 0x0c, 0x3df0, 0x0200 },
3227 };
3228
3229 rtl_hw_start_8168f(tp);
3230 rtl_pcie_state_l2l3_disable(tp);
3231
3232 rtl_ephy_init(tp, e_info_8168f_1);
3233}
3234
3235static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3236{
3237 rtl_set_fifo_size(tp, rx_stat: 0x08, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3238 rtl8168g_set_pause_thresholds(tp, low: 0x38, high: 0x48);
3239
3240 rtl_set_def_aspm_entry_latency(tp);
3241
3242 rtl_reset_packet_filter(tp);
3243 rtl_eri_write(tp, addr: 0x2f8, ERIAR_MASK_0011, val: 0x1d8f);
3244
3245 rtl_disable_rxdvgate(tp);
3246
3247 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3248 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_0011, val: 0x0000);
3249
3250 rtl8168_config_eee_mac(tp);
3251
3252 rtl_w0w1_eri(tp, addr: 0x2fc, p: 0x01, m: 0x06);
3253 rtl_eri_clear_bits(tp, addr: 0x1b0, BIT(12));
3254
3255 rtl_pcie_state_l2l3_disable(tp);
3256}
3257
3258static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3259{
3260 static const struct ephy_info e_info_8168g_1[] = {
3261 { 0x00, 0x0008, 0x0000 },
3262 { 0x0c, 0x3ff0, 0x0820 },
3263 { 0x1e, 0x0000, 0x0001 },
3264 { 0x19, 0x8000, 0x0000 }
3265 };
3266
3267 rtl_hw_start_8168g(tp);
3268 rtl_ephy_init(tp, e_info_8168g_1);
3269}
3270
3271static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3272{
3273 static const struct ephy_info e_info_8168g_2[] = {
3274 { 0x00, 0x0008, 0x0000 },
3275 { 0x0c, 0x3ff0, 0x0820 },
3276 { 0x19, 0xffff, 0x7c00 },
3277 { 0x1e, 0xffff, 0x20eb },
3278 { 0x0d, 0xffff, 0x1666 },
3279 { 0x00, 0xffff, 0x10a3 },
3280 { 0x06, 0xffff, 0xf050 },
3281 { 0x04, 0x0000, 0x0010 },
3282 { 0x1d, 0x4000, 0x0000 },
3283 };
3284
3285 rtl_hw_start_8168g(tp);
3286 rtl_ephy_init(tp, e_info_8168g_2);
3287}
3288
3289static void rtl8411b_fix_phy_down(struct rtl8169_private *tp)
3290{
3291 static const u16 fix_data[] = {
3292/* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065,
3293/* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00,
3294/* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009,
3295/* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006,
3296/* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2,
3297/* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400,
3298/* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519,
3299/* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4,
3300/* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508,
3301/* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434,
3302/* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007,
3303/* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00,
3304/* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1,
3305/* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132
3306 };
3307 unsigned long flags;
3308 int i;
3309
3310 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
3311 for (i = 0; i < ARRAY_SIZE(fix_data); i++)
3312 __r8168_mac_ocp_write(tp, reg: 0xf800 + 2 * i, data: fix_data[i]);
3313 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
3314}
3315
3316static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3317{
3318 static const struct ephy_info e_info_8411_2[] = {
3319 { 0x00, 0x0008, 0x0000 },
3320 { 0x0c, 0x37d0, 0x0820 },
3321 { 0x1e, 0x0000, 0x0001 },
3322 { 0x19, 0x8021, 0x0000 },
3323 { 0x1e, 0x0000, 0x2000 },
3324 { 0x0d, 0x0100, 0x0200 },
3325 { 0x00, 0x0000, 0x0080 },
3326 { 0x06, 0x0000, 0x0010 },
3327 { 0x04, 0x0000, 0x0010 },
3328 { 0x1d, 0x0000, 0x4000 },
3329 };
3330
3331 rtl_hw_start_8168g(tp);
3332
3333 rtl_ephy_init(tp, e_info_8411_2);
3334
3335 /* The following Realtek-provided magic fixes an issue with the RX unit
3336 * getting confused after the PHY having been powered-down.
3337 */
3338 r8168_mac_ocp_write(tp, reg: 0xFC28, data: 0x0000);
3339 r8168_mac_ocp_write(tp, reg: 0xFC2A, data: 0x0000);
3340 r8168_mac_ocp_write(tp, reg: 0xFC2C, data: 0x0000);
3341 r8168_mac_ocp_write(tp, reg: 0xFC2E, data: 0x0000);
3342 r8168_mac_ocp_write(tp, reg: 0xFC30, data: 0x0000);
3343 r8168_mac_ocp_write(tp, reg: 0xFC32, data: 0x0000);
3344 r8168_mac_ocp_write(tp, reg: 0xFC34, data: 0x0000);
3345 r8168_mac_ocp_write(tp, reg: 0xFC36, data: 0x0000);
3346 mdelay(3);
3347 r8168_mac_ocp_write(tp, reg: 0xFC26, data: 0x0000);
3348
3349 rtl8411b_fix_phy_down(tp);
3350
3351 r8168_mac_ocp_write(tp, reg: 0xFC26, data: 0x8000);
3352
3353 r8168_mac_ocp_write(tp, reg: 0xFC2A, data: 0x0743);
3354 r8168_mac_ocp_write(tp, reg: 0xFC2C, data: 0x0801);
3355 r8168_mac_ocp_write(tp, reg: 0xFC2E, data: 0x0BE9);
3356 r8168_mac_ocp_write(tp, reg: 0xFC30, data: 0x02FD);
3357 r8168_mac_ocp_write(tp, reg: 0xFC32, data: 0x0C25);
3358 r8168_mac_ocp_write(tp, reg: 0xFC34, data: 0x00A9);
3359 r8168_mac_ocp_write(tp, reg: 0xFC36, data: 0x012D);
3360}
3361
3362static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3363{
3364 static const struct ephy_info e_info_8168h_1[] = {
3365 { 0x1e, 0x0800, 0x0001 },
3366 { 0x1d, 0x0000, 0x0800 },
3367 { 0x05, 0xffff, 0x2089 },
3368 { 0x06, 0xffff, 0x5881 },
3369 { 0x04, 0xffff, 0x854a },
3370 { 0x01, 0xffff, 0x068b }
3371 };
3372 int rg_saw_cnt;
3373
3374 rtl_ephy_init(tp, e_info_8168h_1);
3375
3376 rtl_set_fifo_size(tp, rx_stat: 0x08, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3377 rtl8168g_set_pause_thresholds(tp, low: 0x38, high: 0x48);
3378
3379 rtl_set_def_aspm_entry_latency(tp);
3380
3381 rtl_reset_packet_filter(tp);
3382
3383 rtl_eri_set_bits(tp, addr: 0xdc, p: 0x001c);
3384
3385 rtl_eri_write(tp, addr: 0x5f0, ERIAR_MASK_0011, val: 0x4f87);
3386
3387 rtl_disable_rxdvgate(tp);
3388
3389 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3390 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_0011, val: 0x0000);
3391
3392 rtl8168_config_eee_mac(tp);
3393
3394 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3395 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3396
3397 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3398
3399 rtl_eri_clear_bits(tp, addr: 0x1b0, BIT(12));
3400
3401 rtl_pcie_state_l2l3_disable(tp);
3402
3403 rg_saw_cnt = phy_read_paged(phydev: tp->phydev, page: 0x0c42, regnum: 0x13) & 0x3fff;
3404 if (rg_saw_cnt > 0) {
3405 u16 sw_cnt_1ms_ini;
3406
3407 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3408 sw_cnt_1ms_ini &= 0x0fff;
3409 r8168_mac_ocp_modify(tp, reg: 0xd412, mask: 0x0fff, set: sw_cnt_1ms_ini);
3410 }
3411
3412 r8168_mac_ocp_modify(tp, reg: 0xe056, mask: 0x00f0, set: 0x0000);
3413 r8168_mac_ocp_modify(tp, reg: 0xe052, mask: 0x6000, set: 0x8008);
3414 r8168_mac_ocp_modify(tp, reg: 0xe0d6, mask: 0x01ff, set: 0x017f);
3415 r8168_mac_ocp_modify(tp, reg: 0xd420, mask: 0x0fff, set: 0x047f);
3416
3417 r8168_mac_ocp_write(tp, reg: 0xe63e, data: 0x0001);
3418 r8168_mac_ocp_write(tp, reg: 0xe63e, data: 0x0000);
3419 r8168_mac_ocp_write(tp, reg: 0xc094, data: 0x0000);
3420 r8168_mac_ocp_write(tp, reg: 0xc09e, data: 0x0000);
3421}
3422
3423static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3424{
3425 rtl8168ep_stop_cmac(tp);
3426
3427 rtl_set_fifo_size(tp, rx_stat: 0x08, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3428 rtl8168g_set_pause_thresholds(tp, low: 0x2f, high: 0x5f);
3429
3430 rtl_set_def_aspm_entry_latency(tp);
3431
3432 rtl_reset_packet_filter(tp);
3433
3434 rtl_eri_write(tp, addr: 0x5f0, ERIAR_MASK_0011, val: 0x4f87);
3435
3436 rtl_disable_rxdvgate(tp);
3437
3438 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3439 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_0011, val: 0x0000);
3440
3441 rtl8168_config_eee_mac(tp);
3442
3443 rtl_w0w1_eri(tp, addr: 0x2fc, p: 0x01, m: 0x06);
3444
3445 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3446
3447 rtl_pcie_state_l2l3_disable(tp);
3448}
3449
3450static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3451{
3452 static const struct ephy_info e_info_8168ep_3[] = {
3453 { 0x00, 0x0000, 0x0080 },
3454 { 0x0d, 0x0100, 0x0200 },
3455 { 0x19, 0x8021, 0x0000 },
3456 { 0x1e, 0x0000, 0x2000 },
3457 };
3458
3459 rtl_ephy_init(tp, e_info_8168ep_3);
3460
3461 rtl_hw_start_8168ep(tp);
3462
3463 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3464 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3465
3466 r8168_mac_ocp_modify(tp, reg: 0xd3e2, mask: 0x0fff, set: 0x0271);
3467 r8168_mac_ocp_modify(tp, reg: 0xd3e4, mask: 0x00ff, set: 0x0000);
3468 r8168_mac_ocp_modify(tp, reg: 0xe860, mask: 0x0000, set: 0x0080);
3469}
3470
3471static void rtl_hw_start_8117(struct rtl8169_private *tp)
3472{
3473 static const struct ephy_info e_info_8117[] = {
3474 { 0x19, 0x0040, 0x1100 },
3475 { 0x59, 0x0040, 0x1100 },
3476 };
3477 int rg_saw_cnt;
3478
3479 rtl8168ep_stop_cmac(tp);
3480 rtl_ephy_init(tp, e_info_8117);
3481
3482 rtl_set_fifo_size(tp, rx_stat: 0x08, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3483 rtl8168g_set_pause_thresholds(tp, low: 0x2f, high: 0x5f);
3484
3485 rtl_set_def_aspm_entry_latency(tp);
3486
3487 rtl_reset_packet_filter(tp);
3488
3489 rtl_eri_set_bits(tp, addr: 0xd4, p: 0x0010);
3490
3491 rtl_eri_write(tp, addr: 0x5f0, ERIAR_MASK_0011, val: 0x4f87);
3492
3493 rtl_disable_rxdvgate(tp);
3494
3495 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3496 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_0011, val: 0x0000);
3497
3498 rtl8168_config_eee_mac(tp);
3499
3500 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3501 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3502
3503 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3504
3505 rtl_eri_clear_bits(tp, addr: 0x1b0, BIT(12));
3506
3507 rtl_pcie_state_l2l3_disable(tp);
3508
3509 rg_saw_cnt = phy_read_paged(phydev: tp->phydev, page: 0x0c42, regnum: 0x13) & 0x3fff;
3510 if (rg_saw_cnt > 0) {
3511 u16 sw_cnt_1ms_ini;
3512
3513 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3514 r8168_mac_ocp_modify(tp, reg: 0xd412, mask: 0x0fff, set: sw_cnt_1ms_ini);
3515 }
3516
3517 r8168_mac_ocp_modify(tp, reg: 0xe056, mask: 0x00f0, set: 0x0000);
3518 r8168_mac_ocp_write(tp, reg: 0xea80, data: 0x0003);
3519 r8168_mac_ocp_modify(tp, reg: 0xe052, mask: 0x0000, set: 0x0009);
3520 r8168_mac_ocp_modify(tp, reg: 0xd420, mask: 0x0fff, set: 0x047f);
3521
3522 r8168_mac_ocp_write(tp, reg: 0xe63e, data: 0x0001);
3523 r8168_mac_ocp_write(tp, reg: 0xe63e, data: 0x0000);
3524 r8168_mac_ocp_write(tp, reg: 0xc094, data: 0x0000);
3525 r8168_mac_ocp_write(tp, reg: 0xc09e, data: 0x0000);
3526
3527 /* firmware is for MAC only */
3528 r8169_apply_firmware(tp);
3529}
3530
3531static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3532{
3533 static const struct ephy_info e_info_8102e_1[] = {
3534 { 0x01, 0, 0x6e65 },
3535 { 0x02, 0, 0x091f },
3536 { 0x03, 0, 0xc2f9 },
3537 { 0x06, 0, 0xafb5 },
3538 { 0x07, 0, 0x0e00 },
3539 { 0x19, 0, 0xec80 },
3540 { 0x01, 0, 0x2e65 },
3541 { 0x01, 0, 0x6e65 }
3542 };
3543 u8 cfg1;
3544
3545 rtl_set_def_aspm_entry_latency(tp);
3546
3547 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3548
3549 RTL_W8(tp, Config1,
3550 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3551 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3552
3553 cfg1 = RTL_R8(tp, Config1);
3554 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3555 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3556
3557 rtl_ephy_init(tp, e_info_8102e_1);
3558}
3559
3560static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3561{
3562 rtl_set_def_aspm_entry_latency(tp);
3563
3564 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3565 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3566}
3567
3568static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3569{
3570 rtl_hw_start_8102e_2(tp);
3571
3572 rtl_ephy_write(tp, reg_addr: 0x03, value: 0xc2f9);
3573}
3574
3575static void rtl_hw_start_8401(struct rtl8169_private *tp)
3576{
3577 static const struct ephy_info e_info_8401[] = {
3578 { 0x01, 0xffff, 0x6fe5 },
3579 { 0x03, 0xffff, 0x0599 },
3580 { 0x06, 0xffff, 0xaf25 },
3581 { 0x07, 0xffff, 0x8e68 },
3582 };
3583
3584 rtl_ephy_init(tp, e_info_8401);
3585 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3586}
3587
3588static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3589{
3590 static const struct ephy_info e_info_8105e_1[] = {
3591 { 0x07, 0, 0x4000 },
3592 { 0x19, 0, 0x0200 },
3593 { 0x19, 0, 0x0020 },
3594 { 0x1e, 0, 0x2000 },
3595 { 0x03, 0, 0x0001 },
3596 { 0x19, 0, 0x0100 },
3597 { 0x19, 0, 0x0004 },
3598 { 0x0a, 0, 0x0020 }
3599 };
3600
3601 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3602 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3603
3604 /* Disable Early Tally Counter */
3605 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3606
3607 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3608 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3609
3610 rtl_ephy_init(tp, e_info_8105e_1);
3611
3612 rtl_pcie_state_l2l3_disable(tp);
3613}
3614
3615static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3616{
3617 rtl_hw_start_8105e_1(tp);
3618 rtl_ephy_write(tp, reg_addr: 0x1e, value: rtl_ephy_read(tp, reg_addr: 0x1e) | 0x8000);
3619}
3620
3621static void rtl_hw_start_8402(struct rtl8169_private *tp)
3622{
3623 static const struct ephy_info e_info_8402[] = {
3624 { 0x19, 0xffff, 0xff64 },
3625 { 0x1e, 0, 0x4000 }
3626 };
3627
3628 rtl_set_def_aspm_entry_latency(tp);
3629
3630 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3631 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3632
3633 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3634
3635 rtl_ephy_init(tp, e_info_8402);
3636
3637 rtl_set_fifo_size(tp, rx_stat: 0x00, tx_stat: 0x00, rx_dyn: 0x02, tx_dyn: 0x06);
3638 rtl_reset_packet_filter(tp);
3639 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3640 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_0011, val: 0x0000);
3641 rtl_w0w1_eri(tp, addr: 0x0d4, p: 0x0e00, m: 0xff00);
3642
3643 /* disable EEE */
3644 rtl_eri_write(tp, addr: 0x1b0, ERIAR_MASK_0011, val: 0x0000);
3645
3646 rtl_pcie_state_l2l3_disable(tp);
3647}
3648
3649static void rtl_hw_start_8106(struct rtl8169_private *tp)
3650{
3651 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3652 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3653
3654 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3655 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3656 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3657
3658 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3659 rtl_set_aspm_entry_latency(tp, val: 0x2f);
3660
3661 rtl_eri_write(tp, addr: 0x1d0, ERIAR_MASK_0011, val: 0x0000);
3662
3663 /* disable EEE */
3664 rtl_eri_write(tp, addr: 0x1b0, ERIAR_MASK_0011, val: 0x0000);
3665
3666 rtl_pcie_state_l2l3_disable(tp);
3667}
3668
3669DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3670{
3671 return r8168_mac_ocp_read(tp, reg: 0xe00e) & BIT(13);
3672}
3673
3674static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3675{
3676 rtl_pcie_state_l2l3_disable(tp);
3677
3678 RTL_W16(tp, 0x382, 0x221b);
3679 RTL_W32(tp, RSS_CTRL_8125, 0);
3680 RTL_W16(tp, Q_NUM_CTRL_8125, 0);
3681
3682 /* disable UPS */
3683 r8168_mac_ocp_modify(tp, reg: 0xd40a, mask: 0x0010, set: 0x0000);
3684
3685 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3686
3687 r8168_mac_ocp_write(tp, reg: 0xc140, data: 0xffff);
3688 r8168_mac_ocp_write(tp, reg: 0xc142, data: 0xffff);
3689
3690 r8168_mac_ocp_modify(tp, reg: 0xd3e2, mask: 0x0fff, set: 0x03a9);
3691 r8168_mac_ocp_modify(tp, reg: 0xd3e4, mask: 0x00ff, set: 0x0000);
3692 r8168_mac_ocp_modify(tp, reg: 0xe860, mask: 0x0000, set: 0x0080);
3693
3694 /* disable new tx descriptor format */
3695 r8168_mac_ocp_modify(tp, reg: 0xeb58, mask: 0x0001, set: 0x0000);
3696
3697 if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||
3698 tp->mac_version == RTL_GIGA_MAC_VER_80)
3699 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);
3700
3701 if (tp->mac_version == RTL_GIGA_MAC_VER_80)
3702 r8168_mac_ocp_modify(tp, reg: 0xe614, mask: 0x0f00, set: 0x0f00);
3703 else if (tp->mac_version == RTL_GIGA_MAC_VER_70)
3704 r8168_mac_ocp_modify(tp, reg: 0xe614, mask: 0x0700, set: 0x0400);
3705 else if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3706 r8168_mac_ocp_modify(tp, reg: 0xe614, mask: 0x0700, set: 0x0200);
3707 else
3708 r8168_mac_ocp_modify(tp, reg: 0xe614, mask: 0x0700, set: 0x0300);
3709
3710 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3711 r8168_mac_ocp_modify(tp, reg: 0xe63e, mask: 0x0c30, set: 0x0000);
3712 else
3713 r8168_mac_ocp_modify(tp, reg: 0xe63e, mask: 0x0c30, set: 0x0020);
3714
3715 r8168_mac_ocp_modify(tp, reg: 0xc0b4, mask: 0x0000, set: 0x000c);
3716 r8168_mac_ocp_modify(tp, reg: 0xeb6a, mask: 0x00ff, set: 0x0033);
3717 r8168_mac_ocp_modify(tp, reg: 0xeb50, mask: 0x03e0, set: 0x0040);
3718 r8168_mac_ocp_modify(tp, reg: 0xe056, mask: 0x00f0, set: 0x0000);
3719 r8168_mac_ocp_modify(tp, reg: 0xe040, mask: 0x1000, set: 0x0000);
3720 r8168_mac_ocp_modify(tp, reg: 0xea1c, mask: 0x0003, set: 0x0001);
3721 if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||
3722 tp->mac_version == RTL_GIGA_MAC_VER_80)
3723 r8168_mac_ocp_modify(tp, reg: 0xea1c, mask: 0x0300, set: 0x0000);
3724 else
3725 r8168_mac_ocp_modify(tp, reg: 0xea1c, mask: 0x0004, set: 0x0000);
3726 r8168_mac_ocp_modify(tp, reg: 0xe0c0, mask: 0x4f0f, set: 0x4403);
3727 r8168_mac_ocp_modify(tp, reg: 0xe052, mask: 0x0080, set: 0x0068);
3728 r8168_mac_ocp_modify(tp, reg: 0xd430, mask: 0x0fff, set: 0x047f);
3729
3730 r8168_mac_ocp_modify(tp, reg: 0xea1c, mask: 0x0004, set: 0x0000);
3731 r8168_mac_ocp_modify(tp, reg: 0xeb54, mask: 0x0000, set: 0x0001);
3732 udelay(usec: 1);
3733 r8168_mac_ocp_modify(tp, reg: 0xeb54, mask: 0x0001, set: 0x0000);
3734 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3735
3736 r8168_mac_ocp_write(tp, reg: 0xe098, data: 0xc302);
3737
3738 rtl_loop_wait_low(tp, c: &rtl_mac_ocp_e00e_cond, d: 1000, n: 10);
3739
3740 if (tp->mac_version == RTL_GIGA_MAC_VER_61)
3741 rtl8125a_config_eee_mac(tp);
3742 else
3743 rtl8125b_config_eee_mac(tp);
3744
3745 rtl_disable_rxdvgate(tp);
3746}
3747
3748static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3749{
3750 static const struct ephy_info e_info_8125a_2[] = {
3751 { 0x04, 0xffff, 0xd000 },
3752 { 0x0a, 0xffff, 0x8653 },
3753 { 0x23, 0xffff, 0xab66 },
3754 { 0x20, 0xffff, 0x9455 },
3755 { 0x21, 0xffff, 0x99ff },
3756 { 0x29, 0xffff, 0xfe04 },
3757
3758 { 0x44, 0xffff, 0xd000 },
3759 { 0x4a, 0xffff, 0x8653 },
3760 { 0x63, 0xffff, 0xab66 },
3761 { 0x60, 0xffff, 0x9455 },
3762 { 0x61, 0xffff, 0x99ff },
3763 { 0x69, 0xffff, 0xfe04 },
3764 };
3765
3766 rtl_set_def_aspm_entry_latency(tp);
3767 rtl_ephy_init(tp, e_info_8125a_2);
3768 rtl_hw_start_8125_common(tp);
3769}
3770
3771static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3772{
3773 static const struct ephy_info e_info_8125b[] = {
3774 { 0x0b, 0xffff, 0xa908 },
3775 { 0x1e, 0xffff, 0x20eb },
3776 { 0x4b, 0xffff, 0xa908 },
3777 { 0x5e, 0xffff, 0x20eb },
3778 { 0x22, 0x0030, 0x0020 },
3779 { 0x62, 0x0030, 0x0020 },
3780 };
3781
3782 rtl_set_def_aspm_entry_latency(tp);
3783 rtl_ephy_init(tp, e_info_8125b);
3784 rtl_hw_start_8125_common(tp);
3785}
3786
3787static void rtl_hw_start_8125d(struct rtl8169_private *tp)
3788{
3789 rtl_set_def_aspm_entry_latency(tp);
3790 rtl_hw_start_8125_common(tp);
3791}
3792
3793static void rtl_hw_start_8126a(struct rtl8169_private *tp)
3794{
3795 rtl_disable_zrxdc_timeout(tp);
3796 rtl_set_def_aspm_entry_latency(tp);
3797 rtl_hw_start_8125_common(tp);
3798}
3799
3800static void rtl_hw_start_8127a(struct rtl8169_private *tp)
3801{
3802 rtl_set_def_aspm_entry_latency(tp);
3803 rtl_hw_start_8125_common(tp);
3804}
3805
3806static void rtl_hw_config(struct rtl8169_private *tp)
3807{
3808 static const rtl_generic_fct hw_configs[] = {
3809 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3810 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3811 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3812 [RTL_GIGA_MAC_VER_10] = NULL,
3813 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3814 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3815 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3816 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3817 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3818 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3819 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3820 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3821 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3822 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3823 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3824 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3825 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3826 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3827 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3828 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3829 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3830 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3831 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3832 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3833 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3834 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3835 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3836 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3837 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3838 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3839 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3840 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3841 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3842 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3843 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3844 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3845 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3846 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d,
3847 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d,
3848 [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a,
3849 [RTL_GIGA_MAC_VER_80] = rtl_hw_start_8127a,
3850 };
3851
3852 if (hw_configs[tp->mac_version])
3853 hw_configs[tp->mac_version](tp);
3854}
3855
3856static void rtl_hw_start_8125(struct rtl8169_private *tp)
3857{
3858 int i;
3859
3860 RTL_W8(tp, INT_CFG0_8125, 0x00);
3861
3862 /* disable interrupt coalescing */
3863 switch (tp->mac_version) {
3864 case RTL_GIGA_MAC_VER_61:
3865 case RTL_GIGA_MAC_VER_64:
3866 case RTL_GIGA_MAC_VER_66:
3867 case RTL_GIGA_MAC_VER_80:
3868 for (i = 0xa00; i < 0xb00; i += 4)
3869 RTL_W32(tp, i, 0);
3870 if (tp->mac_version == RTL_GIGA_MAC_VER_80)
3871 RTL_W16(tp, INT_CFG1_8125, 0x0000);
3872 break;
3873 case RTL_GIGA_MAC_VER_63:
3874 case RTL_GIGA_MAC_VER_70:
3875 for (i = 0xa00; i < 0xa80; i += 4)
3876 RTL_W32(tp, i, 0);
3877 RTL_W16(tp, INT_CFG1_8125, 0x0000);
3878 break;
3879 default:
3880 break;
3881 }
3882
3883 /* enable extended tally counter */
3884 r8168_mac_ocp_modify(tp, reg: 0xea84, mask: 0, BIT(1) | BIT(0));
3885
3886 rtl_hw_config(tp);
3887}
3888
3889static void rtl_hw_start_8168(struct rtl8169_private *tp)
3890{
3891 if (rtl_is_8168evl_up(tp))
3892 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3893 else
3894 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3895
3896 rtl_hw_config(tp);
3897
3898 /* disable interrupt coalescing */
3899 RTL_W16(tp, IntrMitigate, 0x0000);
3900}
3901
3902static void rtl_hw_start_8169(struct rtl8169_private *tp)
3903{
3904 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3905
3906 tp->cp_cmd |= PCIMulRW;
3907
3908 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3909 tp->mac_version == RTL_GIGA_MAC_VER_03)
3910 tp->cp_cmd |= EnAnaPLL;
3911
3912 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3913
3914 rtl8169_set_magic_reg(tp);
3915
3916 /* disable interrupt coalescing */
3917 RTL_W16(tp, IntrMitigate, 0x0000);
3918}
3919
3920static void rtl_hw_start(struct rtl8169_private *tp)
3921{
3922 rtl_unlock_config_regs(tp);
3923 /* disable aspm and clock request before ephy access */
3924 rtl_hw_aspm_clkreq_enable(tp, enable: false);
3925 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3926
3927 rtl_set_eee_txidle_timer(tp);
3928
3929 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3930 rtl_hw_start_8169(tp);
3931 else if (rtl_is_8125(tp))
3932 rtl_hw_start_8125(tp);
3933 else
3934 rtl_hw_start_8168(tp);
3935
3936 rtl_enable_exit_l1(tp);
3937 rtl_hw_aspm_clkreq_enable(tp, enable: true);
3938 rtl_set_rx_max_size(tp);
3939 rtl_set_rx_tx_desc_registers(tp);
3940 rtl_lock_config_regs(tp);
3941
3942 rtl_jumbo_config(tp);
3943
3944 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3945 rtl_pci_commit(tp);
3946
3947 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3948 rtl_init_rxcfg(tp);
3949 rtl_set_tx_config_registers(tp);
3950 rtl_set_rx_config_features(tp, features: tp->dev->features);
3951 rtl_set_rx_mode(dev: tp->dev);
3952 rtl_irq_enable(tp);
3953}
3954
3955static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3956{
3957 struct rtl8169_private *tp = netdev_priv(dev);
3958
3959 WRITE_ONCE(dev->mtu, new_mtu);
3960 netdev_update_features(dev);
3961 rtl_jumbo_config(tp);
3962 rtl_set_eee_txidle_timer(tp);
3963
3964 return 0;
3965}
3966
3967static void rtl8169_mark_to_asic(struct RxDesc *desc)
3968{
3969 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3970
3971 desc->opts2 = 0;
3972 /* Force memory writes to complete before releasing descriptor */
3973 dma_wmb();
3974 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3975}
3976
3977static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3978 struct RxDesc *desc)
3979{
3980 struct device *d = tp_to_dev(tp);
3981 int node = dev_to_node(dev: d);
3982 dma_addr_t mapping;
3983 struct page *data;
3984
3985 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3986 if (!data)
3987 return NULL;
3988
3989 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3990 if (unlikely(dma_mapping_error(d, mapping))) {
3991 netdev_err(dev: tp->dev, format: "Failed to map RX DMA!\n");
3992 __free_pages(page: data, order: get_order(R8169_RX_BUF_SIZE));
3993 return NULL;
3994 }
3995
3996 desc->addr = cpu_to_le64(mapping);
3997 rtl8169_mark_to_asic(desc);
3998
3999 return data;
4000}
4001
4002static void rtl8169_rx_clear(struct rtl8169_private *tp)
4003{
4004 int i;
4005
4006 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
4007 dma_unmap_page(tp_to_dev(tp),
4008 le64_to_cpu(tp->RxDescArray[i].addr),
4009 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
4010 __free_pages(page: tp->Rx_databuff[i], order: get_order(R8169_RX_BUF_SIZE));
4011 tp->Rx_databuff[i] = NULL;
4012 tp->RxDescArray[i].addr = 0;
4013 tp->RxDescArray[i].opts1 = 0;
4014 }
4015}
4016
4017static int rtl8169_rx_fill(struct rtl8169_private *tp)
4018{
4019 int i;
4020
4021 for (i = 0; i < NUM_RX_DESC; i++) {
4022 struct page *data;
4023
4024 data = rtl8169_alloc_rx_data(tp, desc: tp->RxDescArray + i);
4025 if (!data) {
4026 rtl8169_rx_clear(tp);
4027 return -ENOMEM;
4028 }
4029 tp->Rx_databuff[i] = data;
4030 }
4031
4032 /* mark as last descriptor in the ring */
4033 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
4034
4035 return 0;
4036}
4037
4038static int rtl8169_init_ring(struct rtl8169_private *tp)
4039{
4040 rtl8169_init_ring_indexes(tp);
4041
4042 memset(s: tp->tx_skb, c: 0, n: sizeof(tp->tx_skb));
4043 memset(s: tp->Rx_databuff, c: 0, n: sizeof(tp->Rx_databuff));
4044
4045 return rtl8169_rx_fill(tp);
4046}
4047
4048static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
4049{
4050 struct ring_info *tx_skb = tp->tx_skb + entry;
4051 struct TxDesc *desc = tp->TxDescArray + entry;
4052
4053 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
4054 DMA_TO_DEVICE);
4055 memset(s: desc, c: 0, n: sizeof(*desc));
4056 memset(s: tx_skb, c: 0, n: sizeof(*tx_skb));
4057}
4058
4059static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4060 unsigned int n)
4061{
4062 unsigned int i;
4063
4064 for (i = 0; i < n; i++) {
4065 unsigned int entry = (start + i) % NUM_TX_DESC;
4066 struct ring_info *tx_skb = tp->tx_skb + entry;
4067 unsigned int len = tx_skb->len;
4068
4069 if (len) {
4070 struct sk_buff *skb = tx_skb->skb;
4071
4072 rtl8169_unmap_tx_skb(tp, entry);
4073 if (skb)
4074 dev_consume_skb_any(skb);
4075 }
4076 }
4077}
4078
4079static void rtl8169_tx_clear(struct rtl8169_private *tp)
4080{
4081 rtl8169_tx_clear_range(tp, start: tp->dirty_tx, NUM_TX_DESC);
4082 netdev_reset_queue(dev_queue: tp->dev);
4083}
4084
4085static void rtl8169_cleanup(struct rtl8169_private *tp)
4086{
4087 napi_disable(n: &tp->napi);
4088
4089 /* Give a racing hard_start_xmit a few cycles to complete. */
4090 synchronize_net();
4091
4092 /* Disable interrupts */
4093 rtl8169_irq_mask_and_ack(tp);
4094
4095 rtl_rx_close(tp);
4096
4097 switch (tp->mac_version) {
4098 case RTL_GIGA_MAC_VER_28:
4099 case RTL_GIGA_MAC_VER_31:
4100 rtl_loop_wait_low(tp, c: &rtl_npq_cond, d: 20, n: 2000);
4101 break;
4102 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4103 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4104 rtl_loop_wait_high(tp, c: &rtl_txcfg_empty_cond, d: 100, n: 666);
4105 break;
4106 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
4107 rtl_enable_rxdvgate(tp);
4108 fsleep(usecs: 2000);
4109 break;
4110 default:
4111 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4112 fsleep(usecs: 100);
4113 break;
4114 }
4115
4116 rtl_hw_reset(tp);
4117
4118 rtl8169_tx_clear(tp);
4119 rtl8169_init_ring_indexes(tp);
4120}
4121
4122static void rtl_reset_work(struct rtl8169_private *tp)
4123{
4124 int i;
4125
4126 netif_stop_queue(dev: tp->dev);
4127
4128 rtl8169_cleanup(tp);
4129
4130 for (i = 0; i < NUM_RX_DESC; i++)
4131 rtl8169_mark_to_asic(desc: tp->RxDescArray + i);
4132
4133 napi_enable(n: &tp->napi);
4134 rtl_hw_start(tp);
4135}
4136
4137static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4138{
4139 struct rtl8169_private *tp = netdev_priv(dev);
4140
4141 rtl_schedule_task(tp, flag: RTL_FLAG_TASK_TX_TIMEOUT);
4142}
4143
4144static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4145 void *addr, unsigned int entry, bool desc_own)
4146{
4147 struct TxDesc *txd = tp->TxDescArray + entry;
4148 struct device *d = tp_to_dev(tp);
4149 dma_addr_t mapping;
4150 u32 opts1;
4151 int ret;
4152
4153 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4154 ret = dma_mapping_error(dev: d, dma_addr: mapping);
4155 if (unlikely(ret)) {
4156 if (net_ratelimit())
4157 netdev_err(dev: tp->dev, format: "Failed to map TX data!\n");
4158 return ret;
4159 }
4160
4161 txd->addr = cpu_to_le64(mapping);
4162 txd->opts2 = cpu_to_le32(opts[1]);
4163
4164 opts1 = opts[0] | len;
4165 if (entry == NUM_TX_DESC - 1)
4166 opts1 |= RingEnd;
4167 if (desc_own)
4168 opts1 |= DescOwn;
4169 txd->opts1 = cpu_to_le32(opts1);
4170
4171 tp->tx_skb[entry].len = len;
4172
4173 return 0;
4174}
4175
4176static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4177 const u32 *opts, unsigned int entry)
4178{
4179 struct skb_shared_info *info = skb_shinfo(skb);
4180 unsigned int cur_frag;
4181
4182 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4183 const skb_frag_t *frag = info->frags + cur_frag;
4184 void *addr = skb_frag_address(frag);
4185 u32 len = skb_frag_size(frag);
4186
4187 entry = (entry + 1) % NUM_TX_DESC;
4188
4189 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4190 goto err_out;
4191 }
4192
4193 return 0;
4194
4195err_out:
4196 rtl8169_tx_clear_range(tp, start: tp->cur_tx + 1, n: cur_frag);
4197 return -EIO;
4198}
4199
4200static bool rtl_skb_is_udp(struct sk_buff *skb)
4201{
4202 int no = skb_network_offset(skb);
4203 struct ipv6hdr *i6h, _i6h;
4204 struct iphdr *ih, _ih;
4205
4206 switch (vlan_get_protocol(skb)) {
4207 case htons(ETH_P_IP):
4208 ih = skb_header_pointer(skb, offset: no, len: sizeof(_ih), buffer: &_ih);
4209 return ih && ih->protocol == IPPROTO_UDP;
4210 case htons(ETH_P_IPV6):
4211 i6h = skb_header_pointer(skb, offset: no, len: sizeof(_i6h), buffer: &_i6h);
4212 return i6h && i6h->nexthdr == IPPROTO_UDP;
4213 default:
4214 return false;
4215 }
4216}
4217
4218#define RTL_MIN_PATCH_LEN 47
4219
4220/* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4221static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4222 struct sk_buff *skb)
4223{
4224 unsigned int padto = 0, len = skb->len;
4225
4226 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) &&
4227 skb_transport_header_was_set(skb)) {
4228 unsigned int trans_data_len = skb_tail_pointer(skb) -
4229 skb_transport_header(skb);
4230
4231 if (trans_data_len >= offsetof(struct udphdr, len) &&
4232 trans_data_len < RTL_MIN_PATCH_LEN) {
4233 u16 dest = ntohs(udp_hdr(skb)->dest);
4234
4235 /* dest is a standard PTP port */
4236 if (dest == 319 || dest == 320)
4237 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4238 }
4239
4240 if (trans_data_len < sizeof(struct udphdr))
4241 padto = max_t(unsigned int, padto,
4242 len + sizeof(struct udphdr) - trans_data_len);
4243 }
4244
4245 return padto;
4246}
4247
4248static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4249 struct sk_buff *skb)
4250{
4251 unsigned int padto = 0;
4252
4253 switch (tp->mac_version) {
4254 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
4255 padto = rtl8125_quirk_udp_padto(tp, skb);
4256 break;
4257 default:
4258 break;
4259 }
4260
4261 switch (tp->mac_version) {
4262 case RTL_GIGA_MAC_VER_34:
4263 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
4264 padto = max_t(unsigned int, padto, ETH_ZLEN);
4265 break;
4266 default:
4267 break;
4268 }
4269
4270 return padto;
4271}
4272
4273static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4274{
4275 u32 mss = skb_shinfo(skb)->gso_size;
4276
4277 if (mss) {
4278 opts[0] |= TD_LSO;
4279 opts[0] |= mss << TD0_MSS_SHIFT;
4280 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4281 const struct iphdr *ip = ip_hdr(skb);
4282
4283 if (ip->protocol == IPPROTO_TCP)
4284 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4285 else if (ip->protocol == IPPROTO_UDP)
4286 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4287 else
4288 WARN_ON_ONCE(1);
4289 }
4290}
4291
4292static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4293 struct sk_buff *skb, u32 *opts)
4294{
4295 struct skb_shared_info *shinfo = skb_shinfo(skb);
4296 u32 mss = shinfo->gso_size;
4297
4298 if (mss) {
4299 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4300 opts[0] |= TD1_GTSENV4;
4301 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4302 if (skb_cow_head(skb, headroom: 0))
4303 return false;
4304
4305 tcp_v6_gso_csum_prep(skb);
4306 opts[0] |= TD1_GTSENV6;
4307 } else {
4308 WARN_ON_ONCE(1);
4309 }
4310
4311 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4312 opts[1] |= mss << TD1_MSS_SHIFT;
4313 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4314 u8 ip_protocol;
4315
4316 switch (vlan_get_protocol(skb)) {
4317 case htons(ETH_P_IP):
4318 opts[1] |= TD1_IPv4_CS;
4319 ip_protocol = ip_hdr(skb)->protocol;
4320 break;
4321
4322 case htons(ETH_P_IPV6):
4323 opts[1] |= TD1_IPv6_CS;
4324 ip_protocol = ipv6_hdr(skb)->nexthdr;
4325 break;
4326
4327 default:
4328 ip_protocol = IPPROTO_RAW;
4329 break;
4330 }
4331
4332 if (ip_protocol == IPPROTO_TCP)
4333 opts[1] |= TD1_TCP_CS;
4334 else if (ip_protocol == IPPROTO_UDP)
4335 opts[1] |= TD1_UDP_CS;
4336 else
4337 WARN_ON_ONCE(1);
4338
4339 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4340 } else {
4341 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4342
4343 /* skb_padto would free the skb on error */
4344 return !__skb_put_padto(skb, len: padto, free_on_error: false);
4345 }
4346
4347 return true;
4348}
4349
4350static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4351{
4352 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4353}
4354
4355/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4356static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4357{
4358 switch (tp->mac_version) {
4359 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4360 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4361 return false;
4362 default:
4363 return true;
4364 }
4365}
4366
4367static void rtl8169_doorbell(struct rtl8169_private *tp)
4368{
4369 if (rtl_is_8125(tp))
4370 RTL_W16(tp, TxPoll_8125, BIT(0));
4371 else
4372 RTL_W8(tp, TxPoll, NPQ);
4373}
4374
4375static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4376 struct net_device *dev)
4377{
4378 struct rtl8169_private *tp = netdev_priv(dev);
4379 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4380 struct TxDesc *txd_first, *txd_last;
4381 bool stop_queue, door_bell;
4382 unsigned int frags;
4383 u32 opts[2];
4384
4385 if (unlikely(!rtl_tx_slots_avail(tp))) {
4386 if (net_ratelimit())
4387 netdev_err(dev, format: "BUG! Tx Ring full when queue awake!\n");
4388 netif_stop_queue(dev);
4389 return NETDEV_TX_BUSY;
4390 }
4391
4392 opts[1] = rtl8169_tx_vlan_tag(skb);
4393 opts[0] = 0;
4394
4395 if (!rtl_chip_supports_csum_v2(tp))
4396 rtl8169_tso_csum_v1(skb, opts);
4397 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4398 goto err_dma_0;
4399
4400 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4401 entry, false)))
4402 goto err_dma_0;
4403
4404 txd_first = tp->TxDescArray + entry;
4405
4406 frags = skb_shinfo(skb)->nr_frags;
4407 if (frags) {
4408 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4409 goto err_dma_1;
4410 entry = (entry + frags) % NUM_TX_DESC;
4411 }
4412
4413 txd_last = tp->TxDescArray + entry;
4414 txd_last->opts1 |= cpu_to_le32(LastFrag);
4415 tp->tx_skb[entry].skb = skb;
4416
4417 skb_tx_timestamp(skb);
4418
4419 /* Force memory writes to complete before releasing descriptor */
4420 dma_wmb();
4421
4422 door_bell = __netdev_sent_queue(dev, bytes: skb->len, xmit_more: netdev_xmit_more());
4423
4424 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4425
4426 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4427 smp_wmb();
4428
4429 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4430
4431 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4432 R8169_TX_STOP_THRS,
4433 R8169_TX_START_THRS);
4434 if (door_bell || stop_queue)
4435 rtl8169_doorbell(tp);
4436
4437 return NETDEV_TX_OK;
4438
4439err_dma_1:
4440 rtl8169_unmap_tx_skb(tp, entry);
4441err_dma_0:
4442 dev_kfree_skb_any(skb);
4443 dev->stats.tx_dropped++;
4444 return NETDEV_TX_OK;
4445}
4446
4447static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4448{
4449 struct skb_shared_info *info = skb_shinfo(skb);
4450 unsigned int nr_frags = info->nr_frags;
4451
4452 if (!nr_frags)
4453 return UINT_MAX;
4454
4455 return skb_frag_size(frag: info->frags + nr_frags - 1);
4456}
4457
4458/* Workaround for hw issues with TSO on RTL8168evl */
4459static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4460 netdev_features_t features)
4461{
4462 /* IPv4 header has options field */
4463 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4464 ip_hdrlen(skb) > sizeof(struct iphdr))
4465 features &= ~NETIF_F_ALL_TSO;
4466
4467 /* IPv4 TCP header has options field */
4468 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4469 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4470 features &= ~NETIF_F_ALL_TSO;
4471
4472 else if (rtl_last_frag_len(skb) <= 6)
4473 features &= ~NETIF_F_ALL_TSO;
4474
4475 return features;
4476}
4477
4478static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4479 struct net_device *dev,
4480 netdev_features_t features)
4481{
4482 struct rtl8169_private *tp = netdev_priv(dev);
4483
4484 if (skb_is_gso(skb)) {
4485 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4486 features = rtl8168evl_fix_tso(skb, features);
4487
4488 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4489 rtl_chip_supports_csum_v2(tp))
4490 features &= ~NETIF_F_ALL_TSO;
4491 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4492 /* work around hw bug on some chip versions */
4493 if (skb->len < ETH_ZLEN)
4494 features &= ~NETIF_F_CSUM_MASK;
4495
4496 if (rtl_quirk_packet_padto(tp, skb))
4497 features &= ~NETIF_F_CSUM_MASK;
4498
4499 if (skb_transport_offset(skb) > TCPHO_MAX &&
4500 rtl_chip_supports_csum_v2(tp))
4501 features &= ~NETIF_F_CSUM_MASK;
4502 }
4503
4504 return vlan_features_check(skb, features);
4505}
4506
4507static void rtl8169_pcierr_interrupt(struct net_device *dev)
4508{
4509 struct rtl8169_private *tp = netdev_priv(dev);
4510 struct pci_dev *pdev = tp->pci_dev;
4511 int pci_status_errs;
4512 u16 pci_cmd;
4513
4514 pci_read_config_word(dev: pdev, PCI_COMMAND, val: &pci_cmd);
4515
4516 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4517
4518 if (net_ratelimit())
4519 netdev_err(dev, format: "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4520 pci_cmd, pci_status_errs);
4521
4522 rtl_schedule_task(tp, flag: RTL_FLAG_TASK_RESET_PENDING);
4523}
4524
4525static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4526 int budget)
4527{
4528 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4529 struct sk_buff *skb;
4530
4531 dirty_tx = tp->dirty_tx;
4532
4533 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4534 unsigned int entry = dirty_tx % NUM_TX_DESC;
4535 u32 status;
4536
4537 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4538 if (status & DescOwn)
4539 break;
4540
4541 skb = tp->tx_skb[entry].skb;
4542 rtl8169_unmap_tx_skb(tp, entry);
4543
4544 if (skb) {
4545 pkts_compl++;
4546 bytes_compl += skb->len;
4547 napi_consume_skb(skb, budget);
4548 }
4549 dirty_tx++;
4550 }
4551
4552 if (tp->dirty_tx != dirty_tx) {
4553 dev_sw_netstats_tx_add(dev, packets: pkts_compl, len: bytes_compl);
4554 WRITE_ONCE(tp->dirty_tx, dirty_tx);
4555
4556 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4557 rtl_tx_slots_avail(tp),
4558 R8169_TX_START_THRS);
4559 /*
4560 * 8168 hack: TxPoll requests are lost when the Tx packets are
4561 * too close. Let's kick an extra TxPoll request when a burst
4562 * of start_xmit activity is detected (if it is not detected,
4563 * it is slow enough). -- FR
4564 * If skb is NULL then we come here again once a tx irq is
4565 * triggered after the last fragment is marked transmitted.
4566 */
4567 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4568 rtl8169_doorbell(tp);
4569 }
4570}
4571
4572static inline int rtl8169_fragmented_frame(u32 status)
4573{
4574 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4575}
4576
4577static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4578{
4579 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4580
4581 if (status == RxProtoTCP || status == RxProtoUDP)
4582 skb->ip_summed = CHECKSUM_UNNECESSARY;
4583 else
4584 skb_checksum_none_assert(skb);
4585}
4586
4587static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4588{
4589 struct device *d = tp_to_dev(tp);
4590 int count;
4591
4592 for (count = 0; count < budget; count++, tp->cur_rx++) {
4593 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4594 struct RxDesc *desc = tp->RxDescArray + entry;
4595 struct sk_buff *skb;
4596 const void *rx_buf;
4597 dma_addr_t addr;
4598 u32 status;
4599
4600 status = le32_to_cpu(READ_ONCE(desc->opts1));
4601 if (status & DescOwn)
4602 break;
4603
4604 /* This barrier is needed to keep us from reading
4605 * any other fields out of the Rx descriptor until
4606 * we know the status of DescOwn
4607 */
4608 dma_rmb();
4609
4610 if (unlikely(status & RxRES)) {
4611 if (net_ratelimit())
4612 netdev_warn(dev, format: "Rx ERROR. status = %08x\n",
4613 status);
4614 dev->stats.rx_errors++;
4615 if (status & (RxRWT | RxRUNT))
4616 dev->stats.rx_length_errors++;
4617 if (status & RxCRC)
4618 dev->stats.rx_crc_errors++;
4619
4620 if (!(dev->features & NETIF_F_RXALL))
4621 goto release_descriptor;
4622 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4623 goto release_descriptor;
4624 }
4625
4626 pkt_size = status & GENMASK(13, 0);
4627 if (likely(!(dev->features & NETIF_F_RXFCS)))
4628 pkt_size -= ETH_FCS_LEN;
4629
4630 /* The driver does not support incoming fragmented frames.
4631 * They are seen as a symptom of over-mtu sized frames.
4632 */
4633 if (unlikely(rtl8169_fragmented_frame(status))) {
4634 dev->stats.rx_dropped++;
4635 dev->stats.rx_length_errors++;
4636 goto release_descriptor;
4637 }
4638
4639 skb = napi_alloc_skb(napi: &tp->napi, length: pkt_size);
4640 if (unlikely(!skb)) {
4641 dev->stats.rx_dropped++;
4642 goto release_descriptor;
4643 }
4644
4645 addr = le64_to_cpu(desc->addr);
4646 rx_buf = page_address(tp->Rx_databuff[entry]);
4647
4648 dma_sync_single_for_cpu(dev: d, addr, size: pkt_size, dir: DMA_FROM_DEVICE);
4649 prefetch(rx_buf);
4650 skb_copy_to_linear_data(skb, from: rx_buf, len: pkt_size);
4651 skb->tail += pkt_size;
4652 skb->len = pkt_size;
4653 dma_sync_single_for_device(dev: d, addr, size: pkt_size, dir: DMA_FROM_DEVICE);
4654
4655 rtl8169_rx_csum(skb, opts1: status);
4656 skb->protocol = eth_type_trans(skb, dev);
4657
4658 rtl8169_rx_vlan_tag(desc, skb);
4659
4660 if (skb->pkt_type == PACKET_MULTICAST)
4661 dev->stats.multicast++;
4662
4663 napi_gro_receive(napi: &tp->napi, skb);
4664
4665 dev_sw_netstats_rx_add(dev, len: pkt_size);
4666release_descriptor:
4667 rtl8169_mark_to_asic(desc);
4668 }
4669
4670 return count;
4671}
4672
4673static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4674{
4675 struct rtl8169_private *tp = dev_instance;
4676 u32 status = rtl_get_events(tp);
4677
4678 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4679 return IRQ_NONE;
4680
4681 /* At least RTL8168fp may unexpectedly set the SYSErr bit */
4682 if (unlikely(status & SYSErr &&
4683 tp->mac_version <= RTL_GIGA_MAC_VER_06)) {
4684 rtl8169_pcierr_interrupt(dev: tp->dev);
4685 goto out;
4686 }
4687
4688 if (status & LinkChg)
4689 phy_mac_interrupt(phydev: tp->phydev);
4690
4691 rtl_irq_disable(tp);
4692 napi_schedule(n: &tp->napi);
4693out:
4694 rtl_ack_events(tp, bits: status);
4695
4696 return IRQ_HANDLED;
4697}
4698
4699static void rtl_task(struct work_struct *work)
4700{
4701 struct rtl8169_private *tp =
4702 container_of(work, struct rtl8169_private, wk.work);
4703 int ret;
4704
4705 if (test_and_clear_bit(nr: RTL_FLAG_TASK_TX_TIMEOUT, addr: tp->wk.flags)) {
4706 /* if chip isn't accessible, reset bus to revive it */
4707 if (RTL_R32(tp, TxConfig) == ~0) {
4708 ret = pci_reset_bus(dev: tp->pci_dev);
4709 if (ret < 0) {
4710 netdev_err(dev: tp->dev, format: "Can't reset secondary PCI bus, detach NIC\n");
4711 netif_device_detach(dev: tp->dev);
4712 return;
4713 }
4714 }
4715
4716 /* ASPM compatibility issues are a typical reason for tx timeouts */
4717 ret = pci_disable_link_state(pdev: tp->pci_dev, PCIE_LINK_STATE_L1 |
4718 PCIE_LINK_STATE_L0S);
4719 if (!ret)
4720 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4721 goto reset;
4722 }
4723
4724 if (test_and_clear_bit(nr: RTL_FLAG_TASK_RESET_PENDING, addr: tp->wk.flags)) {
4725reset:
4726 rtl_reset_work(tp);
4727 netif_wake_queue(dev: tp->dev);
4728 }
4729}
4730
4731static int rtl8169_poll(struct napi_struct *napi, int budget)
4732{
4733 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4734 struct net_device *dev = tp->dev;
4735 int work_done;
4736
4737 rtl_tx(dev, tp, budget);
4738
4739 work_done = rtl_rx(dev, tp, budget);
4740
4741 if (work_done < budget && napi_complete_done(n: napi, work_done))
4742 rtl_irq_enable(tp);
4743
4744 return work_done;
4745}
4746
4747static void r8169_phylink_handler(struct net_device *ndev)
4748{
4749 struct rtl8169_private *tp = netdev_priv(dev: ndev);
4750 struct device *d = tp_to_dev(tp);
4751
4752 if (netif_carrier_ok(dev: ndev)) {
4753 rtl_link_chg_patch(tp);
4754 pm_request_resume(dev: d);
4755 } else {
4756 pm_runtime_idle(dev: d);
4757 }
4758
4759 phy_print_status(phydev: tp->phydev);
4760}
4761
4762static int r8169_phy_connect(struct rtl8169_private *tp)
4763{
4764 struct phy_device *phydev = tp->phydev;
4765 phy_interface_t phy_mode;
4766 int ret;
4767
4768 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4769 PHY_INTERFACE_MODE_MII;
4770
4771 ret = phy_connect_direct(dev: tp->dev, phydev, handler: r8169_phylink_handler,
4772 interface: phy_mode);
4773 if (ret)
4774 return ret;
4775
4776 if (!tp->supports_gmii)
4777 phy_set_max_speed(phydev, SPEED_100);
4778
4779 phy_attached_info(phydev);
4780
4781 return 0;
4782}
4783
4784static void rtl8169_down(struct rtl8169_private *tp)
4785{
4786 disable_work_sync(work: &tp->wk.work);
4787 /* Clear all task flags */
4788 bitmap_zero(dst: tp->wk.flags, nbits: RTL_FLAG_MAX);
4789
4790 phy_stop(phydev: tp->phydev);
4791
4792 rtl8169_update_counters(tp);
4793
4794 pci_clear_master(dev: tp->pci_dev);
4795 rtl_pci_commit(tp);
4796
4797 rtl8169_cleanup(tp);
4798 rtl_disable_exit_l1(tp);
4799 rtl_prepare_power_down(tp);
4800
4801 if (tp->dash_type != RTL_DASH_NONE)
4802 rtl8168_driver_stop(tp);
4803}
4804
4805static void rtl8169_up(struct rtl8169_private *tp)
4806{
4807 if (tp->dash_type != RTL_DASH_NONE)
4808 rtl8168_driver_start(tp);
4809
4810 pci_set_master(dev: tp->pci_dev);
4811 phy_init_hw(phydev: tp->phydev);
4812 phy_resume(phydev: tp->phydev);
4813 rtl8169_init_phy(tp);
4814 napi_enable(n: &tp->napi);
4815 enable_work(work: &tp->wk.work);
4816 rtl_reset_work(tp);
4817
4818 phy_start(phydev: tp->phydev);
4819}
4820
4821static int rtl8169_close(struct net_device *dev)
4822{
4823 struct rtl8169_private *tp = netdev_priv(dev);
4824 struct pci_dev *pdev = tp->pci_dev;
4825
4826 pm_runtime_get_sync(dev: &pdev->dev);
4827
4828 netif_stop_queue(dev);
4829 rtl8169_down(tp);
4830 rtl8169_rx_clear(tp);
4831
4832 free_irq(tp->irq, tp);
4833
4834 phy_disconnect(phydev: tp->phydev);
4835
4836 dma_free_coherent(dev: &pdev->dev, R8169_RX_RING_BYTES, cpu_addr: tp->RxDescArray,
4837 dma_handle: tp->RxPhyAddr);
4838 dma_free_coherent(dev: &pdev->dev, R8169_TX_RING_BYTES, cpu_addr: tp->TxDescArray,
4839 dma_handle: tp->TxPhyAddr);
4840 tp->TxDescArray = NULL;
4841 tp->RxDescArray = NULL;
4842
4843 pm_runtime_put_sync(dev: &pdev->dev);
4844
4845 return 0;
4846}
4847
4848#ifdef CONFIG_NET_POLL_CONTROLLER
4849static void rtl8169_netpoll(struct net_device *dev)
4850{
4851 struct rtl8169_private *tp = netdev_priv(dev);
4852
4853 rtl8169_interrupt(irq: tp->irq, dev_instance: tp);
4854}
4855#endif
4856
4857static int rtl_open(struct net_device *dev)
4858{
4859 struct rtl8169_private *tp = netdev_priv(dev);
4860 struct pci_dev *pdev = tp->pci_dev;
4861 unsigned long irqflags;
4862 int retval = -ENOMEM;
4863
4864 pm_runtime_get_sync(dev: &pdev->dev);
4865
4866 /*
4867 * Rx and Tx descriptors needs 256 bytes alignment.
4868 * dma_alloc_coherent provides more.
4869 */
4870 tp->TxDescArray = dma_alloc_coherent(dev: &pdev->dev, R8169_TX_RING_BYTES,
4871 dma_handle: &tp->TxPhyAddr, GFP_KERNEL);
4872 if (!tp->TxDescArray)
4873 goto out;
4874
4875 tp->RxDescArray = dma_alloc_coherent(dev: &pdev->dev, R8169_RX_RING_BYTES,
4876 dma_handle: &tp->RxPhyAddr, GFP_KERNEL);
4877 if (!tp->RxDescArray)
4878 goto err_free_tx_0;
4879
4880 retval = rtl8169_init_ring(tp);
4881 if (retval < 0)
4882 goto err_free_rx_1;
4883
4884 rtl_request_firmware(tp);
4885
4886 irqflags = pci_dev_msi_enabled(pci_dev: pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4887 retval = request_irq(irq: tp->irq, handler: rtl8169_interrupt, flags: irqflags, name: dev->name, dev: tp);
4888 if (retval < 0)
4889 goto err_release_fw_2;
4890
4891 retval = r8169_phy_connect(tp);
4892 if (retval)
4893 goto err_free_irq;
4894
4895 rtl8169_up(tp);
4896 rtl8169_init_counter_offsets(tp);
4897 netif_start_queue(dev);
4898out:
4899 pm_runtime_put_sync(dev: &pdev->dev);
4900
4901 return retval;
4902
4903err_free_irq:
4904 free_irq(tp->irq, tp);
4905err_release_fw_2:
4906 rtl_release_firmware(tp);
4907 rtl8169_rx_clear(tp);
4908err_free_rx_1:
4909 dma_free_coherent(dev: &pdev->dev, R8169_RX_RING_BYTES, cpu_addr: tp->RxDescArray,
4910 dma_handle: tp->RxPhyAddr);
4911 tp->RxDescArray = NULL;
4912err_free_tx_0:
4913 dma_free_coherent(dev: &pdev->dev, R8169_TX_RING_BYTES, cpu_addr: tp->TxDescArray,
4914 dma_handle: tp->TxPhyAddr);
4915 tp->TxDescArray = NULL;
4916 goto out;
4917}
4918
4919static void
4920rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4921{
4922 struct rtl8169_private *tp = netdev_priv(dev);
4923 struct pci_dev *pdev = tp->pci_dev;
4924 struct rtl8169_counters *counters = tp->counters;
4925
4926 pm_runtime_get_noresume(dev: &pdev->dev);
4927
4928 netdev_stats_to_stats64(stats64: stats, netdev_stats: &dev->stats);
4929 dev_fetch_sw_netstats(s: stats, netstats: dev->tstats);
4930
4931 /*
4932 * Fetch additional counter values missing in stats collected by driver
4933 * from tally counters.
4934 */
4935 if (pm_runtime_active(dev: &pdev->dev))
4936 rtl8169_update_counters(tp);
4937
4938 /*
4939 * Subtract values fetched during initalization.
4940 * See rtl8169_init_counter_offsets for a description why we do that.
4941 */
4942 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4943 le64_to_cpu(tp->tc_offset.tx_errors);
4944 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4945 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4946 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4947 le16_to_cpu(tp->tc_offset.tx_aborted);
4948 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4949 le16_to_cpu(tp->tc_offset.rx_missed);
4950
4951 pm_runtime_put_noidle(dev: &pdev->dev);
4952}
4953
4954static void rtl8169_net_suspend(struct rtl8169_private *tp)
4955{
4956 netif_device_detach(dev: tp->dev);
4957
4958 if (netif_running(dev: tp->dev))
4959 rtl8169_down(tp);
4960}
4961
4962static int rtl8169_runtime_resume(struct device *dev)
4963{
4964 struct rtl8169_private *tp = dev_get_drvdata(dev);
4965
4966 rtl_rar_set(tp, addr: tp->dev->dev_addr);
4967 __rtl8169_set_wol(tp, wolopts: tp->saved_wolopts);
4968
4969 if (tp->TxDescArray)
4970 rtl8169_up(tp);
4971
4972 netif_device_attach(dev: tp->dev);
4973
4974 return 0;
4975}
4976
4977static int rtl8169_suspend(struct device *device)
4978{
4979 struct rtl8169_private *tp = dev_get_drvdata(dev: device);
4980
4981 rtnl_lock();
4982 rtl8169_net_suspend(tp);
4983 if (!device_may_wakeup(dev: tp_to_dev(tp)))
4984 clk_disable_unprepare(clk: tp->clk);
4985 rtnl_unlock();
4986
4987 return 0;
4988}
4989
4990static int rtl8169_resume(struct device *device)
4991{
4992 struct rtl8169_private *tp = dev_get_drvdata(dev: device);
4993
4994 if (!device_may_wakeup(dev: tp_to_dev(tp)))
4995 clk_prepare_enable(clk: tp->clk);
4996
4997 /* Reportedly at least Asus X453MA truncates packets otherwise */
4998 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4999 rtl_init_rxcfg(tp);
5000
5001 return rtl8169_runtime_resume(dev: device);
5002}
5003
5004static int rtl8169_runtime_suspend(struct device *device)
5005{
5006 struct rtl8169_private *tp = dev_get_drvdata(dev: device);
5007
5008 if (!tp->TxDescArray) {
5009 netif_device_detach(dev: tp->dev);
5010 return 0;
5011 }
5012
5013 rtnl_lock();
5014 __rtl8169_set_wol(tp, WAKE_PHY);
5015 rtl8169_net_suspend(tp);
5016 rtnl_unlock();
5017
5018 return 0;
5019}
5020
5021static int rtl8169_runtime_idle(struct device *device)
5022{
5023 struct rtl8169_private *tp = dev_get_drvdata(dev: device);
5024
5025 if (tp->dash_enabled)
5026 return -EBUSY;
5027
5028 if (!netif_running(dev: tp->dev) || !netif_carrier_ok(dev: tp->dev))
5029 pm_schedule_suspend(dev: device, delay: 10000);
5030
5031 return -EBUSY;
5032}
5033
5034static const struct dev_pm_ops rtl8169_pm_ops = {
5035 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
5036 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
5037 rtl8169_runtime_idle)
5038};
5039
5040static void rtl_shutdown(struct pci_dev *pdev)
5041{
5042 struct rtl8169_private *tp = pci_get_drvdata(pdev);
5043
5044 rtnl_lock();
5045 rtl8169_net_suspend(tp);
5046 rtnl_unlock();
5047
5048 /* Restore original MAC address */
5049 rtl_rar_set(tp, addr: tp->dev->perm_addr);
5050
5051 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled)
5052 pci_prepare_to_sleep(dev: pdev);
5053}
5054
5055static void rtl_remove_one(struct pci_dev *pdev)
5056{
5057 struct rtl8169_private *tp = pci_get_drvdata(pdev);
5058
5059 if (pci_dev_run_wake(dev: pdev))
5060 pm_runtime_get_noresume(dev: &pdev->dev);
5061
5062 disable_work_sync(work: &tp->wk.work);
5063
5064 if (IS_ENABLED(CONFIG_R8169_LEDS))
5065 r8169_remove_leds(leds: tp->leds);
5066
5067 unregister_netdev(dev: tp->dev);
5068
5069 if (tp->dash_type != RTL_DASH_NONE)
5070 rtl8168_driver_stop(tp);
5071
5072 rtl_release_firmware(tp);
5073
5074 /* restore original MAC address */
5075 rtl_rar_set(tp, addr: tp->dev->perm_addr);
5076}
5077
5078static const struct net_device_ops rtl_netdev_ops = {
5079 .ndo_open = rtl_open,
5080 .ndo_stop = rtl8169_close,
5081 .ndo_get_stats64 = rtl8169_get_stats64,
5082 .ndo_start_xmit = rtl8169_start_xmit,
5083 .ndo_features_check = rtl8169_features_check,
5084 .ndo_tx_timeout = rtl8169_tx_timeout,
5085 .ndo_validate_addr = eth_validate_addr,
5086 .ndo_change_mtu = rtl8169_change_mtu,
5087 .ndo_fix_features = rtl8169_fix_features,
5088 .ndo_set_features = rtl8169_set_features,
5089 .ndo_set_mac_address = rtl_set_mac_address,
5090 .ndo_eth_ioctl = phy_do_ioctl_running,
5091 .ndo_set_rx_mode = rtl_set_rx_mode,
5092#ifdef CONFIG_NET_POLL_CONTROLLER
5093 .ndo_poll_controller = rtl8169_netpoll,
5094#endif
5095
5096};
5097
5098static void rtl_set_irq_mask(struct rtl8169_private *tp)
5099{
5100 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5101
5102 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5103 tp->irq_mask |= SYSErr | RxFIFOOver;
5104}
5105
5106static int rtl_alloc_irq(struct rtl8169_private *tp)
5107{
5108 unsigned int flags;
5109
5110 switch (tp->mac_version) {
5111 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5112 rtl_unlock_config_regs(tp);
5113 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5114 rtl_lock_config_regs(tp);
5115 fallthrough;
5116 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5117 flags = PCI_IRQ_INTX;
5118 break;
5119 default:
5120 flags = PCI_IRQ_ALL_TYPES;
5121 break;
5122 }
5123
5124 return pci_alloc_irq_vectors(dev: tp->pci_dev, min_vecs: 1, max_vecs: 1, flags);
5125}
5126
5127static void rtl_read_mac_address(struct rtl8169_private *tp,
5128 u8 mac_addr[ETH_ALEN])
5129{
5130 /* Get MAC address */
5131 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5132 u32 value;
5133
5134 value = rtl_eri_read(tp, addr: 0xe0);
5135 put_unaligned_le32(val: value, p: mac_addr);
5136 value = rtl_eri_read(tp, addr: 0xe4);
5137 put_unaligned_le16(val: value, p: mac_addr + 4);
5138 } else if (rtl_is_8125(tp)) {
5139 rtl_read_mac_from_reg(tp, mac: mac_addr, reg: MAC0_BKP);
5140 }
5141}
5142
5143DECLARE_RTL_COND(rtl_link_list_ready_cond)
5144{
5145 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5146}
5147
5148static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5149{
5150 rtl_loop_wait_high(tp, c: &rtl_link_list_ready_cond, d: 100, n: 42);
5151}
5152
5153static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5154{
5155 struct rtl8169_private *tp = mii_bus->priv;
5156
5157 if (phyaddr > 0)
5158 return -ENODEV;
5159
5160 return rtl_readphy(tp, location: phyreg);
5161}
5162
5163static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5164 int phyreg, u16 val)
5165{
5166 struct rtl8169_private *tp = mii_bus->priv;
5167
5168 if (phyaddr > 0)
5169 return -ENODEV;
5170
5171 rtl_writephy(tp, location: phyreg, val);
5172
5173 return 0;
5174}
5175
5176static int r8169_mdio_read_reg_c45(struct mii_bus *mii_bus, int addr,
5177 int devnum, int regnum)
5178{
5179 struct rtl8169_private *tp = mii_bus->priv;
5180
5181 if (addr > 0)
5182 return -ENODEV;
5183
5184 if (devnum == MDIO_MMD_VEND2 && regnum > MDIO_STAT2)
5185 return r8168_phy_ocp_read(tp, reg: regnum);
5186
5187 return 0;
5188}
5189
5190static int r8169_mdio_write_reg_c45(struct mii_bus *mii_bus, int addr,
5191 int devnum, int regnum, u16 val)
5192{
5193 struct rtl8169_private *tp = mii_bus->priv;
5194
5195 if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2)
5196 return -ENODEV;
5197
5198 r8168_phy_ocp_write(tp, reg: regnum, data: val);
5199
5200 return 0;
5201}
5202
5203static int r8169_mdio_register(struct rtl8169_private *tp)
5204{
5205 struct pci_dev *pdev = tp->pci_dev;
5206 struct mii_bus *new_bus;
5207 int ret;
5208
5209 /* On some boards with this chip version the BIOS is buggy and misses
5210 * to reset the PHY page selector. This results in the PHY ID read
5211 * accessing registers on a different page, returning a more or
5212 * less random value. Fix this by resetting the page selector first.
5213 */
5214 if (tp->mac_version == RTL_GIGA_MAC_VER_25 ||
5215 tp->mac_version == RTL_GIGA_MAC_VER_26)
5216 r8169_mdio_write(tp, reg: 0x1f, value: 0);
5217
5218 new_bus = devm_mdiobus_alloc(dev: &pdev->dev);
5219 if (!new_bus)
5220 return -ENOMEM;
5221
5222 new_bus->name = "r8169";
5223 new_bus->priv = tp;
5224 new_bus->parent = &pdev->dev;
5225 new_bus->irq[0] = PHY_MAC_INTERRUPT;
5226 new_bus->phy_mask = GENMASK(31, 1);
5227 snprintf(buf: new_bus->id, MII_BUS_ID_SIZE, fmt: "r8169-%x-%x",
5228 pci_domain_nr(bus: pdev->bus), pci_dev_id(dev: pdev));
5229
5230 new_bus->read = r8169_mdio_read_reg;
5231 new_bus->write = r8169_mdio_write_reg;
5232
5233 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) {
5234 new_bus->read_c45 = r8169_mdio_read_reg_c45;
5235 new_bus->write_c45 = r8169_mdio_write_reg_c45;
5236 }
5237
5238 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5239 if (ret)
5240 return ret;
5241
5242 tp->phydev = mdiobus_get_phy(bus: new_bus, addr: 0);
5243 if (!tp->phydev) {
5244 return -ENODEV;
5245 } else if (!tp->phydev->drv) {
5246 /* Most chip versions fail with the genphy driver.
5247 * Therefore ensure that the dedicated PHY driver is loaded.
5248 */
5249 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5250 tp->phydev->phy_id);
5251 return -EUNATCH;
5252 }
5253
5254 tp->phydev->mac_managed_pm = true;
5255 if (rtl_supports_eee(tp))
5256 phy_support_eee(phydev: tp->phydev);
5257 phy_support_asym_pause(phydev: tp->phydev);
5258
5259 /* mimic behavior of r8125/r8126 vendor drivers */
5260 if (tp->mac_version == RTL_GIGA_MAC_VER_61)
5261 phy_disable_eee_mode(phydev: tp->phydev,
5262 link_mode: ETHTOOL_LINK_MODE_2500baseT_Full_BIT);
5263
5264 /* PHY will be woken up in rtl_open() */
5265 phy_suspend(phydev: tp->phydev);
5266
5267 return 0;
5268}
5269
5270static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5271{
5272 rtl_enable_rxdvgate(tp);
5273
5274 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5275 msleep(msecs: 1);
5276 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5277
5278 r8168_mac_ocp_modify(tp, reg: 0xe8de, BIT(14), set: 0);
5279 r8168g_wait_ll_share_fifo_ready(tp);
5280
5281 r8168_mac_ocp_modify(tp, reg: 0xe8de, mask: 0, BIT(15));
5282 r8168g_wait_ll_share_fifo_ready(tp);
5283}
5284
5285static void rtl_hw_init_8125(struct rtl8169_private *tp)
5286{
5287 rtl_enable_rxdvgate(tp);
5288
5289 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5290 msleep(msecs: 1);
5291 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5292
5293 r8168_mac_ocp_modify(tp, reg: 0xe8de, BIT(14), set: 0);
5294 r8168g_wait_ll_share_fifo_ready(tp);
5295
5296 r8168_mac_ocp_write(tp, reg: 0xc0aa, data: 0x07d0);
5297 r8168_mac_ocp_write(tp, reg: 0xc0a6, data: 0x0150);
5298 r8168_mac_ocp_write(tp, reg: 0xc01e, data: 0x5555);
5299 r8168g_wait_ll_share_fifo_ready(tp);
5300}
5301
5302static void rtl_hw_initialize(struct rtl8169_private *tp)
5303{
5304 switch (tp->mac_version) {
5305 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52:
5306 rtl8168ep_stop_cmac(tp);
5307 fallthrough;
5308 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5309 rtl_hw_init_8168g(tp);
5310 break;
5311 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
5312 rtl_hw_init_8125(tp);
5313 break;
5314 default:
5315 break;
5316 }
5317}
5318
5319static int rtl_jumbo_max(struct rtl8169_private *tp)
5320{
5321 /* Non-GBit versions don't support jumbo frames */
5322 if (!tp->supports_gmii)
5323 return 0;
5324
5325 switch (tp->mac_version) {
5326 /* RTL8169 */
5327 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5328 return JUMBO_7K;
5329 /* RTL8168b */
5330 case RTL_GIGA_MAC_VER_17:
5331 return JUMBO_4K;
5332 /* RTL8168c */
5333 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5334 return JUMBO_6K;
5335 /* RTL8125/8126 */
5336 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
5337 return JUMBO_16K;
5338 default:
5339 return JUMBO_9K;
5340 }
5341}
5342
5343static void rtl_init_mac_address(struct rtl8169_private *tp)
5344{
5345 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5346 struct net_device *dev = tp->dev;
5347 int rc;
5348
5349 rc = eth_platform_get_mac_address(dev: tp_to_dev(tp), mac_addr);
5350 if (!rc)
5351 goto done;
5352
5353 rtl_read_mac_address(tp, mac_addr);
5354 if (is_valid_ether_addr(addr: mac_addr))
5355 goto done;
5356
5357 rtl_read_mac_from_reg(tp, mac: mac_addr, reg: MAC0);
5358 if (is_valid_ether_addr(addr: mac_addr))
5359 goto done;
5360
5361 eth_random_addr(addr: mac_addr);
5362 dev->addr_assign_type = NET_ADDR_RANDOM;
5363 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5364done:
5365 eth_hw_addr_set(dev, addr: mac_addr);
5366 rtl_rar_set(tp, addr: mac_addr);
5367}
5368
5369/* register is set if system vendor successfully tested ASPM 1.2 */
5370static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5371{
5372 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 &&
5373 r8168_mac_ocp_read(tp, reg: 0xc0b2) & 0xf)
5374 return true;
5375
5376 return false;
5377}
5378
5379static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5380{
5381 const struct rtl_chip_info *chip;
5382 struct rtl8169_private *tp;
5383 int jumbo_max, region, rc;
5384 struct net_device *dev;
5385 u32 txconfig;
5386 u16 xid;
5387
5388 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5389 if (!dev)
5390 return -ENOMEM;
5391
5392 SET_NETDEV_DEV(dev, &pdev->dev);
5393 dev->netdev_ops = &rtl_netdev_ops;
5394 tp = netdev_priv(dev);
5395 tp->dev = dev;
5396 tp->pci_dev = pdev;
5397 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5398 tp->ocp_base = OCP_STD_PHY_BASE;
5399
5400 raw_spin_lock_init(&tp->mac_ocp_lock);
5401 mutex_init(&tp->led_lock);
5402
5403 /* Get the *optional* external "ether_clk" used on some boards */
5404 tp->clk = devm_clk_get_optional_enabled(dev: &pdev->dev, id: "ether_clk");
5405 if (IS_ERR(ptr: tp->clk))
5406 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: tp->clk), fmt: "failed to get ether_clk\n");
5407
5408 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5409 rc = pcim_enable_device(pdev);
5410 if (rc < 0)
5411 return dev_err_probe(dev: &pdev->dev, err: rc, fmt: "enable failure\n");
5412
5413 if (pcim_set_mwi(dev: pdev) < 0)
5414 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5415
5416 /* use first MMIO region */
5417 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5418 if (region < 0)
5419 return dev_err_probe(dev: &pdev->dev, err: -ENODEV, fmt: "no MMIO resource found\n");
5420
5421 tp->mmio_addr = pcim_iomap_region(pdev, bar: region, KBUILD_MODNAME);
5422 if (IS_ERR(ptr: tp->mmio_addr))
5423 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: tp->mmio_addr),
5424 fmt: "cannot remap MMIO, aborting\n");
5425
5426 txconfig = RTL_R32(tp, TxConfig);
5427 if (txconfig == ~0U)
5428 return dev_err_probe(dev: &pdev->dev, err: -EIO, fmt: "PCI read failed\n");
5429
5430 xid = (txconfig >> 20) & 0xfcf;
5431
5432 /* Identify chip attached to board */
5433 chip = rtl8169_get_chip_version(xid, gmii: tp->supports_gmii);
5434 if (chip->mac_version == RTL_GIGA_MAC_NONE)
5435 return dev_err_probe(dev: &pdev->dev, err: -ENODEV,
5436 fmt: "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5437 xid);
5438 tp->mac_version = chip->mac_version;
5439 tp->fw_name = chip->fw_name;
5440
5441 /* Disable ASPM L1 as that cause random device stop working
5442 * problems as well as full system hangs for some PCIe devices users.
5443 */
5444 if (rtl_aspm_is_safe(tp)) {
5445 dev_info(&pdev->dev, "System vendor flags ASPM as safe\n");
5446 rc = 0;
5447 } else {
5448 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5449 }
5450 tp->aspm_manageable = !rc;
5451
5452 tp->dash_type = rtl_get_dash_type(tp);
5453 tp->dash_enabled = rtl_dash_is_enabled(tp);
5454
5455 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5456
5457 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5458 !dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(64)))
5459 dev->features |= NETIF_F_HIGHDMA;
5460
5461 rtl_init_rxcfg(tp);
5462
5463 rtl8169_irq_mask_and_ack(tp);
5464
5465 rtl_hw_initialize(tp);
5466
5467 rtl_hw_reset(tp);
5468
5469 rc = rtl_alloc_irq(tp);
5470 if (rc < 0)
5471 return dev_err_probe(dev: &pdev->dev, err: rc, fmt: "Can't allocate interrupt\n");
5472
5473 tp->irq = pci_irq_vector(dev: pdev, nr: 0);
5474
5475 INIT_WORK(&tp->wk.work, rtl_task);
5476 disable_work(work: &tp->wk.work);
5477
5478 rtl_init_mac_address(tp);
5479
5480 dev->ethtool_ops = &rtl8169_ethtool_ops;
5481
5482 netif_napi_add(dev, napi: &tp->napi, poll: rtl8169_poll);
5483
5484 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5485 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5486 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5487 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5488
5489 /*
5490 * Pretend we are using VLANs; This bypasses a nasty bug where
5491 * Interrupts stop flowing on high load on 8110SCd controllers.
5492 */
5493 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5494 /* Disallow toggling */
5495 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5496
5497 if (rtl_chip_supports_csum_v2(tp))
5498 dev->hw_features |= NETIF_F_IPV6_CSUM;
5499
5500 dev->features |= dev->hw_features;
5501
5502 if (rtl_chip_supports_csum_v2(tp)) {
5503 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5504 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5505 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5506 } else {
5507 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5508 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5509 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5510 }
5511
5512 /* There has been a number of reports that using SG/TSO results in
5513 * tx timeouts. However for a lot of people SG/TSO works fine.
5514 * It's not fully clear which chip versions are affected. Vendor
5515 * drivers enable SG/TSO for certain chip versions per default,
5516 * let's mimic this here. On other chip versions users can
5517 * use ethtool to enable SG/TSO, use at own risk!
5518 */
5519 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 &&
5520 tp->mac_version != RTL_GIGA_MAC_VER_61)
5521 dev->features |= dev->hw_features;
5522
5523 dev->hw_features |= NETIF_F_RXALL;
5524 dev->hw_features |= NETIF_F_RXFCS;
5525
5526 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS;
5527
5528 netdev_sw_irq_coalesce_default_on(dev);
5529
5530 /* configure chip for default features */
5531 rtl8169_set_features(dev, features: dev->features);
5532
5533 if (!tp->dash_enabled) {
5534 rtl_set_d3_pll_down(tp, enable: true);
5535 } else {
5536 rtl_set_d3_pll_down(tp, enable: false);
5537 dev->ethtool->wol_enabled = 1;
5538 }
5539
5540 jumbo_max = rtl_jumbo_max(tp);
5541 if (jumbo_max)
5542 dev->max_mtu = jumbo_max;
5543
5544 rtl_set_irq_mask(tp);
5545
5546 tp->counters = dmam_alloc_coherent (dev: &pdev->dev, size: sizeof(*tp->counters),
5547 dma_handle: &tp->counters_phys_addr,
5548 GFP_KERNEL);
5549 if (!tp->counters)
5550 return -ENOMEM;
5551
5552 pci_set_drvdata(pdev, data: tp);
5553
5554 rc = r8169_mdio_register(tp);
5555 if (rc)
5556 return rc;
5557
5558 rc = register_netdev(dev);
5559 if (rc)
5560 return rc;
5561
5562 if (IS_ENABLED(CONFIG_R8169_LEDS)) {
5563 if (rtl_is_8125(tp))
5564 tp->leds = rtl8125_init_leds(ndev: dev);
5565 else if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5566 tp->leds = rtl8168_init_leds(ndev: dev);
5567 }
5568
5569 netdev_info(dev, format: "%s, %pM, XID %03x, IRQ %d\n",
5570 chip->name, dev->dev_addr, xid, tp->irq);
5571
5572 if (jumbo_max)
5573 netdev_info(dev, format: "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5574 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5575 "ok" : "ko");
5576
5577 if (tp->dash_type != RTL_DASH_NONE) {
5578 netdev_info(dev, format: "DASH %s\n",
5579 tp->dash_enabled ? "enabled" : "disabled");
5580 rtl8168_driver_start(tp);
5581 }
5582
5583 if (pci_dev_run_wake(dev: pdev))
5584 pm_runtime_put_sync(dev: &pdev->dev);
5585
5586 return 0;
5587}
5588
5589static struct pci_driver rtl8169_pci_driver = {
5590 .name = KBUILD_MODNAME,
5591 .id_table = rtl8169_pci_tbl,
5592 .probe = rtl_init_one,
5593 .remove = rtl_remove_one,
5594 .shutdown = rtl_shutdown,
5595 .driver.pm = pm_ptr(&rtl8169_pm_ops),
5596};
5597
5598module_pci_driver(rtl8169_pci_driver);
5599