1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 *
5 * Based on drivers/tty/serial/8250/8250_pci.c,
6 *
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 */
9#include <linux/bitfield.h>
10#include <linux/bits.h>
11#include <linux/delay.h>
12#include <linux/device.h>
13#include <linux/dmi.h>
14#include <linux/eeprom_93cx6.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/math.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/platform_device.h>
21#include <linux/pm.h>
22#include <linux/property.h>
23#include <linux/string.h>
24#include <linux/types.h>
25
26#include <linux/serial_8250.h>
27#include <linux/serial_core.h>
28#include <linux/serial_reg.h>
29
30#include <asm/byteorder.h>
31
32#include "8250.h"
33#include "8250_pcilib.h"
34
35#define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
36#define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
37#define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
38#define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
39#define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
40#define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
41#define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
42
43#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
44#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
45#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
46#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
47#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
48#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
49#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
50
51#define PCI_VENDOR_ID_CONNECT_TECH 0x12c4
52#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO 0x0340
53#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A 0x0341
54#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B 0x0342
55#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS 0x0350
56#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A 0x0351
57#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B 0x0352
58#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS 0x0353
59#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A 0x0354
60#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B 0x0355
61#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO 0x0360
62#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A 0x0361
63#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B 0x0362
64#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP 0x0370
65#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232 0x0371
66#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485 0x0372
67#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP 0x0373
68#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP 0x0374
69#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP 0x0375
70#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS 0x0376
71#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT 0x0380
72#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT 0x0381
73#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO 0x0382
74#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO 0x0392
75#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP 0x03A0
76#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232 0x03A1
77#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485 0x03A2
78#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS 0x03A3
79#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XEG001 0x0602
80#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_BASE 0x1000
81#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_2 0x1002
82#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_4 0x1004
83#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_8 0x1008
84#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_12 0x100C
85#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_16 0x1010
86#define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X 0x110c
87#define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X 0x110d
88#define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16 0x1110
89
90#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
91#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
92#define PCI_DEVICE_ID_EXAR_XR17V252 0x0252
93#define PCI_DEVICE_ID_EXAR_XR17V254 0x0254
94#define PCI_DEVICE_ID_EXAR_XR17V258 0x0258
95
96#define PCI_SUBDEVICE_ID_USR_2980 0x0128
97#define PCI_SUBDEVICE_ID_USR_2981 0x0129
98
99#define UART_EXAR_INT0 0x80
100#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
101#define UART_EXAR_SLEEP 0x8b /* Sleep mode */
102#define UART_EXAR_DVID 0x8d /* Device identification */
103
104#define UART_EXAR_FCTR 0x08 /* Feature Control Register */
105#define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
106#define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
107#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
108#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
109#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
110#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
111
112#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
113#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
114
115#define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
116#define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
117#define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
118#define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
119#define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
120#define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
121#define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
122#define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
123#define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
124#define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
125#define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
126#define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
127
128#define UART_EXAR_RS485_DLY(x) ((x) << 4)
129
130#define UART_EXAR_DLD 0x02 /* Divisor Fractional */
131#define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */
132
133/* EEPROM registers */
134#define UART_EXAR_REGB 0x8e
135#define UART_EXAR_REGB_EECK BIT(4)
136#define UART_EXAR_REGB_EECS BIT(5)
137#define UART_EXAR_REGB_EEDI BIT(6)
138#define UART_EXAR_REGB_EEDO BIT(7)
139
140#define UART_EXAR_XR17C15X_PORT_OFFSET 0x200
141#define UART_EXAR_XR17V25X_PORT_OFFSET 0x200
142#define UART_EXAR_XR17V35X_PORT_OFFSET 0x400
143
144/*
145 * IOT2040 MPIO wiring semantics:
146 *
147 * MPIO Port Function
148 * ---- ---- --------
149 * 0 2 Mode bit 0
150 * 1 2 Mode bit 1
151 * 2 2 Terminate bus
152 * 3 - <reserved>
153 * 4 3 Mode bit 0
154 * 5 3 Mode bit 1
155 * 6 3 Terminate bus
156 * 7 - <reserved>
157 * 8 2 Enable
158 * 9 3 Enable
159 * 10 - Red LED
160 * 11..15 - <unused>
161 */
162
163/* IOT2040 MPIOs 0..7 */
164#define IOT2040_UART_MODE_RS232 0x01
165#define IOT2040_UART_MODE_RS485 0x02
166#define IOT2040_UART_MODE_RS422 0x03
167#define IOT2040_UART_TERMINATE_BUS 0x04
168
169#define IOT2040_UART1_MASK 0x0f
170#define IOT2040_UART2_SHIFT 4
171
172#define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
173#define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
174
175/* IOT2040 MPIOs 8..15 */
176#define IOT2040_UARTS_ENABLE 0x03
177#define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
178
179/* CTI EEPROM offsets */
180#define CTI_EE_OFF_XR17C15X_OSC_FREQ 0x04 /* 2 words */
181#define CTI_EE_OFF_XR17C15X_PART_NUM 0x0A /* 4 words */
182#define CTI_EE_OFF_XR17C15X_SERIAL_NUM 0x0E /* 1 word */
183
184#define CTI_EE_OFF_XR17V25X_OSC_FREQ 0x08 /* 2 words */
185#define CTI_EE_OFF_XR17V25X_PART_NUM 0x0E /* 4 words */
186#define CTI_EE_OFF_XR17V25X_SERIAL_NUM 0x12 /* 1 word */
187
188#define CTI_EE_OFF_XR17V35X_SERIAL_NUM 0x11 /* 2 word */
189#define CTI_EE_OFF_XR17V35X_BRD_FLAGS 0x13 /* 1 word */
190#define CTI_EE_OFF_XR17V35X_PORT_FLAGS 0x14 /* 1 word */
191
192#define CTI_EE_MASK_PORT_FLAGS_TYPE GENMASK(7, 0)
193#define CTI_EE_MASK_OSC_FREQ GENMASK(31, 0)
194
195#define CTI_FPGA_RS485_IO_REG 0x2008
196#define CTI_FPGA_CFG_INT_EN_REG 0x48
197#define CTI_FPGA_CFG_INT_EN_EXT_BIT BIT(15) /* External int enable bit */
198
199#define CTI_DEFAULT_PCI_OSC_FREQ 29491200
200#define CTI_DEFAULT_PCIE_OSC_FREQ 125000000
201#define CTI_DEFAULT_FPGA_OSC_FREQ 33333333
202
203/*
204 * CTI Serial port line types. These match the values stored in the first
205 * nibble of the CTI EEPROM port_flags word.
206 */
207enum cti_port_type {
208 CTI_PORT_TYPE_NONE = 0,
209 CTI_PORT_TYPE_RS232, // RS232 ONLY
210 CTI_PORT_TYPE_RS422_485, // RS422/RS485 ONLY
211 CTI_PORT_TYPE_RS232_422_485_HW, // RS232/422/485 HW ONLY Switchable
212 CTI_PORT_TYPE_RS232_422_485_SW, // RS232/422/485 SW ONLY Switchable
213 CTI_PORT_TYPE_RS232_422_485_4B, // RS232/422/485 HW/SW (4bit ex. BCG004)
214 CTI_PORT_TYPE_RS232_422_485_2B, // RS232/422/485 HW/SW (2bit ex. BBG008)
215 CTI_PORT_TYPE_MAX,
216};
217
218#define CTI_PORT_TYPE_VALID(_port_type) \
219 (((_port_type) > CTI_PORT_TYPE_NONE) && \
220 ((_port_type) < CTI_PORT_TYPE_MAX))
221
222#define CTI_PORT_TYPE_RS485(_port_type) \
223 (((_port_type) > CTI_PORT_TYPE_RS232) && \
224 ((_port_type) < CTI_PORT_TYPE_MAX))
225
226struct exar8250;
227
228struct exar8250_platform {
229 int (*rs485_config)(struct uart_port *port, struct ktermios *termios,
230 struct serial_rs485 *rs485);
231 const struct serial_rs485 *rs485_supported;
232 int (*register_gpio)(struct pci_dev *pcidev, struct uart_8250_port *port);
233 void (*unregister_gpio)(struct uart_8250_port *port);
234};
235
236/**
237 * struct exar8250_board - board information
238 * @num_ports: number of serial ports
239 * @reg_shift: describes UART register mapping in PCI memory
240 * @setup: quirk run at ->probe() stage for each port
241 * @exit: quirk run at ->remove() stage
242 */
243struct exar8250_board {
244 unsigned int num_ports;
245 unsigned int reg_shift;
246 int (*setup)(struct exar8250 *priv, struct pci_dev *pcidev,
247 struct uart_8250_port *port, int idx);
248 void (*exit)(struct pci_dev *pcidev);
249};
250
251struct exar8250 {
252 unsigned int nr;
253 unsigned int osc_freq;
254 struct exar8250_board *board;
255 struct eeprom_93cx6 eeprom;
256 void __iomem *virt;
257 int line[];
258};
259
260static inline void exar_write_reg(struct exar8250 *priv,
261 unsigned int reg, u8 value)
262{
263 writeb(val: value, addr: priv->virt + reg);
264}
265
266static inline u8 exar_read_reg(struct exar8250 *priv, unsigned int reg)
267{
268 return readb(addr: priv->virt + reg);
269}
270
271static void exar_eeprom_93cx6_reg_read(struct eeprom_93cx6 *eeprom)
272{
273 struct exar8250 *priv = eeprom->data;
274 u8 regb = exar_read_reg(priv, UART_EXAR_REGB);
275
276 /* EECK and EECS always read 0 from REGB so only set EEDO */
277 eeprom->reg_data_out = regb & UART_EXAR_REGB_EEDO;
278}
279
280static void exar_eeprom_93cx6_reg_write(struct eeprom_93cx6 *eeprom)
281{
282 struct exar8250 *priv = eeprom->data;
283 u8 regb = 0;
284
285 if (eeprom->reg_data_in)
286 regb |= UART_EXAR_REGB_EEDI;
287 if (eeprom->reg_data_clock)
288 regb |= UART_EXAR_REGB_EECK;
289 if (eeprom->reg_chip_select)
290 regb |= UART_EXAR_REGB_EECS;
291
292 exar_write_reg(priv, UART_EXAR_REGB, value: regb);
293}
294
295static void exar_eeprom_init(struct exar8250 *priv)
296{
297 priv->eeprom.data = priv;
298 priv->eeprom.register_read = exar_eeprom_93cx6_reg_read;
299 priv->eeprom.register_write = exar_eeprom_93cx6_reg_write;
300 priv->eeprom.width = PCI_EEPROM_WIDTH_93C46;
301 priv->eeprom.quirks |= PCI_EEPROM_QUIRK_EXTRA_READ_CYCLE;
302}
303
304/**
305 * exar_mpio_config_output() - Configure an Exar MPIO as an output
306 * @priv: Device's private structure
307 * @mpio_num: MPIO number/offset to configure
308 *
309 * Configure a single MPIO as an output and disable tristate. It is recommended
310 * to set the level with exar_mpio_set_high()/exar_mpio_set_low() prior to
311 * calling this function to ensure default MPIO pin state.
312 *
313 * Return: 0 on success, negative error code on failure
314 */
315static int exar_mpio_config_output(struct exar8250 *priv,
316 unsigned int mpio_num)
317{
318 unsigned int mpio_offset;
319 u8 sel_reg; // MPIO Select register (input/output)
320 u8 tri_reg; // MPIO Tristate register
321 u8 value;
322
323 if (mpio_num < 8) {
324 sel_reg = UART_EXAR_MPIOSEL_7_0;
325 tri_reg = UART_EXAR_MPIO3T_7_0;
326 mpio_offset = mpio_num;
327 } else if (mpio_num >= 8 && mpio_num < 16) {
328 sel_reg = UART_EXAR_MPIOSEL_15_8;
329 tri_reg = UART_EXAR_MPIO3T_15_8;
330 mpio_offset = mpio_num - 8;
331 } else {
332 return -EINVAL;
333 }
334
335 // Disable MPIO pin tri-state
336 value = exar_read_reg(priv, reg: tri_reg);
337 value &= ~BIT(mpio_offset);
338 exar_write_reg(priv, reg: tri_reg, value);
339
340 value = exar_read_reg(priv, reg: sel_reg);
341 value &= ~BIT(mpio_offset);
342 exar_write_reg(priv, reg: sel_reg, value);
343
344 return 0;
345}
346
347/**
348 * _exar_mpio_set() - Set an Exar MPIO output high or low
349 * @priv: Device's private structure
350 * @mpio_num: MPIO number/offset to set
351 * @high: Set MPIO high if true, low if false
352 *
353 * Set a single MPIO high or low. exar_mpio_config_output() must also be called
354 * to configure the pin as an output.
355 *
356 * Return: 0 on success, negative error code on failure
357 */
358static int _exar_mpio_set(struct exar8250 *priv,
359 unsigned int mpio_num, bool high)
360{
361 unsigned int mpio_offset;
362 u8 lvl_reg;
363 u8 value;
364
365 if (mpio_num < 8) {
366 lvl_reg = UART_EXAR_MPIOLVL_7_0;
367 mpio_offset = mpio_num;
368 } else if (mpio_num >= 8 && mpio_num < 16) {
369 lvl_reg = UART_EXAR_MPIOLVL_15_8;
370 mpio_offset = mpio_num - 8;
371 } else {
372 return -EINVAL;
373 }
374
375 value = exar_read_reg(priv, reg: lvl_reg);
376 if (high)
377 value |= BIT(mpio_offset);
378 else
379 value &= ~BIT(mpio_offset);
380 exar_write_reg(priv, reg: lvl_reg, value);
381
382 return 0;
383}
384
385static int exar_mpio_set_low(struct exar8250 *priv, unsigned int mpio_num)
386{
387 return _exar_mpio_set(priv, mpio_num, high: false);
388}
389
390static int exar_mpio_set_high(struct exar8250 *priv, unsigned int mpio_num)
391{
392 return _exar_mpio_set(priv, mpio_num, high: true);
393}
394
395static int generic_rs485_config(struct uart_port *port, struct ktermios *termios,
396 struct serial_rs485 *rs485)
397{
398 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
399 u8 __iomem *p = port->membase;
400 u8 value;
401
402 value = readb(addr: p + UART_EXAR_FCTR);
403 if (is_rs485)
404 value |= UART_FCTR_EXAR_485;
405 else
406 value &= ~UART_FCTR_EXAR_485;
407
408 writeb(val: value, addr: p + UART_EXAR_FCTR);
409
410 if (is_rs485)
411 writeb(UART_EXAR_RS485_DLY(4), addr: p + UART_MSR);
412
413 return 0;
414}
415
416static const struct serial_rs485 generic_rs485_supported = {
417 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
418};
419
420static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
421{
422 /*
423 * Exar UARTs have a SLEEP register that enables or disables each UART
424 * to enter sleep mode separately. On the XR17V35x the register
425 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
426 * the UART channel may only write to the corresponding bit.
427 */
428 serial_port_out(up: port, UART_EXAR_SLEEP, value: state ? 0xff : 0);
429}
430
431/*
432 * XR17V35x UARTs have an extra fractional divisor register (DLD)
433 * Calculate divisor with extra 4-bit fractional portion
434 */
435static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
436 unsigned int *frac)
437{
438 unsigned int quot_16;
439
440 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
441 *frac = quot_16 & 0x0f;
442
443 return quot_16 >> 4;
444}
445
446static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
447 unsigned int quot, unsigned int quot_frac)
448{
449 serial8250_do_set_divisor(port: p, baud, quot);
450
451 /* Preserve bits not related to baudrate; DLD[7:4]. */
452 quot_frac |= serial_port_in(up: p, offset: 0x2) & 0xf0;
453 serial_port_out(up: p, offset: 0x2, value: quot_frac);
454}
455
456static int xr17v35x_startup(struct uart_port *port)
457{
458 /*
459 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
460 * MCR [7:5] and MSR [7:0]
461 */
462 serial_port_out(up: port, UART_XR_EFR, UART_EFR_ECB);
463
464 /*
465 * Make sure all interrupts are masked until initialization is
466 * complete and the FIFOs are cleared
467 *
468 * Synchronize UART_IER access against the console.
469 */
470 uart_port_lock_irq(up: port);
471 serial_port_out(up: port, UART_IER, value: 0);
472 uart_port_unlock_irq(up: port);
473
474 return serial8250_do_startup(port);
475}
476
477static void exar_shutdown(struct uart_port *port)
478{
479 bool tx_complete = false;
480 struct uart_8250_port *up = up_to_u8250p(up: port);
481 struct tty_port *tport = &port->state->port;
482 int i = 0;
483 u16 lsr;
484
485 do {
486 lsr = serial_in(up, UART_LSR);
487 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
488 tx_complete = true;
489 else
490 tx_complete = false;
491 usleep_range(min: 1000, max: 1100);
492 } while (!kfifo_is_empty(&tport->xmit_fifo) &&
493 !tx_complete && i++ < 1000);
494
495 serial8250_do_shutdown(port);
496}
497
498static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
499 int idx, unsigned int offset,
500 struct uart_8250_port *port)
501{
502 const struct exar8250_board *board = priv->board;
503 unsigned char status;
504 int err;
505
506 err = serial8250_pci_setup_port(dev: pcidev, port, bar: 0, offset, regshift: board->reg_shift);
507 if (err)
508 return err;
509
510 /*
511 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
512 * with when DLAB is set which will cause the device to incorrectly match
513 * and assign port type to PORT_16650. The EFR for this UART is found
514 * at offset 0x09. Instead check the Deice ID (DVID) register
515 * for a 2, 4 or 8 port UART.
516 */
517 status = readb(addr: port->port.membase + UART_EXAR_DVID);
518 if (status == 0x82 || status == 0x84 || status == 0x88) {
519 port->port.type = PORT_XR17V35X;
520
521 port->port.get_divisor = xr17v35x_get_divisor;
522 port->port.set_divisor = xr17v35x_set_divisor;
523
524 port->port.startup = xr17v35x_startup;
525 } else {
526 port->port.type = PORT_XR17D15X;
527 }
528
529 port->port.pm = exar_pm;
530 port->port.shutdown = exar_shutdown;
531
532 return 0;
533}
534
535static int
536pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
537 struct uart_8250_port *port, int idx)
538{
539 unsigned int offset = idx * 0x200;
540 unsigned int baud = 1843200;
541 u8 __iomem *p;
542 int err;
543
544 port->port.uartclk = baud * 16;
545
546 err = default_setup(priv, pcidev, idx, offset, port);
547 if (err)
548 return err;
549
550 p = port->port.membase;
551
552 writeb(val: 0x00, addr: p + UART_EXAR_8XMODE);
553 writeb(UART_FCTR_EXAR_TRGD, addr: p + UART_EXAR_FCTR);
554 writeb(val: 32, addr: p + UART_EXAR_TXTRG);
555 writeb(val: 32, addr: p + UART_EXAR_RXTRG);
556
557 /* Skip the initial (per device) setup */
558 if (idx)
559 return 0;
560
561 /*
562 * Setup Multipurpose Input/Output pins.
563 */
564 switch (pcidev->device) {
565 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
566 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
567 writeb(val: 0x78, addr: p + UART_EXAR_MPIOLVL_7_0);
568 writeb(val: 0x00, addr: p + UART_EXAR_MPIOINV_7_0);
569 writeb(val: 0x00, addr: p + UART_EXAR_MPIOSEL_7_0);
570 break;
571 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
572 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
573 writeb(val: 0x00, addr: p + UART_EXAR_MPIOLVL_7_0);
574 writeb(val: 0xc0, addr: p + UART_EXAR_MPIOINV_7_0);
575 writeb(val: 0xc0, addr: p + UART_EXAR_MPIOSEL_7_0);
576 break;
577 default:
578 break;
579 }
580 writeb(val: 0x00, addr: p + UART_EXAR_MPIOINT_7_0);
581 writeb(val: 0x00, addr: p + UART_EXAR_MPIO3T_7_0);
582 writeb(val: 0x00, addr: p + UART_EXAR_MPIOOD_7_0);
583
584 return 0;
585}
586
587/**
588 * cti_tristate_disable() - Disable RS485 transciever tristate
589 * @priv: Device's private structure
590 * @port_num: Port number to set tristate off
591 *
592 * Most RS485 capable cards have a power on tristate jumper/switch that ensures
593 * the RS422/RS485 transceiver does not drive a multi-drop RS485 bus when it is
594 * not the master. When this jumper is installed the user must set the RS485
595 * mode to Full or Half duplex to disable tristate prior to using the port.
596 *
597 * Some Exar UARTs have an auto-tristate feature while others require setting
598 * an MPIO to disable the tristate.
599 *
600 * Return: 0 on success, negative error code on failure
601 */
602static int cti_tristate_disable(struct exar8250 *priv, unsigned int port_num)
603{
604 int ret;
605
606 ret = exar_mpio_set_high(priv, mpio_num: port_num);
607 if (ret)
608 return ret;
609
610 return exar_mpio_config_output(priv, mpio_num: port_num);
611}
612
613/**
614 * cti_plx_int_enable() - Enable UART interrupts to PLX bridge
615 * @priv: Device's private structure
616 *
617 * Some older CTI cards require MPIO_0 to be set low to enable the
618 * interrupts from the UART to the PLX PCI->PCIe bridge.
619 *
620 * Return: 0 on success, negative error code on failure
621 */
622static int cti_plx_int_enable(struct exar8250 *priv)
623{
624 int ret;
625
626 ret = exar_mpio_set_low(priv, mpio_num: 0);
627 if (ret)
628 return ret;
629
630 return exar_mpio_config_output(priv, mpio_num: 0);
631}
632
633/**
634 * cti_read_osc_freq() - Read the UART oscillator frequency from EEPROM
635 * @priv: Device's private structure
636 * @eeprom_offset: Offset where the oscillator frequency is stored
637 *
638 * CTI XR17x15X and XR17V25X cards have the serial boards oscillator frequency
639 * stored in the EEPROM. FPGA and XR17V35X based cards use the PCI/PCIe clock.
640 *
641 * Return: frequency on success, negative error code on failure
642 */
643static int cti_read_osc_freq(struct exar8250 *priv, u8 eeprom_offset)
644{
645 __le16 ee_words[2];
646 u32 osc_freq;
647
648 eeprom_93cx6_multiread(eeprom: &priv->eeprom, word: eeprom_offset, data: ee_words, ARRAY_SIZE(ee_words));
649
650 osc_freq = le16_to_cpu(ee_words[0]) | (le16_to_cpu(ee_words[1]) << 16);
651 if (osc_freq == CTI_EE_MASK_OSC_FREQ)
652 return -EIO;
653
654 return osc_freq;
655}
656
657/**
658 * cti_get_port_type_xr17c15x_xr17v25x() - Get port type of xr17c15x/xr17v25x
659 * @priv: Device's private structure
660 * @pcidev: Pointer to the PCI device for this port
661 * @port_num: Port to get type of
662 *
663 * CTI xr17c15x and xr17v25x based cards port types are based on PCI IDs.
664 *
665 * Return: port type on success, CTI_PORT_TYPE_NONE on failure
666 */
667static enum cti_port_type cti_get_port_type_xr17c15x_xr17v25x(struct exar8250 *priv,
668 struct pci_dev *pcidev,
669 unsigned int port_num)
670{
671 switch (pcidev->subsystem_device) {
672 // RS232 only cards
673 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232:
674 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232:
675 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232:
676 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232:
677 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS:
678 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232:
679 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS:
680 return CTI_PORT_TYPE_RS232;
681 // 1x RS232, 1x RS422/RS485
682 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1:
683 return (port_num == 0) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
684 // 2x RS232, 2x RS422/RS485
685 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2:
686 return (port_num < 2) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
687 // 4x RS232, 4x RS422/RS485
688 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4:
689 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP:
690 return (port_num < 4) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
691 // RS232/RS422/RS485 HW (jumper) selectable
692 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2:
693 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4:
694 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8:
695 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO:
696 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A:
697 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B:
698 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS:
699 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A:
700 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B:
701 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS:
702 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A:
703 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B:
704 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO:
705 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A:
706 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B:
707 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP:
708 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT:
709 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT:
710 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO:
711 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO:
712 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP:
713 return CTI_PORT_TYPE_RS232_422_485_HW;
714 // RS422/RS485 HW (jumper) selectable
715 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485:
716 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485:
717 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485:
718 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485:
719 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485:
720 return CTI_PORT_TYPE_RS422_485;
721 // 6x RS232, 2x RS422/RS485
722 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP:
723 return (port_num < 6) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
724 // 2x RS232, 6x RS422/RS485
725 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP:
726 return (port_num < 2) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
727 default:
728 dev_err(&pcidev->dev, "unknown/unsupported device\n");
729 return CTI_PORT_TYPE_NONE;
730 }
731}
732
733/**
734 * cti_get_port_type_fpga() - Get the port type of a CTI FPGA card
735 * @priv: Device's private structure
736 * @pcidev: Pointer to the PCI device for this port
737 * @port_num: Port to get type of
738 *
739 * FPGA based cards port types are based on PCI IDs.
740 *
741 * Return: port type on success, CTI_PORT_TYPE_NONE on failure
742 */
743static enum cti_port_type cti_get_port_type_fpga(struct exar8250 *priv,
744 struct pci_dev *pcidev,
745 unsigned int port_num)
746{
747 switch (pcidev->device) {
748 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X:
749 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X:
750 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16:
751 return CTI_PORT_TYPE_RS232_422_485_HW;
752 default:
753 dev_err(&pcidev->dev, "unknown/unsupported device\n");
754 return CTI_PORT_TYPE_NONE;
755 }
756}
757
758/**
759 * cti_get_port_type_xr17v35x() - Read port type from the EEPROM
760 * @priv: Device's private structure
761 * @pcidev: Pointer to the PCI device for this port
762 * @port_num: port offset
763 *
764 * CTI XR17V35X based cards have the port types stored in the EEPROM.
765 * This function reads the port type for a single port.
766 *
767 * Return: port type on success, CTI_PORT_TYPE_NONE on failure
768 */
769static enum cti_port_type cti_get_port_type_xr17v35x(struct exar8250 *priv,
770 struct pci_dev *pcidev,
771 unsigned int port_num)
772{
773 enum cti_port_type port_type;
774 u16 port_flags;
775 u8 offset;
776
777 offset = CTI_EE_OFF_XR17V35X_PORT_FLAGS + port_num;
778 eeprom_93cx6_read(eeprom: &priv->eeprom, word: offset, data: &port_flags);
779
780 port_type = FIELD_GET(CTI_EE_MASK_PORT_FLAGS_TYPE, port_flags);
781 if (CTI_PORT_TYPE_VALID(port_type))
782 return port_type;
783
784 /*
785 * If the port type is missing the card assume it is a
786 * RS232/RS422/RS485 card to be safe.
787 *
788 * There is one known board (BEG013) that only has 3 of 4 port types
789 * written to the EEPROM so this acts as a work around.
790 */
791 dev_warn(&pcidev->dev, "failed to get port %d type from EEPROM\n", port_num);
792
793 return CTI_PORT_TYPE_RS232_422_485_HW;
794}
795
796static int cti_rs485_config_mpio_tristate(struct uart_port *port,
797 struct ktermios *termios,
798 struct serial_rs485 *rs485)
799{
800 struct exar8250 *priv = (struct exar8250 *)port->private_data;
801 int ret;
802
803 ret = generic_rs485_config(port, termios, rs485);
804 if (ret)
805 return ret;
806
807 // Disable power-on RS485 tri-state via MPIO
808 return cti_tristate_disable(priv, port_num: port->port_id);
809}
810
811static void cti_board_init_osc_freq(struct exar8250 *priv, struct pci_dev *pcidev, u8 eeprom_offset)
812{
813 int osc_freq;
814
815 osc_freq = cti_read_osc_freq(priv, eeprom_offset);
816 if (osc_freq <= 0) {
817 dev_warn(&pcidev->dev, "failed to read OSC freq from EEPROM, using default\n");
818 osc_freq = CTI_DEFAULT_PCI_OSC_FREQ;
819 }
820
821 priv->osc_freq = osc_freq;
822}
823
824static int cti_port_setup_common(struct exar8250 *priv,
825 struct pci_dev *pcidev,
826 int idx, unsigned int offset,
827 struct uart_8250_port *port)
828{
829 int ret;
830
831 port->port.port_id = idx;
832 port->port.uartclk = priv->osc_freq;
833
834 ret = serial8250_pci_setup_port(dev: pcidev, port, bar: 0, offset, regshift: 0);
835 if (ret)
836 return ret;
837
838 port->port.private_data = (void *)priv;
839 port->port.pm = exar_pm;
840 port->port.shutdown = exar_shutdown;
841
842 return 0;
843}
844
845static int cti_board_init_fpga(struct exar8250 *priv, struct pci_dev *pcidev)
846{
847 int ret;
848 u16 cfg_val;
849
850 // FPGA OSC is fixed to the 33MHz PCI clock
851 priv->osc_freq = CTI_DEFAULT_FPGA_OSC_FREQ;
852
853 // Enable external interrupts in special cfg space register
854 ret = pci_read_config_word(dev: pcidev, CTI_FPGA_CFG_INT_EN_REG, val: &cfg_val);
855 if (ret)
856 return pcibios_err_to_errno(err: ret);
857
858 cfg_val |= CTI_FPGA_CFG_INT_EN_EXT_BIT;
859 ret = pci_write_config_word(dev: pcidev, CTI_FPGA_CFG_INT_EN_REG, val: cfg_val);
860 if (ret)
861 return pcibios_err_to_errno(err: ret);
862
863 // RS485 gate needs to be enabled; otherwise RTS/CTS will not work
864 exar_write_reg(priv, CTI_FPGA_RS485_IO_REG, value: 0x01);
865
866 return 0;
867}
868
869static int cti_port_setup_fpga(struct exar8250 *priv,
870 struct pci_dev *pcidev,
871 struct uart_8250_port *port,
872 int idx)
873{
874 enum cti_port_type port_type;
875 unsigned int offset;
876 int ret;
877
878 if (idx == 0) {
879 ret = cti_board_init_fpga(priv, pcidev);
880 if (ret)
881 return ret;
882 }
883
884 port_type = cti_get_port_type_fpga(priv, pcidev, port_num: idx);
885
886 // FPGA shares port offsets with XR17C15X
887 offset = idx * UART_EXAR_XR17C15X_PORT_OFFSET;
888 port->port.type = PORT_XR17D15X;
889
890 port->port.get_divisor = xr17v35x_get_divisor;
891 port->port.set_divisor = xr17v35x_set_divisor;
892 port->port.startup = xr17v35x_startup;
893
894 if (CTI_PORT_TYPE_RS485(port_type)) {
895 port->port.rs485_config = generic_rs485_config;
896 port->port.rs485_supported = generic_rs485_supported;
897 }
898
899 return cti_port_setup_common(priv, pcidev, idx, offset, port);
900}
901
902static void cti_board_init_xr17v35x(struct exar8250 *priv, struct pci_dev *pcidev)
903{
904 // XR17V35X uses the PCIe clock rather than an oscillator
905 priv->osc_freq = CTI_DEFAULT_PCIE_OSC_FREQ;
906}
907
908static int cti_port_setup_xr17v35x(struct exar8250 *priv,
909 struct pci_dev *pcidev,
910 struct uart_8250_port *port,
911 int idx)
912{
913 enum cti_port_type port_type;
914 unsigned int offset;
915 int ret;
916
917 if (idx == 0)
918 cti_board_init_xr17v35x(priv, pcidev);
919
920 port_type = cti_get_port_type_xr17v35x(priv, pcidev, port_num: idx);
921
922 offset = idx * UART_EXAR_XR17V35X_PORT_OFFSET;
923 port->port.type = PORT_XR17V35X;
924
925 port->port.get_divisor = xr17v35x_get_divisor;
926 port->port.set_divisor = xr17v35x_set_divisor;
927 port->port.startup = xr17v35x_startup;
928
929 switch (port_type) {
930 case CTI_PORT_TYPE_RS422_485:
931 case CTI_PORT_TYPE_RS232_422_485_HW:
932 port->port.rs485_config = cti_rs485_config_mpio_tristate;
933 port->port.rs485_supported = generic_rs485_supported;
934 break;
935 case CTI_PORT_TYPE_RS232_422_485_SW:
936 case CTI_PORT_TYPE_RS232_422_485_4B:
937 case CTI_PORT_TYPE_RS232_422_485_2B:
938 port->port.rs485_config = generic_rs485_config;
939 port->port.rs485_supported = generic_rs485_supported;
940 break;
941 default:
942 break;
943 }
944
945 ret = cti_port_setup_common(priv, pcidev, idx, offset, port);
946 if (ret)
947 return ret;
948
949 exar_write_reg(priv, reg: (offset + UART_EXAR_8XMODE), value: 0x00);
950 exar_write_reg(priv, reg: (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD);
951 exar_write_reg(priv, reg: (offset + UART_EXAR_TXTRG), value: 128);
952 exar_write_reg(priv, reg: (offset + UART_EXAR_RXTRG), value: 128);
953
954 return 0;
955}
956
957static void cti_board_init_xr17v25x(struct exar8250 *priv, struct pci_dev *pcidev)
958{
959 cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17V25X_OSC_FREQ);
960
961 /* enable interrupts on cards that need the "PLX fix" */
962 switch (pcidev->subsystem_device) {
963 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS:
964 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A:
965 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B:
966 cti_plx_int_enable(priv);
967 break;
968 default:
969 break;
970 }
971}
972
973static int cti_port_setup_xr17v25x(struct exar8250 *priv,
974 struct pci_dev *pcidev,
975 struct uart_8250_port *port,
976 int idx)
977{
978 enum cti_port_type port_type;
979 unsigned int offset;
980 int ret;
981
982 if (idx == 0)
983 cti_board_init_xr17v25x(priv, pcidev);
984
985 port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, port_num: idx);
986
987 offset = idx * UART_EXAR_XR17V25X_PORT_OFFSET;
988 port->port.type = PORT_XR17D15X;
989
990 // XR17V25X supports fractional baudrates
991 port->port.get_divisor = xr17v35x_get_divisor;
992 port->port.set_divisor = xr17v35x_set_divisor;
993 port->port.startup = xr17v35x_startup;
994
995 if (CTI_PORT_TYPE_RS485(port_type)) {
996 switch (pcidev->subsystem_device) {
997 // These cards support power on 485 tri-state via MPIO
998 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP:
999 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485:
1000 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP:
1001 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP:
1002 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP:
1003 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT:
1004 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT:
1005 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO:
1006 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO:
1007 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP:
1008 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485:
1009 port->port.rs485_config = cti_rs485_config_mpio_tristate;
1010 break;
1011 // Otherwise auto or no power on 485 tri-state support
1012 default:
1013 port->port.rs485_config = generic_rs485_config;
1014 break;
1015 }
1016
1017 port->port.rs485_supported = generic_rs485_supported;
1018 }
1019
1020 ret = cti_port_setup_common(priv, pcidev, idx, offset, port);
1021 if (ret)
1022 return ret;
1023
1024 exar_write_reg(priv, reg: (offset + UART_EXAR_8XMODE), value: 0x00);
1025 exar_write_reg(priv, reg: (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD);
1026 exar_write_reg(priv, reg: (offset + UART_EXAR_TXTRG), value: 32);
1027 exar_write_reg(priv, reg: (offset + UART_EXAR_RXTRG), value: 32);
1028
1029 return 0;
1030}
1031
1032static void cti_board_init_xr17c15x(struct exar8250 *priv, struct pci_dev *pcidev)
1033{
1034 cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17C15X_OSC_FREQ);
1035
1036 /* enable interrupts on cards that need the "PLX fix" */
1037 switch (pcidev->subsystem_device) {
1038 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS:
1039 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A:
1040 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B:
1041 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO:
1042 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A:
1043 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B:
1044 cti_plx_int_enable(priv);
1045 break;
1046 default:
1047 break;
1048 }
1049}
1050
1051static int cti_port_setup_xr17c15x(struct exar8250 *priv,
1052 struct pci_dev *pcidev,
1053 struct uart_8250_port *port,
1054 int idx)
1055{
1056 enum cti_port_type port_type;
1057 unsigned int offset;
1058
1059 if (idx == 0)
1060 cti_board_init_xr17c15x(priv, pcidev);
1061
1062 port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, port_num: idx);
1063
1064 offset = idx * UART_EXAR_XR17C15X_PORT_OFFSET;
1065 port->port.type = PORT_XR17D15X;
1066
1067 if (CTI_PORT_TYPE_RS485(port_type)) {
1068 switch (pcidev->subsystem_device) {
1069 // These cards support power on 485 tri-state via MPIO
1070 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP:
1071 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485:
1072 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP:
1073 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP:
1074 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP:
1075 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT:
1076 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT:
1077 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO:
1078 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO:
1079 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP:
1080 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485:
1081 port->port.rs485_config = cti_rs485_config_mpio_tristate;
1082 break;
1083 // Otherwise auto or no power on 485 tri-state support
1084 default:
1085 port->port.rs485_config = generic_rs485_config;
1086 break;
1087 }
1088
1089 port->port.rs485_supported = generic_rs485_supported;
1090 }
1091
1092 return cti_port_setup_common(priv, pcidev, idx, offset, port);
1093}
1094
1095static int
1096pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
1097 struct uart_8250_port *port, int idx)
1098{
1099 unsigned int offset = idx * 0x200;
1100 unsigned int baud = 921600;
1101
1102 port->port.uartclk = baud * 16;
1103 return default_setup(priv, pcidev, idx, offset, port);
1104}
1105
1106static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
1107{
1108 /*
1109 * The Commtech adapters required the MPIOs to be driven low. The Exar
1110 * devices will export them as GPIOs, so we pre-configure them safely
1111 * as inputs.
1112 */
1113 u8 dir = 0x00;
1114
1115 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
1116 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
1117 // Configure GPIO as inputs for Commtech adapters
1118 dir = 0xff;
1119 } else {
1120 // Configure GPIO as outputs for SeaLevel adapters
1121 dir = 0x00;
1122 }
1123
1124 writeb(val: 0x00, addr: p + UART_EXAR_MPIOINT_7_0);
1125 writeb(val: 0x00, addr: p + UART_EXAR_MPIOLVL_7_0);
1126 writeb(val: 0x00, addr: p + UART_EXAR_MPIO3T_7_0);
1127 writeb(val: 0x00, addr: p + UART_EXAR_MPIOINV_7_0);
1128 writeb(val: dir, addr: p + UART_EXAR_MPIOSEL_7_0);
1129 writeb(val: 0x00, addr: p + UART_EXAR_MPIOOD_7_0);
1130 writeb(val: 0x00, addr: p + UART_EXAR_MPIOINT_15_8);
1131 writeb(val: 0x00, addr: p + UART_EXAR_MPIOLVL_15_8);
1132 writeb(val: 0x00, addr: p + UART_EXAR_MPIO3T_15_8);
1133 writeb(val: 0x00, addr: p + UART_EXAR_MPIOINV_15_8);
1134 writeb(val: dir, addr: p + UART_EXAR_MPIOSEL_15_8);
1135 writeb(val: 0x00, addr: p + UART_EXAR_MPIOOD_15_8);
1136}
1137
1138static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev,
1139 const struct software_node *node)
1140{
1141 struct platform_device *pdev;
1142
1143 pdev = platform_device_alloc(name: "gpio_exar", PLATFORM_DEVID_AUTO);
1144 if (!pdev)
1145 return NULL;
1146
1147 pdev->dev.parent = &pcidev->dev;
1148 device_set_node(dev: &pdev->dev, dev_fwnode(&pcidev->dev));
1149
1150 if (device_add_software_node(dev: &pdev->dev, node) < 0 ||
1151 platform_device_add(pdev) < 0) {
1152 platform_device_put(pdev);
1153 return NULL;
1154 }
1155
1156 return pdev;
1157}
1158
1159static void __xr17v35x_unregister_gpio(struct platform_device *pdev)
1160{
1161 device_remove_software_node(dev: &pdev->dev);
1162 platform_device_unregister(pdev);
1163}
1164
1165static const struct property_entry exar_gpio_properties[] = {
1166 PROPERTY_ENTRY_U32("exar,first-pin", 0),
1167 PROPERTY_ENTRY_U32("ngpios", 16),
1168 { }
1169};
1170
1171static const struct software_node exar_gpio_node = {
1172 .properties = exar_gpio_properties,
1173};
1174
1175static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port)
1176{
1177 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
1178 port->port.private_data =
1179 __xr17v35x_register_gpio(pcidev, node: &exar_gpio_node);
1180
1181 return 0;
1182}
1183
1184static void xr17v35x_unregister_gpio(struct uart_8250_port *port)
1185{
1186 if (!port->port.private_data)
1187 return;
1188
1189 __xr17v35x_unregister_gpio(pdev: port->port.private_data);
1190 port->port.private_data = NULL;
1191}
1192
1193static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termios,
1194 struct serial_rs485 *rs485)
1195{
1196 u8 __iomem *p = port->membase;
1197 u8 old_lcr;
1198 u8 efr;
1199 u8 dld;
1200 int ret;
1201
1202 ret = generic_rs485_config(port, termios, rs485);
1203 if (ret)
1204 return ret;
1205
1206 if (!(rs485->flags & SER_RS485_ENABLED))
1207 return 0;
1208
1209 old_lcr = readb(addr: p + UART_LCR);
1210
1211 /* Set EFR[4]=1 to enable enhanced feature registers */
1212 efr = readb(addr: p + UART_XR_EFR);
1213 efr |= UART_EFR_ECB;
1214 writeb(val: efr, addr: p + UART_XR_EFR);
1215
1216 /* Set MCR to use DTR as Auto-RS485 Enable signal */
1217 writeb(UART_MCR_OUT1, addr: p + UART_MCR);
1218
1219 /* Set LCR[7]=1 to enable access to DLD register */
1220 writeb(val: old_lcr | UART_LCR_DLAB, addr: p + UART_LCR);
1221
1222 /* Set DLD[7]=1 for inverted RS485 Enable logic */
1223 dld = readb(addr: p + UART_EXAR_DLD);
1224 dld |= UART_EXAR_DLD_485_POLARITY;
1225 writeb(val: dld, addr: p + UART_EXAR_DLD);
1226
1227 writeb(val: old_lcr, addr: p + UART_LCR);
1228
1229 return 0;
1230}
1231
1232static const struct exar8250_platform exar8250_default_platform = {
1233 .register_gpio = xr17v35x_register_gpio,
1234 .unregister_gpio = xr17v35x_unregister_gpio,
1235 .rs485_config = generic_rs485_config,
1236 .rs485_supported = &generic_rs485_supported,
1237};
1238
1239static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios,
1240 struct serial_rs485 *rs485)
1241{
1242 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
1243 u8 __iomem *p = port->membase;
1244 u8 mask = IOT2040_UART1_MASK;
1245 u8 mode, value;
1246
1247 if (is_rs485) {
1248 if (rs485->flags & SER_RS485_RX_DURING_TX)
1249 mode = IOT2040_UART_MODE_RS422;
1250 else
1251 mode = IOT2040_UART_MODE_RS485;
1252
1253 if (rs485->flags & SER_RS485_TERMINATE_BUS)
1254 mode |= IOT2040_UART_TERMINATE_BUS;
1255 } else {
1256 mode = IOT2040_UART_MODE_RS232;
1257 }
1258
1259 if (port->line == 3) {
1260 mask <<= IOT2040_UART2_SHIFT;
1261 mode <<= IOT2040_UART2_SHIFT;
1262 }
1263
1264 value = readb(addr: p + UART_EXAR_MPIOLVL_7_0);
1265 value &= ~mask;
1266 value |= mode;
1267 writeb(val: value, addr: p + UART_EXAR_MPIOLVL_7_0);
1268
1269 return generic_rs485_config(port, termios, rs485);
1270}
1271
1272static const struct serial_rs485 iot2040_rs485_supported = {
1273 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
1274 SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS,
1275};
1276
1277static const struct property_entry iot2040_gpio_properties[] = {
1278 PROPERTY_ENTRY_U32("exar,first-pin", 10),
1279 PROPERTY_ENTRY_U32("ngpios", 1),
1280 { }
1281};
1282
1283static const struct software_node iot2040_gpio_node = {
1284 .properties = iot2040_gpio_properties,
1285};
1286
1287static int iot2040_register_gpio(struct pci_dev *pcidev,
1288 struct uart_8250_port *port)
1289{
1290 u8 __iomem *p = port->port.membase;
1291
1292 writeb(IOT2040_UARTS_DEFAULT_MODE, addr: p + UART_EXAR_MPIOLVL_7_0);
1293 writeb(IOT2040_UARTS_GPIO_LO_MODE, addr: p + UART_EXAR_MPIOSEL_7_0);
1294 writeb(IOT2040_UARTS_ENABLE, addr: p + UART_EXAR_MPIOLVL_15_8);
1295 writeb(IOT2040_UARTS_GPIO_HI_MODE, addr: p + UART_EXAR_MPIOSEL_15_8);
1296
1297 port->port.private_data =
1298 __xr17v35x_register_gpio(pcidev, node: &iot2040_gpio_node);
1299
1300 return 0;
1301}
1302
1303static const struct exar8250_platform iot2040_platform = {
1304 .rs485_config = iot2040_rs485_config,
1305 .rs485_supported = &iot2040_rs485_supported,
1306 .register_gpio = iot2040_register_gpio,
1307 .unregister_gpio = xr17v35x_unregister_gpio,
1308};
1309
1310/*
1311 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
1312 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
1313 * board name after the device was found.
1314 */
1315static const struct dmi_system_id exar_platforms[] = {
1316 {
1317 .matches = {
1318 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
1319 },
1320 .driver_data = (void *)&iot2040_platform,
1321 },
1322 {}
1323};
1324
1325static const struct exar8250_platform *exar_get_platform(void)
1326{
1327 const struct dmi_system_id *dmi_match;
1328
1329 dmi_match = dmi_first_match(list: exar_platforms);
1330 if (dmi_match)
1331 return dmi_match->driver_data;
1332
1333 return &exar8250_default_platform;
1334}
1335
1336static int
1337pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
1338 struct uart_8250_port *port, int idx)
1339{
1340 const struct exar8250_platform *platform = exar_get_platform();
1341 unsigned int offset = idx * 0x400;
1342 unsigned int baud = 7812500;
1343 u8 __iomem *p;
1344 int ret;
1345
1346 port->port.uartclk = baud * 16;
1347 port->port.rs485_config = platform->rs485_config;
1348 port->port.rs485_supported = *(platform->rs485_supported);
1349
1350 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_SEALEVEL)
1351 port->port.rs485_config = sealevel_rs485_config;
1352
1353 /*
1354 * Setup the UART clock for the devices on expansion slot to
1355 * half the clock speed of the main chip (which is 125MHz)
1356 */
1357 if (idx >= 8)
1358 port->port.uartclk /= 2;
1359
1360 ret = default_setup(priv, pcidev, idx, offset, port);
1361 if (ret)
1362 return ret;
1363
1364 p = port->port.membase;
1365
1366 writeb(val: 0x00, addr: p + UART_EXAR_8XMODE);
1367 writeb(UART_FCTR_EXAR_TRGD, addr: p + UART_EXAR_FCTR);
1368 writeb(val: 128, addr: p + UART_EXAR_TXTRG);
1369 writeb(val: 128, addr: p + UART_EXAR_RXTRG);
1370
1371 if (idx == 0) {
1372 /* Setup Multipurpose Input/Output pins. */
1373 setup_gpio(pcidev, p);
1374
1375 ret = platform->register_gpio(pcidev, port);
1376 }
1377
1378 return ret;
1379}
1380
1381static void pci_xr17v35x_exit(struct pci_dev *pcidev)
1382{
1383 const struct exar8250_platform *platform = exar_get_platform();
1384 struct exar8250 *priv = pci_get_drvdata(pdev: pcidev);
1385 struct uart_8250_port *port = serial8250_get_port(line: priv->line[0]);
1386
1387 platform->unregister_gpio(port);
1388}
1389
1390static inline void exar_misc_clear(struct exar8250 *priv)
1391{
1392 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
1393 readb(addr: priv->virt + UART_EXAR_INT0);
1394
1395 /* Clear INT0 for Expansion Interface slave ports, too */
1396 if (priv->board->num_ports > 8)
1397 readb(addr: priv->virt + 0x2000 + UART_EXAR_INT0);
1398}
1399
1400/*
1401 * These Exar UARTs have an extra interrupt indicator that could fire for a
1402 * few interrupts that are not presented/cleared through IIR. One of which is
1403 * a wakeup interrupt when coming out of sleep. These interrupts are only
1404 * cleared by reading global INT0 or INT1 registers as interrupts are
1405 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
1406 * channel's address space, but for the sake of bus efficiency we register a
1407 * dedicated handler at the PCI device level to handle them.
1408 */
1409static irqreturn_t exar_misc_handler(int irq, void *data)
1410{
1411 exar_misc_clear(priv: data);
1412
1413 return IRQ_HANDLED;
1414}
1415
1416static unsigned int exar_get_nr_ports(struct exar8250_board *board, struct pci_dev *pcidev)
1417{
1418 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
1419 return BIT(((pcidev->device & 0x38) >> 3) - 1);
1420
1421 // Check if board struct overrides number of ports
1422 if (board->num_ports > 0)
1423 return board->num_ports;
1424
1425 // Exar encodes # ports in last nibble of PCI Device ID ex. 0358
1426 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
1427 return pcidev->device & 0x0f;
1428
1429 // Handle CTI FPGA cards
1430 if (pcidev->vendor == PCI_VENDOR_ID_CONNECT_TECH) {
1431 switch (pcidev->device) {
1432 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X:
1433 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X:
1434 return 12;
1435 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16:
1436 return 16;
1437 default:
1438 return 0;
1439 }
1440 }
1441
1442 return 0;
1443}
1444
1445static int
1446exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
1447{
1448 unsigned int nr_ports, i, bar = 0, maxnr;
1449 struct exar8250_board *board;
1450 struct uart_8250_port uart;
1451 struct exar8250 *priv;
1452 int rc;
1453
1454 board = (struct exar8250_board *)ent->driver_data;
1455 if (!board)
1456 return -EINVAL;
1457
1458 rc = pcim_enable_device(pdev: pcidev);
1459 if (rc)
1460 return rc;
1461
1462 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
1463
1464 nr_ports = exar_get_nr_ports(board, pcidev);
1465 if (nr_ports == 0)
1466 return dev_err_probe(dev: &pcidev->dev, err: -ENODEV, fmt: "failed to get number of ports\n");
1467
1468 priv = devm_kzalloc(dev: &pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
1469 if (!priv)
1470 return -ENOMEM;
1471
1472 priv->board = board;
1473 priv->virt = pcim_iomap(pdev: pcidev, bar, maxlen: 0);
1474 if (!priv->virt)
1475 return -ENOMEM;
1476
1477 pci_set_master(dev: pcidev);
1478
1479 rc = pci_alloc_irq_vectors(dev: pcidev, min_vecs: 1, max_vecs: 1, PCI_IRQ_ALL_TYPES);
1480 if (rc < 0)
1481 return rc;
1482
1483 memset(s: &uart, c: 0, n: sizeof(uart));
1484 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
1485 uart.port.irq = pci_irq_vector(dev: pcidev, nr: 0);
1486 uart.port.dev = &pcidev->dev;
1487
1488 /* Clear interrupts */
1489 exar_misc_clear(priv);
1490
1491 rc = devm_request_irq(dev: &pcidev->dev, irq: uart.port.irq, handler: exar_misc_handler,
1492 IRQF_SHARED, devname: "exar_uart", dev_id: priv);
1493 if (rc)
1494 return rc;
1495
1496 exar_eeprom_init(priv);
1497
1498 for (i = 0; i < nr_ports && i < maxnr; i++) {
1499 rc = board->setup(priv, pcidev, &uart, i);
1500 if (rc) {
1501 dev_err_probe(dev: &pcidev->dev, err: rc, fmt: "Failed to setup port %u\n", i);
1502 break;
1503 }
1504
1505 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
1506 uart.port.iobase, uart.port.irq, uart.port.iotype);
1507
1508 priv->line[i] = serial8250_register_8250_port(&uart);
1509 if (priv->line[i] < 0) {
1510 dev_err_probe(dev: &pcidev->dev, err: priv->line[i],
1511 fmt: "Couldn't register serial port %lx, type %d, irq %d\n",
1512 uart.port.iobase, uart.port.iotype, uart.port.irq);
1513 break;
1514 }
1515 }
1516 priv->nr = i;
1517 pci_set_drvdata(pdev: pcidev, data: priv);
1518 return 0;
1519}
1520
1521static void exar_pci_remove(struct pci_dev *pcidev)
1522{
1523 struct exar8250 *priv = pci_get_drvdata(pdev: pcidev);
1524 unsigned int i;
1525
1526 for (i = 0; i < priv->nr; i++)
1527 serial8250_unregister_port(line: priv->line[i]);
1528
1529 /* Ensure that every init quirk is properly torn down */
1530 if (priv->board->exit)
1531 priv->board->exit(pcidev);
1532}
1533
1534static int exar_suspend(struct device *dev)
1535{
1536 struct exar8250 *priv = dev_get_drvdata(dev);
1537 unsigned int i;
1538
1539 for (i = 0; i < priv->nr; i++)
1540 if (priv->line[i] >= 0)
1541 serial8250_suspend_port(line: priv->line[i]);
1542
1543 return 0;
1544}
1545
1546static int exar_resume(struct device *dev)
1547{
1548 struct exar8250 *priv = dev_get_drvdata(dev);
1549 unsigned int i;
1550
1551 exar_misc_clear(priv);
1552
1553 for (i = 0; i < priv->nr; i++)
1554 if (priv->line[i] >= 0)
1555 serial8250_resume_port(line: priv->line[i]);
1556
1557 return 0;
1558}
1559
1560static DEFINE_SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
1561
1562static const struct exar8250_board pbn_fastcom335_2 = {
1563 .num_ports = 2,
1564 .setup = pci_fastcom335_setup,
1565};
1566
1567static const struct exar8250_board pbn_fastcom335_4 = {
1568 .num_ports = 4,
1569 .setup = pci_fastcom335_setup,
1570};
1571
1572static const struct exar8250_board pbn_fastcom335_8 = {
1573 .num_ports = 8,
1574 .setup = pci_fastcom335_setup,
1575};
1576
1577static const struct exar8250_board pbn_cti_xr17c15x = {
1578 .setup = cti_port_setup_xr17c15x,
1579};
1580
1581static const struct exar8250_board pbn_cti_xr17v25x = {
1582 .setup = cti_port_setup_xr17v25x,
1583};
1584
1585static const struct exar8250_board pbn_cti_xr17v35x = {
1586 .setup = cti_port_setup_xr17v35x,
1587};
1588
1589static const struct exar8250_board pbn_cti_fpga = {
1590 .setup = cti_port_setup_fpga,
1591};
1592
1593static const struct exar8250_board pbn_exar_ibm_saturn = {
1594 .num_ports = 1,
1595 .setup = pci_xr17c154_setup,
1596};
1597
1598static const struct exar8250_board pbn_exar_XR17C15x = {
1599 .setup = pci_xr17c154_setup,
1600};
1601
1602static const struct exar8250_board pbn_exar_XR17V35x = {
1603 .setup = pci_xr17v35x_setup,
1604 .exit = pci_xr17v35x_exit,
1605};
1606
1607static const struct exar8250_board pbn_fastcom35x_2 = {
1608 .num_ports = 2,
1609 .setup = pci_xr17v35x_setup,
1610 .exit = pci_xr17v35x_exit,
1611};
1612
1613static const struct exar8250_board pbn_fastcom35x_4 = {
1614 .num_ports = 4,
1615 .setup = pci_xr17v35x_setup,
1616 .exit = pci_xr17v35x_exit,
1617};
1618
1619static const struct exar8250_board pbn_fastcom35x_8 = {
1620 .num_ports = 8,
1621 .setup = pci_xr17v35x_setup,
1622 .exit = pci_xr17v35x_exit,
1623};
1624
1625static const struct exar8250_board pbn_exar_XR17V4358 = {
1626 .num_ports = 12,
1627 .setup = pci_xr17v35x_setup,
1628 .exit = pci_xr17v35x_exit,
1629};
1630
1631static const struct exar8250_board pbn_exar_XR17V8358 = {
1632 .num_ports = 16,
1633 .setup = pci_xr17v35x_setup,
1634 .exit = pci_xr17v35x_exit,
1635};
1636
1637#define CTI_EXAR_DEVICE(devid, bd) { \
1638 PCI_DEVICE_SUB( \
1639 PCI_VENDOR_ID_EXAR, \
1640 PCI_DEVICE_ID_EXAR_##devid, \
1641 PCI_SUBVENDOR_ID_CONNECT_TECH, \
1642 PCI_ANY_ID), 0, 0, \
1643 (kernel_ulong_t)&bd \
1644 }
1645
1646#define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
1647
1648#define IBM_DEVICE(devid, sdevid, bd) { \
1649 PCI_DEVICE_SUB( \
1650 PCI_VENDOR_ID_EXAR, \
1651 PCI_DEVICE_ID_EXAR_##devid, \
1652 PCI_SUBVENDOR_ID_IBM, \
1653 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
1654 (kernel_ulong_t)&bd \
1655 }
1656
1657#define USR_DEVICE(devid, sdevid, bd) { \
1658 PCI_DEVICE_SUB( \
1659 PCI_VENDOR_ID_USR, \
1660 PCI_DEVICE_ID_EXAR_##devid, \
1661 PCI_VENDOR_ID_EXAR, \
1662 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \
1663 (kernel_ulong_t)&bd \
1664 }
1665
1666static const struct pci_device_id exar_pci_tbl[] = {
1667 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
1668 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
1669 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
1670 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
1671 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
1672 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
1673 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
1674
1675 /* Connect Tech cards with Exar vendor/device PCI IDs */
1676 CTI_EXAR_DEVICE(XR17C152, pbn_cti_xr17c15x),
1677 CTI_EXAR_DEVICE(XR17C154, pbn_cti_xr17c15x),
1678 CTI_EXAR_DEVICE(XR17C158, pbn_cti_xr17c15x),
1679
1680 CTI_EXAR_DEVICE(XR17V252, pbn_cti_xr17v25x),
1681 CTI_EXAR_DEVICE(XR17V254, pbn_cti_xr17v25x),
1682 CTI_EXAR_DEVICE(XR17V258, pbn_cti_xr17v25x),
1683
1684 CTI_EXAR_DEVICE(XR17V352, pbn_cti_xr17v35x),
1685 CTI_EXAR_DEVICE(XR17V354, pbn_cti_xr17v35x),
1686 CTI_EXAR_DEVICE(XR17V358, pbn_cti_xr17v35x),
1687
1688 /* Connect Tech cards with Connect Tech vendor/device PCI IDs (FPGA based) */
1689 EXAR_DEVICE(CONNECT_TECH, PCI_XR79X_12_XIG00X, pbn_cti_fpga),
1690 EXAR_DEVICE(CONNECT_TECH, PCI_XR79X_12_XIG01X, pbn_cti_fpga),
1691 EXAR_DEVICE(CONNECT_TECH, PCI_XR79X_16, pbn_cti_fpga),
1692
1693 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
1694
1695 /* USRobotics USR298x-OEM PCI Modems */
1696 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x),
1697 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x),
1698
1699 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
1700 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
1701 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
1702 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
1703
1704 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
1705 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
1706 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
1707 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
1708 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
1709 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
1710 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
1711 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
1712 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
1713
1714 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
1715 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
1716 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
1717 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
1718 { 0, }
1719};
1720MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
1721
1722static struct pci_driver exar_pci_driver = {
1723 .name = "exar_serial",
1724 .probe = exar_pci_probe,
1725 .remove = exar_pci_remove,
1726 .driver = {
1727 .pm = pm_sleep_ptr(&exar_pci_pm),
1728 },
1729 .id_table = exar_pci_tbl,
1730};
1731module_pci_driver(exar_pci_driver);
1732
1733MODULE_IMPORT_NS("SERIAL_8250_PCI");
1734MODULE_LICENSE("GPL");
1735MODULE_DESCRIPTION("Exar Serial Driver");
1736MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
1737