1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Base port operations for 8250/16550-type serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 *
8 * A note about mapbase / membase
9 *
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/irq.h>
19#include <linux/console.h>
20#include <linux/gpio/consumer.h>
21#include <linux/sysrq.h>
22#include <linux/delay.h>
23#include <linux/platform_device.h>
24#include <linux/tty.h>
25#include <linux/ratelimit.h>
26#include <linux/tty_flip.h>
27#include <linux/serial.h>
28#include <linux/serial_8250.h>
29#include <linux/nmi.h>
30#include <linux/mutex.h>
31#include <linux/slab.h>
32#include <linux/uaccess.h>
33#include <linux/pm_runtime.h>
34#include <linux/ktime.h>
35
36#include <asm/io.h>
37#include <asm/irq.h>
38
39#include "8250.h"
40
41/*
42 * Here we define the default xmit fifo size used for each type of UART.
43 */
44static const struct serial8250_config uart_config[] = {
45 [PORT_UNKNOWN] = {
46 .name = "unknown",
47 .fifo_size = 1,
48 .tx_loadsz = 1,
49 },
50 [PORT_8250] = {
51 .name = "8250",
52 .fifo_size = 1,
53 .tx_loadsz = 1,
54 },
55 [PORT_16450] = {
56 .name = "16450",
57 .fifo_size = 1,
58 .tx_loadsz = 1,
59 },
60 [PORT_16550] = {
61 .name = "16550",
62 .fifo_size = 1,
63 .tx_loadsz = 1,
64 },
65 [PORT_16550A] = {
66 .name = "16550A",
67 .fifo_size = 16,
68 .tx_loadsz = 16,
69 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
70 .rxtrig_bytes = {1, 4, 8, 14},
71 .flags = UART_CAP_FIFO,
72 },
73 [PORT_CIRRUS] = {
74 .name = "Cirrus",
75 .fifo_size = 1,
76 .tx_loadsz = 1,
77 },
78 [PORT_16650] = {
79 .name = "ST16650",
80 .fifo_size = 1,
81 .tx_loadsz = 1,
82 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
83 },
84 [PORT_16650V2] = {
85 .name = "ST16650V2",
86 .fifo_size = 32,
87 .tx_loadsz = 16,
88 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
89 UART_FCR_T_TRIG_00,
90 .rxtrig_bytes = {8, 16, 24, 28},
91 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
92 },
93 [PORT_16750] = {
94 .name = "TI16750",
95 .fifo_size = 64,
96 .tx_loadsz = 64,
97 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
98 UART_FCR7_64BYTE,
99 .rxtrig_bytes = {1, 16, 32, 56},
100 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
101 },
102 [PORT_STARTECH] = {
103 .name = "Startech",
104 .fifo_size = 1,
105 .tx_loadsz = 1,
106 },
107 [PORT_16C950] = {
108 .name = "16C950/954",
109 .fifo_size = 128,
110 .tx_loadsz = 128,
111 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
112 .rxtrig_bytes = {16, 32, 112, 120},
113 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
114 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
115 },
116 [PORT_16654] = {
117 .name = "ST16654",
118 .fifo_size = 64,
119 .tx_loadsz = 32,
120 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
121 UART_FCR_T_TRIG_10,
122 .rxtrig_bytes = {8, 16, 56, 60},
123 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
124 },
125 [PORT_16850] = {
126 .name = "XR16850",
127 .fifo_size = 128,
128 .tx_loadsz = 128,
129 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
130 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
131 },
132 [PORT_RSA] = {
133 .name = "RSA",
134 .fifo_size = 2048,
135 .tx_loadsz = 2048,
136 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
137 .flags = UART_CAP_FIFO,
138 },
139 [PORT_NS16550A] = {
140 .name = "NS16550A",
141 .fifo_size = 16,
142 .tx_loadsz = 16,
143 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
144 .flags = UART_CAP_FIFO | UART_NATSEMI,
145 },
146 [PORT_XSCALE] = {
147 .name = "XScale",
148 .fifo_size = 32,
149 .tx_loadsz = 32,
150 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
151 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
152 },
153 [PORT_OCTEON] = {
154 .name = "OCTEON",
155 .fifo_size = 64,
156 .tx_loadsz = 64,
157 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
158 .flags = UART_CAP_FIFO,
159 },
160 [PORT_U6_16550A] = {
161 .name = "U6_16550A",
162 .fifo_size = 64,
163 .tx_loadsz = 64,
164 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
165 .flags = UART_CAP_FIFO | UART_CAP_AFE,
166 },
167 [PORT_TEGRA] = {
168 .name = "Tegra",
169 .fifo_size = 32,
170 .tx_loadsz = 8,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
172 UART_FCR_T_TRIG_01,
173 .rxtrig_bytes = {1, 4, 8, 14},
174 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
175 },
176 [PORT_XR17D15X] = {
177 .name = "XR17D15X",
178 .fifo_size = 64,
179 .tx_loadsz = 64,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
181 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
182 UART_CAP_SLEEP,
183 },
184 [PORT_XR17V35X] = {
185 .name = "XR17V35X",
186 .fifo_size = 256,
187 .tx_loadsz = 256,
188 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
189 UART_FCR_T_TRIG_11,
190 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
191 UART_CAP_SLEEP,
192 },
193 [PORT_LPC3220] = {
194 .name = "LPC3220",
195 .fifo_size = 64,
196 .tx_loadsz = 32,
197 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
198 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
199 .flags = UART_CAP_FIFO,
200 },
201 [PORT_BRCM_TRUMANAGE] = {
202 .name = "TruManage",
203 .fifo_size = 1,
204 .tx_loadsz = 1024,
205 .flags = UART_CAP_HFIFO,
206 },
207 [PORT_8250_CIR] = {
208 .name = "CIR port"
209 },
210 [PORT_ALTR_16550_F32] = {
211 .name = "Altera 16550 FIFO32",
212 .fifo_size = 32,
213 .tx_loadsz = 32,
214 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
215 .rxtrig_bytes = {1, 8, 16, 30},
216 .flags = UART_CAP_FIFO | UART_CAP_AFE,
217 },
218 [PORT_ALTR_16550_F64] = {
219 .name = "Altera 16550 FIFO64",
220 .fifo_size = 64,
221 .tx_loadsz = 64,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
223 .rxtrig_bytes = {1, 16, 32, 62},
224 .flags = UART_CAP_FIFO | UART_CAP_AFE,
225 },
226 [PORT_ALTR_16550_F128] = {
227 .name = "Altera 16550 FIFO128",
228 .fifo_size = 128,
229 .tx_loadsz = 128,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
231 .rxtrig_bytes = {1, 32, 64, 126},
232 .flags = UART_CAP_FIFO | UART_CAP_AFE,
233 },
234 /*
235 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
236 * workaround of errata A-008006 which states that tx_loadsz should
237 * be configured less than Maximum supported fifo bytes.
238 */
239 [PORT_16550A_FSL64] = {
240 .name = "16550A_FSL64",
241 .fifo_size = 64,
242 .tx_loadsz = 63,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
244 UART_FCR7_64BYTE,
245 .flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
246 },
247 [PORT_RT2880] = {
248 .name = "Palmchip BK-3103",
249 .fifo_size = 16,
250 .tx_loadsz = 16,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .rxtrig_bytes = {1, 4, 8, 14},
253 .flags = UART_CAP_FIFO,
254 },
255 [PORT_DA830] = {
256 .name = "TI DA8xx/66AK2x",
257 .fifo_size = 16,
258 .tx_loadsz = 16,
259 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
260 UART_FCR_R_TRIG_10,
261 .rxtrig_bytes = {1, 4, 8, 14},
262 .flags = UART_CAP_FIFO | UART_CAP_AFE,
263 },
264 [PORT_MTK_BTIF] = {
265 .name = "MediaTek BTIF",
266 .fifo_size = 16,
267 .tx_loadsz = 16,
268 .fcr = UART_FCR_ENABLE_FIFO |
269 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
270 .flags = UART_CAP_FIFO,
271 },
272 [PORT_NPCM] = {
273 .name = "Nuvoton 16550",
274 .fifo_size = 16,
275 .tx_loadsz = 16,
276 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
277 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
278 .rxtrig_bytes = {1, 4, 8, 14},
279 .flags = UART_CAP_FIFO,
280 },
281 [PORT_SUNIX] = {
282 .name = "Sunix",
283 .fifo_size = 128,
284 .tx_loadsz = 128,
285 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
286 .rxtrig_bytes = {1, 32, 64, 112},
287 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
288 },
289 [PORT_ASPEED_VUART] = {
290 .name = "ASPEED VUART",
291 .fifo_size = 16,
292 .tx_loadsz = 16,
293 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
294 .rxtrig_bytes = {1, 4, 8, 14},
295 .flags = UART_CAP_FIFO,
296 },
297 [PORT_MCHP16550A] = {
298 .name = "MCHP16550A",
299 .fifo_size = 256,
300 .tx_loadsz = 256,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
302 .rxtrig_bytes = {2, 66, 130, 194},
303 .flags = UART_CAP_FIFO,
304 },
305 [PORT_BCM7271] = {
306 .name = "Broadcom BCM7271 UART",
307 .fifo_size = 32,
308 .tx_loadsz = 32,
309 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
310 .rxtrig_bytes = {1, 8, 16, 30},
311 .flags = UART_CAP_FIFO | UART_CAP_AFE,
312 },
313};
314
315/* Uart divisor latch read */
316static u32 default_serial_dl_read(struct uart_8250_port *up)
317{
318 /* Assign these in pieces to truncate any bits above 7. */
319 unsigned char dll = serial_in(up, UART_DLL);
320 unsigned char dlm = serial_in(up, UART_DLM);
321
322 return dll | dlm << 8;
323}
324
325/* Uart divisor latch write */
326static void default_serial_dl_write(struct uart_8250_port *up, u32 value)
327{
328 serial_out(up, UART_DLL, value: value & 0xff);
329 serial_out(up, UART_DLM, value: value >> 8 & 0xff);
330}
331
332#ifdef CONFIG_HAS_IOPORT
333static u32 hub6_serial_in(struct uart_port *p, unsigned int offset)
334{
335 offset = offset << p->regshift;
336 outb(value: p->hub6 - 1 + offset, port: p->iobase);
337 return inb(port: p->iobase + 1);
338}
339
340static void hub6_serial_out(struct uart_port *p, unsigned int offset, u32 value)
341{
342 offset = offset << p->regshift;
343 outb(value: p->hub6 - 1 + offset, port: p->iobase);
344 outb(value, port: p->iobase + 1);
345}
346#endif /* CONFIG_HAS_IOPORT */
347
348static u32 mem_serial_in(struct uart_port *p, unsigned int offset)
349{
350 offset = offset << p->regshift;
351 return readb(addr: p->membase + offset);
352}
353
354static void mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)
355{
356 offset = offset << p->regshift;
357 writeb(val: value, addr: p->membase + offset);
358}
359
360static void mem16_serial_out(struct uart_port *p, unsigned int offset, u32 value)
361{
362 offset = offset << p->regshift;
363 writew(val: value, addr: p->membase + offset);
364}
365
366static u32 mem16_serial_in(struct uart_port *p, unsigned int offset)
367{
368 offset = offset << p->regshift;
369 return readw(addr: p->membase + offset);
370}
371
372static void mem32_serial_out(struct uart_port *p, unsigned int offset, u32 value)
373{
374 offset = offset << p->regshift;
375 writel(val: value, addr: p->membase + offset);
376}
377
378static u32 mem32_serial_in(struct uart_port *p, unsigned int offset)
379{
380 offset = offset << p->regshift;
381 return readl(addr: p->membase + offset);
382}
383
384static void mem32be_serial_out(struct uart_port *p, unsigned int offset, u32 value)
385{
386 offset = offset << p->regshift;
387 iowrite32be(value, p->membase + offset);
388}
389
390static u32 mem32be_serial_in(struct uart_port *p, unsigned int offset)
391{
392 offset = offset << p->regshift;
393 return ioread32be(p->membase + offset);
394}
395
396#ifdef CONFIG_HAS_IOPORT
397static u32 io_serial_in(struct uart_port *p, unsigned int offset)
398{
399 offset = offset << p->regshift;
400 return inb(port: p->iobase + offset);
401}
402
403static void io_serial_out(struct uart_port *p, unsigned int offset, u32 value)
404{
405 offset = offset << p->regshift;
406 outb(value, port: p->iobase + offset);
407}
408#endif
409static u32 no_serial_in(struct uart_port *p, unsigned int offset)
410{
411 return ~0U;
412}
413
414static void no_serial_out(struct uart_port *p, unsigned int offset, u32 value)
415{
416}
417
418static int serial8250_default_handle_irq(struct uart_port *port);
419
420static void set_io_from_upio(struct uart_port *p)
421{
422 struct uart_8250_port *up = up_to_u8250p(up: p);
423
424 up->dl_read = default_serial_dl_read;
425 up->dl_write = default_serial_dl_write;
426
427 switch (p->iotype) {
428#ifdef CONFIG_HAS_IOPORT
429 case UPIO_HUB6:
430 p->serial_in = hub6_serial_in;
431 p->serial_out = hub6_serial_out;
432 break;
433#endif
434
435 case UPIO_MEM:
436 p->serial_in = mem_serial_in;
437 p->serial_out = mem_serial_out;
438 break;
439
440 case UPIO_MEM16:
441 p->serial_in = mem16_serial_in;
442 p->serial_out = mem16_serial_out;
443 break;
444
445 case UPIO_MEM32:
446 p->serial_in = mem32_serial_in;
447 p->serial_out = mem32_serial_out;
448 break;
449
450 case UPIO_MEM32BE:
451 p->serial_in = mem32be_serial_in;
452 p->serial_out = mem32be_serial_out;
453 break;
454#ifdef CONFIG_HAS_IOPORT
455 case UPIO_PORT:
456 p->serial_in = io_serial_in;
457 p->serial_out = io_serial_out;
458 break;
459#endif
460 default:
461 WARN(p->iotype != UPIO_PORT || p->iobase,
462 "Unsupported UART type %x\n", p->iotype);
463 p->serial_in = no_serial_in;
464 p->serial_out = no_serial_out;
465 }
466 /* Remember loaded iotype */
467 up->cur_iotype = p->iotype;
468 p->handle_irq = serial8250_default_handle_irq;
469}
470
471static void
472serial_port_out_sync(struct uart_port *p, int offset, int value)
473{
474 switch (p->iotype) {
475 case UPIO_MEM:
476 case UPIO_MEM16:
477 case UPIO_MEM32:
478 case UPIO_MEM32BE:
479 case UPIO_AU:
480 p->serial_out(p, offset, value);
481 p->serial_in(p, UART_LCR); /* safe, no side-effects */
482 break;
483 default:
484 p->serial_out(p, offset, value);
485 }
486}
487
488/*
489 * FIFO support.
490 */
491static void serial8250_clear_fifos(struct uart_8250_port *p)
492{
493 if (p->capabilities & UART_CAP_FIFO) {
494 serial_out(up: p, UART_FCR, UART_FCR_ENABLE_FIFO);
495 serial_out(up: p, UART_FCR, UART_FCR_ENABLE_FIFO |
496 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
497 serial_out(up: p, UART_FCR, value: 0);
498 }
499}
500
501static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
502static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
503
504void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
505{
506 serial8250_clear_fifos(p);
507 serial_out(up: p, UART_FCR, value: p->fcr);
508}
509EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
510
511void serial8250_rpm_get(struct uart_8250_port *p)
512{
513 if (!(p->capabilities & UART_CAP_RPM))
514 return;
515 pm_runtime_get_sync(dev: p->port.dev);
516}
517EXPORT_SYMBOL_GPL(serial8250_rpm_get);
518
519void serial8250_rpm_put(struct uart_8250_port *p)
520{
521 if (!(p->capabilities & UART_CAP_RPM))
522 return;
523 pm_runtime_mark_last_busy(dev: p->port.dev);
524 pm_runtime_put_autosuspend(dev: p->port.dev);
525}
526EXPORT_SYMBOL_GPL(serial8250_rpm_put);
527
528/**
529 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
530 * @p: uart_8250_port port instance
531 *
532 * The function is used to start rs485 software emulating on the
533 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
534 * transmission. The function is idempotent, so it is safe to call it
535 * multiple times.
536 *
537 * The caller MUST enable interrupt on empty shift register before
538 * calling serial8250_em485_init(). This interrupt is not a part of
539 * 8250 standard, but implementation defined.
540 *
541 * The function is supposed to be called from .rs485_config callback
542 * or from any other callback protected with p->port.lock spinlock.
543 *
544 * See also serial8250_em485_destroy()
545 *
546 * Return 0 - success, -errno - otherwise
547 */
548static int serial8250_em485_init(struct uart_8250_port *p)
549{
550 /* Port locked to synchronize UART_IER access against the console. */
551 lockdep_assert_held_once(&p->port.lock);
552
553 if (p->em485)
554 goto deassert_rts;
555
556 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
557 if (!p->em485)
558 return -ENOMEM;
559
560 hrtimer_setup(timer: &p->em485->stop_tx_timer, function: &serial8250_em485_handle_stop_tx, CLOCK_MONOTONIC,
561 mode: HRTIMER_MODE_REL);
562 hrtimer_setup(timer: &p->em485->start_tx_timer, function: &serial8250_em485_handle_start_tx, CLOCK_MONOTONIC,
563 mode: HRTIMER_MODE_REL);
564 p->em485->port = p;
565 p->em485->active_timer = NULL;
566 p->em485->tx_stopped = true;
567
568deassert_rts:
569 if (p->em485->tx_stopped)
570 p->rs485_stop_tx(p, true);
571
572 return 0;
573}
574
575/**
576 * serial8250_em485_destroy() - put uart_8250_port into normal state
577 * @p: uart_8250_port port instance
578 *
579 * The function is used to stop rs485 software emulating on the
580 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
581 * call it multiple times.
582 *
583 * The function is supposed to be called from .rs485_config callback
584 * or from any other callback protected with p->port.lock spinlock.
585 *
586 * See also serial8250_em485_init()
587 */
588void serial8250_em485_destroy(struct uart_8250_port *p)
589{
590 if (!p->em485)
591 return;
592
593 hrtimer_cancel(timer: &p->em485->start_tx_timer);
594 hrtimer_cancel(timer: &p->em485->stop_tx_timer);
595
596 kfree(objp: p->em485);
597 p->em485 = NULL;
598}
599EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
600
601struct serial_rs485 serial8250_em485_supported = {
602 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
603 SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
604 .delay_rts_before_send = 1,
605 .delay_rts_after_send = 1,
606};
607EXPORT_SYMBOL_GPL(serial8250_em485_supported);
608
609/**
610 * serial8250_em485_config() - generic ->rs485_config() callback
611 * @port: uart port
612 * @termios: termios structure
613 * @rs485: rs485 settings
614 *
615 * Generic callback usable by 8250 uart drivers to activate rs485 settings
616 * if the uart is incapable of driving RTS as a Transmit Enable signal in
617 * hardware, relying on software emulation instead.
618 */
619int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
620 struct serial_rs485 *rs485)
621{
622 struct uart_8250_port *up = up_to_u8250p(up: port);
623
624 /*
625 * Both serial8250_em485_init() and serial8250_em485_destroy()
626 * are idempotent.
627 */
628 if (rs485->flags & SER_RS485_ENABLED)
629 return serial8250_em485_init(p: up);
630
631 serial8250_em485_destroy(up);
632 return 0;
633}
634EXPORT_SYMBOL_GPL(serial8250_em485_config);
635
636/*
637 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
638 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
639 * empty and the HW can idle again.
640 */
641static void serial8250_rpm_get_tx(struct uart_8250_port *p)
642{
643 unsigned char rpm_active;
644
645 if (!(p->capabilities & UART_CAP_RPM))
646 return;
647
648 rpm_active = xchg(&p->rpm_tx_active, 1);
649 if (rpm_active)
650 return;
651 pm_runtime_get_sync(dev: p->port.dev);
652}
653
654static void serial8250_rpm_put_tx(struct uart_8250_port *p)
655{
656 unsigned char rpm_active;
657
658 if (!(p->capabilities & UART_CAP_RPM))
659 return;
660
661 rpm_active = xchg(&p->rpm_tx_active, 0);
662 if (!rpm_active)
663 return;
664 pm_runtime_mark_last_busy(dev: p->port.dev);
665 pm_runtime_put_autosuspend(dev: p->port.dev);
666}
667
668/*
669 * IER sleep support. UARTs which have EFRs need the "extended
670 * capability" bit enabled. Note that on XR16C850s, we need to
671 * reset LCR to write to IER.
672 */
673static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
674{
675 unsigned char lcr = 0, efr = 0;
676
677 guard(serial8250_rpm)(T: p);
678
679 if (!(p->capabilities & UART_CAP_SLEEP))
680 return;
681
682 /* Synchronize UART_IER access against the console. */
683 guard(uart_port_lock_irq)(T: &p->port);
684
685 if (p->capabilities & UART_CAP_EFR) {
686 lcr = serial_in(up: p, UART_LCR);
687 efr = serial_in(up: p, UART_EFR);
688 serial_out(up: p, UART_LCR, UART_LCR_CONF_MODE_B);
689 serial_out(up: p, UART_EFR, UART_EFR_ECB);
690 serial_out(up: p, UART_LCR, value: 0);
691 }
692 serial_out(up: p, UART_IER, value: sleep ? UART_IERX_SLEEP : 0);
693 if (p->capabilities & UART_CAP_EFR) {
694 serial_out(up: p, UART_LCR, UART_LCR_CONF_MODE_B);
695 serial_out(up: p, UART_EFR, value: efr);
696 serial_out(up: p, UART_LCR, value: lcr);
697 }
698}
699
700/* Clear the interrupt registers. */
701static void serial8250_clear_interrupts(struct uart_port *port)
702{
703 serial_port_in(up: port, UART_LSR);
704 serial_port_in(up: port, UART_RX);
705 serial_port_in(up: port, UART_IIR);
706 serial_port_in(up: port, UART_MSR);
707}
708
709static void serial8250_clear_IER(struct uart_8250_port *up)
710{
711 if (up->capabilities & UART_CAP_UUE)
712 serial_out(up, UART_IER, UART_IER_UUE);
713 else
714 serial_out(up, UART_IER, value: 0);
715}
716
717/*
718 * This is a quickie test to see how big the FIFO is.
719 * It doesn't work at all the time, more's the pity.
720 */
721static int size_fifo(struct uart_8250_port *up)
722{
723 unsigned char old_fcr, old_mcr, old_lcr;
724 u32 old_dl;
725 int count;
726
727 old_lcr = serial_in(up, UART_LCR);
728 serial_out(up, UART_LCR, value: 0);
729 old_fcr = serial_in(up, UART_FCR);
730 old_mcr = serial8250_in_MCR(up);
731 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
732 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
733 serial8250_out_MCR(up, UART_MCR_LOOP);
734 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
735 old_dl = serial_dl_read(up);
736 serial_dl_write(up, value: 0x0001);
737 serial_out(up, UART_LCR, UART_LCR_WLEN8);
738 for (count = 0; count < 256; count++)
739 serial_out(up, UART_TX, value: count);
740 mdelay(20);/* FIXME - schedule_timeout */
741 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
742 (count < 256); count++)
743 serial_in(up, UART_RX);
744 serial_out(up, UART_FCR, value: old_fcr);
745 serial8250_out_MCR(up, value: old_mcr);
746 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
747 serial_dl_write(up, value: old_dl);
748 serial_out(up, UART_LCR, value: old_lcr);
749
750 return count;
751}
752
753/*
754 * Read UART ID using the divisor method - set DLL and DLM to zero
755 * and the revision will be in DLL and device type in DLM. We
756 * preserve the device state across this.
757 */
758static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
759{
760 unsigned char old_lcr;
761 unsigned int id, old_dl;
762
763 old_lcr = serial_in(up: p, UART_LCR);
764 serial_out(up: p, UART_LCR, UART_LCR_CONF_MODE_A);
765 old_dl = serial_dl_read(up: p);
766 serial_dl_write(up: p, value: 0);
767 id = serial_dl_read(up: p);
768 serial_dl_write(up: p, value: old_dl);
769
770 serial_out(up: p, UART_LCR, value: old_lcr);
771
772 return id;
773}
774
775/*
776 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
777 * When this function is called we know it is at least a StarTech
778 * 16650 V2, but it might be one of several StarTech UARTs, or one of
779 * its clones. (We treat the broken original StarTech 16650 V1 as a
780 * 16550, and why not? Startech doesn't seem to even acknowledge its
781 * existence.)
782 *
783 * What evil have men's minds wrought...
784 */
785static void autoconfig_has_efr(struct uart_8250_port *up)
786{
787 unsigned int id1, id2, id3, rev;
788
789 /*
790 * Everything with an EFR has SLEEP
791 */
792 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
793
794 /*
795 * First we check to see if it's an Oxford Semiconductor UART.
796 *
797 * If we have to do this here because some non-National
798 * Semiconductor clone chips lock up if you try writing to the
799 * LSR register (which serial_icr_read does)
800 */
801
802 /*
803 * Check for Oxford Semiconductor 16C950.
804 *
805 * EFR [4] must be set else this test fails.
806 *
807 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
808 * claims that it's needed for 952 dual UART's (which are not
809 * recommended for new designs).
810 */
811 up->acr = 0;
812 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
813 serial_out(up, UART_EFR, UART_EFR_ECB);
814 serial_out(up, UART_LCR, value: 0x00);
815 id1 = serial_icr_read(up, UART_ID1);
816 id2 = serial_icr_read(up, UART_ID2);
817 id3 = serial_icr_read(up, UART_ID3);
818 rev = serial_icr_read(up, UART_REV);
819
820 if (id1 == 0x16 && id2 == 0xC9 &&
821 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
822 up->port.type = PORT_16C950;
823
824 /*
825 * Enable work around for the Oxford Semiconductor 952 rev B
826 * chip which causes it to seriously miscalculate baud rates
827 * when DLL is 0.
828 */
829 if (id3 == 0x52 && rev == 0x01)
830 up->bugs |= UART_BUG_QUOT;
831 return;
832 }
833
834 /*
835 * We check for a XR16C850 by setting DLL and DLM to 0, and then
836 * reading back DLL and DLM. The chip type depends on the DLM
837 * value read back:
838 * 0x10 - XR16C850 and the DLL contains the chip revision.
839 * 0x12 - XR16C2850.
840 * 0x14 - XR16C854.
841 */
842 id1 = autoconfig_read_divisor_id(p: up);
843
844 id2 = id1 >> 8;
845 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
846 up->port.type = PORT_16850;
847 return;
848 }
849
850 /*
851 * It wasn't an XR16C850.
852 *
853 * We distinguish between the '654 and the '650 by counting
854 * how many bytes are in the FIFO. I'm using this for now,
855 * since that's the technique that was sent to me in the
856 * serial driver update, but I'm not convinced this works.
857 * I've had problems doing this in the past. -TYT
858 */
859 if (size_fifo(up) == 64)
860 up->port.type = PORT_16654;
861 else
862 up->port.type = PORT_16650V2;
863}
864
865/*
866 * We detected a chip without a FIFO. Only two fall into
867 * this category - the original 8250 and the 16450. The
868 * 16450 has a scratch register (accessible with LCR=0)
869 */
870static void autoconfig_8250(struct uart_8250_port *up)
871{
872 unsigned char scratch, status1, status2;
873
874 up->port.type = PORT_8250;
875
876 scratch = serial_in(up, UART_SCR);
877 serial_out(up, UART_SCR, value: 0xa5);
878 status1 = serial_in(up, UART_SCR);
879 serial_out(up, UART_SCR, value: 0x5a);
880 status2 = serial_in(up, UART_SCR);
881 serial_out(up, UART_SCR, value: scratch);
882
883 if (status1 == 0xa5 && status2 == 0x5a)
884 up->port.type = PORT_16450;
885}
886
887static int broken_efr(struct uart_8250_port *up)
888{
889 /*
890 * Exar ST16C2550 "A2" devices incorrectly detect as
891 * having an EFR, and report an ID of 0x0201. See
892 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
893 */
894 if (autoconfig_read_divisor_id(p: up) == 0x0201 && size_fifo(up) == 16)
895 return 1;
896
897 return 0;
898}
899
900/*
901 * We know that the chip has FIFOs. Does it have an EFR? The
902 * EFR is located in the same register position as the IIR and
903 * we know the top two bits of the IIR are currently set. The
904 * EFR should contain zero. Try to read the EFR.
905 */
906static void autoconfig_16550a(struct uart_8250_port *up)
907{
908 unsigned char status1, status2;
909 unsigned int iersave;
910
911 /* Port locked to synchronize UART_IER access against the console. */
912 lockdep_assert_held_once(&up->port.lock);
913
914 up->port.type = PORT_16550A;
915 up->capabilities |= UART_CAP_FIFO;
916
917 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
918 !(up->port.flags & UPF_FULL_PROBE))
919 return;
920
921 /*
922 * Check for presence of the EFR when DLAB is set.
923 * Only ST16C650V1 UARTs pass this test.
924 */
925 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
926 if (serial_in(up, UART_EFR) == 0) {
927 serial_out(up, UART_EFR, value: 0xA8);
928 if (serial_in(up, UART_EFR) != 0) {
929 up->port.type = PORT_16650;
930 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
931 } else {
932 serial_out(up, UART_LCR, value: 0);
933 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
934 UART_FCR7_64BYTE);
935 status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
936 serial_out(up, UART_FCR, value: 0);
937 serial_out(up, UART_LCR, value: 0);
938
939 if (status1 == UART_IIR_FIFO_ENABLED_16750)
940 up->port.type = PORT_16550A_FSL64;
941 }
942 serial_out(up, UART_EFR, value: 0);
943 return;
944 }
945
946 /*
947 * Maybe it requires 0xbf to be written to the LCR.
948 * (other ST16C650V2 UARTs, TI16C752A, etc)
949 */
950 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
951 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
952 autoconfig_has_efr(up);
953 return;
954 }
955
956 /*
957 * Check for a National Semiconductor SuperIO chip.
958 * Attempt to switch to bank 2, read the value of the LOOP bit
959 * from EXCR1. Switch back to bank 0, change it in MCR. Then
960 * switch back to bank 2, read it from EXCR1 again and check
961 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
962 */
963 serial_out(up, UART_LCR, value: 0);
964 status1 = serial8250_in_MCR(up);
965 serial_out(up, UART_LCR, value: 0xE0);
966 status2 = serial_in(up, offset: 0x02); /* EXCR1 */
967
968 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
969 serial_out(up, UART_LCR, value: 0);
970 serial8250_out_MCR(up, value: status1 ^ UART_MCR_LOOP);
971 serial_out(up, UART_LCR, value: 0xE0);
972 status2 = serial_in(up, offset: 0x02); /* EXCR1 */
973 serial_out(up, UART_LCR, value: 0);
974 serial8250_out_MCR(up, value: status1);
975
976 if ((status2 ^ status1) & UART_MCR_LOOP) {
977 unsigned short quot;
978
979 serial_out(up, UART_LCR, value: 0xE0);
980
981 quot = serial_dl_read(up);
982 quot <<= 3;
983
984 if (ns16550a_goto_highspeed(up))
985 serial_dl_write(up, value: quot);
986
987 serial_out(up, UART_LCR, value: 0);
988
989 up->port.uartclk = 921600*16;
990 up->port.type = PORT_NS16550A;
991 up->capabilities |= UART_NATSEMI;
992 return;
993 }
994 }
995
996 /*
997 * No EFR. Try to detect a TI16750, which only sets bit 5 of
998 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
999 * Try setting it with and without DLAB set. Cheap clones
1000 * set bit 5 without DLAB set.
1001 */
1002 serial_out(up, UART_LCR, value: 0);
1003 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1004 status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
1005 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1006
1007 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1008 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1009 status2 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
1010 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1011
1012 serial_out(up, UART_LCR, value: 0);
1013
1014 if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
1015 status2 == UART_IIR_FIFO_ENABLED_16750) {
1016 up->port.type = PORT_16750;
1017 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1018 return;
1019 }
1020
1021 /*
1022 * Try writing and reading the UART_IER_UUE bit (b6).
1023 * If it works, this is probably one of the Xscale platform's
1024 * internal UARTs.
1025 * We're going to explicitly set the UUE bit to 0 before
1026 * trying to write and read a 1 just to make sure it's not
1027 * already a 1 and maybe locked there before we even start.
1028 */
1029 iersave = serial_in(up, UART_IER);
1030 serial_out(up, UART_IER, value: iersave & ~UART_IER_UUE);
1031 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1032 /*
1033 * OK it's in a known zero state, try writing and reading
1034 * without disturbing the current state of the other bits.
1035 */
1036 serial_out(up, UART_IER, value: iersave | UART_IER_UUE);
1037 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1038 /*
1039 * It's an Xscale.
1040 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1041 */
1042 up->port.type = PORT_XSCALE;
1043 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1044 return;
1045 }
1046 }
1047 serial_out(up, UART_IER, value: iersave);
1048
1049 /*
1050 * We distinguish between 16550A and U6 16550A by counting
1051 * how many bytes are in the FIFO.
1052 */
1053 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1054 up->port.type = PORT_U6_16550A;
1055 up->capabilities |= UART_CAP_AFE;
1056 }
1057}
1058
1059/*
1060 * This routine is called by rs_init() to initialize a specific serial
1061 * port. It determines what type of UART chip this serial port is
1062 * using: 8250, 16450, 16550, 16550A. The important question is
1063 * whether or not this UART is a 16550A or not, since this will
1064 * determine whether or not we can use its FIFO features or not.
1065 */
1066static void autoconfig(struct uart_8250_port *up)
1067{
1068 unsigned char status1, scratch, scratch2, scratch3;
1069 unsigned char save_lcr, save_mcr;
1070 struct uart_port *port = &up->port;
1071 unsigned long flags;
1072 unsigned int old_capabilities;
1073
1074 if (!port->iobase && !port->mapbase && !port->membase)
1075 return;
1076
1077 /*
1078 * We really do need global IRQs disabled here - we're going to
1079 * be frobbing the chips IRQ enable register to see if it exists.
1080 *
1081 * Synchronize UART_IER access against the console.
1082 */
1083 uart_port_lock_irqsave(up: port, flags: &flags);
1084
1085 up->capabilities = 0;
1086 up->bugs = 0;
1087
1088 if (!(port->flags & UPF_BUGGY_UART)) {
1089 /*
1090 * Do a simple existence test first; if we fail this,
1091 * there's no point trying anything else.
1092 *
1093 * 0x80 is used as a nonsense port to prevent against
1094 * false positives due to ISA bus float. The
1095 * assumption is that 0x80 is a non-existent port;
1096 * which should be safe since include/asm/io.h also
1097 * makes this assumption.
1098 *
1099 * Note: this is safe as long as MCR bit 4 is clear
1100 * and the device is in "PC" mode.
1101 */
1102 scratch = serial_in(up, UART_IER);
1103 serial_out(up, UART_IER, value: 0);
1104#if defined(__i386__) && defined(CONFIG_HAS_IOPORT)
1105 outb(0xff, 0x080);
1106#endif
1107 /*
1108 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1109 * 16C754B) allow only to modify them if an EFR bit is set.
1110 */
1111 scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1112 serial_out(up, UART_IER, UART_IER_ALL_INTR);
1113#if defined(__i386__) && defined(CONFIG_HAS_IOPORT)
1114 outb(0, 0x080);
1115#endif
1116 scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1117 serial_out(up, UART_IER, value: scratch);
1118 if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) {
1119 /*
1120 * We failed; there's nothing here
1121 */
1122 uart_port_unlock_irqrestore(up: port, flags);
1123 return;
1124 }
1125 }
1126
1127 save_mcr = serial8250_in_MCR(up);
1128 save_lcr = serial_in(up, UART_LCR);
1129
1130 /*
1131 * Check to see if a UART is really there. Certain broken
1132 * internal modems based on the Rockwell chipset fail this
1133 * test, because they apparently don't implement the loopback
1134 * test mode. So this test is skipped on the COM 1 through
1135 * COM 4 ports. This *should* be safe, since no board
1136 * manufacturer would be stupid enough to design a board
1137 * that conflicts with COM 1-4 --- we hope!
1138 */
1139 if (!(port->flags & UPF_SKIP_TEST)) {
1140 serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
1141 status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
1142 serial8250_out_MCR(up, value: save_mcr);
1143 if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
1144 uart_port_unlock_irqrestore(up: port, flags);
1145 return;
1146 }
1147 }
1148
1149 /*
1150 * We're pretty sure there's a port here. Lets find out what
1151 * type of port it is. The IIR top two bits allows us to find
1152 * out if it's 8250 or 16450, 16550, 16550A or later. This
1153 * determines what we test for next.
1154 *
1155 * We also initialise the EFR (if any) to zero for later. The
1156 * EFR occupies the same register location as the FCR and IIR.
1157 */
1158 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1159 serial_out(up, UART_EFR, value: 0);
1160 serial_out(up, UART_LCR, value: 0);
1161
1162 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1163
1164 switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) {
1165 case UART_IIR_FIFO_ENABLED_8250:
1166 autoconfig_8250(up);
1167 break;
1168 case UART_IIR_FIFO_ENABLED_16550:
1169 port->type = PORT_16550;
1170 break;
1171 case UART_IIR_FIFO_ENABLED_16550A:
1172 autoconfig_16550a(up);
1173 break;
1174 default:
1175 port->type = PORT_UNKNOWN;
1176 break;
1177 }
1178
1179 rsa_autoconfig(up);
1180
1181 serial_out(up, UART_LCR, value: save_lcr);
1182
1183 port->fifosize = uart_config[up->port.type].fifo_size;
1184 old_capabilities = up->capabilities;
1185 up->capabilities = uart_config[port->type].flags;
1186 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1187
1188 if (port->type != PORT_UNKNOWN) {
1189 /*
1190 * Reset the UART.
1191 */
1192 rsa_reset(up);
1193 serial8250_out_MCR(up, value: save_mcr);
1194 serial8250_clear_fifos(p: up);
1195 serial_in(up, UART_RX);
1196 serial8250_clear_IER(up);
1197 }
1198
1199 uart_port_unlock_irqrestore(up: port, flags);
1200
1201 /*
1202 * Check if the device is a Fintek F81216A
1203 */
1204 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1205 fintek_8250_probe(uart: up);
1206
1207 if (up->capabilities != old_capabilities) {
1208 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1209 old_capabilities, up->capabilities);
1210 }
1211}
1212
1213static void autoconfig_irq(struct uart_8250_port *up)
1214{
1215 struct uart_port *port = &up->port;
1216 unsigned char save_mcr, save_ier;
1217 unsigned char save_ICP = 0;
1218 unsigned int ICP = 0;
1219 unsigned long irqs;
1220 int irq;
1221
1222 if (port->flags & UPF_FOURPORT) {
1223 ICP = (port->iobase & 0xfe0) | 0x1f;
1224 save_ICP = inb_p(port: ICP);
1225 outb_p(value: 0x80, port: ICP);
1226 inb_p(port: ICP);
1227 }
1228
1229 /* forget possible initially masked and pending IRQ */
1230 probe_irq_off(probe_irq_on());
1231 save_mcr = serial8250_in_MCR(up);
1232 /* Synchronize UART_IER access against the console. */
1233 scoped_guard(uart_port_lock_irq, port)
1234 save_ier = serial_in(up, UART_IER);
1235 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1236
1237 irqs = probe_irq_on();
1238 serial8250_out_MCR(up, value: 0);
1239 udelay(usec: 10);
1240 if (port->flags & UPF_FOURPORT) {
1241 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1242 } else {
1243 serial8250_out_MCR(up,
1244 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1245 }
1246 /* Synchronize UART_IER access against the console. */
1247 scoped_guard(uart_port_lock_irq, port)
1248 serial_out(up, UART_IER, UART_IER_ALL_INTR);
1249 serial8250_clear_interrupts(port);
1250 serial_out(up, UART_TX, value: 0xFF);
1251 udelay(usec: 20);
1252 irq = probe_irq_off(irqs);
1253
1254 serial8250_out_MCR(up, value: save_mcr);
1255 /* Synchronize UART_IER access against the console. */
1256 scoped_guard(uart_port_lock_irq, port)
1257 serial_out(up, UART_IER, value: save_ier);
1258
1259 if (port->flags & UPF_FOURPORT)
1260 outb_p(value: save_ICP, port: ICP);
1261
1262 port->irq = (irq > 0) ? irq : 0;
1263}
1264
1265static void serial8250_stop_rx(struct uart_port *port)
1266{
1267 struct uart_8250_port *up = up_to_u8250p(up: port);
1268
1269 /* Port locked to synchronize UART_IER access against the console. */
1270 lockdep_assert_held_once(&port->lock);
1271
1272 guard(serial8250_rpm)(T: up);
1273
1274 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1275 serial_port_out(up: port, UART_IER, value: up->ier);
1276}
1277
1278/**
1279 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1280 * @p: uart 8250 port
1281 * @toggle_ier: true to allow enabling receive interrupts
1282 *
1283 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1284 */
1285void serial8250_em485_stop_tx(struct uart_8250_port *p, bool toggle_ier)
1286{
1287 unsigned char mcr = serial8250_in_MCR(up: p);
1288
1289 /* Port locked to synchronize UART_IER access against the console. */
1290 lockdep_assert_held_once(&p->port.lock);
1291
1292 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1293 mcr |= UART_MCR_RTS;
1294 else
1295 mcr &= ~UART_MCR_RTS;
1296 serial8250_out_MCR(up: p, value: mcr);
1297
1298 /*
1299 * Empty the RX FIFO, we are not interested in anything
1300 * received during the half-duplex transmission.
1301 * Enable previously disabled RX interrupts.
1302 */
1303 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1304 serial8250_clear_and_reinit_fifos(p);
1305
1306 if (toggle_ier) {
1307 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1308 serial_port_out(up: &p->port, UART_IER, value: p->ier);
1309 }
1310 }
1311}
1312EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1313
1314static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1315{
1316 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1317 stop_tx_timer);
1318 struct uart_8250_port *p = em485->port;
1319
1320 guard(serial8250_rpm)(T: p);
1321 guard(uart_port_lock_irqsave)(l: &p->port);
1322
1323 if (em485->active_timer == &em485->stop_tx_timer) {
1324 p->rs485_stop_tx(p, true);
1325 em485->active_timer = NULL;
1326 em485->tx_stopped = true;
1327 }
1328
1329 return HRTIMER_NORESTART;
1330}
1331
1332static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1333{
1334 hrtimer_start(timer: hrt, tim: ms_to_ktime(ms: msec), mode: HRTIMER_MODE_REL);
1335}
1336
1337static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1338{
1339 struct uart_8250_em485 *em485 = p->em485;
1340
1341 /* Port locked to synchronize UART_IER access against the console. */
1342 lockdep_assert_held_once(&p->port.lock);
1343
1344 stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1345
1346 /*
1347 * rs485_stop_tx() is going to set RTS according to config
1348 * AND flush RX FIFO if required.
1349 */
1350 if (stop_delay > 0) {
1351 em485->active_timer = &em485->stop_tx_timer;
1352 hrtimer_start(timer: &em485->stop_tx_timer, tim: ns_to_ktime(ns: stop_delay), mode: HRTIMER_MODE_REL);
1353 } else {
1354 p->rs485_stop_tx(p, true);
1355 em485->active_timer = NULL;
1356 em485->tx_stopped = true;
1357 }
1358}
1359
1360static inline void __stop_tx(struct uart_8250_port *p)
1361{
1362 struct uart_8250_em485 *em485 = p->em485;
1363
1364 if (em485) {
1365 u16 lsr = serial_lsr_in(up: p);
1366 u64 stop_delay = 0;
1367
1368 if (!(lsr & UART_LSR_THRE))
1369 return;
1370 /*
1371 * To provide required timing and allow FIFO transfer,
1372 * __stop_tx_rs485() must be called only when both FIFO and
1373 * shift register are empty. The device driver should either
1374 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1375 * enlarge stop_tx_timer by the tx time of one frame to cover
1376 * for emptying of the shift register.
1377 */
1378 if (!(lsr & UART_LSR_TEMT)) {
1379 if (!(p->capabilities & UART_CAP_NOTEMT))
1380 return;
1381 /*
1382 * RTS might get deasserted too early with the normal
1383 * frame timing formula. It seems to suggest THRE might
1384 * get asserted already during tx of the stop bit
1385 * rather than after it is fully sent.
1386 * Roughly estimate 1 extra bit here with / 7.
1387 */
1388 stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1389 }
1390
1391 __stop_tx_rs485(p, stop_delay);
1392 }
1393
1394 if (serial8250_clear_THRI(up: p))
1395 serial8250_rpm_put_tx(p);
1396}
1397
1398static void serial8250_stop_tx(struct uart_port *port)
1399{
1400 struct uart_8250_port *up = up_to_u8250p(up: port);
1401
1402 guard(serial8250_rpm)(T: up);
1403 __stop_tx(p: up);
1404
1405 /*
1406 * We really want to stop the transmitter from sending.
1407 */
1408 if (port->type == PORT_16C950) {
1409 up->acr |= UART_ACR_TXDIS;
1410 serial_icr_write(up, UART_ACR, value: up->acr);
1411 }
1412}
1413
1414static inline void __start_tx(struct uart_port *port)
1415{
1416 struct uart_8250_port *up = up_to_u8250p(up: port);
1417
1418 if (up->dma && !up->dma->tx_dma(up))
1419 return;
1420
1421 if (serial8250_set_THRI(up)) {
1422 if (up->bugs & UART_BUG_TXEN) {
1423 u16 lsr = serial_lsr_in(up);
1424
1425 if (lsr & UART_LSR_THRE)
1426 serial8250_tx_chars(up);
1427 }
1428 }
1429
1430 /*
1431 * Re-enable the transmitter if we disabled it.
1432 */
1433 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1434 up->acr &= ~UART_ACR_TXDIS;
1435 serial_icr_write(up, UART_ACR, value: up->acr);
1436 }
1437}
1438
1439/**
1440 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1441 * @up: uart 8250 port
1442 * @toggle_ier: true to allow disabling receive interrupts
1443 *
1444 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1445 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1446 * (Some chips use inverse semantics.) Further assumes that reception is
1447 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1448 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1449 */
1450void serial8250_em485_start_tx(struct uart_8250_port *up, bool toggle_ier)
1451{
1452 unsigned char mcr = serial8250_in_MCR(up);
1453
1454 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && toggle_ier)
1455 serial8250_stop_rx(port: &up->port);
1456
1457 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1458 mcr |= UART_MCR_RTS;
1459 else
1460 mcr &= ~UART_MCR_RTS;
1461 serial8250_out_MCR(up, value: mcr);
1462}
1463EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1464
1465/* Returns false, if start_tx_timer was setup to defer TX start */
1466static bool start_tx_rs485(struct uart_port *port)
1467{
1468 struct uart_8250_port *up = up_to_u8250p(up: port);
1469 struct uart_8250_em485 *em485 = up->em485;
1470
1471 /*
1472 * While serial8250_em485_handle_stop_tx() is a noop if
1473 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1474 * the timer is still armed and triggers only after the current bunch of
1475 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1476 * So cancel the timer. There is still a theoretical race condition if
1477 * the timer is already running and only comes around to check for
1478 * em485->active_timer when &em485->stop_tx_timer is armed again.
1479 */
1480 if (em485->active_timer == &em485->stop_tx_timer)
1481 hrtimer_try_to_cancel(timer: &em485->stop_tx_timer);
1482
1483 em485->active_timer = NULL;
1484
1485 if (em485->tx_stopped) {
1486 em485->tx_stopped = false;
1487
1488 up->rs485_start_tx(up, true);
1489
1490 if (up->port.rs485.delay_rts_before_send > 0) {
1491 em485->active_timer = &em485->start_tx_timer;
1492 start_hrtimer_ms(hrt: &em485->start_tx_timer,
1493 msec: up->port.rs485.delay_rts_before_send);
1494 return false;
1495 }
1496 }
1497
1498 return true;
1499}
1500
1501static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1502{
1503 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1504 start_tx_timer);
1505 struct uart_8250_port *p = em485->port;
1506
1507 guard(uart_port_lock_irqsave)(l: &p->port);
1508
1509 if (em485->active_timer == &em485->start_tx_timer) {
1510 __start_tx(port: &p->port);
1511 em485->active_timer = NULL;
1512 }
1513
1514 return HRTIMER_NORESTART;
1515}
1516
1517static void serial8250_start_tx(struct uart_port *port)
1518{
1519 struct uart_8250_port *up = up_to_u8250p(up: port);
1520 struct uart_8250_em485 *em485 = up->em485;
1521
1522 /* Port locked to synchronize UART_IER access against the console. */
1523 lockdep_assert_held_once(&port->lock);
1524
1525 if (!port->x_char && kfifo_is_empty(&port->state->port.xmit_fifo))
1526 return;
1527
1528 serial8250_rpm_get_tx(p: up);
1529
1530 if (em485) {
1531 if ((em485->active_timer == &em485->start_tx_timer) ||
1532 !start_tx_rs485(port))
1533 return;
1534 }
1535 __start_tx(port);
1536}
1537
1538static void serial8250_throttle(struct uart_port *port)
1539{
1540 port->throttle(port);
1541}
1542
1543static void serial8250_unthrottle(struct uart_port *port)
1544{
1545 port->unthrottle(port);
1546}
1547
1548static void serial8250_disable_ms(struct uart_port *port)
1549{
1550 struct uart_8250_port *up = up_to_u8250p(up: port);
1551
1552 /* Port locked to synchronize UART_IER access against the console. */
1553 lockdep_assert_held_once(&port->lock);
1554
1555 /* no MSR capabilities */
1556 if (up->bugs & UART_BUG_NOMSR)
1557 return;
1558
1559 mctrl_gpio_disable_ms_no_sync(gpios: up->gpios);
1560
1561 up->ier &= ~UART_IER_MSI;
1562 serial_port_out(up: port, UART_IER, value: up->ier);
1563}
1564
1565static void serial8250_enable_ms(struct uart_port *port)
1566{
1567 struct uart_8250_port *up = up_to_u8250p(up: port);
1568
1569 /* Port locked to synchronize UART_IER access against the console. */
1570 lockdep_assert_held_once(&port->lock);
1571
1572 /* no MSR capabilities */
1573 if (up->bugs & UART_BUG_NOMSR)
1574 return;
1575
1576 mctrl_gpio_enable_ms(gpios: up->gpios);
1577
1578 up->ier |= UART_IER_MSI;
1579
1580 guard(serial8250_rpm)(T: up);
1581 serial_port_out(up: port, UART_IER, value: up->ier);
1582}
1583
1584void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1585{
1586 struct uart_port *port = &up->port;
1587 u8 ch, flag = TTY_NORMAL;
1588
1589 if (likely(lsr & UART_LSR_DR))
1590 ch = serial_in(up, UART_RX);
1591 else
1592 /*
1593 * Intel 82571 has a Serial Over Lan device that will
1594 * set UART_LSR_BI without setting UART_LSR_DR when
1595 * it receives a break. To avoid reading from the
1596 * receive buffer without UART_LSR_DR bit set, we
1597 * just force the read character to be 0
1598 */
1599 ch = 0;
1600
1601 port->icount.rx++;
1602
1603 lsr |= up->lsr_saved_flags;
1604 up->lsr_saved_flags = 0;
1605
1606 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1607 if (lsr & UART_LSR_BI) {
1608 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1609 port->icount.brk++;
1610 /*
1611 * We do the SysRQ and SAK checking
1612 * here because otherwise the break
1613 * may get masked by ignore_status_mask
1614 * or read_status_mask.
1615 */
1616 if (uart_handle_break(port))
1617 return;
1618 } else if (lsr & UART_LSR_PE)
1619 port->icount.parity++;
1620 else if (lsr & UART_LSR_FE)
1621 port->icount.frame++;
1622 if (lsr & UART_LSR_OE)
1623 port->icount.overrun++;
1624
1625 /*
1626 * Mask off conditions which should be ignored.
1627 */
1628 lsr &= port->read_status_mask;
1629
1630 if (lsr & UART_LSR_BI) {
1631 dev_dbg(port->dev, "handling break\n");
1632 flag = TTY_BREAK;
1633 } else if (lsr & UART_LSR_PE)
1634 flag = TTY_PARITY;
1635 else if (lsr & UART_LSR_FE)
1636 flag = TTY_FRAME;
1637 }
1638 if (uart_prepare_sysrq_char(port, ch))
1639 return;
1640
1641 uart_insert_char(port, status: lsr, UART_LSR_OE, ch, flag);
1642}
1643EXPORT_SYMBOL_GPL(serial8250_read_char);
1644
1645/*
1646 * serial8250_rx_chars - Read characters. The first LSR value must be passed in.
1647 *
1648 * Returns LSR bits. The caller should rely only on non-Rx related LSR bits
1649 * (such as THRE) because the LSR value might come from an already consumed
1650 * character.
1651 */
1652u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1653{
1654 struct uart_port *port = &up->port;
1655 int max_count = 256;
1656
1657 do {
1658 serial8250_read_char(up, lsr);
1659 if (--max_count == 0)
1660 break;
1661 lsr = serial_in(up, UART_LSR);
1662 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1663
1664 tty_flip_buffer_push(port: &port->state->port);
1665 return lsr;
1666}
1667EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1668
1669void serial8250_tx_chars(struct uart_8250_port *up)
1670{
1671 struct uart_port *port = &up->port;
1672 struct tty_port *tport = &port->state->port;
1673 int count;
1674
1675 if (port->x_char) {
1676 uart_xchar_out(uport: port, UART_TX);
1677 return;
1678 }
1679 if (uart_tx_stopped(port)) {
1680 serial8250_stop_tx(port);
1681 return;
1682 }
1683 if (kfifo_is_empty(&tport->xmit_fifo)) {
1684 __stop_tx(p: up);
1685 return;
1686 }
1687
1688 count = up->tx_loadsz;
1689 do {
1690 unsigned char c;
1691
1692 if (!uart_fifo_get(up: port, ch: &c))
1693 break;
1694
1695 serial_out(up, UART_TX, value: c);
1696 if (up->bugs & UART_BUG_TXRACE) {
1697 /*
1698 * The Aspeed BMC virtual UARTs have a bug where data
1699 * may get stuck in the BMC's Tx FIFO from bursts of
1700 * writes on the APB interface.
1701 *
1702 * Delay back-to-back writes by a read cycle to avoid
1703 * stalling the VUART. Read a register that won't have
1704 * side-effects and discard the result.
1705 */
1706 serial_in(up, UART_SCR);
1707 }
1708
1709 if ((up->capabilities & UART_CAP_HFIFO) &&
1710 !uart_lsr_tx_empty(lsr: serial_in(up, UART_LSR)))
1711 break;
1712 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1713 if ((up->capabilities & UART_CAP_MINI) &&
1714 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1715 break;
1716 } while (--count > 0);
1717
1718 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1719 uart_write_wakeup(port);
1720
1721 /*
1722 * With RPM enabled, we have to wait until the FIFO is empty before the
1723 * HW can go idle. So we get here once again with empty FIFO and disable
1724 * the interrupt and RPM in __stop_tx()
1725 */
1726 if (kfifo_is_empty(&tport->xmit_fifo) &&
1727 !(up->capabilities & UART_CAP_RPM))
1728 __stop_tx(p: up);
1729}
1730EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1731
1732/* Caller holds uart port lock */
1733unsigned int serial8250_modem_status(struct uart_8250_port *up)
1734{
1735 struct uart_port *port = &up->port;
1736 unsigned int status = serial_in(up, UART_MSR);
1737
1738 status |= up->msr_saved_flags;
1739 up->msr_saved_flags = 0;
1740 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1741 port->state != NULL) {
1742 if (status & UART_MSR_TERI)
1743 port->icount.rng++;
1744 if (status & UART_MSR_DDSR)
1745 port->icount.dsr++;
1746 if (status & UART_MSR_DDCD)
1747 uart_handle_dcd_change(uport: port, active: status & UART_MSR_DCD);
1748 if (status & UART_MSR_DCTS)
1749 uart_handle_cts_change(uport: port, active: status & UART_MSR_CTS);
1750
1751 wake_up_interruptible(&port->state->port.delta_msr_wait);
1752 }
1753
1754 return status;
1755}
1756EXPORT_SYMBOL_GPL(serial8250_modem_status);
1757
1758static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1759{
1760 switch (iir & 0x3f) {
1761 case UART_IIR_THRI:
1762 /*
1763 * Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT
1764 * because it's impossible to do an informed decision about
1765 * that with IIR_THRI.
1766 *
1767 * This also fixes one known DMA Rx corruption issue where
1768 * DR is asserted but DMA Rx only gets a corrupted zero byte
1769 * (too early DR?).
1770 */
1771 return false;
1772 case UART_IIR_RDI:
1773 if (!up->dma->rx_running)
1774 break;
1775 fallthrough;
1776 case UART_IIR_RLSI:
1777 case UART_IIR_RX_TIMEOUT:
1778 serial8250_rx_dma_flush(up);
1779 return true;
1780 }
1781 return up->dma->rx_dma(up);
1782}
1783
1784/*
1785 * This handles the interrupt from one port.
1786 */
1787int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1788{
1789 struct uart_8250_port *up = up_to_u8250p(up: port);
1790 struct tty_port *tport = &port->state->port;
1791 bool skip_rx = false;
1792 unsigned long flags;
1793 u16 status;
1794
1795 if (iir & UART_IIR_NO_INT)
1796 return 0;
1797
1798 uart_port_lock_irqsave(up: port, flags: &flags);
1799
1800 status = serial_lsr_in(up);
1801
1802 /*
1803 * If port is stopped and there are no error conditions in the
1804 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1805 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1806 * control when FIFO occupancy reaches preset threshold, thus
1807 * halting RX. This only works when auto HW flow control is
1808 * available.
1809 */
1810 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1811 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1812 !(up->ier & (UART_IER_RLSI | UART_IER_RDI)))
1813 skip_rx = true;
1814
1815 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1816 struct irq_data *d;
1817
1818 d = irq_get_irq_data(irq: port->irq);
1819 if (d && irqd_is_wakeup_set(d))
1820 pm_wakeup_event(dev: tport->tty->dev, msec: 0);
1821 if (!up->dma || handle_rx_dma(up, iir))
1822 status = serial8250_rx_chars(up, status);
1823 }
1824 serial8250_modem_status(up);
1825 if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1826 if (!up->dma || up->dma->tx_err)
1827 serial8250_tx_chars(up);
1828 else if (!up->dma->tx_running)
1829 __stop_tx(p: up);
1830 }
1831
1832 uart_unlock_and_check_sysrq_irqrestore(port, flags);
1833
1834 return 1;
1835}
1836EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1837
1838static int serial8250_default_handle_irq(struct uart_port *port)
1839{
1840 struct uart_8250_port *up = up_to_u8250p(up: port);
1841 unsigned int iir;
1842
1843 guard(serial8250_rpm)(T: up);
1844
1845 iir = serial_port_in(up: port, UART_IIR);
1846 return serial8250_handle_irq(port, iir);
1847}
1848
1849/*
1850 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1851 * have a programmable TX threshold that triggers the THRE interrupt in
1852 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1853 * has space available. Load it up with tx_loadsz bytes.
1854 */
1855static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1856{
1857 unsigned int iir = serial_port_in(up: port, UART_IIR);
1858
1859 /* TX Threshold IRQ triggered so load up FIFO */
1860 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1861 struct uart_8250_port *up = up_to_u8250p(up: port);
1862
1863 guard(uart_port_lock_irqsave)(l: port);
1864 serial8250_tx_chars(up);
1865 }
1866
1867 iir = serial_port_in(up: port, UART_IIR);
1868 return serial8250_handle_irq(port, iir);
1869}
1870
1871static unsigned int serial8250_tx_empty(struct uart_port *port)
1872{
1873 struct uart_8250_port *up = up_to_u8250p(up: port);
1874
1875 guard(serial8250_rpm)(T: up);
1876 guard(uart_port_lock_irqsave)(l: port);
1877
1878 if (!serial8250_tx_dma_running(p: up) && uart_lsr_tx_empty(lsr: serial_lsr_in(up)))
1879 return TIOCSER_TEMT;
1880
1881 return 0;
1882}
1883
1884unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1885{
1886 struct uart_8250_port *up = up_to_u8250p(up: port);
1887 unsigned int status;
1888 unsigned int val;
1889
1890 scoped_guard(serial8250_rpm, up)
1891 status = serial8250_modem_status(up);
1892
1893 val = serial8250_MSR_to_TIOCM(msr: status);
1894 if (up->gpios)
1895 return mctrl_gpio_get(gpios: up->gpios, mctrl: &val);
1896
1897 return val;
1898}
1899EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1900
1901static unsigned int serial8250_get_mctrl(struct uart_port *port)
1902{
1903 if (port->get_mctrl)
1904 return port->get_mctrl(port);
1905 return serial8250_do_get_mctrl(port);
1906}
1907
1908void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1909{
1910 struct uart_8250_port *up = up_to_u8250p(up: port);
1911 unsigned char mcr;
1912
1913 mcr = serial8250_TIOCM_to_MCR(tiocm: mctrl);
1914
1915 mcr |= up->mcr;
1916
1917 serial8250_out_MCR(up, value: mcr);
1918}
1919EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1920
1921static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1922{
1923 if (port->rs485.flags & SER_RS485_ENABLED)
1924 return;
1925
1926 if (port->set_mctrl)
1927 port->set_mctrl(port, mctrl);
1928 else
1929 serial8250_do_set_mctrl(port, mctrl);
1930}
1931
1932static void serial8250_break_ctl(struct uart_port *port, int break_state)
1933{
1934 struct uart_8250_port *up = up_to_u8250p(up: port);
1935
1936 guard(serial8250_rpm)(T: up);
1937 guard(uart_port_lock_irqsave)(l: port);
1938
1939 if (break_state == -1)
1940 up->lcr |= UART_LCR_SBC;
1941 else
1942 up->lcr &= ~UART_LCR_SBC;
1943 serial_port_out(up: port, UART_LCR, value: up->lcr);
1944}
1945
1946/* Returns true if @bits were set, false on timeout */
1947static bool wait_for_lsr(struct uart_8250_port *up, int bits)
1948{
1949 unsigned int status, tmout;
1950
1951 /*
1952 * Wait for a character to be sent. Fallback to a safe default
1953 * timeout value if @frame_time is not available.
1954 */
1955 if (up->port.frame_time)
1956 tmout = up->port.frame_time * 2 / NSEC_PER_USEC;
1957 else
1958 tmout = 10000;
1959
1960 for (;;) {
1961 status = serial_lsr_in(up);
1962
1963 if ((status & bits) == bits)
1964 break;
1965 if (--tmout == 0)
1966 break;
1967 udelay(usec: 1);
1968 touch_nmi_watchdog();
1969 }
1970
1971 return (tmout != 0);
1972}
1973
1974/* Wait for transmitter and holding register to empty with timeout */
1975static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1976{
1977 unsigned int tmout;
1978
1979 wait_for_lsr(up, bits);
1980
1981 /* Wait up to 1s for flow control if necessary */
1982 if (up->port.flags & UPF_CONS_FLOW) {
1983 for (tmout = 1000000; tmout; tmout--) {
1984 unsigned int msr = serial_in(up, UART_MSR);
1985 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1986 if (msr & UART_MSR_CTS)
1987 break;
1988 udelay(usec: 1);
1989 touch_nmi_watchdog();
1990 }
1991 }
1992}
1993
1994#ifdef CONFIG_CONSOLE_POLL
1995/*
1996 * Console polling routines for writing and reading from the uart while
1997 * in an interrupt or debug context.
1998 */
1999
2000static int serial8250_get_poll_char(struct uart_port *port)
2001{
2002 struct uart_8250_port *up = up_to_u8250p(port);
2003 u16 lsr;
2004
2005 guard(serial8250_rpm)(up);
2006
2007 lsr = serial_port_in(port, UART_LSR);
2008 if (!(lsr & UART_LSR_DR))
2009 return NO_POLL_CHAR;
2010
2011 return serial_port_in(port, UART_RX);
2012}
2013
2014
2015static void serial8250_put_poll_char(struct uart_port *port,
2016 unsigned char c)
2017{
2018 unsigned int ier;
2019 struct uart_8250_port *up = up_to_u8250p(port);
2020
2021 /*
2022 * Normally the port is locked to synchronize UART_IER access
2023 * against the console. However, this function is only used by
2024 * KDB/KGDB, where it may not be possible to acquire the port
2025 * lock because all other CPUs are quiesced. The quiescence
2026 * should allow safe lockless usage here.
2027 */
2028
2029 guard(serial8250_rpm)(up);
2030 /*
2031 * First save the IER then disable the interrupts
2032 */
2033 ier = serial_port_in(port, UART_IER);
2034 serial8250_clear_IER(up);
2035
2036 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2037 /*
2038 * Send the character out.
2039 */
2040 serial_port_out(port, UART_TX, c);
2041
2042 /*
2043 * Finally, wait for transmitter to become empty
2044 * and restore the IER
2045 */
2046 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2047 serial_port_out(port, UART_IER, ier);
2048}
2049
2050#endif /* CONFIG_CONSOLE_POLL */
2051
2052static void serial8250_startup_special(struct uart_port *port)
2053{
2054 struct uart_8250_port *up = up_to_u8250p(up: port);
2055
2056 switch (port->type) {
2057 case PORT_16C950: {
2058 /*
2059 * Wake up and initialize UART
2060 *
2061 * Synchronize UART_IER access against the console.
2062 */
2063 guard(uart_port_lock_irqsave)(l: port);
2064 up->acr = 0;
2065 serial_port_out(up: port, UART_LCR, UART_LCR_CONF_MODE_B);
2066 serial_port_out(up: port, UART_EFR, UART_EFR_ECB);
2067 serial_port_out(up: port, UART_IER, value: 0);
2068 serial_port_out(up: port, UART_LCR, value: 0);
2069 serial_icr_write(up, UART_CSR, value: 0); /* Reset the UART */
2070 serial_port_out(up: port, UART_LCR, UART_LCR_CONF_MODE_B);
2071 serial_port_out(up: port, UART_EFR, UART_EFR_ECB);
2072 serial_port_out(up: port, UART_LCR, value: 0);
2073 break;
2074 }
2075 case PORT_DA830:
2076 /*
2077 * Reset the port
2078 *
2079 * Synchronize UART_IER access against the console.
2080 */
2081 scoped_guard(uart_port_lock_irqsave, port) {
2082 serial_port_out(up: port, UART_IER, value: 0);
2083 serial_port_out(up: port, UART_DA830_PWREMU_MGMT, value: 0);
2084 }
2085 mdelay(10);
2086
2087 /* Enable Tx, Rx and free run mode */
2088 serial_port_out(up: port, UART_DA830_PWREMU_MGMT,
2089 UART_DA830_PWREMU_MGMT_UTRST |
2090 UART_DA830_PWREMU_MGMT_URRST |
2091 UART_DA830_PWREMU_MGMT_FREE);
2092 break;
2093 case PORT_RSA:
2094 rsa_enable(up);
2095 break;
2096 }
2097}
2098
2099static void serial8250_set_TRG_levels(struct uart_port *port)
2100{
2101 struct uart_8250_port *up = up_to_u8250p(up: port);
2102
2103 switch (port->type) {
2104 /* For a XR16C850, we need to set the trigger levels */
2105 case PORT_16850: {
2106 u8 fctr;
2107
2108 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2109
2110 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2111 fctr |= UART_FCTR_TRGD;
2112 serial_port_out(up: port, UART_FCTR, value: fctr | UART_FCTR_RX);
2113 serial_port_out(up: port, UART_TRG, UART_TRG_96);
2114 serial_port_out(up: port, UART_FCTR, value: fctr | UART_FCTR_TX);
2115 serial_port_out(up: port, UART_TRG, UART_TRG_96);
2116
2117 serial_port_out(up: port, UART_LCR, value: 0);
2118 break;
2119 }
2120 /* For the Altera 16550 variants, set TX threshold trigger level. */
2121 case PORT_ALTR_16550_F32:
2122 case PORT_ALTR_16550_F64:
2123 case PORT_ALTR_16550_F128:
2124 if (port->fifosize <= 1)
2125 return;
2126
2127 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2128 if (up->tx_loadsz < 2 || up->tx_loadsz > port->fifosize) {
2129 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2130 return;
2131 }
2132 serial_port_out(up: port, UART_ALTR_AFR, UART_ALTR_EN_TXFIFO_LW);
2133 serial_port_out(up: port, UART_ALTR_TX_LOW, value: port->fifosize - up->tx_loadsz);
2134 port->handle_irq = serial8250_tx_threshold_handle_irq;
2135 break;
2136 }
2137}
2138
2139static void serial8250_THRE_test(struct uart_port *port)
2140{
2141 struct uart_8250_port *up = up_to_u8250p(up: port);
2142 bool iir_noint1, iir_noint2;
2143
2144 if (!port->irq)
2145 return;
2146
2147 if (up->port.flags & UPF_NO_THRE_TEST)
2148 return;
2149
2150 if (port->irqflags & IRQF_SHARED)
2151 disable_irq_nosync(irq: port->irq);
2152
2153 /*
2154 * Test for UARTs that do not reassert THRE when the transmitter is idle and the interrupt
2155 * has already been cleared. Real 16550s should always reassert this interrupt whenever the
2156 * transmitter is idle and the interrupt is enabled. Delays are necessary to allow register
2157 * changes to become visible.
2158 *
2159 * Synchronize UART_IER access against the console.
2160 */
2161 scoped_guard(uart_port_lock_irqsave, port) {
2162 wait_for_xmitr(up, UART_LSR_THRE);
2163 serial_port_out_sync(p: port, UART_IER, UART_IER_THRI);
2164 udelay(usec: 1); /* allow THRE to set */
2165 iir_noint1 = serial_port_in(up: port, UART_IIR) & UART_IIR_NO_INT;
2166 serial_port_out(up: port, UART_IER, value: 0);
2167 serial_port_out_sync(p: port, UART_IER, UART_IER_THRI);
2168 udelay(usec: 1); /* allow a working UART time to re-assert THRE */
2169 iir_noint2 = serial_port_in(up: port, UART_IIR) & UART_IIR_NO_INT;
2170 serial_port_out(up: port, UART_IER, value: 0);
2171 }
2172
2173 if (port->irqflags & IRQF_SHARED)
2174 enable_irq(irq: port->irq);
2175
2176 /*
2177 * If the interrupt is not reasserted, or we otherwise don't trust the iir, setup a timer to
2178 * kick the UART on a regular basis.
2179 */
2180 if ((!iir_noint1 && iir_noint2) || up->port.flags & UPF_BUG_THRE)
2181 up->bugs |= UART_BUG_THRE;
2182}
2183
2184static void serial8250_init_mctrl(struct uart_port *port)
2185{
2186 if (port->flags & UPF_FOURPORT) {
2187 if (!port->irq)
2188 port->mctrl |= TIOCM_OUT1;
2189 } else {
2190 /* Most PC uarts need OUT2 raised to enable interrupts. */
2191 if (port->irq)
2192 port->mctrl |= TIOCM_OUT2;
2193 }
2194
2195 serial8250_set_mctrl(port, mctrl: port->mctrl);
2196}
2197
2198static void serial8250_iir_txen_test(struct uart_port *port)
2199{
2200 struct uart_8250_port *up = up_to_u8250p(up: port);
2201 bool lsr_temt, iir_noint;
2202
2203 if (port->quirks & UPQ_NO_TXEN_TEST)
2204 return;
2205
2206 /* Do a quick test to see if we receive an interrupt when we enable the TX irq. */
2207 serial_port_out(up: port, UART_IER, UART_IER_THRI);
2208 lsr_temt = serial_port_in(up: port, UART_LSR) & UART_LSR_TEMT;
2209 iir_noint = serial_port_in(up: port, UART_IIR) & UART_IIR_NO_INT;
2210 serial_port_out(up: port, UART_IER, value: 0);
2211
2212 /*
2213 * Serial over Lan (SoL) hack:
2214 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be used for Serial Over
2215 * Lan. Those chips take a longer time than a normal serial device to signalize that a
2216 * transmission data was queued. Due to that, the above test generally fails. One solution
2217 * would be to delay the reading of iir. However, this is not reliable, since the timeout is
2218 * variable. So, in case of UPQ_NO_TXEN_TEST, let's just don't test if we receive TX irq.
2219 * This way, we'll never enable UART_BUG_TXEN.
2220 */
2221 if (lsr_temt && iir_noint) {
2222 if (!(up->bugs & UART_BUG_TXEN)) {
2223 up->bugs |= UART_BUG_TXEN;
2224 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2225 }
2226 return;
2227 }
2228
2229 /* FIXME: why is this needed? */
2230 up->bugs &= ~UART_BUG_TXEN;
2231}
2232
2233static void serial8250_initialize(struct uart_port *port)
2234{
2235 guard(uart_port_lock_irqsave)(l: port);
2236 serial_port_out(up: port, UART_LCR, UART_LCR_WLEN8);
2237
2238 serial8250_init_mctrl(port);
2239 serial8250_iir_txen_test(port);
2240}
2241
2242int serial8250_do_startup(struct uart_port *port)
2243{
2244 struct uart_8250_port *up = up_to_u8250p(up: port);
2245 int retval;
2246
2247 if (!port->fifosize)
2248 port->fifosize = uart_config[port->type].fifo_size;
2249 if (!up->tx_loadsz)
2250 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2251 if (!up->capabilities)
2252 up->capabilities = uart_config[port->type].flags;
2253 up->mcr = 0;
2254
2255 if (port->iotype != up->cur_iotype)
2256 set_io_from_upio(port);
2257
2258 guard(serial8250_rpm)(T: up);
2259
2260 serial8250_startup_special(port);
2261
2262 /*
2263 * Clear the FIFO buffers and disable them.
2264 * (they will be reenabled in set_termios())
2265 */
2266 serial8250_clear_fifos(p: up);
2267
2268 serial8250_clear_interrupts(port);
2269
2270 /*
2271 * At this point, there's no way the LSR could still be 0xff;
2272 * if it is, then bail out, because there's likely no UART
2273 * here.
2274 */
2275 if (!(port->flags & UPF_BUGGY_UART) &&
2276 (serial_port_in(up: port, UART_LSR) == 0xff)) {
2277 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2278 return -ENODEV;
2279 }
2280
2281 serial8250_set_TRG_levels(port);
2282
2283 /* Check if we need to have shared IRQs */
2284 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2285 up->port.irqflags |= IRQF_SHARED;
2286
2287 retval = up->ops->setup_irq(up);
2288 if (retval)
2289 return retval;
2290
2291 serial8250_THRE_test(port);
2292
2293 up->ops->setup_timer(up);
2294
2295 serial8250_initialize(port);
2296
2297 /*
2298 * Clear the interrupt registers again for luck, and clear the
2299 * saved flags to avoid getting false values from polling
2300 * routines or the previous session.
2301 */
2302 serial8250_clear_interrupts(port);
2303 up->lsr_saved_flags = 0;
2304 up->msr_saved_flags = 0;
2305
2306 /*
2307 * Request DMA channels for both RX and TX.
2308 */
2309 if (up->dma) {
2310 const char *msg = NULL;
2311
2312 if (uart_console(port))
2313 msg = "forbid DMA for kernel console";
2314 else if (serial8250_request_dma(up))
2315 msg = "failed to request DMA";
2316 if (msg) {
2317 dev_warn_ratelimited(port->dev, "%s\n", msg);
2318 up->dma = NULL;
2319 }
2320 }
2321
2322 /*
2323 * Set the IER shadow for rx interrupts but defer actual interrupt
2324 * enable until after the FIFOs are enabled; otherwise, an already-
2325 * active sender can swamp the interrupt handler with "too much work".
2326 */
2327 up->ier = UART_IER_RLSI | UART_IER_RDI;
2328
2329 if (port->flags & UPF_FOURPORT) {
2330 unsigned int icp;
2331 /*
2332 * Enable interrupts on the AST Fourport board
2333 */
2334 icp = (port->iobase & 0xfe0) | 0x01f;
2335 outb_p(value: 0x80, port: icp);
2336 inb_p(port: icp);
2337 }
2338
2339 return 0;
2340}
2341EXPORT_SYMBOL_GPL(serial8250_do_startup);
2342
2343static int serial8250_startup(struct uart_port *port)
2344{
2345 if (port->startup)
2346 return port->startup(port);
2347 return serial8250_do_startup(port);
2348}
2349
2350void serial8250_do_shutdown(struct uart_port *port)
2351{
2352 struct uart_8250_port *up = up_to_u8250p(up: port);
2353
2354 serial8250_rpm_get(up);
2355 /*
2356 * Disable interrupts from this port
2357 *
2358 * Synchronize UART_IER access against the console.
2359 */
2360 scoped_guard(uart_port_lock_irqsave, port) {
2361 up->ier = 0;
2362 serial_port_out(up: port, UART_IER, value: 0);
2363 }
2364
2365 synchronize_irq(irq: port->irq);
2366
2367 if (up->dma)
2368 serial8250_release_dma(up);
2369
2370 scoped_guard(uart_port_lock_irqsave, port) {
2371 if (port->flags & UPF_FOURPORT) {
2372 /* reset interrupts on the AST Fourport board */
2373 inb(port: (port->iobase & 0xfe0) | 0x1f);
2374 port->mctrl |= TIOCM_OUT1;
2375 } else
2376 port->mctrl &= ~TIOCM_OUT2;
2377
2378 serial8250_set_mctrl(port, mctrl: port->mctrl);
2379 }
2380
2381 /*
2382 * Disable break condition and FIFOs
2383 */
2384 serial_port_out(up: port, UART_LCR,
2385 value: serial_port_in(up: port, UART_LCR) & ~UART_LCR_SBC);
2386 serial8250_clear_fifos(p: up);
2387
2388 rsa_disable(up);
2389
2390 /*
2391 * Read data port to reset things, and then unlink from
2392 * the IRQ chain.
2393 */
2394 serial_port_in(up: port, UART_RX);
2395 serial8250_rpm_put(up);
2396
2397 up->ops->release_irq(up);
2398}
2399EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2400
2401static void serial8250_shutdown(struct uart_port *port)
2402{
2403 if (port->shutdown)
2404 port->shutdown(port);
2405 else
2406 serial8250_do_shutdown(port);
2407}
2408
2409static void serial8250_flush_buffer(struct uart_port *port)
2410{
2411 struct uart_8250_port *up = up_to_u8250p(up: port);
2412
2413 if (up->dma)
2414 serial8250_tx_dma_flush(up);
2415}
2416
2417static unsigned int serial8250_do_get_divisor(struct uart_port *port, unsigned int baud)
2418{
2419 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2420 struct uart_8250_port *up = up_to_u8250p(up: port);
2421 unsigned int quot;
2422
2423 /*
2424 * Handle magic divisors for baud rates above baud_base on SMSC
2425 * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2426 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2427 * magic divisors actually reprogram the baud rate generator's
2428 * reference clock derived from chips's 14.318MHz clock input.
2429 *
2430 * Documentation claims that with these magic divisors the base
2431 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2432 * for the extra baud rates of 460800bps and 230400bps rather
2433 * than the usual base frequency of 1.8462MHz. However empirical
2434 * evidence contradicts that.
2435 *
2436 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2437 * effectively used as a clock prescaler selection bit for the
2438 * base frequency of 7.3728MHz, always used. If set to 0, then
2439 * the base frequency is divided by 4 for use by the Baud Rate
2440 * Generator, for the usual arrangement where the value of 1 of
2441 * the divisor produces the baud rate of 115200bps. Conversely,
2442 * if set to 1 and high-speed operation has been enabled with the
2443 * Serial Port Mode Register in the Device Configuration Space,
2444 * then the base frequency is supplied directly to the Baud Rate
2445 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2446 * 0x8004, etc. the respective baud rates produced are 460800bps,
2447 * 230400bps, 153600bps, 115200bps, etc.
2448 *
2449 * In all cases only low 15 bits of the divisor are used to divide
2450 * the baud base and therefore 32767 is the maximum divisor value
2451 * possible, even though documentation says that the programmable
2452 * Baud Rate Generator is capable of dividing the internal PLL
2453 * clock by any divisor from 1 to 65535.
2454 */
2455 if (magic_multiplier && baud >= port->uartclk / 6)
2456 quot = 0x8001;
2457 else if (magic_multiplier && baud >= port->uartclk / 12)
2458 quot = 0x8002;
2459 else
2460 quot = uart_get_divisor(port, baud);
2461
2462 /*
2463 * Oxford Semi 952 rev B workaround
2464 */
2465 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2466 quot++;
2467
2468 return quot;
2469}
2470
2471static unsigned int serial8250_get_divisor(struct uart_port *port,
2472 unsigned int baud,
2473 unsigned int *frac)
2474{
2475 if (port->get_divisor)
2476 return port->get_divisor(port, baud, frac);
2477
2478 return serial8250_do_get_divisor(port, baud);
2479}
2480
2481static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, tcflag_t c_cflag)
2482{
2483 u8 lcr = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2484
2485 if (c_cflag & CSTOPB)
2486 lcr |= UART_LCR_STOP;
2487 if (c_cflag & PARENB)
2488 lcr |= UART_LCR_PARITY;
2489 if (!(c_cflag & PARODD))
2490 lcr |= UART_LCR_EPAR;
2491 if (c_cflag & CMSPAR)
2492 lcr |= UART_LCR_SPAR;
2493
2494 return lcr;
2495}
2496
2497void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2498 unsigned int quot)
2499{
2500 struct uart_8250_port *up = up_to_u8250p(up: port);
2501
2502 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2503 if (is_omap1510_8250(pt: up)) {
2504 if (baud == 115200) {
2505 quot = 1;
2506 serial_port_out(up: port, UART_OMAP_OSC_12M_SEL, value: 1);
2507 } else
2508 serial_port_out(up: port, UART_OMAP_OSC_12M_SEL, value: 0);
2509 }
2510
2511 /*
2512 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2513 * otherwise just set DLAB
2514 */
2515 if (up->capabilities & UART_NATSEMI)
2516 serial_port_out(up: port, UART_LCR, value: 0xe0);
2517 else
2518 serial_port_out(up: port, UART_LCR, value: up->lcr | UART_LCR_DLAB);
2519
2520 serial_dl_write(up, value: quot);
2521}
2522EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2523
2524static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2525 unsigned int quot, unsigned int quot_frac)
2526{
2527 if (port->set_divisor)
2528 port->set_divisor(port, baud, quot, quot_frac);
2529 else
2530 serial8250_do_set_divisor(port, baud, quot);
2531}
2532
2533static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2534 struct ktermios *termios,
2535 const struct ktermios *old)
2536{
2537 unsigned int tolerance = port->uartclk / 100;
2538 unsigned int min;
2539 unsigned int max;
2540
2541 /*
2542 * Handle magic divisors for baud rates above baud_base on SMSC
2543 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2544 * disable divisor values beyond 32767, which are unavailable.
2545 */
2546 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2547 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2548 max = (port->uartclk + tolerance) / 4;
2549 } else {
2550 min = port->uartclk / 16 / UART_DIV_MAX;
2551 max = (port->uartclk + tolerance) / 16;
2552 }
2553
2554 /*
2555 * Ask the core to calculate the divisor for us.
2556 * Allow 1% tolerance at the upper limit so uart clks marginally
2557 * slower than nominal still match standard baud rates without
2558 * causing transmission errors.
2559 */
2560 return uart_get_baud_rate(port, termios, old, min, max);
2561}
2562
2563/*
2564 * Note in order to avoid the tty port mutex deadlock don't use the next method
2565 * within the uart port callbacks. Primarily it's supposed to be utilized to
2566 * handle a sudden reference clock rate change.
2567 */
2568void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2569{
2570 struct tty_port *tport = &port->state->port;
2571
2572 scoped_guard(tty_port_tty, tport) {
2573 struct tty_struct *tty = scoped_tty();
2574
2575 guard(rwsem_write)(T: &tty->termios_rwsem);
2576 guard(mutex)(T: &tport->mutex);
2577
2578 if (port->uartclk == uartclk)
2579 return;
2580
2581 port->uartclk = uartclk;
2582
2583 if (!tty_port_initialized(port: tport))
2584 return;
2585
2586 serial8250_do_set_termios(port, termios: &tty->termios, NULL);
2587
2588 return;
2589 }
2590 guard(mutex)(T: &tport->mutex);
2591 port->uartclk = uartclk;
2592}
2593EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2594
2595static void serial8250_set_mini(struct uart_port *port, struct ktermios *termios)
2596{
2597 struct uart_8250_port *up = up_to_u8250p(up: port);
2598
2599 if (!(up->capabilities & UART_CAP_MINI))
2600 return;
2601
2602 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2603
2604 tcflag_t csize = termios->c_cflag & CSIZE;
2605 if (csize == CS5 || csize == CS6) {
2606 termios->c_cflag &= ~CSIZE;
2607 termios->c_cflag |= CS7;
2608 }
2609}
2610
2611static void serial8250_set_trigger_for_slow_speed(struct uart_port *port, struct ktermios *termios,
2612 unsigned int baud)
2613{
2614 struct uart_8250_port *up = up_to_u8250p(up: port);
2615
2616 if (!(up->capabilities & UART_CAP_FIFO))
2617 return;
2618 if (port->fifosize <= 1)
2619 return;
2620 if (baud >= 2400)
2621 return;
2622 if (up->dma)
2623 return;
2624
2625 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2626 up->fcr |= UART_FCR_TRIGGER_1;
2627}
2628
2629/*
2630 * MCR-based auto flow control. When AFE is enabled, RTS will be deasserted when the receive FIFO
2631 * contains more characters than the trigger, or the MCR RTS bit is cleared.
2632 */
2633static void serial8250_set_afe(struct uart_port *port, struct ktermios *termios)
2634{
2635 struct uart_8250_port *up = up_to_u8250p(up: port);
2636
2637 if (!(up->capabilities & UART_CAP_AFE))
2638 return;
2639
2640 up->mcr &= ~UART_MCR_AFE;
2641 if (termios->c_cflag & CRTSCTS)
2642 up->mcr |= UART_MCR_AFE;
2643}
2644
2645static void serial8250_set_errors_and_ignores(struct uart_port *port, struct ktermios *termios)
2646{
2647 /*
2648 * Specify which conditions may be considered for error handling and the ignoring of
2649 * characters. The actual ignoring of characters only occurs if the bit is set in
2650 * @ignore_status_mask as well.
2651 */
2652 port->read_status_mask = UART_LSR_OE | UART_LSR_DR;
2653 if (termios->c_iflag & INPCK)
2654 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2655 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2656 port->read_status_mask |= UART_LSR_BI;
2657
2658 /* Characters to ignore */
2659 port->ignore_status_mask = 0;
2660 if (termios->c_iflag & IGNPAR)
2661 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2662 if (termios->c_iflag & IGNBRK) {
2663 port->ignore_status_mask |= UART_LSR_BI;
2664 /*
2665 * If we're ignoring parity and break indicators, ignore overruns too (for real raw
2666 * support).
2667 */
2668 if (termios->c_iflag & IGNPAR)
2669 port->ignore_status_mask |= UART_LSR_OE;
2670 }
2671
2672 /* ignore all characters if CREAD is not set */
2673 if ((termios->c_cflag & CREAD) == 0)
2674 port->ignore_status_mask |= UART_LSR_DR;
2675}
2676
2677static void serial8250_set_ier(struct uart_port *port, struct ktermios *termios)
2678{
2679 struct uart_8250_port *up = up_to_u8250p(up: port);
2680
2681 /* CTS flow control flag and modem status interrupts */
2682 up->ier &= ~UART_IER_MSI;
2683 if (!(up->bugs & UART_BUG_NOMSR) && UART_ENABLE_MS(&up->port, termios->c_cflag))
2684 up->ier |= UART_IER_MSI;
2685 if (up->capabilities & UART_CAP_UUE)
2686 up->ier |= UART_IER_UUE;
2687 if (up->capabilities & UART_CAP_RTOIE)
2688 up->ier |= UART_IER_RTOIE;
2689
2690 serial_port_out(up: port, UART_IER, value: up->ier);
2691}
2692
2693static void serial8250_set_efr(struct uart_port *port, struct ktermios *termios)
2694{
2695 struct uart_8250_port *up = up_to_u8250p(up: port);
2696 u8 efr_reg = UART_EFR;
2697 u8 efr = 0;
2698
2699 if (!(up->capabilities & UART_CAP_EFR))
2700 return;
2701
2702 /*
2703 * TI16C752/Startech hardware flow control. FIXME:
2704 * - TI16C752 requires control thresholds to be set.
2705 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2706 */
2707 if (termios->c_cflag & CRTSCTS)
2708 efr |= UART_EFR_CTS;
2709
2710 if (port->flags & UPF_EXAR_EFR)
2711 efr_reg = UART_XR_EFR;
2712
2713 serial_port_out(up: port, UART_LCR, UART_LCR_CONF_MODE_B);
2714 serial_port_out(up: port, offset: efr_reg, value: efr);
2715}
2716
2717static void serial8250_set_fcr(struct uart_port *port, struct ktermios *termios)
2718{
2719 struct uart_8250_port *up = up_to_u8250p(up: port);
2720 bool is_16750 = port->type == PORT_16750;
2721
2722 if (is_16750)
2723 serial_port_out(up: port, UART_FCR, value: up->fcr);
2724
2725 /*
2726 * LCR DLAB must be reset to enable 64-byte FIFO mode. If the FCR is written without DLAB
2727 * set, this mode will be disabled.
2728 */
2729 serial_port_out(up: port, UART_LCR, value: up->lcr);
2730
2731 if (is_16750)
2732 return;
2733
2734 /* emulated UARTs (Lucent Venus 167x) need two steps */
2735 if (up->fcr & UART_FCR_ENABLE_FIFO)
2736 serial_port_out(up: port, UART_FCR, UART_FCR_ENABLE_FIFO);
2737
2738 serial_port_out(up: port, UART_FCR, value: up->fcr);
2739}
2740
2741void
2742serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2743 const struct ktermios *old)
2744{
2745 struct uart_8250_port *up = up_to_u8250p(up: port);
2746 unsigned int baud, quot, frac = 0;
2747 u8 lcr;
2748
2749 serial8250_set_mini(port, termios);
2750 lcr = serial8250_compute_lcr(up, c_cflag: termios->c_cflag);
2751 baud = serial8250_get_baud_rate(port, termios, old);
2752 quot = serial8250_get_divisor(port, baud, frac: &frac);
2753
2754 /*
2755 * Ok, we're now changing the port state. Do it with interrupts disabled.
2756 *
2757 * Synchronize UART_IER access against the console.
2758 */
2759 scoped_guard(serial8250_rpm, up) {
2760 guard(uart_port_lock_irqsave)(l: port);
2761
2762 up->lcr = lcr;
2763 serial8250_set_trigger_for_slow_speed(port, termios, baud);
2764 serial8250_set_afe(port, termios);
2765 uart_update_timeout(port, cflag: termios->c_cflag, baud);
2766 serial8250_set_errors_and_ignores(port, termios);
2767 serial8250_set_ier(port, termios);
2768 serial8250_set_efr(port, termios);
2769 serial8250_set_divisor(port, baud, quot, quot_frac: frac);
2770 serial8250_set_fcr(port, termios);
2771 serial8250_set_mctrl(port, mctrl: port->mctrl);
2772 }
2773
2774 /* Don't rewrite B0 */
2775 if (tty_termios_baud_rate(termios))
2776 tty_termios_encode_baud_rate(termios, ibaud: baud, obaud: baud);
2777}
2778EXPORT_SYMBOL(serial8250_do_set_termios);
2779
2780static void
2781serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2782 const struct ktermios *old)
2783{
2784 if (port->set_termios)
2785 port->set_termios(port, termios, old);
2786 else
2787 serial8250_do_set_termios(port, termios, old);
2788}
2789
2790void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2791{
2792 if (termios->c_line == N_PPS) {
2793 port->flags |= UPF_HARDPPS_CD;
2794 guard(uart_port_lock_irq)(T: port);
2795 serial8250_enable_ms(port);
2796 } else {
2797 port->flags &= ~UPF_HARDPPS_CD;
2798 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2799 guard(uart_port_lock_irq)(T: port);
2800 serial8250_disable_ms(port);
2801 }
2802 }
2803}
2804EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2805
2806static void
2807serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2808{
2809 if (port->set_ldisc)
2810 port->set_ldisc(port, termios);
2811 else
2812 serial8250_do_set_ldisc(port, termios);
2813}
2814
2815void serial8250_do_pm(struct uart_port *port, unsigned int state,
2816 unsigned int oldstate)
2817{
2818 struct uart_8250_port *p = up_to_u8250p(up: port);
2819
2820 serial8250_set_sleep(p, sleep: state != 0);
2821}
2822EXPORT_SYMBOL(serial8250_do_pm);
2823
2824static void
2825serial8250_pm(struct uart_port *port, unsigned int state,
2826 unsigned int oldstate)
2827{
2828 if (port->pm)
2829 port->pm(port, state, oldstate);
2830 else
2831 serial8250_do_pm(port, state, oldstate);
2832}
2833
2834static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2835{
2836 if (pt->port.mapsize)
2837 return pt->port.mapsize;
2838 if (is_omap1_8250(pt))
2839 return 0x16 << pt->port.regshift;
2840
2841 return 8 << pt->port.regshift;
2842}
2843
2844/*
2845 * Resource handling.
2846 */
2847static int serial8250_request_std_resource(struct uart_8250_port *up)
2848{
2849 unsigned int size = serial8250_port_size(pt: up);
2850 struct uart_port *port = &up->port;
2851
2852 switch (port->iotype) {
2853 case UPIO_AU:
2854 case UPIO_TSI:
2855 case UPIO_MEM32:
2856 case UPIO_MEM32BE:
2857 case UPIO_MEM16:
2858 case UPIO_MEM:
2859 if (!port->mapbase)
2860 return -EINVAL;
2861
2862 if (!request_mem_region(port->mapbase, size, "serial"))
2863 return -EBUSY;
2864
2865 if (port->flags & UPF_IOREMAP) {
2866 port->membase = ioremap(offset: port->mapbase, size);
2867 if (!port->membase) {
2868 release_mem_region(port->mapbase, size);
2869 return -ENOMEM;
2870 }
2871 }
2872 return 0;
2873 case UPIO_HUB6:
2874 case UPIO_PORT:
2875 if (!request_region(port->iobase, size, "serial"))
2876 return -EBUSY;
2877 return 0;
2878 case UPIO_UNKNOWN:
2879 break;
2880 }
2881
2882 return 0;
2883}
2884
2885static void serial8250_release_std_resource(struct uart_8250_port *up)
2886{
2887 unsigned int size = serial8250_port_size(pt: up);
2888 struct uart_port *port = &up->port;
2889
2890 switch (port->iotype) {
2891 case UPIO_AU:
2892 case UPIO_TSI:
2893 case UPIO_MEM32:
2894 case UPIO_MEM32BE:
2895 case UPIO_MEM16:
2896 case UPIO_MEM:
2897 if (!port->mapbase)
2898 break;
2899
2900 if (port->flags & UPF_IOREMAP) {
2901 iounmap(addr: port->membase);
2902 port->membase = NULL;
2903 }
2904
2905 release_mem_region(port->mapbase, size);
2906 break;
2907
2908 case UPIO_HUB6:
2909 case UPIO_PORT:
2910 release_region(port->iobase, size);
2911 break;
2912 case UPIO_UNKNOWN:
2913 break;
2914 }
2915}
2916
2917static void serial8250_release_port(struct uart_port *port)
2918{
2919 struct uart_8250_port *up = up_to_u8250p(up: port);
2920
2921 serial8250_release_std_resource(up);
2922}
2923
2924static int serial8250_request_port(struct uart_port *port)
2925{
2926 struct uart_8250_port *up = up_to_u8250p(up: port);
2927
2928 return serial8250_request_std_resource(up);
2929}
2930
2931static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2932{
2933 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2934 unsigned char bytes;
2935
2936 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2937
2938 return bytes ? bytes : -EOPNOTSUPP;
2939}
2940
2941static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2942{
2943 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2944 int i;
2945
2946 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2947 return -EOPNOTSUPP;
2948
2949 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2950 if (bytes < conf_type->rxtrig_bytes[i])
2951 /* Use the nearest lower value */
2952 return (--i) << UART_FCR_R_TRIG_SHIFT;
2953 }
2954
2955 return UART_FCR_R_TRIG_11;
2956}
2957
2958static int do_get_rxtrig(struct tty_port *port)
2959{
2960 struct uart_state *state = container_of(port, struct uart_state, port);
2961 struct uart_port *uport = state->uart_port;
2962 struct uart_8250_port *up = up_to_u8250p(up: uport);
2963
2964 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2965 return -EINVAL;
2966
2967 return fcr_get_rxtrig_bytes(up);
2968}
2969
2970static int do_serial8250_get_rxtrig(struct tty_port *port)
2971{
2972 int rxtrig_bytes;
2973
2974 mutex_lock(lock: &port->mutex);
2975 rxtrig_bytes = do_get_rxtrig(port);
2976 mutex_unlock(lock: &port->mutex);
2977
2978 return rxtrig_bytes;
2979}
2980
2981static ssize_t rx_trig_bytes_show(struct device *dev,
2982 struct device_attribute *attr, char *buf)
2983{
2984 struct tty_port *port = dev_get_drvdata(dev);
2985 int rxtrig_bytes;
2986
2987 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2988 if (rxtrig_bytes < 0)
2989 return rxtrig_bytes;
2990
2991 return sysfs_emit(buf, fmt: "%d\n", rxtrig_bytes);
2992}
2993
2994static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2995{
2996 struct uart_state *state = container_of(port, struct uart_state, port);
2997 struct uart_port *uport = state->uart_port;
2998 struct uart_8250_port *up = up_to_u8250p(up: uport);
2999 int rxtrig;
3000
3001 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3002 return -EINVAL;
3003
3004 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3005 if (rxtrig < 0)
3006 return rxtrig;
3007
3008 serial8250_clear_fifos(p: up);
3009 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3010 up->fcr |= (unsigned char)rxtrig;
3011 serial_out(up, UART_FCR, value: up->fcr);
3012 return 0;
3013}
3014
3015static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3016{
3017 int ret;
3018
3019 mutex_lock(lock: &port->mutex);
3020 ret = do_set_rxtrig(port, bytes);
3021 mutex_unlock(lock: &port->mutex);
3022
3023 return ret;
3024}
3025
3026static ssize_t rx_trig_bytes_store(struct device *dev,
3027 struct device_attribute *attr, const char *buf, size_t count)
3028{
3029 struct tty_port *port = dev_get_drvdata(dev);
3030 unsigned char bytes;
3031 int ret;
3032
3033 if (!count)
3034 return -EINVAL;
3035
3036 ret = kstrtou8(s: buf, base: 10, res: &bytes);
3037 if (ret < 0)
3038 return ret;
3039
3040 ret = do_serial8250_set_rxtrig(port, bytes);
3041 if (ret < 0)
3042 return ret;
3043
3044 return count;
3045}
3046
3047static DEVICE_ATTR_RW(rx_trig_bytes);
3048
3049static struct attribute *serial8250_dev_attrs[] = {
3050 &dev_attr_rx_trig_bytes.attr,
3051 NULL
3052};
3053
3054static struct attribute_group serial8250_dev_attr_group = {
3055 .attrs = serial8250_dev_attrs,
3056};
3057
3058static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3059{
3060 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3061
3062 if (conf_type->rxtrig_bytes[0])
3063 up->port.attr_group = &serial8250_dev_attr_group;
3064}
3065
3066static void serial8250_config_port(struct uart_port *port, int flags)
3067{
3068 struct uart_8250_port *up = up_to_u8250p(up: port);
3069 int ret;
3070
3071 /*
3072 * Find the region that we can probe for. This in turn
3073 * tells us whether we can probe for the type of port.
3074 */
3075 ret = serial8250_request_std_resource(up);
3076 if (ret < 0)
3077 return;
3078
3079 if (port->iotype != up->cur_iotype)
3080 set_io_from_upio(port);
3081
3082 if (flags & UART_CONFIG_TYPE)
3083 autoconfig(up);
3084
3085 /* HW bugs may trigger IRQ while IIR == NO_INT */
3086 if (port->type == PORT_TEGRA)
3087 up->bugs |= UART_BUG_NOMSR;
3088
3089 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3090 autoconfig_irq(up);
3091
3092 if (port->type == PORT_UNKNOWN)
3093 serial8250_release_std_resource(up);
3094
3095 register_dev_spec_attr_grp(up);
3096 up->fcr = uart_config[up->port.type].fcr;
3097}
3098
3099static int
3100serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3101{
3102 if (ser->irq >= irq_get_nr_irqs() || ser->irq < 0 ||
3103 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3104 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3105 ser->type == PORT_STARTECH)
3106 return -EINVAL;
3107 return 0;
3108}
3109
3110static const char *serial8250_type(struct uart_port *port)
3111{
3112 int type = port->type;
3113
3114 if (type >= ARRAY_SIZE(uart_config))
3115 type = 0;
3116 return uart_config[type].name;
3117}
3118
3119static const struct uart_ops serial8250_pops = {
3120 .tx_empty = serial8250_tx_empty,
3121 .set_mctrl = serial8250_set_mctrl,
3122 .get_mctrl = serial8250_get_mctrl,
3123 .stop_tx = serial8250_stop_tx,
3124 .start_tx = serial8250_start_tx,
3125 .throttle = serial8250_throttle,
3126 .unthrottle = serial8250_unthrottle,
3127 .stop_rx = serial8250_stop_rx,
3128 .enable_ms = serial8250_enable_ms,
3129 .break_ctl = serial8250_break_ctl,
3130 .startup = serial8250_startup,
3131 .shutdown = serial8250_shutdown,
3132 .flush_buffer = serial8250_flush_buffer,
3133 .set_termios = serial8250_set_termios,
3134 .set_ldisc = serial8250_set_ldisc,
3135 .pm = serial8250_pm,
3136 .type = serial8250_type,
3137 .release_port = serial8250_release_port,
3138 .request_port = serial8250_request_port,
3139 .config_port = serial8250_config_port,
3140 .verify_port = serial8250_verify_port,
3141#ifdef CONFIG_CONSOLE_POLL
3142 .poll_get_char = serial8250_get_poll_char,
3143 .poll_put_char = serial8250_put_poll_char,
3144#endif
3145};
3146
3147void serial8250_init_port(struct uart_8250_port *up)
3148{
3149 struct uart_port *port = &up->port;
3150
3151 spin_lock_init(&port->lock);
3152 port->ctrl_id = 0;
3153 port->pm = NULL;
3154 port->ops = &serial8250_pops;
3155 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3156
3157 up->cur_iotype = UPIO_UNKNOWN;
3158}
3159EXPORT_SYMBOL_GPL(serial8250_init_port);
3160
3161void serial8250_set_defaults(struct uart_8250_port *up)
3162{
3163 struct uart_port *port = &up->port;
3164
3165 if (up->port.flags & UPF_FIXED_TYPE) {
3166 unsigned int type = up->port.type;
3167
3168 if (!up->port.fifosize)
3169 up->port.fifosize = uart_config[type].fifo_size;
3170 if (!up->tx_loadsz)
3171 up->tx_loadsz = uart_config[type].tx_loadsz;
3172 if (!up->capabilities)
3173 up->capabilities = uart_config[type].flags;
3174 }
3175
3176 set_io_from_upio(port);
3177
3178 /* default dma handlers */
3179 if (up->dma) {
3180 if (!up->dma->tx_dma)
3181 up->dma->tx_dma = serial8250_tx_dma;
3182 if (!up->dma->rx_dma)
3183 up->dma->rx_dma = serial8250_rx_dma;
3184 }
3185}
3186EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3187
3188#ifdef CONFIG_SERIAL_8250_CONSOLE
3189
3190static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3191{
3192 serial_port_out(up: port, UART_TX, value: ch);
3193}
3194
3195static void serial8250_console_wait_putchar(struct uart_port *port, unsigned char ch)
3196{
3197 struct uart_8250_port *up = up_to_u8250p(up: port);
3198
3199 wait_for_xmitr(up, UART_LSR_THRE);
3200 serial8250_console_putchar(port, ch);
3201}
3202
3203/*
3204 * Restore serial console when h/w power-off detected
3205 */
3206static void serial8250_console_restore(struct uart_8250_port *up)
3207{
3208 struct uart_port *port = &up->port;
3209 struct ktermios termios;
3210 unsigned int baud, quot, frac = 0;
3211
3212 termios.c_cflag = port->cons->cflag;
3213 termios.c_ispeed = port->cons->ispeed;
3214 termios.c_ospeed = port->cons->ospeed;
3215 if (port->state->port.tty && termios.c_cflag == 0) {
3216 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3217 termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3218 termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3219 }
3220
3221 baud = serial8250_get_baud_rate(port, termios: &termios, NULL);
3222 quot = serial8250_get_divisor(port, baud, frac: &frac);
3223
3224 serial8250_set_divisor(port, baud, quot, quot_frac: frac);
3225 serial_port_out(up: port, UART_LCR, value: up->lcr);
3226 serial8250_out_MCR(up, value: up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3227}
3228
3229static void fifo_wait_for_lsr(struct uart_8250_port *up, unsigned int count)
3230{
3231 unsigned int i;
3232
3233 for (i = 0; i < count; i++) {
3234 if (wait_for_lsr(up, UART_LSR_THRE))
3235 return;
3236 }
3237}
3238
3239/*
3240 * Print a string to the serial port using the device FIFO
3241 *
3242 * It sends fifosize bytes and then waits for the fifo
3243 * to get empty.
3244 */
3245static void serial8250_console_fifo_write(struct uart_8250_port *up,
3246 const char *s, unsigned int count)
3247{
3248 const char *end = s + count;
3249 unsigned int fifosize = up->tx_loadsz;
3250 struct uart_port *port = &up->port;
3251 unsigned int tx_count = 0;
3252 bool cr_sent = false;
3253 unsigned int i;
3254
3255 while (s != end) {
3256 /* Allow timeout for each byte of a possibly full FIFO */
3257 fifo_wait_for_lsr(up, count: fifosize);
3258
3259 for (i = 0; i < fifosize && s != end; ++i) {
3260 if (*s == '\n' && !cr_sent) {
3261 serial8250_console_putchar(port, ch: '\r');
3262 cr_sent = true;
3263 } else {
3264 serial8250_console_putchar(port, ch: *s++);
3265 cr_sent = false;
3266 }
3267 }
3268 tx_count = i;
3269 }
3270
3271 /*
3272 * Allow timeout for each byte written since the caller will only wait
3273 * for UART_LSR_BOTH_EMPTY using the timeout of a single character
3274 */
3275 fifo_wait_for_lsr(up, count: tx_count);
3276}
3277
3278/*
3279 * Print a string to the serial port trying not to disturb
3280 * any possible real use of the port...
3281 *
3282 * The console_lock must be held when we get here.
3283 *
3284 * Doing runtime PM is really a bad idea for the kernel console.
3285 * Thus, we assume the function is called when device is powered up.
3286 */
3287void serial8250_console_write(struct uart_8250_port *up, const char *s,
3288 unsigned int count)
3289{
3290 struct uart_8250_em485 *em485 = up->em485;
3291 struct uart_port *port = &up->port;
3292 unsigned long flags;
3293 unsigned int ier, use_fifo;
3294 int locked = 1;
3295
3296 touch_nmi_watchdog();
3297
3298 if (oops_in_progress)
3299 locked = uart_port_trylock_irqsave(up: port, flags: &flags);
3300 else
3301 uart_port_lock_irqsave(up: port, flags: &flags);
3302
3303 /*
3304 * First save the IER then disable the interrupts
3305 */
3306 ier = serial_port_in(up: port, UART_IER);
3307 serial8250_clear_IER(up);
3308
3309 /* check scratch reg to see if port powered off during system sleep */
3310 if (up->canary && (up->canary != serial_port_in(up: port, UART_SCR))) {
3311 serial8250_console_restore(up);
3312 up->canary = 0;
3313 }
3314
3315 if (em485) {
3316 if (em485->tx_stopped)
3317 up->rs485_start_tx(up, false);
3318 mdelay(port->rs485.delay_rts_before_send);
3319 }
3320
3321 use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3322 /*
3323 * BCM283x requires to check the fifo
3324 * after each byte.
3325 */
3326 !(up->capabilities & UART_CAP_MINI) &&
3327 /*
3328 * tx_loadsz contains the transmit fifo size
3329 */
3330 up->tx_loadsz > 1 &&
3331 (up->fcr & UART_FCR_ENABLE_FIFO) &&
3332 port->state &&
3333 test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3334 /*
3335 * After we put a data in the fifo, the controller will send
3336 * it regardless of the CTS state. Therefore, only use fifo
3337 * if we don't use control flow.
3338 */
3339 !(up->port.flags & UPF_CONS_FLOW);
3340
3341 if (likely(use_fifo))
3342 serial8250_console_fifo_write(up, s, count);
3343 else
3344 uart_console_write(port, s, count, putchar: serial8250_console_wait_putchar);
3345
3346 /*
3347 * Finally, wait for transmitter to become empty
3348 * and restore the IER
3349 */
3350 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3351
3352 if (em485) {
3353 mdelay(port->rs485.delay_rts_after_send);
3354 if (em485->tx_stopped)
3355 up->rs485_stop_tx(up, false);
3356 }
3357
3358 serial_port_out(up: port, UART_IER, value: ier);
3359
3360 /*
3361 * The receive handling will happen properly because the
3362 * receive ready bit will still be set; it is not cleared
3363 * on read. However, modem control will not, we must
3364 * call it if we have saved something in the saved flags
3365 * while processing with interrupts off.
3366 */
3367 if (up->msr_saved_flags)
3368 serial8250_modem_status(up);
3369
3370 if (locked)
3371 uart_port_unlock_irqrestore(up: port, flags);
3372}
3373
3374static unsigned int probe_baud(struct uart_port *port)
3375{
3376 unsigned char lcr, dll, dlm;
3377 unsigned int quot;
3378
3379 lcr = serial_port_in(up: port, UART_LCR);
3380 serial_port_out(up: port, UART_LCR, value: lcr | UART_LCR_DLAB);
3381 dll = serial_port_in(up: port, UART_DLL);
3382 dlm = serial_port_in(up: port, UART_DLM);
3383 serial_port_out(up: port, UART_LCR, value: lcr);
3384
3385 quot = (dlm << 8) | dll;
3386 return (port->uartclk / 16) / quot;
3387}
3388
3389int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3390{
3391 int baud = 9600;
3392 int bits = 8;
3393 int parity = 'n';
3394 int flow = 'n';
3395 int ret;
3396
3397 if (!port->iobase && !port->membase)
3398 return -ENODEV;
3399
3400 if (options)
3401 uart_parse_options(options, baud: &baud, parity: &parity, bits: &bits, flow: &flow);
3402 else if (probe)
3403 baud = probe_baud(port);
3404
3405 ret = uart_set_options(port, co: port->cons, baud, parity, bits, flow);
3406 if (ret)
3407 return ret;
3408
3409 if (port->dev)
3410 pm_runtime_get_sync(dev: port->dev);
3411
3412 return 0;
3413}
3414
3415int serial8250_console_exit(struct uart_port *port)
3416{
3417 if (port->dev)
3418 pm_runtime_put_sync(dev: port->dev);
3419
3420 return 0;
3421}
3422
3423#endif /* CONFIG_SERIAL_8250_CONSOLE */
3424
3425MODULE_DESCRIPTION("Base port operations for 8250/16550-type serial ports");
3426MODULE_LICENSE("GPL");
3427