1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Open Host Controller Interface (OHCI) driver for USB.
4 *
5 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 *
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 *
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ohci fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
14 *
15 *
16 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
17 * interfaces (though some non-x86 Intel chips use it). It supports
18 * smarter hardware than UHCI. A download link for the spec available
19 * through the https://www.usb.org website.
20 *
21 * This file is licenced under the GPL.
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/delay.h>
29#include <linux/ioport.h>
30#include <linux/sched.h>
31#include <linux/slab.h>
32#include <linux/errno.h>
33#include <linux/init.h>
34#include <linux/timer.h>
35#include <linux/list.h>
36#include <linux/usb.h>
37#include <linux/usb/otg.h>
38#include <linux/usb/hcd.h>
39#include <linux/dma-mapping.h>
40#include <linux/dmapool.h>
41#include <linux/workqueue.h>
42#include <linux/debugfs.h>
43#include <linux/genalloc.h>
44
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <linux/unaligned.h>
48#include <asm/byteorder.h>
49
50
51#define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
52#define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
53
54/*-------------------------------------------------------------------------*/
55
56/* For initializing controller (mask in an HCFS mode too) */
57#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58#define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
61
62#ifdef __hppa__
63/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
64#define IR_DISABLE
65#endif
66
67#ifdef CONFIG_ARCH_OMAP
68/* OMAP doesn't support IR (no SMM; not needed) */
69#define IR_DISABLE
70#endif
71
72/*-------------------------------------------------------------------------*/
73
74static const char hcd_name [] = "ohci_hcd";
75
76#define STATECHANGE_DELAY msecs_to_jiffies(300)
77#define IO_WATCHDOG_DELAY msecs_to_jiffies(275)
78#define IO_WATCHDOG_OFF 0xffffff00
79
80#include "ohci.h"
81#include "pci-quirks.h"
82
83static void ohci_dump(struct ohci_hcd *ohci);
84static void ohci_stop(struct usb_hcd *hcd);
85static void io_watchdog_func(struct timer_list *t);
86
87#include "ohci-hub.c"
88#include "ohci-dbg.c"
89#include "ohci-mem.c"
90#include "ohci-q.c"
91
92
93/*
94 * On architectures with edge-triggered interrupts we must never return
95 * IRQ_NONE.
96 */
97#if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
98#define IRQ_NOTMINE IRQ_HANDLED
99#else
100#define IRQ_NOTMINE IRQ_NONE
101#endif
102
103
104/* Some boards misreport power switching/overcurrent */
105static bool distrust_firmware;
106module_param (distrust_firmware, bool, 0);
107MODULE_PARM_DESC (distrust_firmware,
108 "true to distrust firmware power/overcurrent setup");
109
110/* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
111static bool no_handshake;
112module_param (no_handshake, bool, 0);
113MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
114
115/*-------------------------------------------------------------------------*/
116
117static int number_of_tds(struct urb *urb)
118{
119 int len, i, num, this_sg_len;
120 struct scatterlist *sg;
121
122 len = urb->transfer_buffer_length;
123 i = urb->num_mapped_sgs;
124
125 if (len > 0 && i > 0) { /* Scatter-gather transfer */
126 num = 0;
127 sg = urb->sg;
128 for (;;) {
129 this_sg_len = min_t(int, sg_dma_len(sg), len);
130 num += DIV_ROUND_UP(this_sg_len, 4096);
131 len -= this_sg_len;
132 if (--i <= 0 || len <= 0)
133 break;
134 sg = sg_next(sg);
135 }
136
137 } else { /* Non-SG transfer */
138 /* one TD for every 4096 Bytes (could be up to 8K) */
139 num = DIV_ROUND_UP(len, 4096);
140 }
141 return num;
142}
143
144/*
145 * queue up an urb for anything except the root hub
146 */
147static int ohci_urb_enqueue (
148 struct usb_hcd *hcd,
149 struct urb *urb,
150 gfp_t mem_flags
151) {
152 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
153 struct ed *ed;
154 urb_priv_t *urb_priv;
155 unsigned int pipe = urb->pipe;
156 int i, size = 0;
157 unsigned long flags;
158 int retval = 0;
159
160 /* every endpoint has a ed, locate and maybe (re)initialize it */
161 ed = ed_get(ohci, ep: urb->ep, udev: urb->dev, pipe, interval: urb->interval);
162 if (! ed)
163 return -ENOMEM;
164
165 /* for the private part of the URB we need the number of TDs (size) */
166 switch (ed->type) {
167 case PIPE_CONTROL:
168 /* td_submit_urb() doesn't yet handle these */
169 if (urb->transfer_buffer_length > 4096)
170 return -EMSGSIZE;
171
172 /* 1 TD for setup, 1 for ACK, plus ... */
173 size = 2;
174 fallthrough;
175 // case PIPE_INTERRUPT:
176 // case PIPE_BULK:
177 default:
178 size += number_of_tds(urb);
179 /* maybe a zero-length packet to wrap it up */
180 if (size == 0)
181 size++;
182 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
183 && (urb->transfer_buffer_length
184 % usb_maxpacket(udev: urb->dev, pipe)) == 0)
185 size++;
186 break;
187 case PIPE_ISOCHRONOUS: /* number of packets from URB */
188 size = urb->number_of_packets;
189 break;
190 }
191
192 /* allocate the private part of the URB */
193 urb_priv = kzalloc(struct_size(urb_priv, td, size), mem_flags);
194 if (!urb_priv)
195 return -ENOMEM;
196 INIT_LIST_HEAD (list: &urb_priv->pending);
197 urb_priv->length = size;
198 urb_priv->ed = ed;
199
200 /* allocate the TDs (deferring hash chain updates) */
201 for (i = 0; i < size; i++) {
202 urb_priv->td [i] = td_alloc (hc: ohci, mem_flags);
203 if (!urb_priv->td [i]) {
204 urb_priv->length = i;
205 urb_free_priv (hc: ohci, urb_priv);
206 return -ENOMEM;
207 }
208 }
209
210 spin_lock_irqsave (&ohci->lock, flags);
211
212 /* don't submit to a dead HC */
213 if (!HCD_HW_ACCESSIBLE(hcd)) {
214 retval = -ENODEV;
215 goto fail;
216 }
217 if (ohci->rh_state != OHCI_RH_RUNNING) {
218 retval = -ENODEV;
219 goto fail;
220 }
221 retval = usb_hcd_link_urb_to_ep(hcd, urb);
222 if (retval)
223 goto fail;
224
225 /* schedule the ed if needed */
226 if (ed->state == ED_IDLE) {
227 retval = ed_schedule (ohci, ed);
228 if (retval < 0) {
229 usb_hcd_unlink_urb_from_ep(hcd, urb);
230 goto fail;
231 }
232
233 /* Start up the I/O watchdog timer, if it's not running */
234 if (ohci->prev_frame_no == IO_WATCHDOG_OFF &&
235 list_empty(head: &ohci->eds_in_use) &&
236 !(ohci->flags & OHCI_QUIRK_QEMU)) {
237 ohci->prev_frame_no = ohci_frame_no(ohci);
238 mod_timer(timer: &ohci->io_watchdog,
239 expires: jiffies + IO_WATCHDOG_DELAY);
240 }
241 list_add(new: &ed->in_use_list, head: &ohci->eds_in_use);
242
243 if (ed->type == PIPE_ISOCHRONOUS) {
244 u16 frame = ohci_frame_no(ohci);
245
246 /* delay a few frames before the first TD */
247 frame += max_t (u16, 8, ed->interval);
248 frame &= ~(ed->interval - 1);
249 frame |= ed->branch;
250 urb->start_frame = frame;
251 ed->last_iso = frame + ed->interval * (size - 1);
252 }
253 } else if (ed->type == PIPE_ISOCHRONOUS) {
254 u16 next = ohci_frame_no(ohci) + 1;
255 u16 frame = ed->last_iso + ed->interval;
256 u16 length = ed->interval * (size - 1);
257
258 /* Behind the scheduling threshold? */
259 if (unlikely(tick_before(frame, next))) {
260
261 /* URB_ISO_ASAP: Round up to the first available slot */
262 if (urb->transfer_flags & URB_ISO_ASAP) {
263 frame += (next - frame + ed->interval - 1) &
264 -ed->interval;
265
266 /*
267 * Not ASAP: Use the next slot in the stream,
268 * no matter what.
269 */
270 } else {
271 /*
272 * Some OHCI hardware doesn't handle late TDs
273 * correctly. After retiring them it proceeds
274 * to the next ED instead of the next TD.
275 * Therefore we have to omit the late TDs
276 * entirely.
277 */
278 urb_priv->td_cnt = DIV_ROUND_UP(
279 (u16) (next - frame),
280 ed->interval);
281 if (urb_priv->td_cnt >= urb_priv->length) {
282 ++urb_priv->td_cnt; /* Mark it */
283 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
284 urb, frame, length,
285 next);
286 }
287 }
288 }
289 urb->start_frame = frame;
290 ed->last_iso = frame + length;
291 }
292
293 /* fill the TDs and link them to the ed; and
294 * enable that part of the schedule, if needed
295 * and update count of queued periodic urbs
296 */
297 urb->hcpriv = urb_priv;
298 td_submit_urb (ohci, urb);
299
300fail:
301 if (retval)
302 urb_free_priv (hc: ohci, urb_priv);
303 spin_unlock_irqrestore (lock: &ohci->lock, flags);
304 return retval;
305}
306
307/*
308 * decouple the URB from the HC queues (TDs, urb_priv).
309 * reporting is always done
310 * asynchronously, and we might be dealing with an urb that's
311 * partially transferred, or an ED with other urbs being unlinked.
312 */
313static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
314{
315 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
316 unsigned long flags;
317 int rc;
318 urb_priv_t *urb_priv;
319
320 spin_lock_irqsave (&ohci->lock, flags);
321 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
322 if (rc == 0) {
323
324 /* Unless an IRQ completed the unlink while it was being
325 * handed to us, flag it for unlink and giveback, and force
326 * some upcoming INTR_SF to call finish_unlinks()
327 */
328 urb_priv = urb->hcpriv;
329 if (urb_priv->ed->state == ED_OPER)
330 start_ed_unlink(ohci, ed: urb_priv->ed);
331
332 if (ohci->rh_state != OHCI_RH_RUNNING) {
333 /* With HC dead, we can clean up right away */
334 ohci_work(ohci);
335 }
336 }
337 spin_unlock_irqrestore (lock: &ohci->lock, flags);
338 return rc;
339}
340
341/*-------------------------------------------------------------------------*/
342
343/* frees config/altsetting state for endpoints,
344 * including ED memory, dummy TD, and bulk/intr data toggle
345 */
346
347static void
348ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
349{
350 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
351 unsigned long flags;
352 struct ed *ed = ep->hcpriv;
353 unsigned limit = 1000;
354
355 /* ASSERT: any requests/urbs are being unlinked */
356 /* ASSERT: nobody can be submitting urbs for this any more */
357
358 if (!ed)
359 return;
360
361rescan:
362 spin_lock_irqsave (&ohci->lock, flags);
363
364 if (ohci->rh_state != OHCI_RH_RUNNING) {
365sanitize:
366 ed->state = ED_IDLE;
367 ohci_work(ohci);
368 }
369
370 switch (ed->state) {
371 case ED_UNLINK: /* wait for hw to finish? */
372 /* major IRQ delivery trouble loses INTR_SF too... */
373 if (limit-- == 0) {
374 ohci_warn(ohci, "ED unlink timeout\n");
375 goto sanitize;
376 }
377 spin_unlock_irqrestore (lock: &ohci->lock, flags);
378 schedule_timeout_uninterruptible(timeout: 1);
379 goto rescan;
380 case ED_IDLE: /* fully unlinked */
381 if (list_empty (head: &ed->td_list)) {
382 td_free (hc: ohci, td: ed->dummy);
383 ed_free (hc: ohci, ed);
384 break;
385 }
386 fallthrough;
387 default:
388 /* caller was supposed to have unlinked any requests;
389 * that's not our job. can't recover; must leak ed.
390 */
391 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
392 ed, ep->desc.bEndpointAddress, ed->state,
393 list_empty (&ed->td_list) ? "" : " (has tds)");
394 td_free (hc: ohci, td: ed->dummy);
395 break;
396 }
397 ep->hcpriv = NULL;
398 spin_unlock_irqrestore (lock: &ohci->lock, flags);
399}
400
401static int ohci_get_frame (struct usb_hcd *hcd)
402{
403 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
404
405 return ohci_frame_no(ohci);
406}
407
408static void ohci_usb_reset (struct ohci_hcd *ohci)
409{
410 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
411 ohci->hc_control &= OHCI_CTRL_RWC;
412 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
413 ohci->rh_state = OHCI_RH_HALTED;
414}
415
416/* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
417 * other cases where the next software may expect clean state from the
418 * "firmware". this is bus-neutral, unlike shutdown() methods.
419 */
420static void _ohci_shutdown(struct usb_hcd *hcd)
421{
422 struct ohci_hcd *ohci;
423
424 ohci = hcd_to_ohci (hcd);
425 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
426
427 /* Software reset, after which the controller goes into SUSPEND */
428 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
429 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
430 udelay(usec: 10);
431
432 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
433 ohci->rh_state = OHCI_RH_HALTED;
434}
435
436static void ohci_shutdown(struct usb_hcd *hcd)
437{
438 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
439 unsigned long flags;
440
441 spin_lock_irqsave(&ohci->lock, flags);
442 _ohci_shutdown(hcd);
443 spin_unlock_irqrestore(lock: &ohci->lock, flags);
444}
445
446/*-------------------------------------------------------------------------*
447 * HC functions
448 *-------------------------------------------------------------------------*/
449
450/* init memory, and kick BIOS/SMM off */
451
452static int ohci_init (struct ohci_hcd *ohci)
453{
454 int ret;
455 struct usb_hcd *hcd = ohci_to_hcd(ohci);
456
457 /* Accept arbitrarily long scatter-gather lists */
458 if (!hcd->localmem_pool)
459 hcd->self.sg_tablesize = ~0;
460
461 if (distrust_firmware)
462 ohci->flags |= OHCI_QUIRK_HUB_POWER;
463
464 ohci->rh_state = OHCI_RH_HALTED;
465 ohci->regs = hcd->regs;
466
467 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
468 * was never needed for most non-PCI systems ... remove the code?
469 */
470
471#ifndef IR_DISABLE
472 /* SMM owns the HC? not for long! */
473 if (!no_handshake && ohci_readl (ohci,
474 &ohci->regs->control) & OHCI_CTRL_IR) {
475 u32 temp;
476
477 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
478
479 /* this timeout is arbitrary. we make it long, so systems
480 * depending on usb keyboards may be usable even if the
481 * BIOS/SMM code seems pretty broken.
482 */
483 temp = 500; /* arbitrary: five seconds */
484
485 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
486 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
487 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
488 msleep (msecs: 10);
489 if (--temp == 0) {
490 ohci_err (ohci, "USB HC takeover failed!"
491 " (BIOS/SMM bug)\n");
492 return -EBUSY;
493 }
494 }
495 ohci_usb_reset (ohci);
496 }
497#endif
498
499 /* Disable HC interrupts */
500 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
501
502 /* flush the writes, and save key bits like RWC */
503 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
504 ohci->hc_control |= OHCI_CTRL_RWC;
505
506 /* Read the number of ports unless overridden */
507 if (ohci->num_ports == 0)
508 ohci->num_ports = roothub_a(hc: ohci) & RH_A_NDP;
509
510 if (ohci->hcca)
511 return 0;
512
513 timer_setup(&ohci->io_watchdog, io_watchdog_func, 0);
514 ohci->prev_frame_no = IO_WATCHDOG_OFF;
515
516 if (hcd->localmem_pool)
517 ohci->hcca = gen_pool_dma_alloc_align(pool: hcd->localmem_pool,
518 size: sizeof(*ohci->hcca),
519 dma: &ohci->hcca_dma, align: 256);
520 else
521 ohci->hcca = dma_alloc_coherent(dev: hcd->self.controller,
522 size: sizeof(*ohci->hcca),
523 dma_handle: &ohci->hcca_dma,
524 GFP_KERNEL);
525 if (!ohci->hcca)
526 return -ENOMEM;
527
528 if ((ret = ohci_mem_init (ohci)) < 0)
529 ohci_stop (hcd);
530 else {
531 create_debug_files (ohci);
532 }
533
534 return ret;
535}
536
537/*-------------------------------------------------------------------------*/
538
539/* Start an OHCI controller, set the BUS operational
540 * resets USB and controller
541 * enable interrupts
542 */
543static int ohci_run (struct ohci_hcd *ohci)
544{
545 u32 mask, val;
546 int first = ohci->fminterval == 0;
547 struct usb_hcd *hcd = ohci_to_hcd(ohci);
548
549 ohci->rh_state = OHCI_RH_HALTED;
550
551 /* boot firmware should have set this up (5.1.1.3.1) */
552 if (first) {
553
554 val = ohci_readl (ohci, &ohci->regs->fminterval);
555 ohci->fminterval = val & 0x3fff;
556 if (ohci->fminterval != FI)
557 ohci_dbg (ohci, "fminterval delta %d\n",
558 ohci->fminterval - FI);
559 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
560 /* also: power/overcurrent flags in roothub.a */
561 }
562
563 /* Reset USB nearly "by the book". RemoteWakeupConnected has
564 * to be checked in case boot firmware (BIOS/SMM/...) has set up
565 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
566 * If the bus glue detected wakeup capability then it should
567 * already be enabled; if so we'll just enable it again.
568 */
569 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
570 device_set_wakeup_capable(dev: hcd->self.controller, capable: 1);
571
572 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
573 case OHCI_USB_OPER:
574 val = 0;
575 break;
576 case OHCI_USB_SUSPEND:
577 case OHCI_USB_RESUME:
578 ohci->hc_control &= OHCI_CTRL_RWC;
579 ohci->hc_control |= OHCI_USB_RESUME;
580 val = 10 /* msec wait */;
581 break;
582 // case OHCI_USB_RESET:
583 default:
584 ohci->hc_control &= OHCI_CTRL_RWC;
585 ohci->hc_control |= OHCI_USB_RESET;
586 val = 50 /* msec wait */;
587 break;
588 }
589 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
590 // flush the writes
591 (void) ohci_readl (ohci, &ohci->regs->control);
592 msleep(msecs: val);
593
594 memset (s: ohci->hcca, c: 0, n: sizeof (struct ohci_hcca));
595
596 /* 2msec timelimit here means no irqs/preempt */
597 spin_lock_irq (lock: &ohci->lock);
598
599retry:
600 /* HC Reset requires max 10 us delay */
601 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
602 val = 30; /* ... allow extra time */
603 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
604 if (--val == 0) {
605 spin_unlock_irq (lock: &ohci->lock);
606 ohci_err (ohci, "USB HC reset timed out!\n");
607 return -1;
608 }
609 udelay (usec: 1);
610 }
611
612 /* now we're in the SUSPEND state ... must go OPERATIONAL
613 * within 2msec else HC enters RESUME
614 *
615 * ... but some hardware won't init fmInterval "by the book"
616 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
617 * this if we write fmInterval after we're OPERATIONAL.
618 * Unclear about ALi, ServerWorks, and others ... this could
619 * easily be a longstanding bug in chip init on Linux.
620 */
621 if (ohci->flags & OHCI_QUIRK_INITRESET) {
622 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
623 // flush those writes
624 (void) ohci_readl (ohci, &ohci->regs->control);
625 }
626
627 /* Tell the controller where the control and bulk lists are
628 * The lists are empty now. */
629 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
630 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
631
632 /* a reset clears this */
633 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
634
635 periodic_reinit (ohci);
636
637 /* some OHCI implementations are finicky about how they init.
638 * bogus values here mean not even enumeration could work.
639 */
640 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
641 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
642 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
643 ohci->flags |= OHCI_QUIRK_INITRESET;
644 ohci_dbg (ohci, "enabling initreset quirk\n");
645 goto retry;
646 }
647 spin_unlock_irq (lock: &ohci->lock);
648 ohci_err (ohci, "init err (%08x %04x)\n",
649 ohci_readl (ohci, &ohci->regs->fminterval),
650 ohci_readl (ohci, &ohci->regs->periodicstart));
651 return -EOVERFLOW;
652 }
653
654 /* use rhsc irqs after hub_wq is allocated */
655 set_bit(HCD_FLAG_POLL_RH, addr: &hcd->flags);
656 hcd->uses_new_polling = 1;
657
658 /* start controller operations */
659 ohci->hc_control &= OHCI_CTRL_RWC;
660 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
661 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
662 ohci->rh_state = OHCI_RH_RUNNING;
663
664 /* wake on ConnectStatusChange, matching external hubs */
665 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
666
667 /* Choose the interrupts we care about now, others later on demand */
668 mask = OHCI_INTR_INIT;
669 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
670 ohci_writel (ohci, mask, &ohci->regs->intrenable);
671
672 /* handle root hub init quirks ... */
673 val = roothub_a (hc: ohci);
674 /* Configure for per-port over-current protection by default */
675 val &= ~RH_A_NOCP;
676 val |= RH_A_OCPM;
677 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
678 /* NSC 87560 and maybe others.
679 * Ganged power switching, no over-current protection.
680 */
681 val |= RH_A_NOCP;
682 val &= ~(RH_A_POTPGT | RH_A_NPS | RH_A_PSM | RH_A_OCPM);
683 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
684 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
685 /* hub power always on; required for AMD-756 and some
686 * Mac platforms.
687 */
688 val |= RH_A_NPS;
689 }
690 ohci_writel(ohci, val, &ohci->regs->roothub.a);
691
692 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
693 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
694 &ohci->regs->roothub.b);
695 // flush those writes
696 (void) ohci_readl (ohci, &ohci->regs->control);
697
698 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
699 spin_unlock_irq (lock: &ohci->lock);
700
701 // POTPGT delay is bits 24-31, in 2 ms units.
702 mdelay ((val >> 23) & 0x1fe);
703
704 ohci_dump(controller: ohci);
705
706 return 0;
707}
708
709/* ohci_setup routine for generic controller initialization */
710
711int ohci_setup(struct usb_hcd *hcd)
712{
713 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
714
715 ohci_hcd_init(ohci);
716
717 return ohci_init(ohci);
718}
719EXPORT_SYMBOL_GPL(ohci_setup);
720
721/* ohci_start routine for generic controller start of all OHCI bus glue */
722static int ohci_start(struct usb_hcd *hcd)
723{
724 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
725 int ret;
726
727 ret = ohci_run(ohci);
728 if (ret < 0) {
729 ohci_err(ohci, "can't start\n");
730 ohci_stop(hcd);
731 }
732 return ret;
733}
734
735/*-------------------------------------------------------------------------*/
736
737/*
738 * Some OHCI controllers are known to lose track of completed TDs. They
739 * don't add the TDs to the hardware done queue, which means we never see
740 * them as being completed.
741 *
742 * This watchdog routine checks for such problems. Without some way to
743 * tell when those TDs have completed, we would never take their EDs off
744 * the unlink list. As a result, URBs could never be dequeued and
745 * endpoints could never be released.
746 */
747static void io_watchdog_func(struct timer_list *t)
748{
749 struct ohci_hcd *ohci = timer_container_of(ohci, t,
750 io_watchdog);
751 bool takeback_all_pending = false;
752 u32 status;
753 u32 head;
754 struct ed *ed;
755 struct td *td, *td_start, *td_next;
756 unsigned frame_no, prev_frame_no = IO_WATCHDOG_OFF;
757 unsigned long flags;
758
759 spin_lock_irqsave(&ohci->lock, flags);
760
761 /*
762 * One way to lose track of completed TDs is if the controller
763 * never writes back the done queue head. If it hasn't been
764 * written back since the last time this function ran and if it
765 * was non-empty at that time, something is badly wrong with the
766 * hardware.
767 */
768 status = ohci_readl(ohci, &ohci->regs->intrstatus);
769 if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) {
770 if (ohci->prev_donehead) {
771 ohci_err(ohci, "HcDoneHead not written back; disabled\n");
772 died:
773 usb_hc_died(hcd: ohci_to_hcd(ohci));
774 ohci_dump(controller: ohci);
775 _ohci_shutdown(hcd: ohci_to_hcd(ohci));
776 goto done;
777 } else {
778 /* No write back because the done queue was empty */
779 takeback_all_pending = true;
780 }
781 }
782
783 /* Check every ED which might have pending TDs */
784 list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) {
785 if (ed->pending_td) {
786 if (takeback_all_pending ||
787 OKAY_TO_TAKEBACK(ohci, ed)) {
788 unsigned tmp = hc32_to_cpu(ohci, x: ed->hwINFO);
789
790 ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n",
791 0x007f & tmp,
792 (0x000f & (tmp >> 7)) +
793 ((tmp & ED_IN) >> 5));
794 add_to_done_list(ohci, td: ed->pending_td);
795 }
796 }
797
798 /* Starting from the latest pending TD, */
799 td = ed->pending_td;
800
801 /* or the last TD on the done list, */
802 if (!td) {
803 list_for_each_entry(td_next, &ed->td_list, td_list) {
804 if (!td_next->next_dl_td)
805 break;
806 td = td_next;
807 }
808 }
809
810 /* find the last TD processed by the controller. */
811 head = hc32_to_cpu(ohci, READ_ONCE(ed->hwHeadP)) & TD_MASK;
812 td_start = td;
813 td_next = list_prepare_entry(td, &ed->td_list, td_list);
814 list_for_each_entry_continue(td_next, &ed->td_list, td_list) {
815 if (head == (u32) td_next->td_dma)
816 break;
817 td = td_next; /* head pointer has passed this TD */
818 }
819 if (td != td_start) {
820 /*
821 * In case a WDH cycle is in progress, we will wait
822 * for the next two cycles to complete before assuming
823 * this TD will never get on the done queue.
824 */
825 ed->takeback_wdh_cnt = ohci->wdh_cnt + 2;
826 ed->pending_td = td;
827 }
828 }
829
830 ohci_work(ohci);
831
832 if (ohci->rh_state == OHCI_RH_RUNNING) {
833
834 /*
835 * Sometimes a controller just stops working. We can tell
836 * by checking that the frame counter has advanced since
837 * the last time we ran.
838 *
839 * But be careful: Some controllers violate the spec by
840 * stopping their frame counter when no ports are active.
841 */
842 frame_no = ohci_frame_no(ohci);
843 if (frame_no == ohci->prev_frame_no) {
844 int active_cnt = 0;
845 int i;
846 unsigned tmp;
847
848 for (i = 0; i < ohci->num_ports; ++i) {
849 tmp = roothub_portstatus(hc: ohci, i);
850 /* Enabled and not suspended? */
851 if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS))
852 ++active_cnt;
853 }
854
855 if (active_cnt > 0) {
856 ohci_err(ohci, "frame counter not updating; disabled\n");
857 goto died;
858 }
859 }
860 if (!list_empty(head: &ohci->eds_in_use)) {
861 prev_frame_no = frame_no;
862 ohci->prev_wdh_cnt = ohci->wdh_cnt;
863 ohci->prev_donehead = ohci_readl(ohci,
864 &ohci->regs->donehead);
865 mod_timer(timer: &ohci->io_watchdog,
866 expires: jiffies + IO_WATCHDOG_DELAY);
867 }
868 }
869
870 done:
871 ohci->prev_frame_no = prev_frame_no;
872 spin_unlock_irqrestore(lock: &ohci->lock, flags);
873}
874
875/* an interrupt happens */
876
877static irqreturn_t ohci_irq (struct usb_hcd *hcd)
878{
879 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
880 struct ohci_regs __iomem *regs = ohci->regs;
881 int ints;
882
883 /* Read interrupt status (and flush pending writes). We ignore the
884 * optimization of checking the LSB of hcca->done_head; it doesn't
885 * work on all systems (edge triggering for OHCI can be a factor).
886 */
887 ints = ohci_readl(ohci, &regs->intrstatus);
888
889 /* Check for an all 1's result which is a typical consequence
890 * of dead, unclocked, or unplugged (CardBus...) devices
891 */
892again:
893 if (ints == ~(u32)0) {
894 ohci->rh_state = OHCI_RH_HALTED;
895 ohci_dbg (ohci, "device removed!\n");
896 usb_hc_died(hcd);
897 return IRQ_HANDLED;
898 }
899
900 /* We only care about interrupts that are enabled */
901 ints &= ohci_readl(ohci, &regs->intrenable);
902
903 /* interrupt for some other device? */
904 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
905 return IRQ_NOTMINE;
906
907 if (ints & OHCI_INTR_UE) {
908 // e.g. due to PCI Master/Target Abort
909 if (quirk_nec(ohci)) {
910 /* Workaround for a silicon bug in some NEC chips used
911 * in Apple's PowerBooks. Adapted from Darwin code.
912 */
913 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
914
915 ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
916
917 schedule_work (work: &ohci->nec_work);
918 } else {
919 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
920 ohci->rh_state = OHCI_RH_HALTED;
921 usb_hc_died(hcd);
922 }
923
924 ohci_dump(controller: ohci);
925 ohci_usb_reset (ohci);
926 }
927
928 if (ints & OHCI_INTR_RHSC) {
929 ohci_dbg(ohci, "rhsc\n");
930 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
931 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
932 &regs->intrstatus);
933
934 /* NOTE: Vendors didn't always make the same implementation
935 * choices for RHSC. Many followed the spec; RHSC triggers
936 * on an edge, like setting and maybe clearing a port status
937 * change bit. With others it's level-triggered, active
938 * until hub_wq clears all the port status change bits. We'll
939 * always disable it here and rely on polling until hub_wq
940 * re-enables it.
941 */
942 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
943 usb_hcd_poll_rh_status(hcd);
944 }
945
946 /* For connect and disconnect events, we expect the controller
947 * to turn on RHSC along with RD. But for remote wakeup events
948 * this might not happen.
949 */
950 else if (ints & OHCI_INTR_RD) {
951 ohci_dbg(ohci, "resume detect\n");
952 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
953 set_bit(HCD_FLAG_POLL_RH, addr: &hcd->flags);
954 if (ohci->autostop) {
955 spin_lock (lock: &ohci->lock);
956 ohci_rh_resume (ohci);
957 spin_unlock (lock: &ohci->lock);
958 } else
959 usb_hcd_resume_root_hub(hcd);
960 }
961
962 spin_lock(lock: &ohci->lock);
963 if (ints & OHCI_INTR_WDH)
964 update_done_list(ohci);
965
966 /* could track INTR_SO to reduce available PCI/... bandwidth */
967
968 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
969 * when there's still unlinking to be done (next frame).
970 */
971 ohci_work(ohci);
972 if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
973 && ohci->rh_state == OHCI_RH_RUNNING)
974 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
975
976 if (ohci->rh_state == OHCI_RH_RUNNING) {
977 ohci_writel (ohci, ints, &regs->intrstatus);
978 if (ints & OHCI_INTR_WDH)
979 ++ohci->wdh_cnt;
980
981 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
982 // flush those writes
983 (void) ohci_readl (ohci, &ohci->regs->control);
984 }
985 spin_unlock(lock: &ohci->lock);
986
987 /* repeat until all enabled interrupts are handled */
988 if (ohci->rh_state != OHCI_RH_HALTED) {
989 ints = ohci_readl(ohci, &regs->intrstatus);
990 if (ints && (ints & ohci_readl(ohci, &regs->intrenable)))
991 goto again;
992 }
993
994 return IRQ_HANDLED;
995}
996
997/*-------------------------------------------------------------------------*/
998
999static void ohci_stop (struct usb_hcd *hcd)
1000{
1001 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1002
1003 ohci_dump(controller: ohci);
1004
1005 if (quirk_nec(ohci))
1006 flush_work(work: &ohci->nec_work);
1007 timer_delete_sync(timer: &ohci->io_watchdog);
1008 ohci->prev_frame_no = IO_WATCHDOG_OFF;
1009
1010 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1011 ohci_usb_reset(ohci);
1012 free_irq(hcd->irq, hcd);
1013 hcd->irq = 0;
1014
1015 if (quirk_amdiso(ohci))
1016 usb_amd_dev_put();
1017
1018 remove_debug_files (ohci);
1019 ohci_mem_cleanup (ohci);
1020 if (ohci->hcca) {
1021 if (hcd->localmem_pool)
1022 gen_pool_free(pool: hcd->localmem_pool,
1023 addr: (unsigned long)ohci->hcca,
1024 size: sizeof(*ohci->hcca));
1025 else
1026 dma_free_coherent(dev: hcd->self.controller,
1027 size: sizeof(*ohci->hcca),
1028 cpu_addr: ohci->hcca, dma_handle: ohci->hcca_dma);
1029 ohci->hcca = NULL;
1030 ohci->hcca_dma = 0;
1031 }
1032}
1033
1034/*-------------------------------------------------------------------------*/
1035
1036#if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
1037
1038/* must not be called from interrupt context */
1039int ohci_restart(struct ohci_hcd *ohci)
1040{
1041 int temp;
1042 int i;
1043 struct urb_priv *priv;
1044
1045 ohci_init(ohci);
1046 spin_lock_irq(lock: &ohci->lock);
1047 ohci->rh_state = OHCI_RH_HALTED;
1048
1049 /* Recycle any "live" eds/tds (and urbs). */
1050 if (!list_empty (head: &ohci->pending))
1051 ohci_dbg(ohci, "abort schedule...\n");
1052 list_for_each_entry (priv, &ohci->pending, pending) {
1053 struct urb *urb = priv->td[0]->urb;
1054 struct ed *ed = priv->ed;
1055
1056 switch (ed->state) {
1057 case ED_OPER:
1058 ed->state = ED_UNLINK;
1059 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
1060 ed_deschedule (ohci, ed);
1061
1062 ed->ed_next = ohci->ed_rm_list;
1063 ed->ed_prev = NULL;
1064 ohci->ed_rm_list = ed;
1065 fallthrough;
1066 case ED_UNLINK:
1067 break;
1068 default:
1069 ohci_dbg(ohci, "bogus ed %p state %d\n",
1070 ed, ed->state);
1071 }
1072
1073 if (!urb->unlinked)
1074 urb->unlinked = -ESHUTDOWN;
1075 }
1076 ohci_work(ohci);
1077 spin_unlock_irq(lock: &ohci->lock);
1078
1079 /* paranoia, in case that didn't work: */
1080
1081 /* empty the interrupt branches */
1082 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1083 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1084
1085 /* no EDs to remove */
1086 ohci->ed_rm_list = NULL;
1087
1088 /* empty control and bulk lists */
1089 ohci->ed_controltail = NULL;
1090 ohci->ed_bulktail = NULL;
1091
1092 if ((temp = ohci_run (ohci)) < 0) {
1093 ohci_err (ohci, "can't restart, %d\n", temp);
1094 return temp;
1095 }
1096 ohci_dbg(ohci, "restart complete\n");
1097 return 0;
1098}
1099EXPORT_SYMBOL_GPL(ohci_restart);
1100
1101#endif
1102
1103#ifdef CONFIG_PM
1104
1105int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1106{
1107 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1108 unsigned long flags;
1109 int rc = 0;
1110
1111 /* Disable irq emission and mark HW unaccessible. Use
1112 * the spinlock to properly synchronize with possible pending
1113 * RH suspend or resume activity.
1114 */
1115 spin_lock_irqsave (&ohci->lock, flags);
1116 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1117 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1118
1119 clear_bit(HCD_FLAG_HW_ACCESSIBLE, addr: &hcd->flags);
1120 spin_unlock_irqrestore (lock: &ohci->lock, flags);
1121
1122 synchronize_irq(irq: hcd->irq);
1123
1124 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1125 ohci_resume(hcd, hibernated: false);
1126 rc = -EBUSY;
1127 }
1128 return rc;
1129}
1130EXPORT_SYMBOL_GPL(ohci_suspend);
1131
1132
1133int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1134{
1135 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1136 int port;
1137 bool need_reinit = false;
1138
1139 set_bit(HCD_FLAG_HW_ACCESSIBLE, addr: &hcd->flags);
1140
1141 /* Make sure resume from hibernation re-enumerates everything */
1142 if (hibernated)
1143 ohci_usb_reset(ohci);
1144
1145 /* See if the controller is already running or has been reset */
1146 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1147 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1148 need_reinit = true;
1149 } else {
1150 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1151 case OHCI_USB_OPER:
1152 case OHCI_USB_RESET:
1153 need_reinit = true;
1154 }
1155 }
1156
1157 /* If needed, reinitialize and suspend the root hub */
1158 if (need_reinit) {
1159 spin_lock_irq(lock: &ohci->lock);
1160 ohci_rh_resume(ohci);
1161 ohci_rh_suspend(ohci, autostop: 0);
1162 spin_unlock_irq(lock: &ohci->lock);
1163 }
1164
1165 /* Normally just turn on port power and enable interrupts */
1166 else {
1167 ohci_dbg(ohci, "powerup ports\n");
1168 for (port = 0; port < ohci->num_ports; port++)
1169 ohci_writel(ohci, RH_PS_PPS,
1170 &ohci->regs->roothub.portstatus[port]);
1171
1172 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1173 ohci_readl(ohci, &ohci->regs->intrenable);
1174 msleep(msecs: 20);
1175 }
1176
1177 usb_hcd_resume_root_hub(hcd);
1178
1179 return 0;
1180}
1181EXPORT_SYMBOL_GPL(ohci_resume);
1182
1183#endif
1184
1185/*-------------------------------------------------------------------------*/
1186
1187/*
1188 * Generic structure: This gets copied for platform drivers so that
1189 * individual entries can be overridden as needed.
1190 */
1191
1192static const struct hc_driver ohci_hc_driver = {
1193 .description = hcd_name,
1194 .product_desc = "OHCI Host Controller",
1195 .hcd_priv_size = sizeof(struct ohci_hcd),
1196
1197 /*
1198 * generic hardware linkage
1199 */
1200 .irq = ohci_irq,
1201 .flags = HCD_MEMORY | HCD_DMA | HCD_USB11,
1202
1203 /*
1204 * basic lifecycle operations
1205 */
1206 .reset = ohci_setup,
1207 .start = ohci_start,
1208 .stop = ohci_stop,
1209 .shutdown = ohci_shutdown,
1210
1211 /*
1212 * managing i/o requests and associated device resources
1213 */
1214 .urb_enqueue = ohci_urb_enqueue,
1215 .urb_dequeue = ohci_urb_dequeue,
1216 .endpoint_disable = ohci_endpoint_disable,
1217
1218 /*
1219 * scheduling support
1220 */
1221 .get_frame_number = ohci_get_frame,
1222
1223 /*
1224 * root hub support
1225 */
1226 .hub_status_data = ohci_hub_status_data,
1227 .hub_control = ohci_hub_control,
1228#ifdef CONFIG_PM
1229 .bus_suspend = ohci_bus_suspend,
1230 .bus_resume = ohci_bus_resume,
1231#endif
1232 .start_port_reset = ohci_start_port_reset,
1233};
1234
1235void ohci_init_driver(struct hc_driver *drv,
1236 const struct ohci_driver_overrides *over)
1237{
1238 /* Copy the generic table to drv and then apply the overrides */
1239 *drv = ohci_hc_driver;
1240
1241 if (over) {
1242 drv->product_desc = over->product_desc;
1243 drv->hcd_priv_size += over->extra_priv_size;
1244 if (over->reset)
1245 drv->reset = over->reset;
1246 }
1247}
1248EXPORT_SYMBOL_GPL(ohci_init_driver);
1249
1250/*-------------------------------------------------------------------------*/
1251
1252MODULE_AUTHOR (DRIVER_AUTHOR);
1253MODULE_DESCRIPTION(DRIVER_DESC);
1254MODULE_LICENSE ("GPL");
1255
1256#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1257#include "ohci-sa1111.c"
1258#define SA1111_DRIVER ohci_hcd_sa1111_driver
1259#endif
1260
1261#ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1262#include "ohci-ppc-of.c"
1263#define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1264#endif
1265
1266#ifdef CONFIG_PPC_PS3
1267#include "ohci-ps3.c"
1268#define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1269#endif
1270
1271#ifdef CONFIG_MFD_SM501
1272#include "ohci-sm501.c"
1273#define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1274#endif
1275
1276static int __init ohci_hcd_mod_init(void)
1277{
1278 int retval = 0;
1279
1280 if (usb_disabled())
1281 return -ENODEV;
1282
1283 pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name,
1284 sizeof (struct ed), sizeof (struct td));
1285 set_bit(USB_OHCI_LOADED, addr: &usb_hcds_loaded);
1286
1287 ohci_debug_root = debugfs_create_dir(name: "ohci", parent: usb_debug_root);
1288
1289#ifdef PS3_SYSTEM_BUS_DRIVER
1290 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1291 if (retval < 0)
1292 goto error_ps3;
1293#endif
1294
1295#ifdef OF_PLATFORM_DRIVER
1296 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1297 if (retval < 0)
1298 goto error_of_platform;
1299#endif
1300
1301#ifdef SA1111_DRIVER
1302 retval = sa1111_driver_register(&SA1111_DRIVER);
1303 if (retval < 0)
1304 goto error_sa1111;
1305#endif
1306
1307#ifdef SM501_OHCI_DRIVER
1308 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1309 if (retval < 0)
1310 goto error_sm501;
1311#endif
1312
1313 return retval;
1314
1315 /* Error path */
1316#ifdef SM501_OHCI_DRIVER
1317 platform_driver_unregister(&SM501_OHCI_DRIVER);
1318 error_sm501:
1319#endif
1320#ifdef SA1111_DRIVER
1321 sa1111_driver_unregister(&SA1111_DRIVER);
1322 error_sa1111:
1323#endif
1324#ifdef OF_PLATFORM_DRIVER
1325 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1326 error_of_platform:
1327#endif
1328#ifdef PS3_SYSTEM_BUS_DRIVER
1329 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1330 error_ps3:
1331#endif
1332 debugfs_remove(dentry: ohci_debug_root);
1333 ohci_debug_root = NULL;
1334
1335 clear_bit(USB_OHCI_LOADED, addr: &usb_hcds_loaded);
1336 return retval;
1337}
1338module_init(ohci_hcd_mod_init);
1339
1340static void __exit ohci_hcd_mod_exit(void)
1341{
1342#ifdef SM501_OHCI_DRIVER
1343 platform_driver_unregister(&SM501_OHCI_DRIVER);
1344#endif
1345#ifdef SA1111_DRIVER
1346 sa1111_driver_unregister(&SA1111_DRIVER);
1347#endif
1348#ifdef OF_PLATFORM_DRIVER
1349 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1350#endif
1351#ifdef PS3_SYSTEM_BUS_DRIVER
1352 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1353#endif
1354 debugfs_remove(dentry: ohci_debug_root);
1355 clear_bit(USB_OHCI_LOADED, addr: &usb_hcds_loaded);
1356}
1357module_exit(ohci_hcd_mod_exit);
1358
1359