1// SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
11 *
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
27 * from Jose Renau
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
38 */
39
40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/export.h>
45#include <linux/sched.h>
46#include <linux/sched/topology.h>
47#include <linux/sched/hotplug.h>
48#include <linux/sched/task_stack.h>
49#include <linux/percpu.h>
50#include <linux/memblock.h>
51#include <linux/err.h>
52#include <linux/nmi.h>
53#include <linux/tboot.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56#include <linux/kexec.h>
57#include <linux/numa.h>
58#include <linux/pgtable.h>
59#include <linux/overflow.h>
60#include <linux/stackprotector.h>
61#include <linux/cpuhotplug.h>
62#include <linux/mc146818rtc.h>
63#include <linux/acpi.h>
64
65#include <asm/acpi.h>
66#include <asm/cacheinfo.h>
67#include <asm/cpuid/api.h>
68#include <asm/desc.h>
69#include <asm/nmi.h>
70#include <asm/irq.h>
71#include <asm/realmode.h>
72#include <asm/cpu.h>
73#include <asm/numa.h>
74#include <asm/tlbflush.h>
75#include <asm/mtrr.h>
76#include <asm/mwait.h>
77#include <asm/apic.h>
78#include <asm/io_apic.h>
79#include <asm/fpu/api.h>
80#include <asm/setup.h>
81#include <asm/uv/uv.h>
82#include <asm/microcode.h>
83#include <asm/i8259.h>
84#include <asm/misc.h>
85#include <asm/qspinlock.h>
86#include <asm/intel-family.h>
87#include <asm/cpu_device_id.h>
88#include <asm/spec-ctrl.h>
89#include <asm/hw_irq.h>
90#include <asm/stackprotector.h>
91#include <asm/sev.h>
92#include <asm/spec-ctrl.h>
93
94/* representing HT siblings of each logical CPU */
95DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
96EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
97
98/* representing HT and core siblings of each logical CPU */
99DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
100EXPORT_PER_CPU_SYMBOL(cpu_core_map);
101
102/* representing HT, core, and die siblings of each logical CPU */
103DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
104EXPORT_PER_CPU_SYMBOL(cpu_die_map);
105
106/* CPUs which are the primary SMT threads */
107struct cpumask __cpu_primary_thread_mask __read_mostly;
108
109/* Representing CPUs for which sibling maps can be computed */
110static cpumask_var_t cpu_sibling_setup_mask;
111
112struct mwait_cpu_dead {
113 unsigned int control;
114 unsigned int status;
115};
116
117#define CPUDEAD_MWAIT_WAIT 0xDEADBEEF
118#define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD
119
120/*
121 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
122 * that it's unlikely to be touched by other CPUs.
123 */
124static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
125
126/* Maximum number of SMT threads on any online core */
127int __read_mostly __max_smt_threads = 1;
128
129/* Flag to indicate if a complete sched domain rebuild is required */
130bool x86_topology_update;
131
132int arch_update_cpu_topology(void)
133{
134 int retval = x86_topology_update;
135
136 x86_topology_update = false;
137 return retval;
138}
139
140static unsigned int smpboot_warm_reset_vector_count;
141
142static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
143{
144 unsigned long flags;
145
146 spin_lock_irqsave(&rtc_lock, flags);
147 if (!smpboot_warm_reset_vector_count++) {
148 CMOS_WRITE(0xa, 0xf);
149 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4;
150 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf;
151 }
152 spin_unlock_irqrestore(lock: &rtc_lock, flags);
153}
154
155static inline void smpboot_restore_warm_reset_vector(void)
156{
157 unsigned long flags;
158
159 /*
160 * Paranoid: Set warm reset code and vector here back
161 * to default values.
162 */
163 spin_lock_irqsave(&rtc_lock, flags);
164 if (!--smpboot_warm_reset_vector_count) {
165 CMOS_WRITE(0, 0xf);
166 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
167 }
168 spin_unlock_irqrestore(lock: &rtc_lock, flags);
169
170}
171
172/* Run the next set of setup steps for the upcoming CPU */
173static void ap_starting(void)
174{
175 int cpuid = smp_processor_id();
176
177 /* Mop up eventual mwait_play_dead() wreckage */
178 this_cpu_write(mwait_cpu_dead.status, 0);
179 this_cpu_write(mwait_cpu_dead.control, 0);
180
181 /*
182 * If woken up by an INIT in an 82489DX configuration the alive
183 * synchronization guarantees that the CPU does not reach this
184 * point before an INIT_deassert IPI reaches the local APIC, so it
185 * is now safe to touch the local APIC.
186 *
187 * Set up this CPU, first the APIC, which is probably redundant on
188 * most boards.
189 */
190 apic_ap_setup();
191
192 /* Save the processor parameters. */
193 identify_secondary_cpu(cpu: cpuid);
194
195 /*
196 * The topology information must be up to date before
197 * notify_cpu_starting().
198 */
199 set_cpu_sibling_map(cpuid);
200
201 ap_init_aperfmperf();
202
203 pr_debug("Stack at about %p\n", &cpuid);
204
205 wmb();
206
207 /*
208 * This runs the AP through all the cpuhp states to its target
209 * state CPUHP_ONLINE.
210 */
211 notify_cpu_starting(cpu: cpuid);
212}
213
214static void ap_calibrate_delay(void)
215{
216 /*
217 * Calibrate the delay loop and update loops_per_jiffy in cpu_data.
218 * identify_secondary_cpu() stored a value that is close but not as
219 * accurate as the value just calculated.
220 *
221 * As this is invoked after the TSC synchronization check,
222 * calibrate_delay_is_known() will skip the calibration routine
223 * when TSC is synchronized across sockets.
224 */
225 calibrate_delay();
226 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy;
227}
228
229/*
230 * Activate a secondary processor.
231 */
232static void notrace __noendbr start_secondary(void *unused)
233{
234 /*
235 * Don't put *anything* except direct CPU state initialization
236 * before cpu_init(), SMP booting is too fragile that we want to
237 * limit the things done here to the most necessary things.
238 */
239 cr4_init();
240
241 /*
242 * 32-bit specific. 64-bit reaches this code with the correct page
243 * table established. Yet another historical divergence.
244 */
245 if (IS_ENABLED(CONFIG_X86_32)) {
246 /* switch away from the initial page table */
247 load_cr3(swapper_pg_dir);
248 __flush_tlb_all();
249 }
250
251 cpu_init_exception_handling(boot_cpu: false);
252
253 /*
254 * Load the microcode before reaching the AP alive synchronization
255 * point below so it is not part of the full per CPU serialized
256 * bringup part when "parallel" bringup is enabled.
257 *
258 * That's even safe when hyperthreading is enabled in the CPU as
259 * the core code starts the primary threads first and leaves the
260 * secondary threads waiting for SIPI. Loading microcode on
261 * physical cores concurrently is a safe operation.
262 *
263 * This covers both the Intel specific issue that concurrent
264 * microcode loading on SMT siblings must be prohibited and the
265 * vendor independent issue`that microcode loading which changes
266 * CPUID, MSRs etc. must be strictly serialized to maintain
267 * software state correctness.
268 */
269 load_ucode_ap();
270
271 /*
272 * Synchronization point with the hotplug core. Sets this CPUs
273 * synchronization state to ALIVE and spin-waits for the control CPU to
274 * release this CPU for further bringup.
275 */
276 cpuhp_ap_sync_alive();
277
278 cpu_init();
279 fpu__init_cpu();
280 rcutree_report_cpu_starting(raw_smp_processor_id());
281 x86_cpuinit.early_percpu_clock_init();
282
283 ap_starting();
284
285 /* Check TSC synchronization with the control CPU. */
286 check_tsc_sync_target();
287
288 /*
289 * Calibrate the delay loop after the TSC synchronization check.
290 * This allows to skip the calibration when TSC is synchronized
291 * across sockets.
292 */
293 ap_calibrate_delay();
294
295 speculative_store_bypass_ht_init();
296
297 /*
298 * Lock vector_lock, set CPU online and bring the vector
299 * allocator online. Online must be set with vector_lock held
300 * to prevent a concurrent irq setup/teardown from seeing a
301 * half valid vector space.
302 */
303 lock_vector_lock();
304 set_cpu_online(smp_processor_id(), online: true);
305 lapic_online();
306 unlock_vector_lock();
307 x86_platform.nmi_init();
308
309 /* enable local interrupts */
310 local_irq_enable();
311
312 x86_cpuinit.setup_percpu_clockev();
313
314 wmb();
315 cpu_startup_entry(state: CPUHP_AP_ONLINE_IDLE);
316}
317ANNOTATE_NOENDBR_SYM(start_secondary);
318
319static bool
320topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
321{
322 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
323
324 return (cpu_to_node(cpu: cpu1) == cpu_to_node(cpu: cpu2));
325}
326
327static bool
328topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
329{
330 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
331
332 return !WARN_ONCE(!topology_same_node(c, o),
333 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
334 "[node: %d != %d]. Ignoring dependency.\n",
335 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
336}
337
338#define link_mask(mfunc, c1, c2) \
339do { \
340 cpumask_set_cpu((c1), mfunc(c2)); \
341 cpumask_set_cpu((c2), mfunc(c1)); \
342} while (0)
343
344static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
345{
346 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
347 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
348
349 if (c->topo.pkg_id == o->topo.pkg_id &&
350 c->topo.die_id == o->topo.die_id &&
351 c->topo.amd_node_id == o->topo.amd_node_id &&
352 per_cpu_llc_id(cpu: cpu1) == per_cpu_llc_id(cpu: cpu2)) {
353 if (c->topo.core_id == o->topo.core_id)
354 return topology_sane(c, o, name: "smt");
355
356 if ((c->topo.cu_id != 0xff) &&
357 (o->topo.cu_id != 0xff) &&
358 (c->topo.cu_id == o->topo.cu_id))
359 return topology_sane(c, o, name: "smt");
360 }
361
362 } else if (c->topo.pkg_id == o->topo.pkg_id &&
363 c->topo.die_id == o->topo.die_id &&
364 c->topo.core_id == o->topo.core_id) {
365 return topology_sane(c, o, name: "smt");
366 }
367
368 return false;
369}
370
371static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
372{
373 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id)
374 return false;
375
376 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1)
377 return c->topo.amd_node_id == o->topo.amd_node_id;
378
379 return true;
380}
381
382static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
383{
384 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
385
386 /* If the arch didn't set up l2c_id, fall back to SMT */
387 if (per_cpu_l2c_id(cpu: cpu1) == BAD_APICID)
388 return match_smt(c, o);
389
390 /* Do not match if L2 cache id does not match: */
391 if (per_cpu_l2c_id(cpu: cpu1) != per_cpu_l2c_id(cpu: cpu2))
392 return false;
393
394 return topology_sane(c, o, name: "l2c");
395}
396
397/*
398 * Unlike the other levels, we do not enforce keeping a
399 * multicore group inside a NUMA node. If this happens, we will
400 * discard the MC level of the topology later.
401 */
402static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
403{
404 if (c->topo.pkg_id == o->topo.pkg_id)
405 return true;
406 return false;
407}
408
409/*
410 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
411 *
412 * Any Intel CPU that has multiple nodes per package and does not
413 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
414 *
415 * When in SNC mode, these CPUs enumerate an LLC that is shared
416 * by multiple NUMA nodes. The LLC is shared for off-package data
417 * access but private to the NUMA node (half of the package) for
418 * on-package access. CPUID (the source of the information about
419 * the LLC) can only enumerate the cache as shared or unshared,
420 * but not this particular configuration.
421 */
422
423static const struct x86_cpu_id intel_cod_cpu[] = {
424 X86_MATCH_VFM(INTEL_HASWELL_X, 0), /* COD */
425 X86_MATCH_VFM(INTEL_BROADWELL_X, 0), /* COD */
426 X86_MATCH_VFM(INTEL_ANY, 1), /* SNC */
427 {}
428};
429
430static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
431{
432 const struct x86_cpu_id *id = x86_match_cpu(match: intel_cod_cpu);
433 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
434 bool intel_snc = id && id->driver_data;
435
436 /* Do not match if we do not have a valid APICID for cpu: */
437 if (per_cpu_llc_id(cpu: cpu1) == BAD_APICID)
438 return false;
439
440 /* Do not match if LLC id does not match: */
441 if (per_cpu_llc_id(cpu: cpu1) != per_cpu_llc_id(cpu: cpu2))
442 return false;
443
444 /*
445 * Allow the SNC topology without warning. Return of false
446 * means 'c' does not share the LLC of 'o'. This will be
447 * reflected to userspace.
448 */
449 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
450 return false;
451
452 return topology_sane(c, o, name: "llc");
453}
454
455
456static inline int x86_sched_itmt_flags(void)
457{
458 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
459}
460
461#ifdef CONFIG_SCHED_MC
462static int x86_core_flags(void)
463{
464 return cpu_core_flags() | x86_sched_itmt_flags();
465}
466#endif
467#ifdef CONFIG_SCHED_CLUSTER
468static int x86_cluster_flags(void)
469{
470 return cpu_cluster_flags() | x86_sched_itmt_flags();
471}
472#endif
473
474/*
475 * Set if a package/die has multiple NUMA nodes inside.
476 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
477 * Sub-NUMA Clustering have this.
478 */
479static bool x86_has_numa_in_package;
480
481static struct sched_domain_topology_level x86_topology[] = {
482 SDTL_INIT(tl_smt_mask, cpu_smt_flags, SMT),
483#ifdef CONFIG_SCHED_CLUSTER
484 SDTL_INIT(tl_cls_mask, x86_cluster_flags, CLS),
485#endif
486#ifdef CONFIG_SCHED_MC
487 SDTL_INIT(tl_mc_mask, x86_core_flags, MC),
488#endif
489 SDTL_INIT(tl_pkg_mask, x86_sched_itmt_flags, PKG),
490 { NULL },
491};
492
493static void __init build_sched_topology(void)
494{
495 struct sched_domain_topology_level *topology = x86_topology;
496
497 /*
498 * When there is NUMA topology inside the package invalidate the
499 * PKG domain since the NUMA domains will auto-magically create the
500 * right spanning domains based on the SLIT.
501 */
502 if (x86_has_numa_in_package) {
503 unsigned int pkgdom = ARRAY_SIZE(x86_topology) - 2;
504
505 memset(s: &x86_topology[pkgdom], c: 0, n: sizeof(x86_topology[pkgdom]));
506 }
507
508 /*
509 * Drop the SMT domains if there is only one thread per-core
510 * since it'll get degenerated by the scheduler anyways.
511 */
512 if (cpu_smt_num_threads <= 1)
513 ++topology;
514
515 set_sched_topology(topology);
516}
517
518void set_cpu_sibling_map(int cpu)
519{
520 bool has_smt = __max_threads_per_core > 1;
521 bool has_mp = has_smt || topology_num_cores_per_package() > 1;
522 struct cpuinfo_x86 *c = &cpu_data(cpu);
523 struct cpuinfo_x86 *o;
524 int i, threads;
525
526 cpumask_set_cpu(cpu, dstp: cpu_sibling_setup_mask);
527
528 if (!has_mp) {
529 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
530 cpumask_set_cpu(cpu, dstp: cpu_llc_shared_mask(cpu));
531 cpumask_set_cpu(cpu, dstp: cpu_l2c_shared_mask(cpu));
532 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
533 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
534 c->booted_cores = 1;
535 return;
536 }
537
538 for_each_cpu(i, cpu_sibling_setup_mask) {
539 o = &cpu_data(i);
540
541 if (match_pkg(c, o) && !topology_same_node(c, o))
542 x86_has_numa_in_package = true;
543
544 if ((i == cpu) || (has_smt && match_smt(c, o)))
545 link_mask(topology_sibling_cpumask, cpu, i);
546
547 if ((i == cpu) || (has_mp && match_llc(c, o)))
548 link_mask(cpu_llc_shared_mask, cpu, i);
549
550 if ((i == cpu) || (has_mp && match_l2c(c, o)))
551 link_mask(cpu_l2c_shared_mask, cpu, i);
552
553 if ((i == cpu) || (has_mp && match_die(c, o)))
554 link_mask(topology_die_cpumask, cpu, i);
555 }
556
557 threads = cpumask_weight(topology_sibling_cpumask(cpu));
558 if (threads > __max_smt_threads)
559 __max_smt_threads = threads;
560
561 for_each_cpu(i, topology_sibling_cpumask(cpu))
562 cpu_data(i).smt_active = threads > 1;
563
564 /*
565 * This needs a separate iteration over the cpus because we rely on all
566 * topology_sibling_cpumask links to be set-up.
567 */
568 for_each_cpu(i, cpu_sibling_setup_mask) {
569 o = &cpu_data(i);
570
571 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
572 link_mask(topology_core_cpumask, cpu, i);
573
574 /*
575 * Does this new cpu bringup a new core?
576 */
577 if (threads == 1) {
578 /*
579 * for each core in package, increment
580 * the booted_cores for this new cpu
581 */
582 if (cpumask_first(
583 topology_sibling_cpumask(i)) == i)
584 c->booted_cores++;
585 /*
586 * increment the core count for all
587 * the other cpus in this package
588 */
589 if (i != cpu)
590 cpu_data(i).booted_cores++;
591 } else if (i != cpu && !c->booted_cores)
592 c->booted_cores = cpu_data(i).booted_cores;
593 }
594 }
595}
596
597/* maps the cpu to the sched domain representing multi-core */
598const struct cpumask *cpu_coregroup_mask(int cpu)
599{
600 return cpu_llc_shared_mask(cpu);
601}
602
603const struct cpumask *cpu_clustergroup_mask(int cpu)
604{
605 return cpu_l2c_shared_mask(cpu);
606}
607EXPORT_SYMBOL_GPL(cpu_clustergroup_mask);
608
609static void impress_friends(void)
610{
611 int cpu;
612 unsigned long bogosum = 0;
613 /*
614 * Allow the user to impress friends.
615 */
616 pr_debug("Before bogomips\n");
617 for_each_online_cpu(cpu)
618 bogosum += cpu_data(cpu).loops_per_jiffy;
619
620 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
621 num_online_cpus(),
622 bogosum/(500000/HZ),
623 (bogosum/(5000/HZ))%100);
624
625 pr_debug("Before bogocount - setting activated=1\n");
626}
627
628/*
629 * The Multiprocessor Specification 1.4 (1997) example code suggests
630 * that there should be a 10ms delay between the BSP asserting INIT
631 * and de-asserting INIT, when starting a remote processor.
632 * But that slows boot and resume on modern processors, which include
633 * many cores and don't require that delay.
634 *
635 * Cmdline "cpu_init_udelay=" is available to override this delay.
636 */
637#define UDELAY_10MS_LEGACY 10000
638
639static unsigned int init_udelay = UINT_MAX;
640
641static int __init cpu_init_udelay(char *str)
642{
643 get_option(str: &str, pint: &init_udelay);
644
645 return 0;
646}
647early_param("cpu_init_udelay", cpu_init_udelay);
648
649static void __init smp_set_init_udelay(void)
650{
651 /* if cmdline changed it from default, leave it alone */
652 if (init_udelay != UINT_MAX)
653 return;
654
655 /* if modern processor, use no delay */
656 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86_vfm >= INTEL_PENTIUM_PRO) ||
657 (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON && boot_cpu_data.x86 >= 0x18) ||
658 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && boot_cpu_data.x86 >= 0xF)) {
659 init_udelay = 0;
660 return;
661 }
662 /* else, use legacy delay */
663 init_udelay = UDELAY_10MS_LEGACY;
664}
665
666/*
667 * Wake up AP by INIT, INIT, STARTUP sequence.
668 */
669static void send_init_sequence(u32 phys_apicid)
670{
671 int maxlvt = lapic_get_maxlvt();
672
673 /* Be paranoid about clearing APIC errors. */
674 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
675 /* Due to the Pentium erratum 3AP. */
676 if (maxlvt > 3)
677 apic_write(APIC_ESR, val: 0);
678 apic_read(APIC_ESR);
679 }
680
681 /* Assert INIT on the target CPU */
682 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, high: phys_apicid);
683 safe_apic_wait_icr_idle();
684
685 udelay(usec: init_udelay);
686
687 /* Deassert INIT on the target CPU */
688 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, high: phys_apicid);
689 safe_apic_wait_icr_idle();
690}
691
692/*
693 * Wake up AP by INIT, INIT, STARTUP sequence.
694 */
695static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip, unsigned int cpu)
696{
697 unsigned long send_status = 0, accept_status = 0;
698 int num_starts, j, maxlvt;
699
700 preempt_disable();
701 maxlvt = lapic_get_maxlvt();
702 send_init_sequence(phys_apicid);
703
704 mb();
705
706 /*
707 * Should we send STARTUP IPIs ?
708 *
709 * Determine this based on the APIC version.
710 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
711 */
712 if (APIC_INTEGRATED(boot_cpu_apic_version))
713 num_starts = 2;
714 else
715 num_starts = 0;
716
717 /*
718 * Run STARTUP IPI loop.
719 */
720 pr_debug("#startup loops: %d\n", num_starts);
721
722 for (j = 1; j <= num_starts; j++) {
723 pr_debug("Sending STARTUP #%d\n", j);
724 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
725 apic_write(APIC_ESR, val: 0);
726 apic_read(APIC_ESR);
727 pr_debug("After apic_write\n");
728
729 /*
730 * STARTUP IPI
731 */
732
733 /* Target chip */
734 /* Boot on the stack */
735 /* Kick the second */
736 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
737 high: phys_apicid);
738
739 /*
740 * Give the other CPU some time to accept the IPI.
741 */
742 if (init_udelay == 0)
743 udelay(usec: 10);
744 else
745 udelay(usec: 300);
746
747 pr_debug("Startup point 1\n");
748
749 pr_debug("Waiting for send to finish...\n");
750 send_status = safe_apic_wait_icr_idle();
751
752 /*
753 * Give the other CPU some time to accept the IPI.
754 */
755 if (init_udelay == 0)
756 udelay(usec: 10);
757 else
758 udelay(usec: 200);
759
760 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
761 apic_write(APIC_ESR, val: 0);
762 accept_status = (apic_read(APIC_ESR) & 0xEF);
763 if (send_status || accept_status)
764 break;
765 }
766 pr_debug("After Startup\n");
767
768 if (send_status)
769 pr_err("APIC never delivered???\n");
770 if (accept_status)
771 pr_err("APIC delivery error (%lx)\n", accept_status);
772
773 preempt_enable();
774 return (send_status | accept_status);
775}
776
777/* reduce the number of lines printed when booting a large cpu count system */
778static void announce_cpu(int cpu, int apicid)
779{
780 static int width, node_width, first = 1;
781 static int current_node = NUMA_NO_NODE;
782 int node = early_cpu_to_node(cpu);
783
784 if (!width)
785 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
786
787 if (!node_width)
788 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
789
790 if (system_state < SYSTEM_RUNNING) {
791 if (first)
792 pr_info("x86: Booting SMP configuration:\n");
793
794 if (node != current_node) {
795 if (current_node > (-1))
796 pr_cont("\n");
797 current_node = node;
798
799 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
800 node_width - num_digits(node), " ", node);
801 }
802
803 /* Add padding for the BSP */
804 if (first)
805 pr_cont("%*s", width + 1, " ");
806 first = 0;
807
808 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
809 } else
810 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
811 node, cpu, apicid);
812}
813
814int common_cpu_up(unsigned int cpu, struct task_struct *idle)
815{
816 int ret;
817
818 /* Just in case we booted with a single CPU. */
819 alternatives_enable_smp();
820
821 per_cpu(current_task, cpu) = idle;
822 cpu_init_stack_canary(cpu, idle);
823
824 /* Initialize the interrupt stack(s) */
825 ret = irq_init_percpu_irqstack(cpu);
826 if (ret)
827 return ret;
828
829#ifdef CONFIG_X86_32
830 /* Stack for startup_32 can be just as for start_secondary onwards */
831 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
832#endif
833 return 0;
834}
835
836/*
837 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
838 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
839 * Returns zero if startup was successfully sent, else error code from
840 * ->wakeup_secondary_cpu.
841 */
842static int do_boot_cpu(u32 apicid, unsigned int cpu, struct task_struct *idle)
843{
844 unsigned long start_ip = real_mode_header->trampoline_start;
845 int ret;
846
847#ifdef CONFIG_X86_64
848 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
849 if (apic->wakeup_secondary_cpu_64)
850 start_ip = real_mode_header->trampoline_start64;
851#endif
852 idle->thread.sp = (unsigned long)task_pt_regs(idle);
853 initial_code = (unsigned long)start_secondary;
854
855 if (IS_ENABLED(CONFIG_X86_32)) {
856 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
857 initial_stack = idle->thread.sp;
858 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) {
859 smpboot_control = cpu;
860 }
861
862 /* Enable the espfix hack for this CPU */
863 init_espfix_ap(cpu);
864
865 /* So we see what's up */
866 announce_cpu(cpu, apicid);
867
868 /*
869 * This grunge runs the startup process for
870 * the targeted processor.
871 */
872 if (x86_platform.legacy.warm_reset) {
873
874 pr_debug("Setting warm reset code and vector.\n");
875
876 smpboot_setup_warm_reset_vector(start_eip: start_ip);
877 /*
878 * Be paranoid about clearing APIC errors.
879 */
880 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
881 apic_write(APIC_ESR, val: 0);
882 apic_read(APIC_ESR);
883 }
884 }
885
886 smp_mb();
887
888 /*
889 * Wake up a CPU in difference cases:
890 * - Use a method from the APIC driver if one defined, with wakeup
891 * straight to 64-bit mode preferred over wakeup to RM.
892 * Otherwise,
893 * - Use an INIT boot APIC message
894 */
895 if (apic->wakeup_secondary_cpu_64)
896 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip, cpu);
897 else if (apic->wakeup_secondary_cpu)
898 ret = apic->wakeup_secondary_cpu(apicid, start_ip, cpu);
899 else
900 ret = wakeup_secondary_cpu_via_init(phys_apicid: apicid, start_eip: start_ip, cpu);
901
902 /* If the wakeup mechanism failed, cleanup the warm reset vector */
903 if (ret)
904 arch_cpuhp_cleanup_kick_cpu(cpu);
905 return ret;
906}
907
908int native_kick_ap(unsigned int cpu, struct task_struct *tidle)
909{
910 u32 apicid = apic->cpu_present_to_apicid(cpu);
911 int err;
912
913 lockdep_assert_irqs_enabled();
914
915 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
916
917 if (apicid == BAD_APICID || !apic_id_valid(apic_id: apicid)) {
918 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid);
919 return -EINVAL;
920 }
921
922 if (!test_bit(apicid, phys_cpu_present_map)) {
923 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid);
924 return -EINVAL;
925 }
926
927 /*
928 * Save current MTRR state in case it was changed since early boot
929 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
930 */
931 mtrr_save_state();
932
933 /* the FPU context is blank, nobody can own it */
934 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
935
936 err = common_cpu_up(cpu, idle: tidle);
937 if (err)
938 return err;
939
940 err = do_boot_cpu(apicid, cpu, idle: tidle);
941 if (err)
942 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
943
944 return err;
945}
946
947int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle)
948{
949 return smp_ops.kick_ap_alive(cpu, tidle);
950}
951
952void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu)
953{
954 /* Cleanup possible dangling ends... */
955 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset)
956 smpboot_restore_warm_reset_vector();
957}
958
959void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
960{
961 if (smp_ops.cleanup_dead_cpu)
962 smp_ops.cleanup_dead_cpu(cpu);
963
964 if (system_state == SYSTEM_RUNNING)
965 pr_info("CPU %u is now offline\n", cpu);
966}
967
968void arch_cpuhp_sync_state_poll(void)
969{
970 if (smp_ops.poll_sync_state)
971 smp_ops.poll_sync_state();
972}
973
974/**
975 * arch_disable_smp_support() - Disables SMP support for x86 at boottime
976 */
977void __init arch_disable_smp_support(void)
978{
979 disable_ioapic_support();
980}
981
982/*
983 * Fall back to non SMP mode after errors.
984 *
985 * RED-PEN audit/test this more. I bet there is more state messed up here.
986 */
987static __init void disable_smp(void)
988{
989 pr_info("SMP disabled\n");
990
991 disable_ioapic_support();
992 topology_reset_possible_cpus_up();
993
994 cpumask_set_cpu(cpu: 0, topology_sibling_cpumask(0));
995 cpumask_set_cpu(cpu: 0, topology_core_cpumask(0));
996 cpumask_set_cpu(cpu: 0, topology_die_cpumask(0));
997}
998
999void __init smp_prepare_cpus_common(void)
1000{
1001 unsigned int cpu, node;
1002
1003 /* Mark all except the boot CPU as hotpluggable */
1004 for_each_possible_cpu(cpu) {
1005 if (cpu)
1006 per_cpu(cpu_info.cpu_index, cpu) = nr_cpu_ids;
1007 }
1008
1009 for_each_possible_cpu(cpu) {
1010 node = cpu_to_node(cpu);
1011
1012 zalloc_cpumask_var_node(mask: &per_cpu(cpu_sibling_map, cpu), GFP_KERNEL, node);
1013 zalloc_cpumask_var_node(mask: &per_cpu(cpu_core_map, cpu), GFP_KERNEL, node);
1014 zalloc_cpumask_var_node(mask: &per_cpu(cpu_die_map, cpu), GFP_KERNEL, node);
1015 zalloc_cpumask_var_node(mask: &per_cpu(cpu_llc_shared_map, cpu), GFP_KERNEL, node);
1016 zalloc_cpumask_var_node(mask: &per_cpu(cpu_l2c_shared_map, cpu), GFP_KERNEL, node);
1017 }
1018
1019 set_cpu_sibling_map(0);
1020}
1021
1022void __init smp_prepare_boot_cpu(void)
1023{
1024 smp_ops.smp_prepare_boot_cpu();
1025}
1026
1027#ifdef CONFIG_X86_64
1028/* Establish whether parallel bringup can be supported. */
1029bool __init arch_cpuhp_init_parallel_bringup(void)
1030{
1031 if (!x86_cpuinit.parallel_bringup) {
1032 pr_info("Parallel CPU startup disabled by the platform\n");
1033 return false;
1034 }
1035
1036 smpboot_control = STARTUP_READ_APICID;
1037 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control);
1038 return true;
1039}
1040#endif
1041
1042/*
1043 * Prepare for SMP bootup.
1044 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1045 * for common interface support.
1046 */
1047void __init native_smp_prepare_cpus(unsigned int max_cpus)
1048{
1049 smp_prepare_cpus_common();
1050
1051 switch (apic_intr_mode) {
1052 case APIC_PIC:
1053 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1054 disable_smp();
1055 return;
1056 case APIC_SYMMETRIC_IO_NO_ROUTING:
1057 disable_smp();
1058 /* Setup local timer */
1059 x86_init.timers.setup_percpu_clockev();
1060 return;
1061 case APIC_VIRTUAL_WIRE:
1062 case APIC_SYMMETRIC_IO:
1063 break;
1064 }
1065
1066 /* Setup local timer */
1067 x86_init.timers.setup_percpu_clockev();
1068
1069 pr_info("CPU0: ");
1070 print_cpu_info(&cpu_data(0));
1071
1072 uv_system_init();
1073
1074 smp_set_init_udelay();
1075
1076 speculative_store_bypass_ht_init();
1077
1078 snp_set_wakeup_secondary_cpu();
1079}
1080
1081void arch_thaw_secondary_cpus_begin(void)
1082{
1083 set_cache_aps_delayed_init(true);
1084}
1085
1086void arch_thaw_secondary_cpus_end(void)
1087{
1088 cache_aps_init();
1089}
1090
1091/*
1092 * Early setup to make printk work.
1093 */
1094void __init native_smp_prepare_boot_cpu(void)
1095{
1096 int me = smp_processor_id();
1097
1098 /* SMP handles this from setup_per_cpu_areas() */
1099 if (!IS_ENABLED(CONFIG_SMP))
1100 switch_gdt_and_percpu_base(me);
1101
1102 native_pv_lock_init();
1103}
1104
1105void __init native_smp_cpus_done(unsigned int max_cpus)
1106{
1107 pr_debug("Boot done\n");
1108
1109 build_sched_topology();
1110 nmi_selftest();
1111 impress_friends();
1112 cache_aps_init();
1113}
1114
1115/* correctly size the local cpu masks */
1116void __init setup_cpu_local_masks(void)
1117{
1118 alloc_bootmem_cpumask_var(mask: &cpu_sibling_setup_mask);
1119}
1120
1121#ifdef CONFIG_HOTPLUG_CPU
1122
1123/* Recompute SMT state for all CPUs on offline */
1124static void recompute_smt_state(void)
1125{
1126 int max_threads, cpu;
1127
1128 max_threads = 0;
1129 for_each_online_cpu (cpu) {
1130 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1131
1132 if (threads > max_threads)
1133 max_threads = threads;
1134 }
1135 __max_smt_threads = max_threads;
1136}
1137
1138static void remove_siblinginfo(int cpu)
1139{
1140 int sibling;
1141 struct cpuinfo_x86 *c = &cpu_data(cpu);
1142
1143 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1144 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1145 /*/
1146 * last thread sibling in this cpu core going down
1147 */
1148 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1149 cpu_data(sibling).booted_cores--;
1150 }
1151
1152 for_each_cpu(sibling, topology_die_cpumask(cpu))
1153 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1154
1155 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1156 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1157 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1158 cpu_data(sibling).smt_active = false;
1159 }
1160
1161 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1162 cpumask_clear_cpu(cpu, dstp: cpu_llc_shared_mask(cpu: sibling));
1163 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1164 cpumask_clear_cpu(cpu, dstp: cpu_l2c_shared_mask(cpu: sibling));
1165 cpumask_clear(dstp: cpu_llc_shared_mask(cpu));
1166 cpumask_clear(dstp: cpu_l2c_shared_mask(cpu));
1167 cpumask_clear(topology_sibling_cpumask(cpu));
1168 cpumask_clear(topology_core_cpumask(cpu));
1169 cpumask_clear(topology_die_cpumask(cpu));
1170 c->topo.core_id = 0;
1171 c->booted_cores = 0;
1172 cpumask_clear_cpu(cpu, dstp: cpu_sibling_setup_mask);
1173 recompute_smt_state();
1174}
1175
1176static void remove_cpu_from_maps(int cpu)
1177{
1178 set_cpu_online(cpu, online: false);
1179 numa_remove_cpu(cpu);
1180}
1181
1182void cpu_disable_common(void)
1183{
1184 int cpu = smp_processor_id();
1185
1186 remove_siblinginfo(cpu);
1187
1188 /*
1189 * Stop allowing kernel-mode FPU. This is needed so that if the CPU is
1190 * brought online again, the initial state is not allowed:
1191 */
1192 this_cpu_write(kernel_fpu_allowed, false);
1193
1194 /* It's now safe to remove this processor from the online map */
1195 lock_vector_lock();
1196 remove_cpu_from_maps(cpu);
1197 unlock_vector_lock();
1198 fixup_irqs();
1199 lapic_offline();
1200}
1201
1202int native_cpu_disable(void)
1203{
1204 int ret;
1205
1206 ret = lapic_can_unplug_cpu();
1207 if (ret)
1208 return ret;
1209
1210 cpu_disable_common();
1211
1212 /*
1213 * Disable the local APIC. Otherwise IPI broadcasts will reach
1214 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1215 * messages.
1216 *
1217 * Disabling the APIC must happen after cpu_disable_common()
1218 * which invokes fixup_irqs().
1219 *
1220 * Disabling the APIC preserves already set bits in IRR, but
1221 * an interrupt arriving after disabling the local APIC does not
1222 * set the corresponding IRR bit.
1223 *
1224 * fixup_irqs() scans IRR for set bits so it can raise a not
1225 * yet handled interrupt on the new destination CPU via an IPI
1226 * but obviously it can't do so for IRR bits which are not set.
1227 * IOW, interrupts arriving after disabling the local APIC will
1228 * be lost.
1229 */
1230 apic_soft_disable();
1231
1232 return 0;
1233}
1234
1235void play_dead_common(void)
1236{
1237 idle_task_exit();
1238
1239 cpuhp_ap_report_dead();
1240
1241 local_irq_disable();
1242}
1243
1244/*
1245 * We need to flush the caches before going to sleep, lest we have
1246 * dirty data in our caches when we come back up.
1247 */
1248void __noreturn mwait_play_dead(unsigned int eax_hint)
1249{
1250 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1251
1252 /* Set up state for the kexec() hack below */
1253 md->status = CPUDEAD_MWAIT_WAIT;
1254 md->control = CPUDEAD_MWAIT_WAIT;
1255
1256 wbinvd();
1257
1258 while (1) {
1259 /*
1260 * The CLFLUSH is a workaround for erratum AAI65 for
1261 * the Xeon 7400 series. It's not clear it is actually
1262 * needed, but it should be harmless in either case.
1263 * The WBINVD is insufficient due to the spurious-wakeup
1264 * case where we return around the loop.
1265 */
1266 mb();
1267 clflush(p: md);
1268 mb();
1269 __monitor(eax: md, ecx: 0, edx: 0);
1270 mb();
1271 __mwait(eax: eax_hint, ecx: 0);
1272
1273 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
1274 /*
1275 * Kexec is about to happen. Don't go back into mwait() as
1276 * the kexec kernel might overwrite text and data including
1277 * page tables and stack. So mwait() would resume when the
1278 * monitor cache line is written to and then the CPU goes
1279 * south due to overwritten text, page tables and stack.
1280 *
1281 * Note: This does _NOT_ protect against a stray MCE, NMI,
1282 * SMI. They will resume execution at the instruction
1283 * following the HLT instruction and run into the problem
1284 * which this is trying to prevent.
1285 */
1286 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
1287 while(1)
1288 native_halt();
1289 }
1290 }
1291}
1292
1293/*
1294 * Kick all "offline" CPUs out of mwait on kexec(). See comment in
1295 * mwait_play_dead().
1296 */
1297void smp_kick_mwait_play_dead(void)
1298{
1299 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
1300 struct mwait_cpu_dead *md;
1301 unsigned int cpu, i;
1302
1303 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
1304 md = per_cpu_ptr(&mwait_cpu_dead, cpu);
1305
1306 /* Does it sit in mwait_play_dead() ? */
1307 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
1308 continue;
1309
1310 /* Wait up to 5ms */
1311 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
1312 /* Bring it out of mwait */
1313 WRITE_ONCE(md->control, newstate);
1314 udelay(usec: 5);
1315 }
1316
1317 if (READ_ONCE(md->status) != newstate)
1318 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
1319 }
1320}
1321
1322void __noreturn hlt_play_dead(void)
1323{
1324 if (__this_cpu_read(cpu_info.x86) >= 4)
1325 wbinvd();
1326
1327 while (1)
1328 native_halt();
1329}
1330
1331/*
1332 * native_play_dead() is essentially a __noreturn function, but it can't
1333 * be marked as such as the compiler may complain about it.
1334 */
1335void native_play_dead(void)
1336{
1337 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
1338 __update_spec_ctrl(val: 0);
1339
1340 play_dead_common();
1341 tboot_shutdown(TB_SHUTDOWN_WFS);
1342
1343 /* Below returns only on error. */
1344 cpuidle_play_dead();
1345 hlt_play_dead();
1346}
1347
1348#else /* ... !CONFIG_HOTPLUG_CPU */
1349int native_cpu_disable(void)
1350{
1351 return -ENOSYS;
1352}
1353
1354void native_play_dead(void)
1355{
1356 BUG();
1357}
1358
1359#endif
1360