1/*
2 * Copyright © 2008 Intel Corporation
3 * 2014 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26#include <linux/log2.h>
27#include <linux/math.h>
28
29#include <drm/drm_atomic.h>
30#include <drm/drm_atomic_helper.h>
31#include <drm/drm_edid.h>
32#include <drm/drm_fixed.h>
33#include <drm/drm_print.h>
34#include <drm/drm_probe_helper.h>
35
36#include "i915_utils.h"
37#include "intel_atomic.h"
38#include "intel_audio.h"
39#include "intel_connector.h"
40#include "intel_crtc.h"
41#include "intel_ddi.h"
42#include "intel_de.h"
43#include "intel_display_driver.h"
44#include "intel_display_regs.h"
45#include "intel_display_types.h"
46#include "intel_dp.h"
47#include "intel_dp_hdcp.h"
48#include "intel_dp_link_training.h"
49#include "intel_dp_mst.h"
50#include "intel_dp_test.h"
51#include "intel_dp_tunnel.h"
52#include "intel_dpio_phy.h"
53#include "intel_hdcp.h"
54#include "intel_hotplug.h"
55#include "intel_link_bw.h"
56#include "intel_pfit.h"
57#include "intel_psr.h"
58#include "intel_step.h"
59#include "intel_vdsc.h"
60#include "intel_vrr.h"
61#include "skl_scaler.h"
62
63/*
64 * DP MST (DisplayPort Multi-Stream Transport)
65 *
66 * MST support on the source depends on the platform and port. DP initialization
67 * sets up MST for each MST capable encoder. This will become the primary
68 * encoder for the port.
69 *
70 * MST initialization of each primary encoder creates MST stream encoders, one
71 * per pipe, and initializes the MST topology manager. The MST stream encoders
72 * are sometimes called "fake encoders", because they're virtual, not
73 * physical. Thus there are (number of MST capable ports) x (number of pipes)
74 * MST stream encoders in total.
75 *
76 * Decision to use MST for a sink happens at detect on the connector attached to
77 * the primary encoder, and this will not change while the sink is connected. We
78 * always use MST when possible, including for SST sinks with sideband messaging
79 * support.
80 *
81 * The connectors for the MST streams are added and removed dynamically by the
82 * topology manager. Their connection status is also determined by the topology
83 * manager.
84 *
85 * On hardware, each transcoder may be associated with a single DDI
86 * port. Multiple transcoders may be associated with the same DDI port only if
87 * the port is in MST mode.
88 *
89 * On TGL+, all the transcoders streaming on the same DDI port will indicate a
90 * primary transcoder; the TGL_DP_TP_CTL and TGL_DP_TP_STATUS registers are
91 * relevant only on the primary transcoder. Prior to that, they are port
92 * registers.
93 */
94
95/* From fake MST stream encoder to primary encoder */
96static struct intel_encoder *to_primary_encoder(struct intel_encoder *encoder)
97{
98 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
99 struct intel_digital_port *dig_port = intel_mst->primary;
100
101 return &dig_port->base;
102}
103
104/* From fake MST stream encoder to primary DP */
105static struct intel_dp *to_primary_dp(struct intel_encoder *encoder)
106{
107 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
108 struct intel_digital_port *dig_port = intel_mst->primary;
109
110 return &dig_port->dp;
111}
112
113int intel_dp_mst_active_streams(struct intel_dp *intel_dp)
114{
115 return intel_dp->mst.active_streams;
116}
117
118static bool intel_dp_mst_dec_active_streams(struct intel_dp *intel_dp)
119{
120 struct intel_display *display = to_intel_display(intel_dp);
121
122 drm_dbg_kms(display->drm, "active MST streams %d -> %d\n",
123 intel_dp->mst.active_streams, intel_dp->mst.active_streams - 1);
124
125 if (drm_WARN_ON(display->drm, intel_dp->mst.active_streams == 0))
126 return true;
127
128 return --intel_dp->mst.active_streams == 0;
129}
130
131static bool intel_dp_mst_inc_active_streams(struct intel_dp *intel_dp)
132{
133 struct intel_display *display = to_intel_display(intel_dp);
134
135 drm_dbg_kms(display->drm, "active MST streams %d -> %d\n",
136 intel_dp->mst.active_streams, intel_dp->mst.active_streams + 1);
137
138 return intel_dp->mst.active_streams++ == 0;
139}
140
141/* TODO: return a bpp_x16 value */
142static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state,
143 bool dsc)
144{
145 struct intel_display *display = to_intel_display(crtc_state);
146 const struct drm_display_mode *adjusted_mode =
147 &crtc_state->hw.adjusted_mode;
148
149 if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc)
150 return 0;
151
152 /*
153 * DSC->DPT interface width:
154 * ICL-MTL: 72 bits (each branch has 72 bits, only left branch is used)
155 * LNL+: 144 bits (not a bottleneck in any config)
156 *
157 * Bspec/49259 suggests that the FEC overhead needs to be
158 * applied here, though HW people claim that neither this FEC
159 * or any other overhead is applicable here (that is the actual
160 * available_bw is just symbol_clock * 72). However based on
161 * testing on MTL-P the
162 * - DELL U3224KBA display
163 * - Unigraf UCD-500 CTS test sink
164 * devices the
165 * - 5120x2880/995.59Mhz
166 * - 6016x3384/1357.23Mhz
167 * - 6144x3456/1413.39Mhz
168 * modes (all the ones having a DPT limit on the above devices),
169 * both the channel coding efficiency and an additional 3%
170 * overhead needs to be accounted for.
171 */
172 return div64_u64(dividend: mul_u32_u32(a: intel_dp_link_symbol_clock(rate: crtc_state->port_clock) * 72,
173 b: drm_dp_bw_channel_coding_efficiency(is_uhbr: true)),
174 divisor: mul_u32_u32(a: adjusted_mode->crtc_clock, b: 1030000));
175}
176
177static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
178 bool ssc, int dsc_slice_count, int bpp_x16)
179{
180 const struct drm_display_mode *adjusted_mode =
181 &crtc_state->hw.adjusted_mode;
182 unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
183 int overhead;
184
185 flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
186 flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
187 flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
188
189 if (dsc_slice_count)
190 flags |= DRM_DP_BW_OVERHEAD_DSC;
191
192 overhead = drm_dp_bw_overhead(lane_count: crtc_state->lane_count,
193 hactive: adjusted_mode->hdisplay,
194 dsc_slice_count,
195 bpp_x16,
196 flags);
197
198 /*
199 * TODO: clarify whether a minimum required by the fixed FEC overhead
200 * in the bspec audio programming sequence is required here.
201 */
202 return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
203}
204
205static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
206 int overhead,
207 int bpp_x16,
208 struct intel_link_m_n *m_n)
209{
210 const struct drm_display_mode *adjusted_mode =
211 &crtc_state->hw.adjusted_mode;
212
213 /* TODO: Check WA 14013163432 to set data M/N for full BW utilization. */
214 intel_link_compute_m_n(bpp: bpp_x16, nlanes: crtc_state->lane_count,
215 pixel_clock: adjusted_mode->crtc_clock,
216 link_clock: crtc_state->port_clock,
217 bw_overhead: overhead,
218 m_n);
219
220 m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
221}
222
223static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead)
224{
225 int effective_data_rate =
226 intel_dp_effective_data_rate(pixel_clock, bpp_x16, bw_overhead);
227
228 /*
229 * TODO: Use drm_dp_calc_pbn_mode() instead, once it's converted
230 * to calculate PBN with the BW overhead passed to it.
231 */
232 return DIV_ROUND_UP(effective_data_rate * 64, 54 * 1000);
233}
234
235static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connector,
236 const struct intel_crtc_state *crtc_state)
237{
238 const struct drm_display_mode *adjusted_mode =
239 &crtc_state->hw.adjusted_mode;
240 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
241
242 return intel_dp_dsc_get_slice_count(connector,
243 mode_clock: adjusted_mode->clock,
244 mode_hdisplay: adjusted_mode->hdisplay,
245 num_joined_pipes);
246}
247
248static void mst_stream_update_slots(const struct intel_crtc_state *crtc_state,
249 struct drm_dp_mst_topology_state *topology_state)
250{
251 u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
252 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
253
254 drm_dp_mst_update_slots(mst_state: topology_state, link_encoding_cap: link_coding_cap);
255}
256
257int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
258 struct intel_crtc_state *crtc_state,
259 struct drm_connector_state *conn_state,
260 int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc)
261{
262 struct intel_display *display = to_intel_display(intel_dp);
263 struct drm_atomic_state *state = crtc_state->uapi.state;
264 struct drm_dp_mst_topology_state *mst_state = NULL;
265 struct intel_connector *connector =
266 to_intel_connector(conn_state->connector);
267 const struct drm_display_mode *adjusted_mode =
268 &crtc_state->hw.adjusted_mode;
269 bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
270 int bpp_x16, slots = -EINVAL;
271 int dsc_slice_count = 0;
272 int max_dpt_bpp_x16;
273
274 /* shouldn't happen, sanity check */
275 drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) ||
276 fxp_q4_to_frac(max_bpp_x16) ||
277 fxp_q4_to_frac(bpp_step_x16)));
278
279 if (!bpp_step_x16) {
280 /* Allow using zero step only to indicate single try for a given bpp. */
281 drm_WARN_ON(display->drm, min_bpp_x16 != max_bpp_x16);
282 bpp_step_x16 = 1;
283 }
284
285 if (is_mst) {
286 mst_state = drm_atomic_get_mst_topology_state(state, mgr: &intel_dp->mst.mgr);
287 if (IS_ERR(ptr: mst_state))
288 return PTR_ERR(ptr: mst_state);
289
290 mst_state->pbn_div = drm_dp_get_vc_payload_bw(link_rate: crtc_state->port_clock,
291 link_lane_count: crtc_state->lane_count);
292
293 mst_stream_update_slots(crtc_state, topology_state: mst_state);
294 }
295
296 if (dsc) {
297 if (!intel_dp_supports_fec(intel_dp, connector, pipe_config: crtc_state))
298 return -EINVAL;
299
300 crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
301 }
302
303 max_dpt_bpp_x16 = fxp_q4_from_int(val_int: intel_dp_mst_max_dpt_bpp(crtc_state, dsc));
304 if (max_dpt_bpp_x16 && max_bpp_x16 > max_dpt_bpp_x16) {
305 drm_dbg_kms(display->drm, "Limiting bpp to max DPT bpp (" FXP_Q4_FMT " -> " FXP_Q4_FMT ")\n",
306 FXP_Q4_ARGS(max_bpp_x16), FXP_Q4_ARGS(max_dpt_bpp_x16));
307 max_bpp_x16 = max_dpt_bpp_x16;
308 }
309
310 drm_dbg_kms(display->drm, "Looking for slots in range min bpp " FXP_Q4_FMT " max bpp " FXP_Q4_FMT "\n",
311 FXP_Q4_ARGS(min_bpp_x16), FXP_Q4_ARGS(max_bpp_x16));
312
313 if (dsc) {
314 dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, crtc_state);
315 if (!dsc_slice_count) {
316 drm_dbg_kms(display->drm, "Can't get valid DSC slice count\n");
317
318 return -ENOSPC;
319 }
320 }
321
322 drm_WARN_ON(display->drm, min_bpp_x16 % bpp_step_x16 || max_bpp_x16 % bpp_step_x16);
323
324 for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) {
325 int local_bw_overhead;
326 int link_bpp_x16;
327
328 drm_dbg_kms(display->drm, "Trying bpp " FXP_Q4_FMT "\n", FXP_Q4_ARGS(bpp_x16));
329
330 if (dsc && !intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) {
331 /* SST must have validated the single bpp tried here already earlier. */
332 drm_WARN_ON(display->drm, !is_mst);
333 continue;
334 }
335
336 link_bpp_x16 = dsc ? bpp_x16 :
337 fxp_q4_from_int(val_int: intel_dp_output_bpp(output_format: crtc_state->output_format,
338 bpp: fxp_q4_to_int(val_q4: bpp_x16)));
339
340 local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
341 ssc: false, dsc_slice_count, bpp_x16: link_bpp_x16);
342
343 intel_dp_mst_compute_m_n(crtc_state,
344 overhead: local_bw_overhead,
345 bpp_x16: link_bpp_x16,
346 m_n: &crtc_state->dp_m_n);
347
348 if (is_mst) {
349 int remote_bw_overhead;
350 int remote_tu;
351 fixed20_12 pbn;
352
353 remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
354 ssc: true, dsc_slice_count, bpp_x16: link_bpp_x16);
355
356 /*
357 * The TU size programmed to the HW determines which slots in
358 * an MTP frame are used for this stream, which needs to match
359 * the payload size programmed to the first downstream branch
360 * device's payload table.
361 *
362 * Note that atm the payload's PBN value DRM core sends via
363 * the ALLOCATE_PAYLOAD side-band message matches the payload
364 * size (which it calculates from the PBN value) it programs
365 * to the first branch device's payload table. The allocation
366 * in the payload table could be reduced though (to
367 * crtc_state->dp_m_n.tu), provided that the driver doesn't
368 * enable SSC on the corresponding link.
369 */
370 pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
371 link_bpp_x16,
372 remote_bw_overhead));
373 remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);
374
375 /*
376 * Aligning the TUs ensures that symbols consisting of multiple
377 * (4) symbol cycles don't get split between two consecutive
378 * MTPs, as required by Bspec.
379 * TODO: remove the alignment restriction for 128b/132b links
380 * on some platforms, where Bspec allows this.
381 */
382 remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
383
384 /*
385 * Also align PBNs accordingly, since MST core will derive its
386 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
387 * The above comment about the difference between the PBN
388 * allocated for the whole path and the TUs allocated for the
389 * first branch device's link also applies here.
390 */
391 pbn.full = remote_tu * mst_state->pbn_div.full;
392
393 drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
394 crtc_state->dp_m_n.tu = remote_tu;
395
396 slots = drm_dp_atomic_find_time_slots(state, mgr: &intel_dp->mst.mgr,
397 port: connector->mst.port,
398 dfixed_trunc(pbn));
399
400 /* TODO: Check this already in drm_dp_atomic_find_time_slots(). */
401 if (slots > mst_state->total_avail_slots)
402 slots = -EINVAL;
403 } else {
404 /* Same as above for remote_tu */
405 crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu,
406 4 / crtc_state->lane_count);
407
408 if (crtc_state->dp_m_n.tu <= 64)
409 slots = crtc_state->dp_m_n.tu;
410 else
411 slots = -EINVAL;
412 }
413
414 if (slots == -EDEADLK)
415 return slots;
416
417 if (slots >= 0) {
418 drm_WARN_ON(display->drm, slots != crtc_state->dp_m_n.tu);
419
420 break;
421 }
422 }
423
424 if (slots < 0) {
425 drm_dbg_kms(display->drm, "failed finding vcpi slots:%d\n",
426 slots);
427 return slots;
428 }
429
430 if (!dsc)
431 crtc_state->pipe_bpp = fxp_q4_to_int(val_q4: bpp_x16);
432 else
433 crtc_state->dsc.compressed_bpp_x16 = bpp_x16;
434
435 drm_dbg_kms(display->drm, "Got %d slots for pipe bpp " FXP_Q4_FMT " dsc %d\n",
436 slots, FXP_Q4_ARGS(bpp_x16), dsc);
437
438 return 0;
439}
440
441static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
442 struct intel_crtc_state *crtc_state,
443 struct drm_connector_state *conn_state,
444 const struct link_config_limits *limits)
445{
446 crtc_state->lane_count = limits->max_lane_count;
447 crtc_state->port_clock = limits->max_rate;
448
449 /*
450 * FIXME: allocate the BW according to link_bpp, which in the case of
451 * YUV420 is only half of the pipe bpp value.
452 */
453 return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,
454 min_bpp_x16: limits->link.min_bpp_x16,
455 max_bpp_x16: limits->link.max_bpp_x16,
456 bpp_step_x16: fxp_q4_from_int(val_int: 2 * 3), dsc: false);
457}
458
459static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,
460 struct intel_crtc_state *crtc_state,
461 struct drm_connector_state *conn_state,
462 const struct link_config_limits *limits)
463{
464 struct intel_display *display = to_intel_display(intel_dp);
465 struct intel_connector *connector = to_intel_connector(conn_state->connector);
466 int num_bpc;
467 u8 dsc_bpc[3] = {};
468 int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
469 int min_compressed_bpp_x16, max_compressed_bpp_x16;
470 int bpp_step_x16;
471
472 max_bpp = limits->pipe.max_bpp;
473 min_bpp = limits->pipe.min_bpp;
474
475 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(dsc_dpc: connector->dp.dsc_dpcd,
476 dsc_bpc);
477
478 drm_dbg_kms(display->drm, "DSC Source supported min bpp %d max bpp %d\n",
479 min_bpp, max_bpp);
480
481 sink_min_bpp = min_array(dsc_bpc, num_bpc) * 3;
482 sink_max_bpp = max_array(dsc_bpc, num_bpc) * 3;
483
484 drm_dbg_kms(display->drm, "DSC Sink supported min bpp %d max bpp %d\n",
485 sink_min_bpp, sink_max_bpp);
486
487 if (min_bpp < sink_min_bpp)
488 min_bpp = sink_min_bpp;
489
490 if (max_bpp > sink_max_bpp)
491 max_bpp = sink_max_bpp;
492
493 crtc_state->pipe_bpp = max_bpp;
494
495 min_compressed_bpp_x16 = limits->link.min_bpp_x16;
496 max_compressed_bpp_x16 = limits->link.max_bpp_x16;
497
498 drm_dbg_kms(display->drm,
499 "DSC Sink supported compressed min bpp " FXP_Q4_FMT " compressed max bpp " FXP_Q4_FMT "\n",
500 FXP_Q4_ARGS(min_compressed_bpp_x16), FXP_Q4_ARGS(max_compressed_bpp_x16));
501
502 bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector);
503
504 max_compressed_bpp_x16 = min(max_compressed_bpp_x16, fxp_q4_from_int(crtc_state->pipe_bpp) - bpp_step_x16);
505
506 drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16));
507 min_compressed_bpp_x16 = round_up(min_compressed_bpp_x16, bpp_step_x16);
508 max_compressed_bpp_x16 = round_down(max_compressed_bpp_x16, bpp_step_x16);
509
510 crtc_state->lane_count = limits->max_lane_count;
511 crtc_state->port_clock = limits->max_rate;
512
513 return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,
514 min_bpp_x16: min_compressed_bpp_x16,
515 max_bpp_x16: max_compressed_bpp_x16,
516 bpp_step_x16, dsc: true);
517}
518
519static int mode_hblank_period_ns(const struct drm_display_mode *mode)
520{
521 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
522 NSEC_PER_SEC / 1000),
523 mode->crtc_clock);
524}
525
526static bool
527hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
528 const struct intel_crtc_state *crtc_state,
529 const struct link_config_limits *limits)
530{
531 const struct drm_display_mode *adjusted_mode =
532 &crtc_state->hw.adjusted_mode;
533 bool is_uhbr_sink = connector->mst.dp &&
534 drm_dp_128b132b_supported(dpcd: connector->mst.dp->dpcd);
535 int hblank_limit = is_uhbr_sink ? 500 : 300;
536
537 if (!connector->dp.dsc_hblank_expansion_quirk)
538 return false;
539
540 if (is_uhbr_sink && !drm_dp_is_uhbr_rate(link_rate: limits->max_rate))
541 return false;
542
543 if (mode_hblank_period_ns(mode: adjusted_mode) > hblank_limit)
544 return false;
545
546 if (!intel_dp_mst_dsc_get_slice_count(connector, crtc_state))
547 return false;
548
549 return true;
550}
551
552static bool
553adjust_limits_for_dsc_hblank_expansion_quirk(struct intel_dp *intel_dp,
554 const struct intel_connector *connector,
555 const struct intel_crtc_state *crtc_state,
556 struct link_config_limits *limits,
557 bool dsc)
558{
559 struct intel_display *display = to_intel_display(connector);
560 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
561 int min_bpp_x16 = limits->link.min_bpp_x16;
562
563 if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))
564 return true;
565
566 if (!dsc) {
567 if (intel_dp_supports_dsc(intel_dp, connector, crtc_state)) {
568 drm_dbg_kms(display->drm,
569 "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n",
570 crtc->base.base.id, crtc->base.name,
571 connector->base.base.id, connector->base.name);
572 return false;
573 }
574
575 drm_dbg_kms(display->drm,
576 "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to 24 due to hblank expansion quirk\n",
577 crtc->base.base.id, crtc->base.name,
578 connector->base.base.id, connector->base.name);
579
580 if (limits->link.max_bpp_x16 < fxp_q4_from_int(val_int: 24))
581 return false;
582
583 limits->link.min_bpp_x16 = fxp_q4_from_int(val_int: 24);
584
585 return true;
586 }
587
588 drm_WARN_ON(display->drm, limits->min_rate != limits->max_rate);
589
590 if (limits->max_rate < 540000)
591 min_bpp_x16 = fxp_q4_from_int(val_int: 13);
592 else if (limits->max_rate < 810000)
593 min_bpp_x16 = fxp_q4_from_int(val_int: 10);
594
595 if (limits->link.min_bpp_x16 >= min_bpp_x16)
596 return true;
597
598 drm_dbg_kms(display->drm,
599 "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " FXP_Q4_FMT " in DSC mode due to hblank expansion quirk\n",
600 crtc->base.base.id, crtc->base.name,
601 connector->base.base.id, connector->base.name,
602 FXP_Q4_ARGS(min_bpp_x16));
603
604 if (limits->link.max_bpp_x16 < min_bpp_x16)
605 return false;
606
607 limits->link.min_bpp_x16 = min_bpp_x16;
608
609 return true;
610}
611
612static bool
613mst_stream_compute_config_limits(struct intel_dp *intel_dp,
614 struct drm_connector_state *conn_state,
615 struct intel_crtc_state *crtc_state,
616 bool dsc,
617 struct link_config_limits *limits)
618{
619 struct intel_connector *connector =
620 to_intel_connector(conn_state->connector);
621
622 if (!intel_dp_compute_config_limits(intel_dp, conn_state,
623 crtc_state, respect_downstream_limits: false, dsc,
624 limits))
625 return false;
626
627 return adjust_limits_for_dsc_hblank_expansion_quirk(intel_dp,
628 connector,
629 crtc_state,
630 limits,
631 dsc);
632}
633
634static int mst_stream_compute_config(struct intel_encoder *encoder,
635 struct intel_crtc_state *pipe_config,
636 struct drm_connector_state *conn_state)
637{
638 struct intel_display *display = to_intel_display(encoder);
639 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
640 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
641 struct intel_dp *intel_dp = to_primary_dp(encoder);
642 struct intel_connector *connector =
643 to_intel_connector(conn_state->connector);
644 const struct drm_display_mode *adjusted_mode =
645 &pipe_config->hw.adjusted_mode;
646 struct link_config_limits limits;
647 bool dsc_needed, joiner_needs_dsc;
648 int num_joined_pipes;
649 int ret = 0;
650
651 if (pipe_config->fec_enable &&
652 !intel_dp_supports_fec(intel_dp, connector, pipe_config))
653 return -EINVAL;
654
655 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
656 return -EINVAL;
657
658 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
659 hdisplay: adjusted_mode->crtc_hdisplay,
660 clock: adjusted_mode->crtc_clock);
661 if (num_joined_pipes > 1)
662 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
663
664 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
665 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
666 pipe_config->has_pch_encoder = false;
667
668 joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
669
670 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
671 !mst_stream_compute_config_limits(intel_dp, conn_state,
672 crtc_state: pipe_config, dsc: false, limits: &limits);
673
674 if (!dsc_needed) {
675 ret = mst_stream_compute_link_config(intel_dp, crtc_state: pipe_config,
676 conn_state, limits: &limits);
677
678 if (ret == -EDEADLK)
679 return ret;
680
681 if (ret)
682 dsc_needed = true;
683 }
684
685 if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, crtc_state: pipe_config)) {
686 drm_dbg_kms(display->drm, "DSC required but not available\n");
687 return -EINVAL;
688 }
689
690 /* enable compression if the mode doesn't fit available BW */
691 if (dsc_needed) {
692 drm_dbg_kms(display->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
693 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
694 str_yes_no(intel_dp->force_dsc_en));
695
696
697 if (!mst_stream_compute_config_limits(intel_dp, conn_state,
698 crtc_state: pipe_config, dsc: true,
699 limits: &limits))
700 return -EINVAL;
701
702 /*
703 * FIXME: As bpc is hardcoded to 8, as mentioned above,
704 * WARN and ignore the debug flag force_dsc_bpc for now.
705 */
706 drm_WARN(display->drm, intel_dp->force_dsc_bpc,
707 "Cannot Force BPC for MST\n");
708 /*
709 * Try to get at least some timeslots and then see, if
710 * we can fit there with DSC.
711 */
712 drm_dbg_kms(display->drm, "Trying to find VCPI slots in DSC mode\n");
713
714 ret = mst_stream_dsc_compute_link_config(intel_dp, crtc_state: pipe_config,
715 conn_state, limits: &limits);
716 if (ret < 0)
717 return ret;
718
719 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
720 conn_state, limits: &limits,
721 timeslots: pipe_config->dp_m_n.tu);
722 }
723
724 if (ret)
725 return ret;
726
727 pipe_config->limited_color_range =
728 intel_dp_limited_color_range(crtc_state: pipe_config, conn_state);
729
730 if (display->platform.geminilake || display->platform.broxton)
731 pipe_config->lane_lat_optim_mask =
732 bxt_dpio_phy_calc_lane_lat_optim_mask(lane_count: pipe_config->lane_count);
733
734 ret = intel_dp_compute_min_hblank(crtc_state: pipe_config, conn_state);
735 if (ret)
736 return ret;
737
738 intel_vrr_compute_config(crtc_state: pipe_config, conn_state);
739
740 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
741
742 intel_ddi_compute_min_voltage_level(crtc_state: pipe_config);
743
744 intel_psr_compute_config(intel_dp, crtc_state: pipe_config, conn_state);
745
746 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
747 crtc_state: pipe_config);
748}
749
750/*
751 * Iterate over all connectors and return a mask of
752 * all CPU transcoders streaming over the same DP link.
753 */
754static unsigned int
755intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
756 struct intel_dp *mst_port)
757{
758 struct intel_display *display = to_intel_display(state);
759 const struct intel_digital_connector_state *conn_state;
760 struct intel_connector *connector;
761 u8 transcoders = 0;
762 int i;
763
764 if (DISPLAY_VER(display) < 12)
765 return 0;
766
767 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
768 const struct intel_crtc_state *crtc_state;
769 struct intel_crtc *crtc;
770
771 if (connector->mst.dp != mst_port || !conn_state->base.crtc)
772 continue;
773
774 crtc = to_intel_crtc(conn_state->base.crtc);
775 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
776
777 if (!crtc_state->hw.active)
778 continue;
779
780 transcoders |= BIT(crtc_state->cpu_transcoder);
781 }
782
783 return transcoders;
784}
785
786static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,
787 struct drm_dp_mst_topology_mgr *mst_mgr,
788 struct drm_dp_mst_port *parent_port)
789{
790 const struct intel_digital_connector_state *conn_state;
791 struct intel_connector *connector;
792 u8 mask = 0;
793 int i;
794
795 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
796 if (!conn_state->base.crtc)
797 continue;
798
799 if (&connector->mst.dp->mst.mgr != mst_mgr)
800 continue;
801
802 if (connector->mst.port != parent_port &&
803 !drm_dp_mst_port_downstream_of_parent(mgr: mst_mgr,
804 port: connector->mst.port,
805 parent: parent_port))
806 continue;
807
808 mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);
809 }
810
811 return mask;
812}
813
814static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,
815 struct drm_dp_mst_topology_mgr *mst_mgr,
816 struct intel_link_bw_limits *limits)
817{
818 struct intel_display *display = to_intel_display(state);
819 struct intel_crtc *crtc;
820 u8 mst_pipe_mask;
821 u8 fec_pipe_mask = 0;
822 int ret;
823
824 mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL);
825
826 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mst_pipe_mask) {
827 struct intel_crtc_state *crtc_state =
828 intel_atomic_get_new_crtc_state(state, crtc);
829
830 /* Atomic connector check should've added all the MST CRTCs. */
831 if (drm_WARN_ON(display->drm, !crtc_state))
832 return -EINVAL;
833
834 if (crtc_state->fec_enable)
835 fec_pipe_mask |= BIT(crtc->pipe);
836 }
837
838 if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)
839 return 0;
840
841 limits->force_fec_pipes |= mst_pipe_mask;
842
843 ret = intel_modeset_pipes_in_mask_early(state, reason: "MST FEC",
844 pipe_mask: mst_pipe_mask);
845
846 return ret ? : -EAGAIN;
847}
848
849static int intel_dp_mst_check_bw(struct intel_atomic_state *state,
850 struct drm_dp_mst_topology_mgr *mst_mgr,
851 struct drm_dp_mst_topology_state *mst_state,
852 struct intel_link_bw_limits *limits)
853{
854 struct drm_dp_mst_port *mst_port;
855 u8 mst_port_pipes;
856 int ret;
857
858 ret = drm_dp_mst_atomic_check_mgr(state: &state->base, mgr: mst_mgr, mst_state, failing_port: &mst_port);
859 if (ret != -ENOSPC)
860 return ret;
861
862 mst_port_pipes = get_pipes_downstream_of_mst_port(state, mst_mgr, parent_port: mst_port);
863
864 ret = intel_link_bw_reduce_bpp(state, limits,
865 pipe_mask: mst_port_pipes, reason: "MST link BW");
866
867 return ret ? : -EAGAIN;
868}
869
870/**
871 * intel_dp_mst_atomic_check_link - check all modeset MST link configuration
872 * @state: intel atomic state
873 * @limits: link BW limits
874 *
875 * Check the link configuration for all modeset MST outputs. If the
876 * configuration is invalid @limits will be updated if possible to
877 * reduce the total BW, after which the configuration for all CRTCs in
878 * @state must be recomputed with the updated @limits.
879 *
880 * Returns:
881 * - 0 if the configuration is valid
882 * - %-EAGAIN, if the configuration is invalid and @limits got updated
883 * with fallback values with which the configuration of all CRTCs in
884 * @state must be recomputed
885 * - Other negative error, if the configuration is invalid without a
886 * fallback possibility, or the check failed for another reason
887 */
888int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
889 struct intel_link_bw_limits *limits)
890{
891 struct drm_dp_mst_topology_mgr *mgr;
892 struct drm_dp_mst_topology_state *mst_state;
893 int ret;
894 int i;
895
896 for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {
897 ret = intel_dp_mst_check_fec_change(state, mst_mgr: mgr, limits);
898 if (ret)
899 return ret;
900
901 ret = intel_dp_mst_check_bw(state, mst_mgr: mgr, mst_state,
902 limits);
903 if (ret)
904 return ret;
905 }
906
907 return 0;
908}
909
910static int mst_stream_compute_config_late(struct intel_encoder *encoder,
911 struct intel_crtc_state *crtc_state,
912 struct drm_connector_state *conn_state)
913{
914 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
915 struct intel_dp *intel_dp = to_primary_dp(encoder);
916
917 /* lowest numbered transcoder will be designated master */
918 crtc_state->mst_master_transcoder =
919 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
920
921 return 0;
922}
923
924/*
925 * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
926 * that shares the same MST stream as mode changed,
927 * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
928 * a fastset when possible.
929 *
930 * On TGL+ this is required since each stream go through a master transcoder,
931 * so if the master transcoder needs modeset, all other streams in the
932 * topology need a modeset. All platforms need to add the atomic state
933 * for all streams in the topology, since a modeset on one may require
934 * changing the MST link BW usage of the others, which in turn needs a
935 * recomputation of the corresponding CRTC states.
936 */
937static int
938mst_connector_atomic_topology_check(struct intel_connector *connector,
939 struct intel_atomic_state *state)
940{
941 struct intel_display *display = to_intel_display(connector);
942 struct drm_connector_list_iter connector_list_iter;
943 struct intel_connector *connector_iter;
944 int ret = 0;
945
946 if (!intel_connector_needs_modeset(state, connector: &connector->base))
947 return 0;
948
949 drm_connector_list_iter_begin(dev: display->drm, iter: &connector_list_iter);
950 for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
951 struct intel_digital_connector_state *conn_iter_state;
952 struct intel_crtc_state *crtc_state;
953 struct intel_crtc *crtc;
954
955 if (connector_iter->mst.dp != connector->mst.dp ||
956 connector_iter == connector)
957 continue;
958
959 conn_iter_state = intel_atomic_get_digital_connector_state(state,
960 connector: connector_iter);
961 if (IS_ERR(ptr: conn_iter_state)) {
962 ret = PTR_ERR(ptr: conn_iter_state);
963 break;
964 }
965
966 if (!conn_iter_state->base.crtc)
967 continue;
968
969 crtc = to_intel_crtc(conn_iter_state->base.crtc);
970 crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
971 if (IS_ERR(ptr: crtc_state)) {
972 ret = PTR_ERR(ptr: crtc_state);
973 break;
974 }
975
976 ret = drm_atomic_add_affected_planes(state: &state->base, crtc: &crtc->base);
977 if (ret)
978 break;
979 crtc_state->uapi.mode_changed = true;
980 }
981 drm_connector_list_iter_end(iter: &connector_list_iter);
982
983 return ret;
984}
985
986static int
987mst_connector_atomic_check(struct drm_connector *_connector,
988 struct drm_atomic_state *_state)
989{
990 struct intel_atomic_state *state = to_intel_atomic_state(_state);
991 struct intel_connector *connector = to_intel_connector(_connector);
992 int ret;
993
994 ret = intel_digital_connector_atomic_check(conn: &connector->base, state: &state->base);
995 if (ret)
996 return ret;
997
998 ret = mst_connector_atomic_topology_check(connector, state);
999 if (ret)
1000 return ret;
1001
1002 if (intel_connector_needs_modeset(state, connector: &connector->base)) {
1003 ret = intel_dp_tunnel_atomic_check_state(state,
1004 intel_dp: connector->mst.dp,
1005 connector);
1006 if (ret)
1007 return ret;
1008 }
1009
1010 return drm_dp_atomic_release_time_slots(state: &state->base,
1011 mgr: &connector->mst.dp->mst.mgr,
1012 port: connector->mst.port);
1013}
1014
1015static void mst_stream_disable(struct intel_atomic_state *state,
1016 struct intel_encoder *encoder,
1017 const struct intel_crtc_state *old_crtc_state,
1018 const struct drm_connector_state *old_conn_state)
1019{
1020 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1021 struct intel_dp *intel_dp = to_primary_dp(encoder);
1022 struct intel_connector *connector =
1023 to_intel_connector(old_conn_state->connector);
1024
1025 if (intel_dp_mst_active_streams(intel_dp) == 1)
1026 intel_dp->link.active = false;
1027
1028 intel_hdcp_disable(connector: intel_mst->connector);
1029
1030 intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
1031}
1032
1033static void mst_stream_post_disable(struct intel_atomic_state *state,
1034 struct intel_encoder *encoder,
1035 const struct intel_crtc_state *old_crtc_state,
1036 const struct drm_connector_state *old_conn_state)
1037{
1038 struct intel_display *display = to_intel_display(encoder);
1039 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1040 struct intel_encoder *primary_encoder = to_primary_encoder(encoder);
1041 struct intel_dp *intel_dp = to_primary_dp(encoder);
1042 struct intel_connector *connector =
1043 to_intel_connector(old_conn_state->connector);
1044 struct drm_dp_mst_topology_state *old_mst_state =
1045 drm_atomic_get_old_mst_topology_state(state: &state->base, mgr: &intel_dp->mst.mgr);
1046 struct drm_dp_mst_topology_state *new_mst_state =
1047 drm_atomic_get_new_mst_topology_state(state: &state->base, mgr: &intel_dp->mst.mgr);
1048 const struct drm_dp_mst_atomic_payload *old_payload =
1049 drm_atomic_get_mst_payload_state(state: old_mst_state, port: connector->mst.port);
1050 struct drm_dp_mst_atomic_payload *new_payload =
1051 drm_atomic_get_mst_payload_state(state: new_mst_state, port: connector->mst.port);
1052 struct intel_crtc *pipe_crtc;
1053 bool last_mst_stream;
1054 int i;
1055
1056 last_mst_stream = intel_dp_mst_dec_active_streams(intel_dp);
1057
1058 drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && last_mst_stream &&
1059 !intel_dp_mst_is_master_trans(old_crtc_state));
1060
1061 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
1062 const struct intel_crtc_state *old_pipe_crtc_state =
1063 intel_atomic_get_old_crtc_state(state, crtc: pipe_crtc);
1064
1065 intel_crtc_vblank_off(crtc_state: old_pipe_crtc_state);
1066 }
1067
1068 intel_disable_transcoder(old_crtc_state);
1069
1070 drm_dp_remove_payload_part1(mgr: &intel_dp->mst.mgr, mst_state: new_mst_state, payload: new_payload);
1071
1072 intel_ddi_clear_act_sent(encoder, crtc_state: old_crtc_state);
1073
1074 intel_de_rmw(display,
1075 TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),
1076 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, set: 0);
1077
1078 intel_ddi_wait_for_act_sent(encoder, crtc_state: old_crtc_state);
1079 drm_dp_check_act_status(mgr: &intel_dp->mst.mgr);
1080
1081 drm_dp_remove_payload_part2(mgr: &intel_dp->mst.mgr, mst_state: new_mst_state,
1082 old_payload, new_payload);
1083
1084 intel_vrr_transcoder_disable(crtc_state: old_crtc_state);
1085
1086 intel_ddi_disable_transcoder_func(crtc_state: old_crtc_state);
1087
1088 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
1089 const struct intel_crtc_state *old_pipe_crtc_state =
1090 intel_atomic_get_old_crtc_state(state, crtc: pipe_crtc);
1091
1092 intel_dsc_disable(crtc_state: old_pipe_crtc_state);
1093
1094 if (DISPLAY_VER(display) >= 9)
1095 skl_scaler_disable(old_crtc_state: old_pipe_crtc_state);
1096 else
1097 ilk_pfit_disable(old_crtc_state: old_pipe_crtc_state);
1098 }
1099
1100 /*
1101 * Power down mst path before disabling the port, otherwise we end
1102 * up getting interrupts from the sink upon detecting link loss.
1103 */
1104 drm_dp_send_power_updown_phy(mgr: &intel_dp->mst.mgr, port: connector->mst.port,
1105 power_up: false);
1106
1107 /*
1108 * BSpec 4287: disable DIP after the transcoder is disabled and before
1109 * the transcoder clock select is set to none.
1110 */
1111 intel_dp_set_infoframes(encoder: primary_encoder, enable: false, crtc_state: old_crtc_state, NULL);
1112 /*
1113 * From TGL spec: "If multi-stream slave transcoder: Configure
1114 * Transcoder Clock Select to direct no clock to the transcoder"
1115 *
1116 * From older GENs spec: "Configure Transcoder Clock Select to direct
1117 * no clock to the transcoder"
1118 */
1119 if (DISPLAY_VER(display) < 12 || !last_mst_stream)
1120 intel_ddi_disable_transcoder_clock(crtc_state: old_crtc_state);
1121
1122
1123 intel_mst->connector = NULL;
1124 if (last_mst_stream)
1125 primary_encoder->post_disable(state, primary_encoder,
1126 old_crtc_state, NULL);
1127
1128}
1129
1130static void mst_stream_post_pll_disable(struct intel_atomic_state *state,
1131 struct intel_encoder *encoder,
1132 const struct intel_crtc_state *old_crtc_state,
1133 const struct drm_connector_state *old_conn_state)
1134{
1135 struct intel_encoder *primary_encoder = to_primary_encoder(encoder);
1136 struct intel_dp *intel_dp = to_primary_dp(encoder);
1137
1138 if (intel_dp_mst_active_streams(intel_dp) == 0 &&
1139 primary_encoder->post_pll_disable)
1140 primary_encoder->post_pll_disable(state, primary_encoder, old_crtc_state, old_conn_state);
1141}
1142
1143static void mst_stream_pre_pll_enable(struct intel_atomic_state *state,
1144 struct intel_encoder *encoder,
1145 const struct intel_crtc_state *pipe_config,
1146 const struct drm_connector_state *conn_state)
1147{
1148 struct intel_encoder *primary_encoder = to_primary_encoder(encoder);
1149 struct intel_dp *intel_dp = to_primary_dp(encoder);
1150
1151 if (intel_dp_mst_active_streams(intel_dp) == 0)
1152 primary_encoder->pre_pll_enable(state, primary_encoder,
1153 pipe_config, NULL);
1154 else
1155 /*
1156 * The port PLL state needs to get updated for secondary
1157 * streams as for the primary stream.
1158 */
1159 intel_ddi_update_active_dpll(state, encoder: primary_encoder,
1160 to_intel_crtc(pipe_config->uapi.crtc));
1161}
1162
1163static bool intel_mst_probed_link_params_valid(struct intel_dp *intel_dp,
1164 int link_rate, int lane_count)
1165{
1166 return intel_dp->link.mst_probed_rate == link_rate &&
1167 intel_dp->link.mst_probed_lane_count == lane_count;
1168}
1169
1170static void intel_mst_set_probed_link_params(struct intel_dp *intel_dp,
1171 int link_rate, int lane_count)
1172{
1173 intel_dp->link.mst_probed_rate = link_rate;
1174 intel_dp->link.mst_probed_lane_count = lane_count;
1175}
1176
1177static void intel_mst_reprobe_topology(struct intel_dp *intel_dp,
1178 const struct intel_crtc_state *crtc_state)
1179{
1180 if (intel_mst_probed_link_params_valid(intel_dp,
1181 link_rate: crtc_state->port_clock, lane_count: crtc_state->lane_count))
1182 return;
1183
1184 drm_dp_mst_topology_queue_probe(mgr: &intel_dp->mst.mgr);
1185
1186 intel_mst_set_probed_link_params(intel_dp,
1187 link_rate: crtc_state->port_clock, lane_count: crtc_state->lane_count);
1188}
1189
1190static void mst_stream_pre_enable(struct intel_atomic_state *state,
1191 struct intel_encoder *encoder,
1192 const struct intel_crtc_state *pipe_config,
1193 const struct drm_connector_state *conn_state)
1194{
1195 struct intel_display *display = to_intel_display(state);
1196 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1197 struct intel_encoder *primary_encoder = to_primary_encoder(encoder);
1198 struct intel_dp *intel_dp = to_primary_dp(encoder);
1199 struct intel_connector *connector =
1200 to_intel_connector(conn_state->connector);
1201 struct drm_dp_mst_topology_state *mst_state =
1202 drm_atomic_get_new_mst_topology_state(state: &state->base, mgr: &intel_dp->mst.mgr);
1203 int ret;
1204 bool first_mst_stream;
1205
1206 /* MST encoders are bound to a crtc, not to a connector,
1207 * force the mapping here for get_hw_state.
1208 */
1209 connector->encoder = encoder;
1210 intel_mst->connector = connector;
1211
1212 first_mst_stream = intel_dp_mst_inc_active_streams(intel_dp);
1213 drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && first_mst_stream &&
1214 !intel_dp_mst_is_master_trans(pipe_config));
1215
1216 if (first_mst_stream)
1217 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
1218
1219 drm_dp_send_power_updown_phy(mgr: &intel_dp->mst.mgr, port: connector->mst.port, power_up: true);
1220
1221 intel_dp_sink_enable_decompression(state, connector, new_crtc_state: pipe_config);
1222
1223 if (first_mst_stream) {
1224 primary_encoder->pre_enable(state, primary_encoder,
1225 pipe_config, NULL);
1226
1227 intel_mst_reprobe_topology(intel_dp, crtc_state: pipe_config);
1228 }
1229
1230 ret = drm_dp_add_payload_part1(mgr: &intel_dp->mst.mgr, mst_state,
1231 payload: drm_atomic_get_mst_payload_state(state: mst_state, port: connector->mst.port));
1232 if (ret < 0)
1233 intel_dp_queue_modeset_retry_for_link(state, encoder: primary_encoder, crtc_state: pipe_config);
1234
1235 /*
1236 * Before Gen 12 this is not done as part of
1237 * primary_encoder->pre_enable() and should be done here. For
1238 * Gen 12+ the step in which this should be done is different for the
1239 * first MST stream, so it's done on the DDI for the first stream and
1240 * here for the following ones.
1241 */
1242 if (DISPLAY_VER(display) < 12 || !first_mst_stream)
1243 intel_ddi_enable_transcoder_clock(encoder, crtc_state: pipe_config);
1244
1245 if (DISPLAY_VER(display) >= 13 && !first_mst_stream)
1246 intel_ddi_config_transcoder_func(encoder, crtc_state: pipe_config);
1247
1248 intel_dsc_dp_pps_write(encoder: primary_encoder, crtc_state: pipe_config);
1249 intel_ddi_set_dp_msa(crtc_state: pipe_config, conn_state);
1250}
1251
1252static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
1253{
1254 struct intel_display *display = to_intel_display(crtc_state);
1255 u32 clear = 0;
1256 u32 set = 0;
1257
1258 if (!display->platform.alderlake_p)
1259 return;
1260
1261 if (!IS_DISPLAY_STEP(display, STEP_D0, STEP_FOREVER))
1262 return;
1263
1264 /* Wa_14013163432:adlp */
1265 if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
1266 set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
1267
1268 /* Wa_14014143976:adlp */
1269 if (IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER)) {
1270 if (intel_dp_is_uhbr(crtc_state))
1271 set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
1272 else if (crtc_state->fec_enable)
1273 clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
1274
1275 if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
1276 set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);
1277 }
1278
1279 if (!clear && !set)
1280 return;
1281
1282 intel_de_rmw(display, CHICKEN_MISC_3, clear, set);
1283}
1284
1285static void mst_stream_enable(struct intel_atomic_state *state,
1286 struct intel_encoder *encoder,
1287 const struct intel_crtc_state *pipe_config,
1288 const struct drm_connector_state *conn_state)
1289{
1290 struct intel_display *display = to_intel_display(encoder);
1291 struct intel_encoder *primary_encoder = to_primary_encoder(encoder);
1292 struct intel_dp *intel_dp = to_primary_dp(encoder);
1293 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1294 struct drm_dp_mst_topology_state *mst_state =
1295 drm_atomic_get_new_mst_topology_state(state: &state->base, mgr: &intel_dp->mst.mgr);
1296 enum transcoder trans = pipe_config->cpu_transcoder;
1297 bool first_mst_stream = intel_dp_mst_active_streams(intel_dp) == 1;
1298 struct intel_crtc *pipe_crtc;
1299 int ret, i;
1300
1301 drm_WARN_ON(display->drm, pipe_config->has_pch_encoder);
1302
1303 if (intel_dp_is_uhbr(crtc_state: pipe_config)) {
1304 const struct drm_display_mode *adjusted_mode =
1305 &pipe_config->hw.adjusted_mode;
1306 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
1307
1308 intel_de_write(display, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
1309 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
1310 intel_de_write(display, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
1311 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
1312 }
1313
1314 enable_bs_jitter_was(crtc_state: pipe_config);
1315
1316 intel_ddi_enable_transcoder_func(encoder, crtc_state: pipe_config);
1317
1318 intel_vrr_transcoder_enable(crtc_state: pipe_config);
1319
1320 intel_ddi_clear_act_sent(encoder, crtc_state: pipe_config);
1321
1322 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), clear: 0,
1323 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1324
1325 intel_ddi_wait_for_act_sent(encoder, crtc_state: pipe_config);
1326 drm_dp_check_act_status(mgr: &intel_dp->mst.mgr);
1327
1328 if (first_mst_stream)
1329 intel_ddi_wait_for_fec_status(encoder, crtc_state: pipe_config, enabled: true);
1330
1331 ret = drm_dp_add_payload_part2(mgr: &intel_dp->mst.mgr,
1332 payload: drm_atomic_get_mst_payload_state(state: mst_state,
1333 port: connector->mst.port));
1334 if (ret < 0)
1335 intel_dp_queue_modeset_retry_for_link(state, encoder: primary_encoder, crtc_state: pipe_config);
1336
1337 if (DISPLAY_VER(display) >= 12)
1338 intel_de_rmw(display, CHICKEN_TRANS(display, trans),
1339 FECSTALL_DIS_DPTSTREAM_DPTTG,
1340 set: pipe_config->fec_enable ? FECSTALL_DIS_DPTSTREAM_DPTTG : 0);
1341
1342 intel_enable_transcoder(new_crtc_state: pipe_config);
1343
1344 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config, i) {
1345 const struct intel_crtc_state *pipe_crtc_state =
1346 intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
1347
1348 intel_crtc_vblank_on(crtc_state: pipe_crtc_state);
1349 }
1350
1351 intel_hdcp_enable(state, encoder, pipe_config, conn_state);
1352}
1353
1354static bool mst_stream_get_hw_state(struct intel_encoder *encoder,
1355 enum pipe *pipe)
1356{
1357 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1358 *pipe = intel_mst->pipe;
1359 if (intel_mst->connector)
1360 return true;
1361 return false;
1362}
1363
1364static void mst_stream_get_config(struct intel_encoder *encoder,
1365 struct intel_crtc_state *pipe_config)
1366{
1367 struct intel_encoder *primary_encoder = to_primary_encoder(encoder);
1368
1369 primary_encoder->get_config(primary_encoder, pipe_config);
1370}
1371
1372static bool mst_stream_initial_fastset_check(struct intel_encoder *encoder,
1373 struct intel_crtc_state *crtc_state)
1374{
1375 struct intel_encoder *primary_encoder = to_primary_encoder(encoder);
1376
1377 return intel_dp_initial_fastset_check(encoder: primary_encoder, crtc_state);
1378}
1379
1380static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
1381{
1382 struct intel_connector *connector = to_intel_connector(_connector);
1383 struct intel_display *display = to_intel_display(connector);
1384 struct intel_dp *intel_dp = connector->mst.dp;
1385 const struct drm_edid *drm_edid;
1386 int ret;
1387
1388 if (drm_connector_is_unregistered(connector: &connector->base))
1389 return intel_connector_update_modes(connector: &connector->base, NULL);
1390
1391 if (!intel_display_driver_check_access(display))
1392 return drm_edid_connector_add_modes(connector: &connector->base);
1393
1394 drm_edid = drm_dp_mst_edid_read(connector: &connector->base, mgr: &intel_dp->mst.mgr, port: connector->mst.port);
1395
1396 ret = intel_connector_update_modes(connector: &connector->base, drm_edid);
1397
1398 drm_edid_free(drm_edid);
1399
1400 return ret;
1401}
1402
1403static int
1404mst_connector_late_register(struct drm_connector *_connector)
1405{
1406 struct intel_connector *connector = to_intel_connector(_connector);
1407 int ret;
1408
1409 ret = drm_dp_mst_connector_late_register(connector: &connector->base, port: connector->mst.port);
1410 if (ret < 0)
1411 return ret;
1412
1413 ret = intel_connector_register(connector: &connector->base);
1414 if (ret < 0)
1415 drm_dp_mst_connector_early_unregister(connector: &connector->base, port: connector->mst.port);
1416
1417 return ret;
1418}
1419
1420static void
1421mst_connector_early_unregister(struct drm_connector *_connector)
1422{
1423 struct intel_connector *connector = to_intel_connector(_connector);
1424
1425 intel_connector_unregister(connector: &connector->base);
1426 drm_dp_mst_connector_early_unregister(connector: &connector->base, port: connector->mst.port);
1427}
1428
1429static const struct drm_connector_funcs mst_connector_funcs = {
1430 .fill_modes = drm_helper_probe_single_connector_modes,
1431 .atomic_get_property = intel_digital_connector_atomic_get_property,
1432 .atomic_set_property = intel_digital_connector_atomic_set_property,
1433 .late_register = mst_connector_late_register,
1434 .early_unregister = mst_connector_early_unregister,
1435 .destroy = intel_connector_destroy,
1436 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1437 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1438};
1439
1440static int mst_connector_get_modes(struct drm_connector *_connector)
1441{
1442 struct intel_connector *connector = to_intel_connector(_connector);
1443
1444 return mst_connector_get_ddc_modes(connector: &connector->base);
1445}
1446
1447static int
1448mst_connector_mode_valid_ctx(struct drm_connector *_connector,
1449 const struct drm_display_mode *mode,
1450 struct drm_modeset_acquire_ctx *ctx,
1451 enum drm_mode_status *status)
1452{
1453 struct intel_connector *connector = to_intel_connector(_connector);
1454 struct intel_display *display = to_intel_display(connector);
1455 struct intel_dp *intel_dp = connector->mst.dp;
1456 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst.mgr;
1457 struct drm_dp_mst_port *port = connector->mst.port;
1458 const int min_bpp = 18;
1459 int max_dotclk = display->cdclk.max_dotclk_freq;
1460 int max_rate, mode_rate, max_lanes, max_link_clock;
1461 int ret;
1462 bool dsc = false;
1463 u16 dsc_max_compressed_bpp = 0;
1464 u8 dsc_slice_count = 0;
1465 int target_clock = mode->clock;
1466 int num_joined_pipes;
1467
1468 if (drm_connector_is_unregistered(connector: &connector->base)) {
1469 *status = MODE_ERROR;
1470 return 0;
1471 }
1472
1473 *status = intel_cpu_transcoder_mode_valid(display, mode);
1474 if (*status != MODE_OK)
1475 return 0;
1476
1477 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1478 *status = MODE_H_ILLEGAL;
1479 return 0;
1480 }
1481
1482 if (mode->clock < 10000) {
1483 *status = MODE_CLOCK_LOW;
1484 return 0;
1485 }
1486
1487 max_link_clock = intel_dp_max_link_rate(intel_dp);
1488 max_lanes = intel_dp_max_lane_count(intel_dp);
1489
1490 max_rate = intel_dp_max_link_data_rate(intel_dp,
1491 max_dprx_rate: max_link_clock, max_dprx_lanes: max_lanes);
1492 mode_rate = intel_dp_link_required(pixel_clock: mode->clock, bpp: min_bpp);
1493
1494 /*
1495 * TODO:
1496 * - Also check if compression would allow for the mode
1497 * - Calculate the overhead using drm_dp_bw_overhead() /
1498 * drm_dp_bw_channel_coding_efficiency(), similarly to the
1499 * compute config code, as drm_dp_calc_pbn_mode() doesn't
1500 * account with all the overheads.
1501 * - Check here and during compute config the BW reported by
1502 * DFP_Link_Available_Payload_Bandwidth_Number (or the
1503 * corresponding link capabilities of the sink) in case the
1504 * stream is uncompressed for it by the last branch device.
1505 */
1506 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
1507 hdisplay: mode->hdisplay, clock: target_clock);
1508 max_dotclk *= num_joined_pipes;
1509
1510 ret = drm_modeset_lock(lock: &mgr->base.lock, ctx);
1511 if (ret)
1512 return ret;
1513
1514 if (mode_rate > max_rate || mode->clock > max_dotclk ||
1515 drm_dp_calc_pbn_mode(clock: mode->clock, bpp: min_bpp << 4) > port->full_pbn) {
1516 *status = MODE_CLOCK_HIGH;
1517 return 0;
1518 }
1519
1520 if (intel_dp_has_dsc(connector)) {
1521 /*
1522 * TBD pass the connector BPC,
1523 * for now U8_MAX so that max BPC on that platform would be picked
1524 */
1525 int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1526
1527 if (drm_dp_sink_supports_fec(fec_capable: connector->dp.fec_capability)) {
1528 dsc_max_compressed_bpp =
1529 intel_dp_dsc_get_max_compressed_bpp(display,
1530 link_clock: max_link_clock,
1531 lane_count: max_lanes,
1532 mode_clock: target_clock,
1533 mode_hdisplay: mode->hdisplay,
1534 num_joined_pipes,
1535 output_format: INTEL_OUTPUT_FORMAT_RGB,
1536 pipe_bpp, timeslots: 64);
1537 dsc_slice_count =
1538 intel_dp_dsc_get_slice_count(connector,
1539 mode_clock: target_clock,
1540 mode_hdisplay: mode->hdisplay,
1541 num_joined_pipes);
1542 }
1543
1544 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1545 }
1546
1547 if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
1548 *status = MODE_CLOCK_HIGH;
1549 return 0;
1550 }
1551
1552 if (mode_rate > max_rate && !dsc) {
1553 *status = MODE_CLOCK_HIGH;
1554 return 0;
1555 }
1556
1557 *status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
1558 return 0;
1559}
1560
1561static struct drm_encoder *
1562mst_connector_atomic_best_encoder(struct drm_connector *_connector,
1563 struct drm_atomic_state *state)
1564{
1565 struct intel_connector *connector = to_intel_connector(_connector);
1566 struct drm_connector_state *connector_state =
1567 drm_atomic_get_new_connector_state(state, connector: &connector->base);
1568 struct intel_dp *intel_dp = connector->mst.dp;
1569 struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
1570
1571 return &intel_dp->mst.stream_encoders[crtc->pipe]->base.base;
1572}
1573
1574static int
1575mst_connector_detect_ctx(struct drm_connector *_connector,
1576 struct drm_modeset_acquire_ctx *ctx, bool force)
1577{
1578 struct intel_connector *connector = to_intel_connector(_connector);
1579 struct intel_display *display = to_intel_display(connector);
1580 struct intel_dp *intel_dp = connector->mst.dp;
1581
1582 if (!intel_display_device_enabled(display))
1583 return connector_status_disconnected;
1584
1585 if (drm_connector_is_unregistered(connector: &connector->base))
1586 return connector_status_disconnected;
1587
1588 if (!intel_display_driver_check_access(display))
1589 return connector->base.status;
1590
1591 intel_dp_flush_connector_commits(connector);
1592
1593 return drm_dp_mst_detect_port(connector: &connector->base, ctx, mgr: &intel_dp->mst.mgr,
1594 port: connector->mst.port);
1595}
1596
1597static const struct drm_connector_helper_funcs mst_connector_helper_funcs = {
1598 .get_modes = mst_connector_get_modes,
1599 .mode_valid_ctx = mst_connector_mode_valid_ctx,
1600 .atomic_best_encoder = mst_connector_atomic_best_encoder,
1601 .atomic_check = mst_connector_atomic_check,
1602 .detect_ctx = mst_connector_detect_ctx,
1603};
1604
1605static void mst_stream_encoder_destroy(struct drm_encoder *encoder)
1606{
1607 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
1608
1609 drm_encoder_cleanup(encoder);
1610 kfree(objp: intel_mst);
1611}
1612
1613static const struct drm_encoder_funcs mst_stream_encoder_funcs = {
1614 .destroy = mst_stream_encoder_destroy,
1615};
1616
1617static bool mst_connector_get_hw_state(struct intel_connector *connector)
1618{
1619 /* This is the MST stream encoder set in ->pre_enable, if any */
1620 struct intel_encoder *encoder = intel_attached_encoder(connector);
1621 enum pipe pipe;
1622
1623 if (!encoder || !connector->base.state->crtc)
1624 return false;
1625
1626 return encoder->get_hw_state(encoder, &pipe);
1627}
1628
1629static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
1630 struct drm_connector *_connector,
1631 const char *pathprop)
1632{
1633 struct intel_display *display = to_intel_display(intel_dp);
1634 struct intel_connector *connector = to_intel_connector(_connector);
1635
1636 drm_object_attach_property(obj: &connector->base.base,
1637 property: display->drm->mode_config.path_property, init_val: 0);
1638 drm_object_attach_property(obj: &connector->base.base,
1639 property: display->drm->mode_config.tile_property, init_val: 0);
1640
1641 intel_attach_force_audio_property(connector: &connector->base);
1642 intel_attach_broadcast_rgb_property(connector: &connector->base);
1643
1644 /*
1645 * Reuse the prop from the SST connector because we're
1646 * not allowed to create new props after device registration.
1647 */
1648 connector->base.max_bpc_property =
1649 intel_dp->attached_connector->base.max_bpc_property;
1650 if (connector->base.max_bpc_property)
1651 drm_connector_attach_max_bpc_property(connector: &connector->base, min: 6, max: 12);
1652
1653 return drm_connector_set_path_property(connector: &connector->base, path: pathprop);
1654}
1655
1656static void
1657intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
1658 struct intel_connector *connector)
1659{
1660 u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
1661
1662 if (!connector->dp.dsc_decompression_aux)
1663 return;
1664
1665 if (drm_dp_read_dpcd_caps(aux: connector->dp.dsc_decompression_aux, dpcd: dpcd_caps) < 0)
1666 return;
1667
1668 intel_dp_get_dsc_sink_cap(dpcd_rev: dpcd_caps[DP_DPCD_REV], connector);
1669}
1670
1671static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
1672{
1673 struct intel_display *display = to_intel_display(connector);
1674 struct drm_dp_aux *aux = connector->dp.dsc_decompression_aux;
1675 struct drm_dp_desc desc;
1676 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1677
1678 if (!aux)
1679 return false;
1680
1681 /*
1682 * A logical port's OUI (at least for affected sinks) is all 0, so
1683 * instead of that the parent port's OUI is used for identification.
1684 */
1685 if (drm_dp_mst_port_is_logical(port: connector->mst.port)) {
1686 aux = drm_dp_mst_aux_for_parent(port: connector->mst.port);
1687 if (!aux)
1688 aux = &connector->mst.dp->aux;
1689 }
1690
1691 if (drm_dp_read_dpcd_caps(aux, dpcd) < 0)
1692 return false;
1693
1694 if (drm_dp_read_desc(aux, desc: &desc, is_branch: drm_dp_is_branch(dpcd)) < 0)
1695 return false;
1696
1697 if (!drm_dp_has_quirk(desc: &desc,
1698 quirk: DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
1699 return false;
1700
1701 /*
1702 * UHBR (MST sink) devices requiring this quirk don't advertise the
1703 * HBLANK expansion support. Presuming that they perform HBLANK
1704 * expansion internally, or are affected by this issue on modes with a
1705 * short HBLANK for other reasons.
1706 */
1707 if (!drm_dp_128b132b_supported(dpcd) &&
1708 !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
1709 return false;
1710
1711 drm_dbg_kms(display->drm,
1712 "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n",
1713 connector->base.base.id, connector->base.name);
1714
1715 return true;
1716}
1717
1718static struct drm_connector *
1719mst_topology_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1720 struct drm_dp_mst_port *port,
1721 const char *pathprop)
1722{
1723 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst.mgr);
1724 struct intel_display *display = to_intel_display(intel_dp);
1725 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1726 struct intel_connector *connector;
1727 enum pipe pipe;
1728 int ret;
1729
1730 connector = intel_connector_alloc();
1731 if (!connector)
1732 return NULL;
1733
1734 connector->get_hw_state = mst_connector_get_hw_state;
1735 connector->sync_state = intel_dp_connector_sync_state;
1736 connector->mst.dp = intel_dp;
1737 connector->mst.port = port;
1738 drm_dp_mst_get_port_malloc(port);
1739
1740 ret = drm_connector_dynamic_init(dev: display->drm, connector: &connector->base, funcs: &mst_connector_funcs,
1741 DRM_MODE_CONNECTOR_DisplayPort, NULL);
1742 if (ret)
1743 goto err_put_port;
1744
1745 connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
1746 intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, connector);
1747 connector->dp.dsc_hblank_expansion_quirk =
1748 detect_dsc_hblank_expansion_quirk(connector);
1749
1750 drm_connector_helper_add(connector: &connector->base, funcs: &mst_connector_helper_funcs);
1751
1752 for_each_pipe(display, pipe) {
1753 struct drm_encoder *enc =
1754 &intel_dp->mst.stream_encoders[pipe]->base.base;
1755
1756 ret = drm_connector_attach_encoder(connector: &connector->base, encoder: enc);
1757 if (ret)
1758 goto err_cleanup_connector;
1759 }
1760
1761 ret = mst_topology_add_connector_properties(intel_dp, connector: &connector->base, pathprop);
1762 if (ret)
1763 goto err_cleanup_connector;
1764
1765 ret = intel_dp_hdcp_init(dig_port, intel_connector: connector);
1766 if (ret)
1767 drm_dbg_kms(display->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
1768 connector->base.name, connector->base.base.id);
1769
1770 return &connector->base;
1771
1772err_cleanup_connector:
1773 drm_connector_cleanup(connector: &connector->base);
1774err_put_port:
1775 drm_dp_mst_put_port_malloc(port);
1776 intel_connector_free(connector);
1777
1778 return NULL;
1779}
1780
1781static void
1782mst_topology_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
1783{
1784 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst.mgr);
1785
1786 intel_hpd_trigger_irq(dig_port: dp_to_dig_port(intel_dp));
1787}
1788
1789static const struct drm_dp_mst_topology_cbs mst_topology_cbs = {
1790 .add_connector = mst_topology_add_connector,
1791 .poll_hpd_irq = mst_topology_poll_hpd_irq,
1792};
1793
1794/* Create a fake encoder for an individual MST stream */
1795static struct intel_dp_mst_encoder *
1796mst_stream_encoder_create(struct intel_digital_port *dig_port, enum pipe pipe)
1797{
1798 struct intel_display *display = to_intel_display(dig_port);
1799 struct intel_encoder *primary_encoder = &dig_port->base;
1800 struct intel_dp_mst_encoder *intel_mst;
1801 struct intel_encoder *encoder;
1802
1803 intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
1804
1805 if (!intel_mst)
1806 return NULL;
1807
1808 intel_mst->pipe = pipe;
1809 encoder = &intel_mst->base;
1810 intel_mst->primary = dig_port;
1811
1812 drm_encoder_init(dev: display->drm, encoder: &encoder->base, funcs: &mst_stream_encoder_funcs,
1813 DRM_MODE_ENCODER_DPMST, name: "DP-MST %c", pipe_name(pipe));
1814
1815 encoder->type = INTEL_OUTPUT_DP_MST;
1816 encoder->power_domain = primary_encoder->power_domain;
1817 encoder->port = primary_encoder->port;
1818 encoder->cloneable = 0;
1819 /*
1820 * This is wrong, but broken userspace uses the intersection
1821 * of possible_crtcs of all the encoders of a given connector
1822 * to figure out which crtcs can drive said connector. What
1823 * should be used instead is the union of possible_crtcs.
1824 * To keep such userspace functioning we must misconfigure
1825 * this to make sure the intersection is not empty :(
1826 */
1827 encoder->pipe_mask = ~0;
1828
1829 encoder->compute_config = mst_stream_compute_config;
1830 encoder->compute_config_late = mst_stream_compute_config_late;
1831 encoder->disable = mst_stream_disable;
1832 encoder->post_disable = mst_stream_post_disable;
1833 encoder->post_pll_disable = mst_stream_post_pll_disable;
1834 encoder->update_pipe = intel_ddi_update_pipe;
1835 encoder->pre_pll_enable = mst_stream_pre_pll_enable;
1836 encoder->pre_enable = mst_stream_pre_enable;
1837 encoder->enable = mst_stream_enable;
1838 encoder->audio_enable = intel_audio_codec_enable;
1839 encoder->audio_disable = intel_audio_codec_disable;
1840 encoder->get_hw_state = mst_stream_get_hw_state;
1841 encoder->get_config = mst_stream_get_config;
1842 encoder->initial_fastset_check = mst_stream_initial_fastset_check;
1843
1844 return intel_mst;
1845
1846}
1847
1848/* Create the fake encoders for MST streams */
1849static bool
1850mst_stream_encoders_create(struct intel_digital_port *dig_port)
1851{
1852 struct intel_display *display = to_intel_display(dig_port);
1853 struct intel_dp *intel_dp = &dig_port->dp;
1854 enum pipe pipe;
1855
1856 for_each_pipe(display, pipe)
1857 intel_dp->mst.stream_encoders[pipe] = mst_stream_encoder_create(dig_port, pipe);
1858 return true;
1859}
1860
1861int
1862intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
1863{
1864 struct intel_display *display = to_intel_display(dig_port);
1865 struct intel_dp *intel_dp = &dig_port->dp;
1866 enum port port = dig_port->base.port;
1867 int ret;
1868
1869 if (!HAS_DP_MST(display) || intel_dp_is_edp(intel_dp))
1870 return 0;
1871
1872 if (DISPLAY_VER(display) < 12 && port == PORT_A)
1873 return 0;
1874
1875 if (DISPLAY_VER(display) < 11 && port == PORT_E)
1876 return 0;
1877
1878 intel_dp->mst.mgr.cbs = &mst_topology_cbs;
1879
1880 /* create encoders */
1881 mst_stream_encoders_create(dig_port);
1882 ret = drm_dp_mst_topology_mgr_init(mgr: &intel_dp->mst.mgr, dev: display->drm,
1883 aux: &intel_dp->aux, max_dpcd_transaction_bytes: 16,
1884 INTEL_NUM_PIPES(display), conn_base_id);
1885 if (ret) {
1886 intel_dp->mst.mgr.cbs = NULL;
1887 return ret;
1888 }
1889
1890 return 0;
1891}
1892
1893bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1894{
1895 return intel_dp->mst.mgr.cbs;
1896}
1897
1898void
1899intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1900{
1901 struct intel_dp *intel_dp = &dig_port->dp;
1902
1903 if (!intel_dp_mst_source_support(intel_dp))
1904 return;
1905
1906 drm_dp_mst_topology_mgr_destroy(mgr: &intel_dp->mst.mgr);
1907 /* encoders will get killed by normal cleanup */
1908
1909 intel_dp->mst.mgr.cbs = NULL;
1910}
1911
1912bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1913{
1914 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1915}
1916
1917bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1918{
1919 return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1920 crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1921}
1922
1923/**
1924 * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1925 * @state: atomic state
1926 * @connector: connector to add the state for
1927 * @crtc: the CRTC @connector is attached to
1928 *
1929 * Add the MST topology state for @connector to @state.
1930 *
1931 * Returns 0 on success, negative error code on failure.
1932 */
1933static int
1934intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,
1935 struct intel_connector *connector,
1936 struct intel_crtc *crtc)
1937{
1938 struct drm_dp_mst_topology_state *mst_state;
1939
1940 if (!connector->mst.dp)
1941 return 0;
1942
1943 mst_state = drm_atomic_get_mst_topology_state(state: &state->base,
1944 mgr: &connector->mst.dp->mst.mgr);
1945 if (IS_ERR(ptr: mst_state))
1946 return PTR_ERR(ptr: mst_state);
1947
1948 mst_state->pending_crtc_mask |= drm_crtc_mask(crtc: &crtc->base);
1949
1950 return 0;
1951}
1952
1953/**
1954 * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1955 * @state: atomic state
1956 * @crtc: CRTC to add the state for
1957 *
1958 * Add the MST topology state for @crtc to @state.
1959 *
1960 * Returns 0 on success, negative error code on failure.
1961 */
1962int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
1963 struct intel_crtc *crtc)
1964{
1965 struct drm_connector *_connector;
1966 struct drm_connector_state *conn_state;
1967 int i;
1968
1969 for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1970 struct intel_connector *connector = to_intel_connector(_connector);
1971 int ret;
1972
1973 if (conn_state->crtc != &crtc->base)
1974 continue;
1975
1976 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);
1977 if (ret)
1978 return ret;
1979 }
1980
1981 return 0;
1982}
1983
1984static struct intel_connector *
1985get_connector_in_state_for_crtc(struct intel_atomic_state *state,
1986 const struct intel_crtc *crtc)
1987{
1988 struct drm_connector_state *old_conn_state;
1989 struct drm_connector_state *new_conn_state;
1990 struct drm_connector *_connector;
1991 int i;
1992
1993 for_each_oldnew_connector_in_state(&state->base, _connector,
1994 old_conn_state, new_conn_state, i) {
1995 struct intel_connector *connector =
1996 to_intel_connector(_connector);
1997
1998 if (old_conn_state->crtc == &crtc->base ||
1999 new_conn_state->crtc == &crtc->base)
2000 return connector;
2001 }
2002
2003 return NULL;
2004}
2005
2006/**
2007 * intel_dp_mst_crtc_needs_modeset - check if changes in topology need to modeset the given CRTC
2008 * @state: atomic state
2009 * @crtc: CRTC for which to check the modeset requirement
2010 *
2011 * Check if any change in a MST topology requires a forced modeset on @crtc in
2012 * this topology. One such change is enabling/disabling the DSC decompression
2013 * state in the first branch device's UFP DPCD as required by one CRTC, while
2014 * the other @crtc in the same topology is still active, requiring a full modeset
2015 * on @crtc.
2016 */
2017bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
2018 struct intel_crtc *crtc)
2019{
2020 const struct intel_connector *crtc_connector;
2021 const struct drm_connector_state *conn_state;
2022 const struct drm_connector *_connector;
2023 int i;
2024
2025 if (!intel_crtc_has_type(crtc_state: intel_atomic_get_new_crtc_state(state, crtc),
2026 type: INTEL_OUTPUT_DP_MST))
2027 return false;
2028
2029 crtc_connector = get_connector_in_state_for_crtc(state, crtc);
2030
2031 if (!crtc_connector)
2032 /* None of the connectors in the topology needs modeset */
2033 return false;
2034
2035 for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
2036 const struct intel_connector *connector =
2037 to_intel_connector(_connector);
2038 const struct intel_crtc_state *new_crtc_state;
2039 const struct intel_crtc_state *old_crtc_state;
2040 struct intel_crtc *crtc_iter;
2041
2042 if (connector->mst.dp != crtc_connector->mst.dp ||
2043 !conn_state->crtc)
2044 continue;
2045
2046 crtc_iter = to_intel_crtc(conn_state->crtc);
2047
2048 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc: crtc_iter);
2049 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc: crtc_iter);
2050
2051 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
2052 continue;
2053
2054 if (old_crtc_state->dsc.compression_enable ==
2055 new_crtc_state->dsc.compression_enable)
2056 continue;
2057 /*
2058 * Toggling the decompression flag because of this stream in
2059 * the first downstream branch device's UFP DPCD may reset the
2060 * whole branch device. To avoid the reset while other streams
2061 * are also active modeset the whole MST topology in this
2062 * case.
2063 */
2064 if (connector->dp.dsc_decompression_aux ==
2065 &connector->mst.dp->aux)
2066 return true;
2067 }
2068
2069 return false;
2070}
2071
2072/**
2073 * intel_dp_mst_prepare_probe - Prepare an MST link for topology probing
2074 * @intel_dp: DP port object
2075 *
2076 * Prepare an MST link for topology probing, programming the target
2077 * link parameters to DPCD. This step is a requirement of the enumeration
2078 * of path resources during probing.
2079 */
2080void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
2081{
2082 int link_rate = intel_dp_max_link_rate(intel_dp);
2083 int lane_count = intel_dp_max_lane_count(intel_dp);
2084 u8 rate_select;
2085 u8 link_bw;
2086
2087 if (intel_dp->link.active)
2088 return;
2089
2090 if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count))
2091 return;
2092
2093 intel_dp_compute_rate(intel_dp, port_clock: link_rate, link_bw: &link_bw, rate_select: &rate_select);
2094
2095 intel_dp_link_training_set_mode(intel_dp, link_rate, is_vrr: false);
2096 intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
2097 enhanced_framing: drm_dp_enhanced_frame_cap(dpcd: intel_dp->dpcd));
2098
2099 intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count);
2100}
2101
2102/*
2103 * intel_dp_mst_verify_dpcd_state - verify the MST SW enabled state wrt. the DPCD
2104 * @intel_dp: DP port object
2105 *
2106 * Verify if @intel_dp's MST enabled SW state matches the corresponding DPCD
2107 * state. A long HPD pulse - not long enough to be detected as a disconnected
2108 * state - could've reset the DPCD state, which requires tearing
2109 * down/recreating the MST topology.
2110 *
2111 * Returns %true if the SW MST enabled and DPCD states match, %false
2112 * otherwise.
2113 */
2114bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp)
2115{
2116 struct intel_display *display = to_intel_display(intel_dp);
2117 struct intel_connector *connector = intel_dp->attached_connector;
2118 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2119 struct intel_encoder *encoder = &dig_port->base;
2120 int ret;
2121 u8 val;
2122
2123 if (!intel_dp->is_mst)
2124 return true;
2125
2126 ret = drm_dp_dpcd_readb(aux: intel_dp->mst.mgr.aux, DP_MSTM_CTRL, valuep: &val);
2127
2128 /* Adjust the expected register value for SST + SideBand. */
2129 if (ret < 0 || val != (DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC)) {
2130 drm_dbg_kms(display->drm,
2131 "[CONNECTOR:%d:%s][ENCODER:%d:%s] MST mode got reset, removing topology (ret=%d, ctrl=0x%02x)\n",
2132 connector->base.base.id, connector->base.name,
2133 encoder->base.base.id, encoder->base.name,
2134 ret, val);
2135
2136 return false;
2137 }
2138
2139 return true;
2140}
2141