1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24/**
25 * DOC: atomic plane helpers
26 *
27 * The functions here are used by the atomic plane helper functions to
28 * implement legacy plane updates (i.e., drm_plane->update_plane() and
29 * drm_plane->disable_plane()). This allows plane updates to use the
30 * atomic state infrastructure and perform plane updates as separate
31 * prepare/check/commit/cleanup steps.
32 */
33
34#include <linux/dma-fence-chain.h>
35#include <linux/dma-resv.h>
36#include <linux/iosys-map.h>
37
38#include <drm/drm_atomic_helper.h>
39#include <drm/drm_blend.h>
40#include <drm/drm_cache.h>
41#include <drm/drm_damage_helper.h>
42#include <drm/drm_fourcc.h>
43#include <drm/drm_gem.h>
44#include <drm/drm_gem_atomic_helper.h>
45#include <drm/drm_panic.h>
46
47#include "gem/i915_gem_object.h"
48#include "i915_scheduler_types.h"
49#include "i9xx_plane_regs.h"
50#include "intel_cdclk.h"
51#include "intel_cursor.h"
52#include "intel_display_rps.h"
53#include "intel_display_trace.h"
54#include "intel_display_types.h"
55#include "intel_fb.h"
56#include "intel_fb_pin.h"
57#include "intel_fbdev.h"
58#include "intel_panic.h"
59#include "intel_plane.h"
60#include "intel_psr.h"
61#include "skl_scaler.h"
62#include "skl_universal_plane.h"
63#include "skl_watermark.h"
64
65static void intel_plane_state_reset(struct intel_plane_state *plane_state,
66 struct intel_plane *plane)
67{
68 memset(s: plane_state, c: 0, n: sizeof(*plane_state));
69
70 __drm_atomic_helper_plane_state_reset(state: &plane_state->uapi, plane: &plane->base);
71
72 plane_state->scaler_id = -1;
73}
74
75struct intel_plane *intel_plane_alloc(void)
76{
77 struct intel_plane_state *plane_state;
78 struct intel_plane *plane;
79
80 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
81 if (!plane)
82 return ERR_PTR(error: -ENOMEM);
83
84 plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
85 if (!plane_state) {
86 kfree(objp: plane);
87 return ERR_PTR(error: -ENOMEM);
88 }
89
90 intel_plane_state_reset(plane_state, plane);
91
92 plane->base.state = &plane_state->uapi;
93
94 return plane;
95}
96
97void intel_plane_free(struct intel_plane *plane)
98{
99 intel_plane_destroy_state(plane: &plane->base, state: plane->base.state);
100 kfree(objp: plane);
101}
102
103/**
104 * intel_plane_destroy - destroy a plane
105 * @plane: plane to destroy
106 *
107 * Common destruction function for all types of planes (primary, cursor,
108 * sprite).
109 */
110void intel_plane_destroy(struct drm_plane *plane)
111{
112 drm_plane_cleanup(plane);
113 kfree(to_intel_plane(plane));
114}
115
116/**
117 * intel_plane_duplicate_state - duplicate plane state
118 * @plane: drm plane
119 *
120 * Allocates and returns a copy of the plane state (both common and
121 * Intel-specific) for the specified plane.
122 *
123 * Returns: The newly allocated plane state, or NULL on failure.
124 */
125struct drm_plane_state *
126intel_plane_duplicate_state(struct drm_plane *plane)
127{
128 struct intel_plane_state *intel_state;
129
130 intel_state = to_intel_plane_state(plane->state);
131 intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
132
133 if (!intel_state)
134 return NULL;
135
136 __drm_atomic_helper_plane_duplicate_state(plane, state: &intel_state->uapi);
137
138 intel_state->ggtt_vma = NULL;
139 intel_state->dpt_vma = NULL;
140 intel_state->flags = 0;
141 intel_state->damage = DRM_RECT_INIT(0, 0, 0, 0);
142
143 /* add reference to fb */
144 if (intel_state->hw.fb)
145 drm_framebuffer_get(fb: intel_state->hw.fb);
146
147 return &intel_state->uapi;
148}
149
150/**
151 * intel_plane_destroy_state - destroy plane state
152 * @plane: drm plane
153 * @state: state object to destroy
154 *
155 * Destroys the plane state (both common and Intel-specific) for the
156 * specified plane.
157 */
158void
159intel_plane_destroy_state(struct drm_plane *plane,
160 struct drm_plane_state *state)
161{
162 struct intel_plane_state *plane_state = to_intel_plane_state(state);
163
164 drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
165 drm_WARN_ON(plane->dev, plane_state->dpt_vma);
166
167 __drm_atomic_helper_plane_destroy_state(state: &plane_state->uapi);
168 if (plane_state->hw.fb)
169 drm_framebuffer_put(fb: plane_state->hw.fb);
170 kfree(objp: plane_state);
171}
172
173bool intel_plane_needs_physical(struct intel_plane *plane)
174{
175 struct intel_display *display = to_intel_display(plane);
176
177 return plane->id == PLANE_CURSOR &&
178 DISPLAY_INFO(display)->cursor_needs_physical;
179}
180
181bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,
182 u64 modifier)
183{
184 if (intel_format_info_is_yuv_semiplanar(info: drm_format_info(format), modifier) ||
185 format == DRM_FORMAT_C8)
186 return false;
187
188 return plane->can_async_flip && plane->can_async_flip(modifier);
189}
190
191bool intel_plane_format_mod_supported_async(struct drm_plane *plane,
192 u32 format,
193 u64 modifier)
194{
195 if (!plane->funcs->format_mod_supported(plane, format, modifier))
196 return false;
197
198 return intel_plane_can_async_flip(to_intel_plane(plane),
199 format, modifier);
200}
201
202unsigned int intel_adjusted_rate(const struct drm_rect *src,
203 const struct drm_rect *dst,
204 unsigned int rate)
205{
206 unsigned int src_w, src_h, dst_w, dst_h;
207
208 src_w = drm_rect_width(r: src) >> 16;
209 src_h = drm_rect_height(r: src) >> 16;
210 dst_w = drm_rect_width(r: dst);
211 dst_h = drm_rect_height(r: dst);
212
213 /* Downscaling limits the maximum pixel rate */
214 dst_w = min(src_w, dst_w);
215 dst_h = min(src_h, dst_h);
216
217 return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
218 dst_w * dst_h);
219}
220
221unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
222 const struct intel_plane_state *plane_state)
223{
224 /*
225 * Note we don't check for plane visibility here as
226 * we want to use this when calculating the cursor
227 * watermarks even if the cursor is fully offscreen.
228 * That depends on the src/dst rectangles being
229 * correctly populated whenever the watermark code
230 * considers the cursor to be visible, whether or not
231 * it is actually visible.
232 *
233 * See: intel_wm_plane_visible() and intel_check_cursor()
234 */
235
236 return intel_adjusted_rate(src: &plane_state->uapi.src,
237 dst: &plane_state->uapi.dst,
238 rate: crtc_state->pixel_rate);
239}
240
241unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
242 const struct intel_plane_state *plane_state,
243 int color_plane)
244{
245 const struct drm_framebuffer *fb = plane_state->hw.fb;
246
247 if (!plane_state->uapi.visible)
248 return 0;
249
250 return intel_plane_pixel_rate(crtc_state, plane_state) *
251 fb->format->cpp[color_plane];
252}
253
254static unsigned int
255intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
256 const struct intel_plane_state *plane_state,
257 int color_plane)
258{
259 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
260 const struct drm_framebuffer *fb = plane_state->hw.fb;
261 unsigned int rel_data_rate;
262 int width, height;
263
264 if (plane->id == PLANE_CURSOR)
265 return 0;
266
267 if (!plane_state->uapi.visible)
268 return 0;
269
270 /*
271 * Src coordinates are already rotated by 270 degrees for
272 * the 90/270 degree plane rotation cases (to match the
273 * GTT mapping), hence no need to account for rotation here.
274 */
275 width = drm_rect_width(r: &plane_state->uapi.src) >> 16;
276 height = drm_rect_height(r: &plane_state->uapi.src) >> 16;
277
278 /* UV plane does 1/2 pixel sub-sampling */
279 if (color_plane == 1) {
280 width /= 2;
281 height /= 2;
282 }
283
284 rel_data_rate =
285 skl_plane_relative_data_rate(crtc_state, plane, width, height,
286 cpp: fb->format->cpp[color_plane]);
287 if (!rel_data_rate)
288 return 0;
289
290 return intel_adjusted_rate(src: &plane_state->uapi.src,
291 dst: &plane_state->uapi.dst,
292 rate: rel_data_rate);
293}
294
295int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
296 struct intel_plane *plane,
297 bool *need_cdclk_calc)
298{
299 struct intel_display *display = to_intel_display(plane);
300 const struct intel_plane_state *plane_state =
301 intel_atomic_get_new_plane_state(state, plane);
302 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
303 const struct intel_cdclk_state *cdclk_state;
304 const struct intel_crtc_state *old_crtc_state;
305 struct intel_crtc_state *new_crtc_state;
306
307 if (!plane_state->uapi.visible || !plane->min_cdclk)
308 return 0;
309
310 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
311 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
312
313 new_crtc_state->min_cdclk[plane->id] =
314 plane->min_cdclk(new_crtc_state, plane_state);
315
316 /*
317 * No need to check against the cdclk state if
318 * the min cdclk for the plane doesn't increase.
319 *
320 * Ie. we only ever increase the cdclk due to plane
321 * requirements. This can reduce back and forth
322 * display blinking due to constant cdclk changes.
323 */
324 if (new_crtc_state->min_cdclk[plane->id] <=
325 old_crtc_state->min_cdclk[plane->id])
326 return 0;
327
328 cdclk_state = intel_atomic_get_cdclk_state(state);
329 if (IS_ERR(ptr: cdclk_state))
330 return PTR_ERR(ptr: cdclk_state);
331
332 /*
333 * No need to recalculate the cdclk state if
334 * the min cdclk for the pipe doesn't increase.
335 *
336 * Ie. we only ever increase the cdclk due to plane
337 * requirements. This can reduce back and forth
338 * display blinking due to constant cdclk changes.
339 */
340 if (new_crtc_state->min_cdclk[plane->id] <=
341 intel_cdclk_min_cdclk(cdclk_state, pipe: crtc->pipe))
342 return 0;
343
344 drm_dbg_kms(display->drm,
345 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
346 plane->base.base.id, plane->base.name,
347 new_crtc_state->min_cdclk[plane->id],
348 crtc->base.base.id, crtc->base.name,
349 intel_cdclk_min_cdclk(cdclk_state, crtc->pipe));
350 *need_cdclk_calc = true;
351
352 return 0;
353}
354
355static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
356{
357 if (plane_state->hw.fb)
358 drm_framebuffer_put(fb: plane_state->hw.fb);
359
360 memset(s: &plane_state->hw, c: 0, n: sizeof(plane_state->hw));
361}
362
363static void
364intel_plane_copy_uapi_plane_damage(struct intel_plane_state *new_plane_state,
365 const struct intel_plane_state *old_uapi_plane_state,
366 const struct intel_plane_state *new_uapi_plane_state)
367{
368 struct intel_display *display = to_intel_display(new_plane_state);
369 struct drm_rect *damage = &new_plane_state->damage;
370
371 /* damage property tracking enabled from display version 12 onwards */
372 if (DISPLAY_VER(display) < 12)
373 return;
374
375 if (!drm_atomic_helper_damage_merged(old_state: &old_uapi_plane_state->uapi,
376 state: &new_uapi_plane_state->uapi,
377 rect: damage))
378 /* Incase helper fails, mark whole plane region as damage */
379 *damage = drm_plane_state_src(state: &new_uapi_plane_state->uapi);
380}
381
382void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
383 const struct intel_plane_state *from_plane_state,
384 struct intel_crtc *crtc)
385{
386 intel_plane_clear_hw_state(plane_state);
387
388 /*
389 * For the joiner secondary uapi.crtc will point at
390 * the primary crtc. So we explicitly assign the right
391 * secondary crtc to hw.crtc. uapi.crtc!=NULL simply
392 * indicates the plane is logically enabled on the uapi level.
393 */
394 plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
395
396 plane_state->hw.fb = from_plane_state->uapi.fb;
397 if (plane_state->hw.fb)
398 drm_framebuffer_get(fb: plane_state->hw.fb);
399
400 plane_state->hw.alpha = from_plane_state->uapi.alpha;
401 plane_state->hw.pixel_blend_mode =
402 from_plane_state->uapi.pixel_blend_mode;
403 plane_state->hw.rotation = from_plane_state->uapi.rotation;
404 plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
405 plane_state->hw.color_range = from_plane_state->uapi.color_range;
406 plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
407
408 plane_state->uapi.src = drm_plane_state_src(state: &from_plane_state->uapi);
409 plane_state->uapi.dst = drm_plane_state_dest(state: &from_plane_state->uapi);
410}
411
412void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
413 const struct intel_plane_state *from_plane_state)
414{
415 intel_plane_clear_hw_state(plane_state);
416
417 memcpy(to: &plane_state->hw, from: &from_plane_state->hw,
418 len: sizeof(plane_state->hw));
419
420 if (plane_state->hw.fb)
421 drm_framebuffer_get(fb: plane_state->hw.fb);
422}
423
424void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
425 struct intel_plane_state *plane_state)
426{
427 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
428
429 crtc_state->active_planes &= ~BIT(plane->id);
430 crtc_state->scaled_planes &= ~BIT(plane->id);
431 crtc_state->nv12_planes &= ~BIT(plane->id);
432 crtc_state->c8_planes &= ~BIT(plane->id);
433 crtc_state->async_flip_planes &= ~BIT(plane->id);
434 crtc_state->data_rate[plane->id] = 0;
435 crtc_state->data_rate_y[plane->id] = 0;
436 crtc_state->rel_data_rate[plane->id] = 0;
437 crtc_state->rel_data_rate_y[plane->id] = 0;
438 crtc_state->min_cdclk[plane->id] = 0;
439
440 plane_state->uapi.visible = false;
441}
442
443static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
444{
445 int src_w = drm_rect_width(r: &plane_state->uapi.src) >> 16;
446 int src_h = drm_rect_height(r: &plane_state->uapi.src) >> 16;
447 int dst_w = drm_rect_width(r: &plane_state->uapi.dst);
448 int dst_h = drm_rect_height(r: &plane_state->uapi.dst);
449
450 return src_w != dst_w || src_h != dst_h;
451}
452
453static bool intel_plane_do_async_flip(struct intel_plane *plane,
454 const struct intel_crtc_state *old_crtc_state,
455 const struct intel_crtc_state *new_crtc_state)
456{
457 struct intel_display *display = to_intel_display(plane);
458
459 if (!plane->async_flip)
460 return false;
461
462 if (!new_crtc_state->uapi.async_flip)
463 return false;
464
465 /*
466 * In platforms after DISPLAY13, we might need to override
467 * first async flip in order to change watermark levels
468 * as part of optimization.
469 *
470 * And let's do this for all skl+ so that we can eg. change the
471 * modifier as well.
472 *
473 * TODO: For older platforms there is less reason to do this as
474 * only X-tile is supported with async flips, though we could
475 * extend this so other scanout parameters (stride/etc) could
476 * be changed as well...
477 */
478 return DISPLAY_VER(display) < 9 || old_crtc_state->uapi.async_flip;
479}
480
481static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
482 const struct intel_plane_state *old_plane_state,
483 const struct intel_plane_state *new_plane_state)
484{
485 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
486 bool old_visible = old_plane_state->uapi.visible;
487 bool new_visible = new_plane_state->uapi.visible;
488 u32 old_ctl = old_plane_state->ctl;
489 u32 new_ctl = new_plane_state->ctl;
490 bool modeset, turn_on, turn_off;
491
492 if (plane->id == PLANE_CURSOR)
493 return false;
494
495 modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
496 turn_off = old_visible && (!new_visible || modeset);
497 turn_on = new_visible && (!old_visible || modeset);
498
499 /* Must disable CxSR around plane enable/disable */
500 if (turn_on || turn_off)
501 return true;
502
503 if (!old_visible || !new_visible)
504 return false;
505
506 /*
507 * Most plane control register updates are blocked while in CxSR.
508 *
509 * Tiling mode is one exception where the primary plane can
510 * apparently handle it, whereas the sprites can not (the
511 * sprite issue being only relevant on VLV/CHV where CxSR
512 * is actually possible with a sprite enabled).
513 */
514 if (plane->id == PLANE_PRIMARY) {
515 old_ctl &= ~DISP_TILED;
516 new_ctl &= ~DISP_TILED;
517 }
518
519 return old_ctl != new_ctl;
520}
521
522static bool ilk_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
523 const struct intel_plane_state *old_plane_state,
524 const struct intel_plane_state *new_plane_state)
525{
526 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
527 bool old_visible = old_plane_state->uapi.visible;
528 bool new_visible = new_plane_state->uapi.visible;
529 bool modeset, turn_on;
530
531 if (plane->id == PLANE_CURSOR)
532 return false;
533
534 modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
535 turn_on = new_visible && (!old_visible || modeset);
536
537 /*
538 * ILK/SNB DVSACNTR/Sprite Enable
539 * IVB SPR_CTL/Sprite Enable
540 * "When in Self Refresh Big FIFO mode, a write to enable the
541 * plane will be internally buffered and delayed while Big FIFO
542 * mode is exiting."
543 *
544 * Which means that enabling the sprite can take an extra frame
545 * when we start in big FIFO mode (LP1+). Thus we need to drop
546 * down to LP0 and wait for vblank in order to make sure the
547 * sprite gets enabled on the next vblank after the register write.
548 * Doing otherwise would risk enabling the sprite one frame after
549 * we've already signalled flip completion. We can resume LP1+
550 * once the sprite has been enabled.
551 *
552 * With experimental results seems this is needed also for primary
553 * plane, not only sprite plane.
554 */
555 if (turn_on)
556 return true;
557
558 /*
559 * WaCxSRDisabledForSpriteScaling:ivb
560 * IVB SPR_SCALE/Scaling Enable
561 * "Low Power watermarks must be disabled for at least one
562 * frame before enabling sprite scaling, and kept disabled
563 * until sprite scaling is disabled."
564 *
565 * ILK/SNB DVSASCALE/Scaling Enable
566 * "When in Self Refresh Big FIFO mode, scaling enable will be
567 * masked off while Big FIFO mode is exiting."
568 *
569 * Despite the w/a only being listed for IVB we assume that
570 * the ILK/SNB note has similar ramifications, hence we apply
571 * the w/a on all three platforms.
572 */
573 return !intel_plane_is_scaled(plane_state: old_plane_state) &&
574 intel_plane_is_scaled(plane_state: new_plane_state);
575}
576
577static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
578 struct intel_crtc_state *new_crtc_state,
579 const struct intel_plane_state *old_plane_state,
580 struct intel_plane_state *new_plane_state)
581{
582 struct intel_display *display = to_intel_display(new_crtc_state);
583 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
584 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
585 bool mode_changed = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
586 bool was_crtc_enabled = old_crtc_state->hw.active;
587 bool is_crtc_enabled = new_crtc_state->hw.active;
588 bool turn_off, turn_on, visible, was_visible;
589 int ret;
590
591 if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_CURSOR) {
592 ret = skl_update_scaler_plane(crtc_state: new_crtc_state, plane_state: new_plane_state);
593 if (ret)
594 return ret;
595 }
596
597 was_visible = old_plane_state->uapi.visible;
598 visible = new_plane_state->uapi.visible;
599
600 if (!was_crtc_enabled && drm_WARN_ON(display->drm, was_visible))
601 was_visible = false;
602
603 /*
604 * Visibility is calculated as if the crtc was on, but
605 * after scaler setup everything depends on it being off
606 * when the crtc isn't active.
607 *
608 * FIXME this is wrong for watermarks. Watermarks should also
609 * be computed as if the pipe would be active. Perhaps move
610 * per-plane wm computation to the .check_plane() hook, and
611 * only combine the results from all planes in the current place?
612 */
613 if (!is_crtc_enabled) {
614 intel_plane_set_invisible(crtc_state: new_crtc_state, plane_state: new_plane_state);
615 visible = false;
616 }
617
618 if (!was_visible && !visible)
619 return 0;
620
621 turn_off = was_visible && (!visible || mode_changed);
622 turn_on = visible && (!was_visible || mode_changed);
623
624 drm_dbg_atomic(display->drm,
625 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
626 crtc->base.base.id, crtc->base.name,
627 plane->base.base.id, plane->base.name,
628 was_visible, visible,
629 turn_off, turn_on, mode_changed);
630
631 if (visible || was_visible)
632 new_crtc_state->fb_bits |= plane->frontbuffer_bit;
633
634 if (HAS_GMCH(display) &&
635 i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
636 new_crtc_state->disable_cxsr = true;
637
638 if ((display->platform.ironlake || display->platform.sandybridge || display->platform.ivybridge) &&
639 ilk_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
640 new_crtc_state->disable_cxsr = true;
641
642 if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
643 new_crtc_state->do_async_flip = true;
644 new_crtc_state->async_flip_planes |= BIT(plane->id);
645 } else if (plane->need_async_flip_toggle_wa &&
646 new_crtc_state->uapi.async_flip) {
647 /*
648 * On platforms with double buffered async flip bit we
649 * set the bit already one frame early during the sync
650 * flip (see {i9xx,skl}_plane_update_arm()). The
651 * hardware will therefore be ready to perform a real
652 * async flip during the next commit, without having
653 * to wait yet another frame for the bit to latch.
654 */
655 new_crtc_state->async_flip_planes |= BIT(plane->id);
656 }
657
658 return 0;
659}
660
661int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
662 struct intel_crtc_state *new_crtc_state,
663 const struct intel_plane_state *old_plane_state,
664 struct intel_plane_state *new_plane_state)
665{
666 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
667 const struct drm_framebuffer *fb = new_plane_state->hw.fb;
668 int ret;
669
670 intel_plane_set_invisible(crtc_state: new_crtc_state, plane_state: new_plane_state);
671 new_crtc_state->enabled_planes &= ~BIT(plane->id);
672
673 if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
674 return 0;
675
676 ret = plane->check_plane(new_crtc_state, new_plane_state);
677 if (ret)
678 return ret;
679
680 if (fb)
681 new_crtc_state->enabled_planes |= BIT(plane->id);
682
683 /* FIXME pre-g4x don't work like this */
684 if (new_plane_state->uapi.visible)
685 new_crtc_state->active_planes |= BIT(plane->id);
686
687 if (new_plane_state->uapi.visible &&
688 intel_plane_is_scaled(plane_state: new_plane_state))
689 new_crtc_state->scaled_planes |= BIT(plane->id);
690
691 if (new_plane_state->uapi.visible &&
692 intel_format_info_is_yuv_semiplanar(info: fb->format, modifier: fb->modifier))
693 new_crtc_state->nv12_planes |= BIT(plane->id);
694
695 if (new_plane_state->uapi.visible &&
696 fb->format->format == DRM_FORMAT_C8)
697 new_crtc_state->c8_planes |= BIT(plane->id);
698
699 if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
700 new_crtc_state->update_planes |= BIT(plane->id);
701
702 if (new_plane_state->uapi.visible &&
703 intel_format_info_is_yuv_semiplanar(info: fb->format, modifier: fb->modifier)) {
704 new_crtc_state->data_rate_y[plane->id] =
705 intel_plane_data_rate(crtc_state: new_crtc_state, plane_state: new_plane_state, color_plane: 0);
706 new_crtc_state->data_rate[plane->id] =
707 intel_plane_data_rate(crtc_state: new_crtc_state, plane_state: new_plane_state, color_plane: 1);
708
709 new_crtc_state->rel_data_rate_y[plane->id] =
710 intel_plane_relative_data_rate(crtc_state: new_crtc_state,
711 plane_state: new_plane_state, color_plane: 0);
712 new_crtc_state->rel_data_rate[plane->id] =
713 intel_plane_relative_data_rate(crtc_state: new_crtc_state,
714 plane_state: new_plane_state, color_plane: 1);
715 } else if (new_plane_state->uapi.visible) {
716 new_crtc_state->data_rate[plane->id] =
717 intel_plane_data_rate(crtc_state: new_crtc_state, plane_state: new_plane_state, color_plane: 0);
718
719 new_crtc_state->rel_data_rate[plane->id] =
720 intel_plane_relative_data_rate(crtc_state: new_crtc_state,
721 plane_state: new_plane_state, color_plane: 0);
722 }
723
724 return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
725 old_plane_state, new_plane_state);
726}
727
728struct intel_plane *
729intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
730{
731 struct intel_display *display = to_intel_display(crtc);
732 struct intel_plane *plane;
733
734 for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
735 if (plane->id == plane_id)
736 return plane;
737 }
738
739 return NULL;
740}
741
742static int plane_atomic_check(struct intel_atomic_state *state,
743 struct intel_plane *plane)
744{
745 struct intel_display *display = to_intel_display(state);
746 struct intel_plane_state *new_plane_state =
747 intel_atomic_get_new_plane_state(state, plane);
748 const struct intel_plane_state *old_plane_state =
749 intel_atomic_get_old_plane_state(state, plane);
750 const struct intel_plane_state *new_primary_crtc_plane_state;
751 const struct intel_plane_state *old_primary_crtc_plane_state;
752 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe: plane->pipe);
753 const struct intel_crtc_state *old_crtc_state =
754 intel_atomic_get_old_crtc_state(state, crtc);
755 struct intel_crtc_state *new_crtc_state =
756 intel_atomic_get_new_crtc_state(state, crtc);
757
758 if (new_crtc_state && intel_crtc_is_joiner_secondary(crtc_state: new_crtc_state)) {
759 struct intel_crtc *primary_crtc =
760 intel_primary_crtc(crtc_state: new_crtc_state);
761 struct intel_plane *primary_crtc_plane =
762 intel_crtc_get_plane(crtc: primary_crtc, plane_id: plane->id);
763
764 new_primary_crtc_plane_state =
765 intel_atomic_get_new_plane_state(state, plane: primary_crtc_plane);
766 old_primary_crtc_plane_state =
767 intel_atomic_get_old_plane_state(state, plane: primary_crtc_plane);
768 } else {
769 new_primary_crtc_plane_state = new_plane_state;
770 old_primary_crtc_plane_state = old_plane_state;
771 }
772
773 intel_plane_copy_uapi_plane_damage(new_plane_state,
774 old_uapi_plane_state: old_primary_crtc_plane_state,
775 new_uapi_plane_state: new_primary_crtc_plane_state);
776
777 intel_plane_copy_uapi_to_hw_state(plane_state: new_plane_state,
778 from_plane_state: new_primary_crtc_plane_state,
779 crtc);
780
781 new_plane_state->uapi.visible = false;
782 if (!new_crtc_state)
783 return 0;
784
785 return intel_plane_atomic_check_with_state(old_crtc_state,
786 new_crtc_state,
787 old_plane_state,
788 new_plane_state);
789}
790
791static struct intel_plane *
792skl_next_plane_to_commit(struct intel_atomic_state *state,
793 struct intel_crtc *crtc,
794 struct skl_ddb_entry ddb[I915_MAX_PLANES],
795 struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
796 unsigned int *update_mask)
797{
798 struct intel_crtc_state *crtc_state =
799 intel_atomic_get_new_crtc_state(state, crtc);
800 struct intel_plane_state __maybe_unused *plane_state;
801 struct intel_plane *plane;
802 int i;
803
804 if (*update_mask == 0)
805 return NULL;
806
807 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
808 enum plane_id plane_id = plane->id;
809
810 if (crtc->pipe != plane->pipe ||
811 !(*update_mask & BIT(plane_id)))
812 continue;
813
814 if (skl_ddb_allocation_overlaps(ddb: &crtc_state->wm.skl.plane_ddb[plane_id],
815 entries: ddb, num_entries: I915_MAX_PLANES, ignore_idx: plane_id) ||
816 skl_ddb_allocation_overlaps(ddb: &crtc_state->wm.skl.plane_ddb_y[plane_id],
817 entries: ddb_y, num_entries: I915_MAX_PLANES, ignore_idx: plane_id))
818 continue;
819
820 *update_mask &= ~BIT(plane_id);
821 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
822 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
823
824 return plane;
825 }
826
827 /* should never happen */
828 drm_WARN_ON(state->base.dev, 1);
829
830 return NULL;
831}
832
833void intel_plane_update_noarm(struct intel_dsb *dsb,
834 struct intel_plane *plane,
835 const struct intel_crtc_state *crtc_state,
836 const struct intel_plane_state *plane_state)
837{
838 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
839
840 trace_intel_plane_update_noarm(plane_state, crtc);
841
842 if (plane->fbc)
843 intel_fbc_dirty_rect_update_noarm(dsb, plane);
844
845 if (plane->update_noarm)
846 plane->update_noarm(dsb, plane, crtc_state, plane_state);
847}
848
849void intel_plane_async_flip(struct intel_dsb *dsb,
850 struct intel_plane *plane,
851 const struct intel_crtc_state *crtc_state,
852 const struct intel_plane_state *plane_state,
853 bool async_flip)
854{
855 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
856
857 trace_intel_plane_async_flip(plane, crtc, async_flip);
858 plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip);
859}
860
861void intel_plane_update_arm(struct intel_dsb *dsb,
862 struct intel_plane *plane,
863 const struct intel_crtc_state *crtc_state,
864 const struct intel_plane_state *plane_state)
865{
866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
867
868 if (crtc_state->do_async_flip && plane->async_flip) {
869 intel_plane_async_flip(dsb, plane, crtc_state, plane_state, async_flip: true);
870 return;
871 }
872
873 trace_intel_plane_update_arm(plane_state, crtc);
874 plane->update_arm(dsb, plane, crtc_state, plane_state);
875}
876
877void intel_plane_disable_arm(struct intel_dsb *dsb,
878 struct intel_plane *plane,
879 const struct intel_crtc_state *crtc_state)
880{
881 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
882
883 trace_intel_plane_disable_arm(plane, crtc);
884 plane->disable_arm(dsb, plane, crtc_state);
885}
886
887void intel_crtc_planes_update_noarm(struct intel_dsb *dsb,
888 struct intel_atomic_state *state,
889 struct intel_crtc *crtc)
890{
891 struct intel_crtc_state *new_crtc_state =
892 intel_atomic_get_new_crtc_state(state, crtc);
893 u32 update_mask = new_crtc_state->update_planes;
894 struct intel_plane_state *new_plane_state;
895 struct intel_plane *plane;
896 int i;
897
898 if (new_crtc_state->do_async_flip)
899 return;
900
901 /*
902 * Since we only write non-arming registers here,
903 * the order does not matter even for skl+.
904 */
905 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
906 if (crtc->pipe != plane->pipe ||
907 !(update_mask & BIT(plane->id)))
908 continue;
909
910 /* TODO: for mailbox updates this should be skipped */
911 if (new_plane_state->uapi.visible ||
912 new_plane_state->is_y_plane)
913 intel_plane_update_noarm(dsb, plane,
914 crtc_state: new_crtc_state, plane_state: new_plane_state);
915 }
916}
917
918static void skl_crtc_planes_update_arm(struct intel_dsb *dsb,
919 struct intel_atomic_state *state,
920 struct intel_crtc *crtc)
921{
922 struct intel_crtc_state *old_crtc_state =
923 intel_atomic_get_old_crtc_state(state, crtc);
924 struct intel_crtc_state *new_crtc_state =
925 intel_atomic_get_new_crtc_state(state, crtc);
926 struct skl_ddb_entry ddb[I915_MAX_PLANES];
927 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
928 u32 update_mask = new_crtc_state->update_planes;
929 struct intel_plane *plane;
930
931 memcpy(to: ddb, from: old_crtc_state->wm.skl.plane_ddb,
932 len: sizeof(old_crtc_state->wm.skl.plane_ddb));
933 memcpy(to: ddb_y, from: old_crtc_state->wm.skl.plane_ddb_y,
934 len: sizeof(old_crtc_state->wm.skl.plane_ddb_y));
935
936 while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, update_mask: &update_mask))) {
937 struct intel_plane_state *new_plane_state =
938 intel_atomic_get_new_plane_state(state, plane);
939
940 /*
941 * TODO: for mailbox updates intel_plane_update_noarm()
942 * would have to be called here as well.
943 */
944 if (new_plane_state->uapi.visible ||
945 new_plane_state->is_y_plane)
946 intel_plane_update_arm(dsb, plane, crtc_state: new_crtc_state, plane_state: new_plane_state);
947 else
948 intel_plane_disable_arm(dsb, plane, crtc_state: new_crtc_state);
949 }
950}
951
952static void i9xx_crtc_planes_update_arm(struct intel_dsb *dsb,
953 struct intel_atomic_state *state,
954 struct intel_crtc *crtc)
955{
956 struct intel_crtc_state *new_crtc_state =
957 intel_atomic_get_new_crtc_state(state, crtc);
958 u32 update_mask = new_crtc_state->update_planes;
959 struct intel_plane_state *new_plane_state;
960 struct intel_plane *plane;
961 int i;
962
963 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
964 if (crtc->pipe != plane->pipe ||
965 !(update_mask & BIT(plane->id)))
966 continue;
967
968 /*
969 * TODO: for mailbox updates intel_plane_update_noarm()
970 * would have to be called here as well.
971 */
972 if (new_plane_state->uapi.visible)
973 intel_plane_update_arm(dsb, plane, crtc_state: new_crtc_state, plane_state: new_plane_state);
974 else
975 intel_plane_disable_arm(dsb, plane, crtc_state: new_crtc_state);
976 }
977}
978
979void intel_crtc_planes_update_arm(struct intel_dsb *dsb,
980 struct intel_atomic_state *state,
981 struct intel_crtc *crtc)
982{
983 struct intel_display *display = to_intel_display(state);
984
985 if (DISPLAY_VER(display) >= 9)
986 skl_crtc_planes_update_arm(dsb, state, crtc);
987 else
988 i9xx_crtc_planes_update_arm(dsb, state, crtc);
989}
990
991int intel_plane_check_clipping(struct intel_plane_state *plane_state,
992 struct intel_crtc_state *crtc_state,
993 int min_scale, int max_scale,
994 bool can_position)
995{
996 struct intel_display *display = to_intel_display(plane_state);
997 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
998 struct drm_framebuffer *fb = plane_state->hw.fb;
999 struct drm_rect *src = &plane_state->uapi.src;
1000 struct drm_rect *dst = &plane_state->uapi.dst;
1001 const struct drm_rect *clip = &crtc_state->pipe_src;
1002 unsigned int rotation = plane_state->hw.rotation;
1003 int hscale, vscale;
1004
1005 if (!fb) {
1006 plane_state->uapi.visible = false;
1007 return 0;
1008 }
1009
1010 drm_rect_rotate(r: src, width: fb->width << 16, height: fb->height << 16, rotation);
1011
1012 /* Check scaling */
1013 hscale = drm_rect_calc_hscale(src, dst, min_hscale: min_scale, max_hscale: max_scale);
1014 vscale = drm_rect_calc_vscale(src, dst, min_vscale: min_scale, max_vscale: max_scale);
1015 if (hscale < 0 || vscale < 0) {
1016 drm_dbg_kms(display->drm,
1017 "[PLANE:%d:%s] invalid scaling "DRM_RECT_FP_FMT " -> " DRM_RECT_FMT "\n",
1018 plane->base.base.id, plane->base.name,
1019 DRM_RECT_FP_ARG(src), DRM_RECT_ARG(dst));
1020 return -ERANGE;
1021 }
1022
1023 /*
1024 * FIXME: This might need further adjustment for seamless scaling
1025 * with phase information, for the 2p2 and 2p1 scenarios.
1026 */
1027 plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
1028
1029 drm_rect_rotate_inv(r: src, width: fb->width << 16, height: fb->height << 16, rotation);
1030
1031 if (!can_position && plane_state->uapi.visible &&
1032 !drm_rect_equals(r1: dst, r2: clip)) {
1033 drm_dbg_kms(display->drm,
1034 "[PLANE:%d:%s] plane (" DRM_RECT_FMT ") must cover entire CRTC (" DRM_RECT_FMT ")\n",
1035 plane->base.base.id, plane->base.name,
1036 DRM_RECT_ARG(dst), DRM_RECT_ARG(clip));
1037 return -EINVAL;
1038 }
1039
1040 /* final plane coordinates will be relative to the plane's pipe */
1041 drm_rect_translate(r: dst, dx: -clip->x1, dy: -clip->y1);
1042
1043 return 0;
1044}
1045
1046int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
1047{
1048 struct intel_display *display = to_intel_display(plane_state);
1049 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1050 const struct drm_framebuffer *fb = plane_state->hw.fb;
1051 struct drm_rect *src = &plane_state->uapi.src;
1052 u32 src_x, src_y, src_w, src_h, hsub, vsub;
1053 bool rotated = drm_rotation_90_or_270(rotation: plane_state->hw.rotation);
1054
1055 /*
1056 * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
1057 * abuses hsub/vsub so we can't use them here. But as they
1058 * are limited to 32bpp RGB formats we don't actually need
1059 * to check anything.
1060 */
1061 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1062 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
1063 return 0;
1064
1065 /*
1066 * Hardware doesn't handle subpixel coordinates.
1067 * Adjust to (macro)pixel boundary, but be careful not to
1068 * increase the source viewport size, because that could
1069 * push the downscaling factor out of bounds.
1070 */
1071 src_x = src->x1 >> 16;
1072 src_w = drm_rect_width(r: src) >> 16;
1073 src_y = src->y1 >> 16;
1074 src_h = drm_rect_height(r: src) >> 16;
1075
1076 drm_rect_init(r: src, x: src_x << 16, y: src_y << 16,
1077 width: src_w << 16, height: src_h << 16);
1078
1079 if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
1080 hsub = 2;
1081 vsub = 2;
1082 } else if (DISPLAY_VER(display) >= 20 &&
1083 intel_format_info_is_yuv_semiplanar(info: fb->format, modifier: fb->modifier)) {
1084 /*
1085 * This allows NV12 and P0xx formats to have odd size and/or odd
1086 * source coordinates on DISPLAY_VER(display) >= 20
1087 */
1088 hsub = 1;
1089 vsub = 1;
1090
1091 /* Wa_16023981245 */
1092 if ((DISPLAY_VERx100(display) == 2000 ||
1093 DISPLAY_VERx100(display) == 3000 ||
1094 DISPLAY_VERx100(display) == 3002) &&
1095 src_x % 2 != 0)
1096 hsub = 2;
1097 } else {
1098 hsub = fb->format->hsub;
1099 vsub = fb->format->vsub;
1100 }
1101
1102 if (rotated)
1103 hsub = vsub = max(hsub, vsub);
1104
1105 if (src_x % hsub || src_w % hsub) {
1106 drm_dbg_kms(display->drm,
1107 "[PLANE:%d:%s] src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
1108 plane->base.base.id, plane->base.name,
1109 src_x, src_w, hsub, str_yes_no(rotated));
1110 return -EINVAL;
1111 }
1112
1113 if (src_y % vsub || src_h % vsub) {
1114 drm_dbg_kms(display->drm,
1115 "[PLANE:%d:%s] src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
1116 plane->base.base.id, plane->base.name,
1117 src_y, src_h, vsub, str_yes_no(rotated));
1118 return -EINVAL;
1119 }
1120
1121 return 0;
1122}
1123
1124static int add_dma_resv_fences(struct dma_resv *resv,
1125 struct drm_plane_state *new_plane_state)
1126{
1127 struct dma_fence *fence = dma_fence_get(fence: new_plane_state->fence);
1128 struct dma_fence *new;
1129 int ret;
1130
1131 ret = dma_resv_get_singleton(obj: resv, usage: dma_resv_usage_rw(write: false), fence: &new);
1132 if (ret)
1133 goto error;
1134
1135 if (new && fence) {
1136 struct dma_fence_chain *chain = dma_fence_chain_alloc();
1137
1138 if (!chain) {
1139 ret = -ENOMEM;
1140 goto error;
1141 }
1142
1143 dma_fence_chain_init(chain, prev: fence, fence: new, seqno: 1);
1144 fence = &chain->base;
1145
1146 } else if (new) {
1147 fence = new;
1148 }
1149
1150 dma_fence_put(fence: new_plane_state->fence);
1151 new_plane_state->fence = fence;
1152 return 0;
1153
1154error:
1155 dma_fence_put(fence);
1156 return ret;
1157}
1158
1159/**
1160 * intel_prepare_plane_fb - Prepare fb for usage on plane
1161 * @_plane: drm plane to prepare for
1162 * @_new_plane_state: the plane state being prepared
1163 *
1164 * Prepares a framebuffer for usage on a display plane. Generally this
1165 * involves pinning the underlying object and updating the frontbuffer tracking
1166 * bits. Some older platforms need special physical address handling for
1167 * cursor planes.
1168 *
1169 * Returns 0 on success, negative error code on failure.
1170 */
1171static int
1172intel_prepare_plane_fb(struct drm_plane *_plane,
1173 struct drm_plane_state *_new_plane_state)
1174{
1175 struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
1176 struct intel_plane *plane = to_intel_plane(_plane);
1177 struct intel_display *display = to_intel_display(plane);
1178 struct intel_plane_state *new_plane_state =
1179 to_intel_plane_state(_new_plane_state);
1180 struct intel_atomic_state *state =
1181 to_intel_atomic_state(new_plane_state->uapi.state);
1182 struct intel_plane_state *old_plane_state =
1183 intel_atomic_get_old_plane_state(state, plane);
1184 struct drm_gem_object *obj = intel_fb_bo(fb: new_plane_state->hw.fb);
1185 struct drm_gem_object *old_obj = intel_fb_bo(fb: old_plane_state->hw.fb);
1186 int ret;
1187
1188 if (old_obj) {
1189 const struct intel_crtc_state *new_crtc_state =
1190 intel_atomic_get_new_crtc_state(state,
1191 to_intel_crtc(old_plane_state->hw.crtc));
1192
1193 /* Big Hammer, we also need to ensure that any pending
1194 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1195 * current scanout is retired before unpinning the old
1196 * framebuffer. Note that we rely on userspace rendering
1197 * into the buffer attached to the pipe they are waiting
1198 * on. If not, userspace generates a GPU hang with IPEHR
1199 * point to the MI_WAIT_FOR_EVENT.
1200 *
1201 * This should only fail upon a hung GPU, in which case we
1202 * can safely continue.
1203 */
1204 if (intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
1205 ret = add_dma_resv_fences(resv: old_obj->resv,
1206 new_plane_state: &new_plane_state->uapi);
1207 if (ret < 0)
1208 return ret;
1209 }
1210 }
1211
1212 if (!obj)
1213 return 0;
1214
1215 ret = intel_plane_pin_fb(new_plane_state, old_plane_state);
1216 if (ret)
1217 return ret;
1218
1219 ret = drm_gem_plane_helper_prepare_fb(plane: &plane->base, state: &new_plane_state->uapi);
1220 if (ret < 0)
1221 goto unpin_fb;
1222
1223 if (new_plane_state->uapi.fence) {
1224 i915_gem_fence_wait_priority(fence: new_plane_state->uapi.fence,
1225 attr: &attr);
1226
1227 intel_display_rps_boost_after_vblank(crtc: new_plane_state->hw.crtc,
1228 fence: new_plane_state->uapi.fence);
1229 }
1230
1231 /*
1232 * We declare pageflips to be interactive and so merit a small bias
1233 * towards upclocking to deliver the frame on time. By only changing
1234 * the RPS thresholds to sample more regularly and aim for higher
1235 * clocks we can hopefully deliver low power workloads (like kodi)
1236 * that are not quite steady state without resorting to forcing
1237 * maximum clocks following a vblank miss (see do_rps_boost()).
1238 */
1239 intel_display_rps_mark_interactive(display, state, interactive: true);
1240
1241 return 0;
1242
1243unpin_fb:
1244 intel_plane_unpin_fb(old_plane_state: new_plane_state);
1245
1246 return ret;
1247}
1248
1249/**
1250 * intel_cleanup_plane_fb - Cleans up an fb after plane use
1251 * @plane: drm plane to clean up for
1252 * @_old_plane_state: the state from the previous modeset
1253 *
1254 * Cleans up a framebuffer that has just been removed from a plane.
1255 */
1256static void
1257intel_cleanup_plane_fb(struct drm_plane *plane,
1258 struct drm_plane_state *_old_plane_state)
1259{
1260 struct intel_display *display = to_intel_display(plane->dev);
1261 struct intel_plane_state *old_plane_state =
1262 to_intel_plane_state(_old_plane_state);
1263 struct intel_atomic_state *state =
1264 to_intel_atomic_state(old_plane_state->uapi.state);
1265 struct drm_gem_object *obj = intel_fb_bo(fb: old_plane_state->hw.fb);
1266
1267 if (!obj)
1268 return;
1269
1270 intel_display_rps_mark_interactive(display, state, interactive: false);
1271
1272 intel_plane_unpin_fb(old_plane_state);
1273}
1274
1275/* Handle Y-tiling, only if DPT is enabled (otherwise disabling tiling is easier)
1276 * All DPT hardware have 128-bytes width tiling, so Y-tile dimension is 32x32
1277 * pixels for 32bits pixels.
1278 */
1279#define YTILE_WIDTH 32
1280#define YTILE_HEIGHT 32
1281#define YTILE_SIZE (YTILE_WIDTH * YTILE_HEIGHT * 4)
1282
1283static unsigned int intel_ytile_get_offset(unsigned int width, unsigned int x, unsigned int y)
1284{
1285 u32 offset;
1286 unsigned int swizzle;
1287 unsigned int width_in_blocks = DIV_ROUND_UP(width, 32);
1288
1289 /* Block offset */
1290 offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * YTILE_SIZE;
1291
1292 x = x % YTILE_WIDTH;
1293 y = y % YTILE_HEIGHT;
1294
1295 /* bit order inside a block is x4 x3 x2 y4 y3 y2 y1 y0 x1 x0 */
1296 swizzle = (x & 3) | ((y & 0x1f) << 2) | ((x & 0x1c) << 5);
1297 offset += swizzle * 4;
1298 return offset;
1299}
1300
1301static unsigned int intel_4tile_get_offset(unsigned int width, unsigned int x, unsigned int y)
1302{
1303 u32 offset;
1304 unsigned int swizzle;
1305 unsigned int width_in_blocks = DIV_ROUND_UP(width, 32);
1306
1307 /* Block offset */
1308 offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * YTILE_SIZE;
1309
1310 x = x % YTILE_WIDTH;
1311 y = y % YTILE_HEIGHT;
1312
1313 /* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */
1314 swizzle = (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 |
1315 ((x & 0x10) << 3) | ((y & 0x18) << 5);
1316 offset += swizzle * 4;
1317 return offset;
1318}
1319
1320static void intel_panic_flush(struct drm_plane *plane)
1321{
1322 struct intel_plane_state *plane_state = to_intel_plane_state(plane->state);
1323 struct intel_crtc_state *crtc_state = to_intel_crtc_state(plane->state->crtc->state);
1324 struct intel_plane *iplane = to_intel_plane(plane);
1325 struct intel_display *display = to_intel_display(iplane);
1326 struct drm_framebuffer *fb = plane_state->hw.fb;
1327 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1328
1329 intel_panic_finish(panic: intel_fb->panic);
1330
1331 if (crtc_state->enable_psr2_sel_fetch) {
1332 /* Force a full update for psr2 */
1333 intel_psr2_panic_force_full_update(display, crtc_state);
1334 }
1335
1336 /* Flush the cache and don't disable tiling if it's the fbdev framebuffer.*/
1337 if (intel_fb == intel_fbdev_framebuffer(fbdev: display->fbdev.fbdev)) {
1338 struct iosys_map map;
1339
1340 intel_fbdev_get_map(fbdev: display->fbdev.fbdev, map: &map);
1341 drm_clflush_virt_range(addr: map.vaddr, length: fb->pitches[0] * fb->height);
1342 return;
1343 }
1344
1345 if (fb->modifier && iplane->disable_tiling)
1346 iplane->disable_tiling(iplane);
1347}
1348
1349static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int width,
1350 unsigned int x,
1351 unsigned int y)
1352{
1353 switch (fb_modifier) {
1354 case I915_FORMAT_MOD_Y_TILED:
1355 case I915_FORMAT_MOD_Y_TILED_CCS:
1356 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1357 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1358 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1359 return intel_ytile_get_offset;
1360 case I915_FORMAT_MOD_4_TILED:
1361 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
1362 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
1363 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
1364 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
1365 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
1366 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
1367 case I915_FORMAT_MOD_4_TILED_BMG_CCS:
1368 case I915_FORMAT_MOD_4_TILED_LNL_CCS:
1369 return intel_4tile_get_offset;
1370 case I915_FORMAT_MOD_X_TILED:
1371 case I915_FORMAT_MOD_Yf_TILED:
1372 case I915_FORMAT_MOD_Yf_TILED_CCS:
1373 default:
1374 /* Not supported yet */
1375 return NULL;
1376 }
1377}
1378
1379static int intel_get_scanout_buffer(struct drm_plane *plane,
1380 struct drm_scanout_buffer *sb)
1381{
1382 struct intel_plane_state *plane_state;
1383 struct drm_gem_object *obj;
1384 struct drm_framebuffer *fb;
1385 struct intel_framebuffer *intel_fb;
1386 struct intel_display *display = to_intel_display(plane->dev);
1387
1388 if (!plane->state || !plane->state->fb || !plane->state->visible)
1389 return -ENODEV;
1390
1391 plane_state = to_intel_plane_state(plane->state);
1392 fb = plane_state->hw.fb;
1393 intel_fb = to_intel_framebuffer(fb);
1394
1395 obj = intel_fb_bo(fb);
1396 if (!obj)
1397 return -ENODEV;
1398
1399 if (intel_fb == intel_fbdev_framebuffer(fbdev: display->fbdev.fbdev)) {
1400 intel_fbdev_get_map(fbdev: display->fbdev.fbdev, map: &sb->map[0]);
1401 } else {
1402 int ret;
1403 /* Can't disable tiling if DPT is in use */
1404 if (intel_fb_uses_dpt(fb)) {
1405 if (fb->format->cpp[0] != 4)
1406 return -EOPNOTSUPP;
1407 intel_fb->panic_tiling = intel_get_tiling_func(fb_modifier: fb->modifier);
1408 if (!intel_fb->panic_tiling)
1409 return -EOPNOTSUPP;
1410 }
1411 sb->private = intel_fb;
1412 ret = intel_panic_setup(panic: intel_fb->panic, sb);
1413 if (ret)
1414 return ret;
1415 }
1416 sb->width = fb->width;
1417 sb->height = fb->height;
1418 /* Use the generic linear format, because tiling, RC, CCS, CC
1419 * will be disabled in disable_tiling()
1420 */
1421 sb->format = drm_format_info(format: fb->format->format);
1422 sb->pitch[0] = fb->pitches[0];
1423
1424 return 0;
1425}
1426
1427static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1428 .prepare_fb = intel_prepare_plane_fb,
1429 .cleanup_fb = intel_cleanup_plane_fb,
1430};
1431
1432static const struct drm_plane_helper_funcs intel_primary_plane_helper_funcs = {
1433 .prepare_fb = intel_prepare_plane_fb,
1434 .cleanup_fb = intel_cleanup_plane_fb,
1435 .get_scanout_buffer = intel_get_scanout_buffer,
1436 .panic_flush = intel_panic_flush,
1437};
1438
1439void intel_plane_helper_add(struct intel_plane *plane)
1440{
1441 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1442 drm_plane_helper_add(plane: &plane->base, funcs: &intel_primary_plane_helper_funcs);
1443 else
1444 drm_plane_helper_add(plane: &plane->base, funcs: &intel_plane_helper_funcs);
1445}
1446
1447void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state,
1448 struct intel_plane_state *new_plane_state)
1449{
1450 if (!old_plane_state->ggtt_vma ||
1451 old_plane_state->ggtt_vma == new_plane_state->ggtt_vma)
1452 return;
1453
1454 drm_vblank_work_init(work: &old_plane_state->unpin_work, crtc: old_plane_state->uapi.crtc,
1455 func: intel_cursor_unpin_work);
1456}
1457
1458static void link_nv12_planes(struct intel_crtc_state *crtc_state,
1459 struct intel_plane_state *uv_plane_state,
1460 struct intel_plane_state *y_plane_state)
1461{
1462 struct intel_display *display = to_intel_display(uv_plane_state);
1463 struct intel_plane *uv_plane = to_intel_plane(uv_plane_state->uapi.plane);
1464 struct intel_plane *y_plane = to_intel_plane(y_plane_state->uapi.plane);
1465
1466 drm_dbg_kms(display->drm, "UV plane [PLANE:%d:%s] using Y plane [PLANE:%d:%s]\n",
1467 uv_plane->base.base.id, uv_plane->base.name,
1468 y_plane->base.base.id, y_plane->base.name);
1469
1470 uv_plane_state->planar_linked_plane = y_plane;
1471
1472 y_plane_state->is_y_plane = true;
1473 y_plane_state->planar_linked_plane = uv_plane;
1474
1475 crtc_state->enabled_planes |= BIT(y_plane->id);
1476 crtc_state->active_planes |= BIT(y_plane->id);
1477 crtc_state->update_planes |= BIT(y_plane->id);
1478
1479 crtc_state->data_rate[y_plane->id] = crtc_state->data_rate_y[uv_plane->id];
1480 crtc_state->rel_data_rate[y_plane->id] = crtc_state->rel_data_rate_y[uv_plane->id];
1481
1482 /* Copy parameters to Y plane */
1483 intel_plane_copy_hw_state(plane_state: y_plane_state, from_plane_state: uv_plane_state);
1484 y_plane_state->uapi.src = uv_plane_state->uapi.src;
1485 y_plane_state->uapi.dst = uv_plane_state->uapi.dst;
1486
1487 y_plane_state->ctl = uv_plane_state->ctl;
1488 y_plane_state->color_ctl = uv_plane_state->color_ctl;
1489 y_plane_state->view = uv_plane_state->view;
1490 y_plane_state->decrypt = uv_plane_state->decrypt;
1491
1492 icl_link_nv12_planes(uv_plane_state, y_plane_state);
1493}
1494
1495static void unlink_nv12_plane(struct intel_crtc_state *crtc_state,
1496 struct intel_plane_state *plane_state)
1497{
1498 struct intel_display *display = to_intel_display(plane_state);
1499 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1500
1501 plane_state->planar_linked_plane = NULL;
1502
1503 if (!plane_state->is_y_plane)
1504 return;
1505
1506 drm_WARN_ON(display->drm, plane_state->uapi.visible);
1507
1508 plane_state->is_y_plane = false;
1509
1510 crtc_state->enabled_planes &= ~BIT(plane->id);
1511 crtc_state->active_planes &= ~BIT(plane->id);
1512 crtc_state->update_planes |= BIT(plane->id);
1513 crtc_state->data_rate[plane->id] = 0;
1514 crtc_state->rel_data_rate[plane->id] = 0;
1515}
1516
1517static int icl_check_nv12_planes(struct intel_atomic_state *state,
1518 struct intel_crtc *crtc)
1519{
1520 struct intel_display *display = to_intel_display(state);
1521 struct intel_crtc_state *crtc_state =
1522 intel_atomic_get_new_crtc_state(state, crtc);
1523 struct intel_plane_state *plane_state;
1524 struct intel_plane *plane;
1525 int i;
1526
1527 if (DISPLAY_VER(display) < 11)
1528 return 0;
1529
1530 /*
1531 * Destroy all old plane links and make the Y plane invisible
1532 * in the crtc_state->active_planes mask.
1533 */
1534 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1535 if (plane->pipe != crtc->pipe)
1536 continue;
1537
1538 if (plane_state->planar_linked_plane)
1539 unlink_nv12_plane(crtc_state, plane_state);
1540 }
1541
1542 if (!crtc_state->nv12_planes)
1543 return 0;
1544
1545 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1546 struct intel_plane_state *y_plane_state = NULL;
1547 struct intel_plane *y_plane;
1548
1549 if (plane->pipe != crtc->pipe)
1550 continue;
1551
1552 if ((crtc_state->nv12_planes & BIT(plane->id)) == 0)
1553 continue;
1554
1555 for_each_intel_plane_on_crtc(display->drm, crtc, y_plane) {
1556 if (!icl_is_nv12_y_plane(display, plane_id: y_plane->id))
1557 continue;
1558
1559 if (crtc_state->active_planes & BIT(y_plane->id))
1560 continue;
1561
1562 y_plane_state = intel_atomic_get_plane_state(state, plane: y_plane);
1563 if (IS_ERR(ptr: y_plane_state))
1564 return PTR_ERR(ptr: y_plane_state);
1565
1566 break;
1567 }
1568
1569 if (!y_plane_state) {
1570 drm_dbg_kms(display->drm,
1571 "[CRTC:%d:%s] need %d free Y planes for planar YUV\n",
1572 crtc->base.base.id, crtc->base.name,
1573 hweight8(crtc_state->nv12_planes));
1574 return -EINVAL;
1575 }
1576
1577 link_nv12_planes(crtc_state, uv_plane_state: plane_state, y_plane_state);
1578 }
1579
1580 return 0;
1581}
1582
1583static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
1584 struct intel_crtc *crtc,
1585 u8 plane_ids_mask)
1586{
1587 struct intel_display *display = to_intel_display(state);
1588 struct intel_plane *plane;
1589
1590 for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
1591 struct intel_plane_state *plane_state;
1592
1593 if ((plane_ids_mask & BIT(plane->id)) == 0)
1594 continue;
1595
1596 plane_state = intel_atomic_get_plane_state(state, plane);
1597 if (IS_ERR(ptr: plane_state))
1598 return PTR_ERR(ptr: plane_state);
1599 }
1600
1601 return 0;
1602}
1603
1604int intel_plane_add_affected(struct intel_atomic_state *state,
1605 struct intel_crtc *crtc)
1606{
1607 const struct intel_crtc_state *old_crtc_state =
1608 intel_atomic_get_old_crtc_state(state, crtc);
1609 const struct intel_crtc_state *new_crtc_state =
1610 intel_atomic_get_new_crtc_state(state, crtc);
1611
1612 return intel_crtc_add_planes_to_state(state, crtc,
1613 plane_ids_mask: old_crtc_state->enabled_planes |
1614 new_crtc_state->enabled_planes);
1615}
1616
1617static bool active_planes_affects_min_cdclk(struct intel_display *display)
1618{
1619 /* See {hsw,vlv,ivb}_plane_ratio() */
1620 return display->platform.broadwell || display->platform.haswell ||
1621 display->platform.cherryview || display->platform.valleyview ||
1622 display->platform.ivybridge;
1623}
1624
1625static u8 intel_joiner_affected_planes(struct intel_atomic_state *state,
1626 u8 joined_pipes)
1627{
1628 const struct intel_plane_state *plane_state;
1629 struct intel_plane *plane;
1630 u8 affected_planes = 0;
1631 int i;
1632
1633 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1634 struct intel_plane *linked = plane_state->planar_linked_plane;
1635
1636 if ((joined_pipes & BIT(plane->pipe)) == 0)
1637 continue;
1638
1639 affected_planes |= BIT(plane->id);
1640 if (linked)
1641 affected_planes |= BIT(linked->id);
1642 }
1643
1644 return affected_planes;
1645}
1646
1647static int intel_joiner_add_affected_planes(struct intel_atomic_state *state,
1648 u8 joined_pipes)
1649{
1650 u8 prev_affected_planes, affected_planes = 0;
1651
1652 /*
1653 * We want all the joined pipes to have the same
1654 * set of planes in the atomic state, to make sure
1655 * state copying always works correctly, and the
1656 * UV<->Y plane linkage is always up to date.
1657 * Keep pulling planes in until we've determined
1658 * the full set of affected planes. A bit complicated
1659 * on account of each pipe being capable of selecting
1660 * their own Y planes independently of the other pipes,
1661 * and the selection being done from the set of
1662 * inactive planes.
1663 */
1664 do {
1665 struct intel_crtc *crtc;
1666
1667 for_each_intel_crtc_in_pipe_mask(state->base.dev, crtc, joined_pipes) {
1668 int ret;
1669
1670 ret = intel_crtc_add_planes_to_state(state, crtc, plane_ids_mask: affected_planes);
1671 if (ret)
1672 return ret;
1673 }
1674
1675 prev_affected_planes = affected_planes;
1676 affected_planes = intel_joiner_affected_planes(state, joined_pipes);
1677 } while (affected_planes != prev_affected_planes);
1678
1679 return 0;
1680}
1681
1682static int intel_add_affected_planes(struct intel_atomic_state *state)
1683{
1684 const struct intel_crtc_state *crtc_state;
1685 struct intel_crtc *crtc;
1686 int i;
1687
1688 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1689 int ret;
1690
1691 ret = intel_joiner_add_affected_planes(state, joined_pipes: intel_crtc_joined_pipe_mask(crtc_state));
1692 if (ret)
1693 return ret;
1694 }
1695
1696 return 0;
1697}
1698
1699int intel_plane_atomic_check(struct intel_atomic_state *state)
1700{
1701 struct intel_display *display = to_intel_display(state);
1702 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
1703 struct intel_plane_state __maybe_unused *plane_state;
1704 struct intel_plane *plane;
1705 struct intel_crtc *crtc;
1706 int i, ret;
1707
1708 ret = intel_add_affected_planes(state);
1709 if (ret)
1710 return ret;
1711
1712 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1713 ret = plane_atomic_check(state, plane);
1714 if (ret) {
1715 drm_dbg_atomic(display->drm,
1716 "[PLANE:%d:%s] atomic driver check failed\n",
1717 plane->base.base.id, plane->base.name);
1718 return ret;
1719 }
1720 }
1721
1722 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
1723 new_crtc_state, i) {
1724 u8 old_active_planes, new_active_planes;
1725
1726 ret = icl_check_nv12_planes(state, crtc);
1727 if (ret)
1728 return ret;
1729
1730 /*
1731 * On some platforms the number of active planes affects
1732 * the planes' minimum cdclk calculation. Add such planes
1733 * to the state before we compute the minimum cdclk.
1734 */
1735 if (!active_planes_affects_min_cdclk(display))
1736 continue;
1737
1738 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1739 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1740
1741 if (hweight8(old_active_planes) == hweight8(new_active_planes))
1742 continue;
1743
1744 ret = intel_crtc_add_planes_to_state(state, crtc, plane_ids_mask: new_active_planes);
1745 if (ret)
1746 return ret;
1747 }
1748
1749 return 0;
1750}
1751