1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#include <linux/aperture.h>
31#include <linux/acpi.h>
32#include <linux/device.h>
33#include <linux/module.h>
34#include <linux/oom.h>
35#include <linux/pci.h>
36#include <linux/pm.h>
37#include <linux/pm_runtime.h>
38#include <linux/slab.h>
39#include <linux/string_helpers.h>
40#include <linux/vga_switcheroo.h>
41#include <linux/vt.h>
42
43#include <drm/drm_atomic_helper.h>
44#include <drm/drm_client.h>
45#include <drm/drm_client_event.h>
46#include <drm/drm_ioctl.h>
47#include <drm/drm_managed.h>
48#include <drm/drm_probe_helper.h>
49
50#include "display/i9xx_display_sr.h"
51#include "display/intel_bw.h"
52#include "display/intel_cdclk.h"
53#include "display/intel_crtc.h"
54#include "display/intel_display_device.h"
55#include "display/intel_display_driver.h"
56#include "display/intel_display_power.h"
57#include "display/intel_dmc.h"
58#include "display/intel_dp.h"
59#include "display/intel_dpt.h"
60#include "display/intel_encoder.h"
61#include "display/intel_fbdev.h"
62#include "display/intel_gmbus.h"
63#include "display/intel_hotplug.h"
64#include "display/intel_opregion.h"
65#include "display/intel_overlay.h"
66#include "display/intel_pch_refclk.h"
67#include "display/intel_pps.h"
68#include "display/intel_sbi.h"
69#include "display/intel_sprite_uapi.h"
70#include "display/skl_watermark.h"
71
72#include "gem/i915_gem_context.h"
73#include "gem/i915_gem_create.h"
74#include "gem/i915_gem_dmabuf.h"
75#include "gem/i915_gem_ioctls.h"
76#include "gem/i915_gem_mman.h"
77#include "gem/i915_gem_pm.h"
78#include "gt/intel_gt.h"
79#include "gt/intel_gt_pm.h"
80#include "gt/intel_gt_print.h"
81#include "gt/intel_rc6.h"
82
83#include "pxp/intel_pxp.h"
84#include "pxp/intel_pxp_debugfs.h"
85#include "pxp/intel_pxp_pm.h"
86
87#include "soc/intel_dram.h"
88#include "soc/intel_gmch.h"
89
90#include "i915_debugfs.h"
91#include "i915_driver.h"
92#include "i915_drm_client.h"
93#include "i915_drv.h"
94#include "i915_file_private.h"
95#include "i915_getparam.h"
96#include "i915_hwmon.h"
97#include "i915_ioc32.h"
98#include "i915_ioctl.h"
99#include "i915_irq.h"
100#include "i915_memcpy.h"
101#include "i915_perf.h"
102#include "i915_query.h"
103#include "i915_reg.h"
104#include "i915_switcheroo.h"
105#include "i915_sysfs.h"
106#include "i915_utils.h"
107#include "i915_vgpu.h"
108#include "intel_clock_gating.h"
109#include "intel_cpu_info.h"
110#include "intel_gvt.h"
111#include "intel_memory_region.h"
112#include "intel_pci_config.h"
113#include "intel_pcode.h"
114#include "intel_region_ttm.h"
115#include "vlv_iosf_sb.h"
116#include "vlv_suspend.h"
117
118static const struct drm_driver i915_drm_driver;
119
120static int i915_workqueues_init(struct drm_i915_private *dev_priv)
121{
122 /*
123 * The i915 workqueue is primarily used for batched retirement of
124 * requests (and thus managing bo) once the task has been completed
125 * by the GPU. i915_retire_requests() is called directly when we
126 * need high-priority retirement, such as waiting for an explicit
127 * bo.
128 *
129 * It is also used for periodic low-priority events, such as
130 * idle-timers and recording error state.
131 *
132 * All tasks on the workqueue are expected to acquire the dev mutex
133 * so there is no point in running more than one instance of the
134 * workqueue at any time. Use an ordered one.
135 */
136 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
137 if (dev_priv->wq == NULL)
138 goto out_err;
139
140 /*
141 * The unordered i915 workqueue should be used for all work
142 * scheduling that do not require running in order, which used
143 * to be scheduled on the system_wq before moving to a driver
144 * instance due deprecation of flush_scheduled_work().
145 */
146 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0);
147 if (dev_priv->unordered_wq == NULL)
148 goto out_free_wq;
149
150 return 0;
151
152out_free_wq:
153 destroy_workqueue(wq: dev_priv->wq);
154out_err:
155 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
156
157 return -ENOMEM;
158}
159
160static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
161{
162 destroy_workqueue(wq: dev_priv->unordered_wq);
163 destroy_workqueue(wq: dev_priv->wq);
164}
165
166/*
167 * We don't keep the workarounds for pre-production hardware, so we expect our
168 * driver to fail on these machines in one way or another. A little warning on
169 * dmesg may help both the user and the bug triagers.
170 *
171 * Our policy for removing pre-production workarounds is to keep the
172 * current gen workarounds as a guide to the bring-up of the next gen
173 * (workarounds have a habit of persisting!). Anything older than that
174 * should be removed along with the complications they introduce.
175 */
176static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
177{
178 bool pre = false;
179
180 pre |= IS_HASWELL_EARLY_SDV(dev_priv);
181 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
182 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
183 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
184 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
185 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
186 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
187 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
188 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;
189 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;
190 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
191
192 if (pre) {
193 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
194 "It may not be fully functional.\n");
195 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
196 }
197}
198
199static void sanitize_gpu(struct drm_i915_private *i915)
200{
201 if (!intel_gt_gpu_reset_clobbers_display(gt: to_gt(i915))) {
202 struct intel_gt *gt;
203 unsigned int i;
204
205 for_each_gt(gt, i915, i)
206 intel_gt_reset_all_engines(gt);
207 }
208}
209
210/**
211 * i915_driver_early_probe - setup state not requiring device access
212 * @dev_priv: device private
213 *
214 * Initialize everything that is a "SW-only" state, that is state not
215 * requiring accessing the device or exposing the driver via kernel internal
216 * or userspace interfaces. Example steps belonging here: lock initialization,
217 * system memory allocation, setting up device specific attributes and
218 * function hooks not requiring accessing the device.
219 */
220static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
221{
222 struct intel_display *display = dev_priv->display;
223 int ret = 0;
224
225 if (i915_inject_probe_failure(dev_priv))
226 return -ENODEV;
227
228 intel_device_info_runtime_init_early(dev_priv);
229
230 intel_step_init(i915: dev_priv);
231
232 intel_uncore_mmio_debug_init_early(i915: dev_priv);
233
234 spin_lock_init(&dev_priv->gpu_error.lock);
235
236 intel_sbi_init(display);
237 vlv_iosf_sb_init(i915: dev_priv);
238 mutex_init(&dev_priv->sb_lock);
239
240 i915_memcpy_init_early(i915: dev_priv);
241 intel_runtime_pm_init_early(rpm: &dev_priv->runtime_pm);
242
243 ret = i915_workqueues_init(dev_priv);
244 if (ret < 0)
245 return ret;
246
247 ret = vlv_suspend_init(i915: dev_priv);
248 if (ret < 0)
249 goto err_workqueues;
250
251 ret = intel_region_ttm_device_init(dev_priv);
252 if (ret)
253 goto err_ttm;
254
255 ret = intel_root_gt_init_early(i915: dev_priv);
256 if (ret < 0)
257 goto err_rootgt;
258
259 i915_gem_init_early(i915: dev_priv);
260
261 intel_irq_init(dev_priv);
262 intel_display_driver_early_probe(display);
263 intel_clock_gating_hooks_init(i915: dev_priv);
264
265 intel_detect_preproduction_hw(dev_priv);
266
267 return 0;
268
269err_rootgt:
270 intel_region_ttm_device_fini(dev_priv);
271err_ttm:
272 vlv_suspend_cleanup(i915: dev_priv);
273err_workqueues:
274 i915_workqueues_cleanup(dev_priv);
275 return ret;
276}
277
278/**
279 * i915_driver_late_release - cleanup the setup done in
280 * i915_driver_early_probe()
281 * @dev_priv: device private
282 */
283static void i915_driver_late_release(struct drm_i915_private *dev_priv)
284{
285 struct intel_display *display = dev_priv->display;
286
287 intel_irq_fini(dev_priv);
288 intel_power_domains_cleanup(display);
289 i915_gem_cleanup_early(i915: dev_priv);
290 intel_gt_driver_late_release_all(i915: dev_priv);
291 intel_region_ttm_device_fini(dev_priv);
292 vlv_suspend_cleanup(i915: dev_priv);
293 i915_workqueues_cleanup(dev_priv);
294
295 mutex_destroy(lock: &dev_priv->sb_lock);
296 vlv_iosf_sb_fini(i915: dev_priv);
297 intel_sbi_fini(display);
298
299 i915_params_free(params: &dev_priv->params);
300
301 intel_display_device_remove(display);
302}
303
304/**
305 * i915_driver_mmio_probe - setup device MMIO
306 * @dev_priv: device private
307 *
308 * Setup minimal device state necessary for MMIO accesses later in the
309 * initialization sequence. The setup here should avoid any other device-wide
310 * side effects or exposing the driver via kernel internal or user space
311 * interfaces.
312 */
313static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
314{
315 struct intel_display *display = dev_priv->display;
316 struct intel_gt *gt;
317 int ret, i;
318
319 if (i915_inject_probe_failure(dev_priv))
320 return -ENODEV;
321
322 ret = intel_gmch_bridge_setup(i915: dev_priv);
323 if (ret < 0)
324 return ret;
325
326 for_each_gt(gt, dev_priv, i) {
327 ret = intel_uncore_init_mmio(uncore: gt->uncore);
328 if (ret)
329 return ret;
330
331 ret = drmm_add_action_or_reset(&dev_priv->drm,
332 intel_uncore_fini_mmio,
333 gt->uncore);
334 if (ret)
335 return ret;
336 }
337
338 /* Try to make sure MCHBAR is enabled before poking at it */
339 intel_gmch_bar_setup(i915: dev_priv);
340 intel_device_info_runtime_init(dev_priv);
341 intel_display_device_info_runtime_init(display);
342
343 for_each_gt(gt, dev_priv, i) {
344 ret = intel_gt_init_mmio(gt);
345 if (ret)
346 goto err_uncore;
347 }
348
349 /* As early as possible, scrub existing GPU state before clobbering */
350 sanitize_gpu(i915: dev_priv);
351
352 return 0;
353
354err_uncore:
355 intel_gmch_bar_teardown(i915: dev_priv);
356
357 return ret;
358}
359
360/**
361 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
362 * @dev_priv: device private
363 */
364static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
365{
366 intel_gmch_bar_teardown(i915: dev_priv);
367}
368
369/**
370 * i915_set_dma_info - set all relevant PCI dma info as configured for the
371 * platform
372 * @i915: valid i915 instance
373 *
374 * Set the dma max segment size, device and coherent masks. The dma mask set
375 * needs to occur before i915_ggtt_probe_hw.
376 *
377 * A couple of platforms have special needs. Address them as well.
378 *
379 */
380static int i915_set_dma_info(struct drm_i915_private *i915)
381{
382 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
383 int ret;
384
385 GEM_BUG_ON(!mask_size);
386
387 /*
388 * We don't have a max segment size, so set it to the max so sg's
389 * debugging layer doesn't complain
390 */
391 dma_set_max_seg_size(dev: i915->drm.dev, UINT_MAX);
392
393 ret = dma_set_mask(dev: i915->drm.dev, DMA_BIT_MASK(mask_size));
394 if (ret)
395 goto mask_err;
396
397 /* overlay on gen2 is broken and can't address above 1G */
398 if (GRAPHICS_VER(i915) == 2)
399 mask_size = 30;
400
401 /*
402 * 965GM sometimes incorrectly writes to hardware status page (HWS)
403 * using 32bit addressing, overwriting memory if HWS is located
404 * above 4GB.
405 *
406 * The documentation also mentions an issue with undefined
407 * behaviour if any general state is accessed within a page above 4GB,
408 * which also needs to be handled carefully.
409 */
410 if (IS_I965G(i915) || IS_I965GM(i915))
411 mask_size = 32;
412
413 ret = dma_set_coherent_mask(dev: i915->drm.dev, DMA_BIT_MASK(mask_size));
414 if (ret)
415 goto mask_err;
416
417 return 0;
418
419mask_err:
420 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
421 return ret;
422}
423
424/* Wa_14022698537:dg2 */
425static void i915_enable_g8(struct drm_i915_private *i915)
426{
427 if (IS_DG2(i915)) {
428 if (IS_DG2_D(i915) && !intel_match_g8_cpu())
429 return;
430
431 snb_pcode_write_p(uncore: &i915->uncore, PCODE_POWER_SETUP,
432 POWER_SETUP_SUBCOMMAND_G8_ENABLE, p2: 0, val: 0);
433 }
434}
435
436static int i915_pcode_init(struct drm_i915_private *i915)
437{
438 struct intel_gt *gt;
439 int id, ret;
440
441 for_each_gt(gt, i915, id) {
442 ret = intel_pcode_init(uncore: gt->uncore);
443 if (ret) {
444 gt_err(gt, "intel_pcode_init failed %d\n", ret);
445 return ret;
446 }
447 }
448
449 i915_enable_g8(i915);
450 return 0;
451}
452
453/**
454 * i915_driver_hw_probe - setup state requiring device access
455 * @dev_priv: device private
456 *
457 * Setup state that requires accessing the device, but doesn't require
458 * exposing the driver via kernel internal or userspace interfaces.
459 */
460static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
461{
462 struct intel_display *display = dev_priv->display;
463 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
464 int ret;
465
466 if (i915_inject_probe_failure(dev_priv))
467 return -ENODEV;
468
469 if (HAS_PPGTT(dev_priv)) {
470 if (intel_vgpu_active(i915: dev_priv) &&
471 !intel_vgpu_has_full_ppgtt(i915: dev_priv)) {
472 drm_err(&dev_priv->drm,
473 "incompatible vGPU found, support for isolated ppGTT required\n");
474 return -ENXIO;
475 }
476 }
477
478 if (HAS_EXECLISTS(dev_priv)) {
479 /*
480 * Older GVT emulation depends upon intercepting CSB mmio,
481 * which we no longer use, preferring to use the HWSP cache
482 * instead.
483 */
484 if (intel_vgpu_active(i915: dev_priv) &&
485 !intel_vgpu_has_hwsp_emulation(i915: dev_priv)) {
486 drm_err(&dev_priv->drm,
487 "old vGPU host found, support for HWSP emulation required\n");
488 return -ENXIO;
489 }
490 }
491
492 /* needs to be done before ggtt probe */
493 intel_dram_edram_detect(i915: dev_priv);
494
495 ret = i915_set_dma_info(i915: dev_priv);
496 if (ret)
497 return ret;
498
499 ret = i915_perf_init(i915: dev_priv);
500 if (ret)
501 return ret;
502
503 ret = i915_ggtt_probe_hw(i915: dev_priv);
504 if (ret)
505 goto err_perf;
506
507 ret = aperture_remove_conflicting_pci_devices(pdev, name: dev_priv->drm.driver->name);
508 if (ret)
509 goto err_ggtt;
510
511 ret = i915_ggtt_init_hw(i915: dev_priv);
512 if (ret)
513 goto err_ggtt;
514
515 /*
516 * Make sure we probe lmem before we probe stolen-lmem. The BAR size
517 * might be different due to bar resizing.
518 */
519 ret = intel_gt_tiles_init(i915: dev_priv);
520 if (ret)
521 goto err_ggtt;
522
523 ret = intel_memory_regions_hw_probe(i915: dev_priv);
524 if (ret)
525 goto err_ggtt;
526
527 ret = i915_ggtt_enable_hw(i915: dev_priv);
528 if (ret) {
529 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
530 goto err_mem_regions;
531 }
532
533 pci_set_master(dev: pdev);
534
535 /* On the 945G/GM, the chipset reports the MSI capability on the
536 * integrated graphics even though the support isn't actually there
537 * according to the published specs. It doesn't appear to function
538 * correctly in testing on 945G.
539 * This may be a side effect of MSI having been made available for PEG
540 * and the registers being closely associated.
541 *
542 * According to chipset errata, on the 965GM, MSI interrupts may
543 * be lost or delayed, and was defeatured. MSI interrupts seem to
544 * get lost on g4x as well, and interrupt delivery seems to stay
545 * properly dead afterwards. So we'll just disable them for all
546 * pre-gen5 chipsets.
547 *
548 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
549 * interrupts even when in MSI mode. This results in spurious
550 * interrupt warnings if the legacy irq no. is shared with another
551 * device. The kernel then disables that interrupt source and so
552 * prevents the other device from working properly.
553 */
554 if (GRAPHICS_VER(dev_priv) >= 5) {
555 if (pci_enable_msi(dev: pdev) < 0)
556 drm_dbg(&dev_priv->drm, "can't enable MSI");
557 }
558
559 ret = intel_gvt_init(dev_priv);
560 if (ret)
561 goto err_msi;
562
563 intel_opregion_setup(display);
564
565 ret = i915_pcode_init(i915: dev_priv);
566 if (ret)
567 goto err_opregion;
568
569 /*
570 * Fill the dram structure to get the system dram info. This will be
571 * used for memory latency calculation.
572 */
573 ret = intel_dram_detect(i915: dev_priv);
574 if (ret)
575 goto err_opregion;
576
577 intel_bw_init_hw(display);
578
579 return 0;
580
581err_opregion:
582 intel_opregion_cleanup(display);
583err_msi:
584 if (pdev->msi_enabled)
585 pci_disable_msi(dev: pdev);
586err_mem_regions:
587 intel_memory_regions_driver_release(i915: dev_priv);
588err_ggtt:
589 i915_ggtt_driver_release(i915: dev_priv);
590 i915_gem_drain_freed_objects(i915: dev_priv);
591 i915_ggtt_driver_late_release(i915: dev_priv);
592err_perf:
593 i915_perf_fini(i915: dev_priv);
594 return ret;
595}
596
597/**
598 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
599 * @dev_priv: device private
600 */
601static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
602{
603 struct intel_display *display = dev_priv->display;
604 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
605
606 i915_perf_fini(i915: dev_priv);
607
608 intel_opregion_cleanup(display);
609
610 if (pdev->msi_enabled)
611 pci_disable_msi(dev: pdev);
612}
613
614/**
615 * i915_driver_register - register the driver with the rest of the system
616 * @dev_priv: device private
617 *
618 * Perform any steps necessary to make the driver available via kernel
619 * internal or userspace interfaces.
620 */
621static int i915_driver_register(struct drm_i915_private *dev_priv)
622{
623 struct intel_display *display = dev_priv->display;
624 struct intel_gt *gt;
625 unsigned int i;
626 int ret;
627
628 i915_gem_driver_register(i915: dev_priv);
629 i915_pmu_register(i915: dev_priv);
630
631 intel_vgpu_register(i915: dev_priv);
632
633 /* Reveal our presence to userspace */
634 ret = drm_dev_register(dev: &dev_priv->drm, flags: 0);
635 if (ret) {
636 i915_probe_error(dev_priv,
637 "Failed to register driver for userspace access!\n");
638 drm_dev_unregister(dev: &dev_priv->drm);
639 i915_pmu_unregister(i915: dev_priv);
640 i915_gem_driver_unregister(i915: dev_priv);
641 return ret;
642 }
643
644 i915_debugfs_register(dev_priv);
645 i915_setup_sysfs(i915: dev_priv);
646
647 /* Depends on sysfs having been initialized */
648 i915_perf_register(i915: dev_priv);
649
650 for_each_gt(gt, dev_priv, i)
651 intel_gt_driver_register(gt);
652
653 intel_pxp_debugfs_register(pxp: dev_priv->pxp);
654
655 i915_hwmon_register(i915: dev_priv);
656
657 intel_display_driver_register(display);
658
659 intel_power_domains_enable(display);
660 intel_runtime_pm_enable(rpm: &dev_priv->runtime_pm);
661
662 if (i915_switcheroo_register(i915: dev_priv))
663 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
664
665 return 0;
666}
667
668/**
669 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
670 * @dev_priv: device private
671 */
672static void i915_driver_unregister(struct drm_i915_private *dev_priv)
673{
674 struct intel_display *display = dev_priv->display;
675 struct intel_gt *gt;
676 unsigned int i;
677
678 i915_switcheroo_unregister(i915: dev_priv);
679
680 intel_runtime_pm_disable(rpm: &dev_priv->runtime_pm);
681 intel_power_domains_disable(display);
682
683 intel_display_driver_unregister(display);
684
685 intel_pxp_fini(i915: dev_priv);
686
687 for_each_gt(gt, dev_priv, i)
688 intel_gt_driver_unregister(gt);
689
690 i915_hwmon_unregister(i915: dev_priv);
691
692 i915_perf_unregister(i915: dev_priv);
693 i915_pmu_unregister(i915: dev_priv);
694
695 i915_teardown_sysfs(i915: dev_priv);
696 drm_dev_unplug(dev: &dev_priv->drm);
697
698 i915_gem_driver_unregister(i915: dev_priv);
699}
700
701void
702i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
703{
704 drm_printf(p, f: "iommu: %s\n",
705 str_enabled_disabled(v: i915_vtd_active(i915)));
706}
707
708static void i915_welcome_messages(struct drm_i915_private *dev_priv)
709{
710 if (drm_debug_enabled(DRM_UT_DRIVER)) {
711 struct drm_printer p = drm_dbg_printer(drm: &dev_priv->drm, category: DRM_UT_DRIVER,
712 prefix: "device info:");
713 struct intel_gt *gt;
714 unsigned int i;
715
716 drm_printf(p: &p, f: "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
717 INTEL_DEVID(dev_priv),
718 INTEL_REVID(dev_priv),
719 intel_platform_name(INTEL_INFO(dev_priv)->platform),
720 intel_subplatform(RUNTIME_INFO(dev_priv),
721 INTEL_INFO(dev_priv)->platform),
722 GRAPHICS_VER(dev_priv));
723
724 intel_device_info_print(INTEL_INFO(dev_priv),
725 RUNTIME_INFO(dev_priv), p: &p);
726 i915_print_iommu_status(i915: dev_priv, p: &p);
727 for_each_gt(gt, dev_priv, i)
728 intel_gt_info_print(info: &gt->info, p: &p);
729 }
730
731 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
732 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
733 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
734 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
735 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
736 drm_info(&dev_priv->drm,
737 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
738}
739
740static struct drm_i915_private *
741i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
742{
743 const struct intel_device_info *match_info =
744 (struct intel_device_info *)ent->driver_data;
745 struct drm_i915_private *i915;
746 struct intel_display *display;
747
748 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
749 struct drm_i915_private, drm);
750 if (IS_ERR(ptr: i915))
751 return i915;
752
753 pci_set_drvdata(pdev, data: &i915->drm);
754
755 /* Device parameters start as a copy of module parameters. */
756 i915_params_copy(dest: &i915->params, src: &i915_modparams);
757
758 /* Set up device info and initial runtime info. */
759 intel_device_info_driver_create(i915, device_id: pdev->device, match_info);
760
761 display = intel_display_device_probe(pdev);
762 if (IS_ERR(ptr: display))
763 return ERR_CAST(ptr: display);
764
765 i915->display = display;
766
767 return i915;
768}
769
770/**
771 * i915_driver_probe - setup chip and create an initial config
772 * @pdev: PCI device
773 * @ent: matching PCI ID entry
774 *
775 * The driver probe routine has to do several things:
776 * - drive output discovery via intel_display_driver_probe()
777 * - initialize the memory manager
778 * - allocate initial config memory
779 * - setup the DRM framebuffer with the allocated memory
780 */
781int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
782{
783 struct drm_i915_private *i915;
784 struct intel_display *display;
785 int ret;
786
787 ret = pci_enable_device(dev: pdev);
788 if (ret) {
789 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
790 return ret;
791 }
792
793 i915 = i915_driver_create(pdev, ent);
794 if (IS_ERR(ptr: i915)) {
795 pci_disable_device(dev: pdev);
796 return PTR_ERR(ptr: i915);
797 }
798
799 display = i915->display;
800
801 ret = i915_driver_early_probe(dev_priv: i915);
802 if (ret < 0)
803 goto out_pci_disable;
804
805 disable_rpm_wakeref_asserts(rpm: &i915->runtime_pm);
806
807 intel_vgpu_detect(i915);
808
809 ret = intel_gt_probe_all(i915);
810 if (ret < 0)
811 goto out_runtime_pm_put;
812
813 ret = i915_driver_mmio_probe(dev_priv: i915);
814 if (ret < 0)
815 goto out_runtime_pm_put;
816
817 ret = i915_driver_hw_probe(dev_priv: i915);
818 if (ret < 0)
819 goto out_cleanup_mmio;
820
821 ret = intel_display_driver_probe_noirq(display);
822 if (ret < 0)
823 goto out_cleanup_hw;
824
825 ret = intel_irq_install(dev_priv: i915);
826 if (ret)
827 goto out_cleanup_modeset;
828
829 ret = intel_display_driver_probe_nogem(display);
830 if (ret)
831 goto out_cleanup_irq;
832
833 ret = i915_gem_init(i915);
834 if (ret)
835 goto out_cleanup_modeset2;
836
837 ret = intel_pxp_init(i915);
838 if (ret && ret != -ENODEV)
839 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret);
840
841 ret = intel_display_driver_probe(display);
842 if (ret)
843 goto out_cleanup_gem;
844
845 ret = i915_driver_register(dev_priv: i915);
846 if (ret)
847 goto out_cleanup_gem;
848
849 enable_rpm_wakeref_asserts(rpm: &i915->runtime_pm);
850
851 i915_welcome_messages(dev_priv: i915);
852
853 i915->do_release = true;
854
855 return 0;
856
857out_cleanup_gem:
858 intel_pxp_fini(i915);
859 i915_gem_suspend(i915);
860 i915_gem_driver_remove(i915);
861 i915_gem_driver_release(i915);
862out_cleanup_modeset2:
863 /* FIXME clean up the error path */
864 intel_display_driver_remove(display);
865 intel_irq_uninstall(dev_priv: i915);
866 intel_display_driver_remove_noirq(display);
867 goto out_cleanup_modeset;
868out_cleanup_irq:
869 intel_irq_uninstall(dev_priv: i915);
870out_cleanup_modeset:
871 intel_display_driver_remove_nogem(display);
872out_cleanup_hw:
873 i915_driver_hw_remove(dev_priv: i915);
874 intel_memory_regions_driver_release(i915);
875 i915_ggtt_driver_release(i915);
876 i915_gem_drain_freed_objects(i915);
877 i915_ggtt_driver_late_release(i915);
878out_cleanup_mmio:
879 i915_driver_mmio_release(dev_priv: i915);
880out_runtime_pm_put:
881 enable_rpm_wakeref_asserts(rpm: &i915->runtime_pm);
882 i915_driver_late_release(dev_priv: i915);
883out_pci_disable:
884 pci_disable_device(dev: pdev);
885 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
886 return ret;
887}
888
889void i915_driver_remove(struct drm_i915_private *i915)
890{
891 struct intel_display *display = i915->display;
892 intel_wakeref_t wakeref;
893
894 wakeref = intel_runtime_pm_get(rpm: &i915->runtime_pm);
895
896 i915_driver_unregister(dev_priv: i915);
897
898 /* Flush any external code that still may be under the RCU lock */
899 synchronize_rcu();
900
901 i915_gem_suspend(i915);
902
903 intel_gvt_driver_remove(dev_priv: i915);
904
905 intel_display_driver_remove(display);
906
907 intel_irq_uninstall(dev_priv: i915);
908
909 intel_display_driver_remove_noirq(display);
910
911 i915_reset_error_state(i915);
912 i915_gem_driver_remove(i915);
913
914 intel_display_driver_remove_nogem(display);
915
916 i915_driver_hw_remove(dev_priv: i915);
917
918 intel_runtime_pm_put(rpm: &i915->runtime_pm, wref: wakeref);
919}
920
921static void i915_driver_release(struct drm_device *dev)
922{
923 struct drm_i915_private *dev_priv = to_i915(dev);
924 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
925 intel_wakeref_t wakeref;
926
927 if (!dev_priv->do_release)
928 return;
929
930 wakeref = intel_runtime_pm_get(rpm);
931
932 i915_gem_driver_release(i915: dev_priv);
933
934 intel_memory_regions_driver_release(i915: dev_priv);
935 i915_ggtt_driver_release(i915: dev_priv);
936 i915_gem_drain_freed_objects(i915: dev_priv);
937 i915_ggtt_driver_late_release(i915: dev_priv);
938
939 i915_driver_mmio_release(dev_priv);
940
941 intel_runtime_pm_put(rpm, wref: wakeref);
942
943 intel_runtime_pm_driver_release(rpm);
944
945 i915_driver_late_release(dev_priv);
946}
947
948static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
949{
950 struct drm_i915_private *i915 = to_i915(dev);
951 int ret;
952
953 ret = i915_gem_open(i915, file);
954 if (ret)
955 return ret;
956
957 return 0;
958}
959
960static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
961{
962 struct drm_i915_file_private *file_priv = file->driver_priv;
963
964 i915_gem_context_close(file);
965 i915_drm_client_put(client: file_priv->client);
966
967 kfree_rcu(file_priv, rcu);
968
969 /* Catch up with all the deferred frees from "this" client */
970 i915_gem_flush_free_objects(i915: to_i915(dev));
971}
972
973void i915_driver_shutdown(struct drm_i915_private *i915)
974{
975 struct intel_display *display = i915->display;
976
977 disable_rpm_wakeref_asserts(rpm: &i915->runtime_pm);
978 intel_runtime_pm_disable(rpm: &i915->runtime_pm);
979 intel_power_domains_disable(display);
980
981 drm_client_dev_suspend(dev: &i915->drm, holds_console_lock: false);
982 if (intel_display_device_present(display)) {
983 drm_kms_helper_poll_disable(dev: &i915->drm);
984 intel_display_driver_disable_user_access(display);
985
986 drm_atomic_helper_shutdown(dev: &i915->drm);
987 }
988
989 intel_dp_mst_suspend(display);
990
991 intel_irq_suspend(i915);
992 intel_hpd_cancel_work(display);
993
994 if (intel_display_device_present(display))
995 intel_display_driver_suspend_access(display);
996
997 intel_encoder_suspend_all(display);
998 intel_encoder_shutdown_all(display);
999
1000 intel_dmc_suspend(display);
1001
1002 i915_gem_suspend(i915);
1003
1004 /*
1005 * The only requirement is to reboot with display DC states disabled,
1006 * for now leaving all display power wells in the INIT power domain
1007 * enabled.
1008 *
1009 * TODO:
1010 * - unify the pci_driver::shutdown sequence here with the
1011 * pci_driver.driver.pm.poweroff,poweroff_late sequence.
1012 * - unify the driver remove and system/runtime suspend sequences with
1013 * the above unified shutdown/poweroff sequence.
1014 */
1015 intel_power_domains_driver_remove(display);
1016 enable_rpm_wakeref_asserts(rpm: &i915->runtime_pm);
1017
1018 intel_runtime_pm_driver_last_release(rpm: &i915->runtime_pm);
1019}
1020
1021static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1022{
1023#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1024 if (acpi_target_system_state() < ACPI_STATE_S3)
1025 return true;
1026#endif
1027 return false;
1028}
1029
1030static void i915_drm_complete(struct drm_device *dev)
1031{
1032 struct drm_i915_private *i915 = to_i915(dev);
1033
1034 intel_pxp_resume_complete(pxp: i915->pxp);
1035}
1036
1037static int i915_drm_prepare(struct drm_device *dev)
1038{
1039 struct drm_i915_private *i915 = to_i915(dev);
1040
1041 intel_pxp_suspend_prepare(pxp: i915->pxp);
1042
1043 /*
1044 * NB intel_display_driver_suspend() may issue new requests after we've
1045 * ostensibly marked the GPU as ready-to-sleep here. We need to
1046 * split out that work and pull it forward so that after point,
1047 * the GPU is not woken again.
1048 */
1049 return i915_gem_backup_suspend(i915);
1050}
1051
1052static int i915_drm_suspend(struct drm_device *dev)
1053{
1054 struct drm_i915_private *dev_priv = to_i915(dev);
1055 struct intel_display *display = dev_priv->display;
1056 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1057 pci_power_t opregion_target_state;
1058
1059 disable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm);
1060
1061 /* We do a lot of poking in a lot of registers, make sure they work
1062 * properly. */
1063 intel_power_domains_disable(display);
1064 drm_client_dev_suspend(dev, holds_console_lock: false);
1065 if (intel_display_device_present(display)) {
1066 drm_kms_helper_poll_disable(dev);
1067 intel_display_driver_disable_user_access(display);
1068 }
1069
1070 pci_save_state(dev: pdev);
1071
1072 intel_display_driver_suspend(display);
1073
1074 intel_irq_suspend(i915: dev_priv);
1075 intel_hpd_cancel_work(display);
1076
1077 if (intel_display_device_present(display))
1078 intel_display_driver_suspend_access(display);
1079
1080 intel_encoder_suspend_all(display);
1081
1082 /* Must be called before GGTT is suspended. */
1083 intel_dpt_suspend(display);
1084 i915_ggtt_suspend(gtt: to_gt(i915: dev_priv)->ggtt);
1085
1086 i9xx_display_sr_save(display);
1087
1088 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1089 intel_opregion_suspend(display, state: opregion_target_state);
1090
1091 dev_priv->suspend_count++;
1092
1093 intel_dmc_suspend(display);
1094
1095 enable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm);
1096
1097 i915_gem_drain_freed_objects(i915: dev_priv);
1098
1099 return 0;
1100}
1101
1102static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1103{
1104 struct drm_i915_private *dev_priv = to_i915(dev);
1105 struct intel_display *display = dev_priv->display;
1106 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1107 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1108 struct intel_gt *gt;
1109 int ret, i;
1110 bool s2idle = !hibernation && suspend_to_idle(dev_priv);
1111
1112 disable_rpm_wakeref_asserts(rpm);
1113
1114 intel_pxp_suspend(pxp: dev_priv->pxp);
1115
1116 i915_gem_suspend_late(i915: dev_priv);
1117
1118 for_each_gt(gt, dev_priv, i)
1119 intel_uncore_suspend(uncore: gt->uncore);
1120
1121 intel_display_power_suspend_late(display, s2idle);
1122
1123 ret = vlv_suspend_complete(i915: dev_priv);
1124 if (ret) {
1125 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1126 intel_display_power_resume_early(display);
1127
1128 goto out;
1129 }
1130
1131 pci_disable_device(dev: pdev);
1132 /*
1133 * During hibernation on some platforms the BIOS may try to access
1134 * the device even though it's already in D3 and hang the machine. So
1135 * leave the device in D0 on those platforms and hope the BIOS will
1136 * power down the device properly. The issue was seen on multiple old
1137 * GENs with different BIOS vendors, so having an explicit blacklist
1138 * is impractical; apply the workaround on everything pre GEN6. The
1139 * platforms where the issue was seen:
1140 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1141 * Fujitsu FSC S7110
1142 * Acer Aspire 1830T
1143 */
1144 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1145 pci_set_power_state(dev: pdev, PCI_D3hot);
1146
1147out:
1148 enable_rpm_wakeref_asserts(rpm);
1149 if (!dev_priv->uncore.user_forcewake_count)
1150 intel_runtime_pm_driver_release(rpm);
1151
1152 return ret;
1153}
1154
1155int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1156 pm_message_t state)
1157{
1158 int error;
1159
1160 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1161 state.event != PM_EVENT_FREEZE))
1162 return -EINVAL;
1163
1164 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1165 return 0;
1166
1167 error = i915_drm_suspend(dev: &i915->drm);
1168 if (error)
1169 return error;
1170
1171 return i915_drm_suspend_late(dev: &i915->drm, hibernation: false);
1172}
1173
1174static int i915_drm_resume(struct drm_device *dev)
1175{
1176 struct drm_i915_private *dev_priv = to_i915(dev);
1177 struct intel_display *display = dev_priv->display;
1178 struct intel_gt *gt;
1179 int ret, i;
1180
1181 disable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm);
1182
1183 ret = i915_pcode_init(i915: dev_priv);
1184 if (ret)
1185 return ret;
1186
1187 sanitize_gpu(i915: dev_priv);
1188
1189 ret = i915_ggtt_enable_hw(i915: dev_priv);
1190 if (ret)
1191 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1192
1193 i915_ggtt_resume(ggtt: to_gt(i915: dev_priv)->ggtt);
1194
1195 for_each_gt(gt, dev_priv, i)
1196 if (GRAPHICS_VER(gt->i915) >= 8)
1197 setup_private_pat(gt);
1198
1199 /* Must be called after GGTT is resumed. */
1200 intel_dpt_resume(display);
1201
1202 intel_dmc_resume(display);
1203
1204 i9xx_display_sr_restore(display);
1205
1206 intel_gmbus_reset(display);
1207
1208 intel_pps_unlock_regs_wa(display);
1209
1210 intel_init_pch_refclk(display);
1211
1212 /*
1213 * Interrupts have to be enabled before any batches are run. If not the
1214 * GPU will hang. i915_gem_init_hw() will initiate batches to
1215 * update/restore the context.
1216 *
1217 * drm_mode_config_reset() needs AUX interrupts.
1218 *
1219 * Modeset enabling in intel_display_driver_init_hw() also needs working
1220 * interrupts.
1221 */
1222 intel_irq_resume(i915: dev_priv);
1223
1224 if (intel_display_device_present(display))
1225 drm_mode_config_reset(dev);
1226
1227 i915_gem_resume(i915: dev_priv);
1228
1229 intel_display_driver_init_hw(display);
1230
1231 intel_clock_gating_init(i915: dev_priv);
1232
1233 if (intel_display_device_present(display))
1234 intel_display_driver_resume_access(display);
1235
1236 intel_hpd_init(display);
1237
1238 intel_display_driver_resume(display);
1239
1240 if (intel_display_device_present(display)) {
1241 intel_display_driver_enable_user_access(display);
1242 drm_kms_helper_poll_enable(dev);
1243 }
1244 intel_hpd_poll_disable(display);
1245
1246 intel_opregion_resume(display);
1247
1248 drm_client_dev_resume(dev, holds_console_lock: false);
1249
1250 intel_power_domains_enable(display);
1251
1252 intel_gvt_resume(dev_priv);
1253
1254 enable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm);
1255
1256 return 0;
1257}
1258
1259static int i915_drm_resume_early(struct drm_device *dev)
1260{
1261 struct drm_i915_private *dev_priv = to_i915(dev);
1262 struct intel_display *display = dev_priv->display;
1263 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1264 struct intel_gt *gt;
1265 int ret, i;
1266
1267 /*
1268 * We have a resume ordering issue with the snd-hda driver also
1269 * requiring our device to be power up. Due to the lack of a
1270 * parent/child relationship we currently solve this with an early
1271 * resume hook.
1272 *
1273 * FIXME: This should be solved with a special hdmi sink device or
1274 * similar so that power domains can be employed.
1275 */
1276
1277 /*
1278 * Note that we need to set the power state explicitly, since we
1279 * powered off the device during freeze and the PCI core won't power
1280 * it back up for us during thaw. Powering off the device during
1281 * freeze is not a hard requirement though, and during the
1282 * suspend/resume phases the PCI core makes sure we get here with the
1283 * device powered on. So in case we change our freeze logic and keep
1284 * the device powered we can also remove the following set power state
1285 * call.
1286 */
1287 ret = pci_set_power_state(dev: pdev, PCI_D0);
1288 if (ret) {
1289 drm_err(&dev_priv->drm,
1290 "failed to set PCI D0 power state (%d)\n", ret);
1291 return ret;
1292 }
1293
1294 /*
1295 * Note that pci_enable_device() first enables any parent bridge
1296 * device and only then sets the power state for this device. The
1297 * bridge enabling is a nop though, since bridge devices are resumed
1298 * first. The order of enabling power and enabling the device is
1299 * imposed by the PCI core as described above, so here we preserve the
1300 * same order for the freeze/thaw phases.
1301 *
1302 * TODO: eventually we should remove pci_disable_device() /
1303 * pci_enable_enable_device() from suspend/resume. Due to how they
1304 * depend on the device enable refcount we can't anyway depend on them
1305 * disabling/enabling the device.
1306 */
1307 if (pci_enable_device(dev: pdev))
1308 return -EIO;
1309
1310 pci_set_master(dev: pdev);
1311
1312 disable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm);
1313
1314 ret = vlv_resume_prepare(i915: dev_priv, rpm_resume: false);
1315 if (ret)
1316 drm_err(&dev_priv->drm,
1317 "Resume prepare failed: %d, continuing anyway\n", ret);
1318
1319 for_each_gt(gt, dev_priv, i)
1320 intel_gt_resume_early(gt);
1321
1322 intel_display_power_resume_early(display);
1323
1324 enable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm);
1325
1326 return ret;
1327}
1328
1329int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1330{
1331 int ret;
1332
1333 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1334 return 0;
1335
1336 ret = i915_drm_resume_early(dev: &i915->drm);
1337 if (ret)
1338 return ret;
1339
1340 return i915_drm_resume(dev: &i915->drm);
1341}
1342
1343static int i915_pm_prepare(struct device *kdev)
1344{
1345 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1346
1347 if (!i915) {
1348 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1349 return -ENODEV;
1350 }
1351
1352 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1353 return 0;
1354
1355 return i915_drm_prepare(dev: &i915->drm);
1356}
1357
1358static int i915_pm_suspend(struct device *kdev)
1359{
1360 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1361
1362 if (!i915) {
1363 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1364 return -ENODEV;
1365 }
1366
1367 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1368 return 0;
1369
1370 return i915_drm_suspend(dev: &i915->drm);
1371}
1372
1373static int i915_pm_suspend_late(struct device *kdev)
1374{
1375 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1376
1377 /*
1378 * We have a suspend ordering issue with the snd-hda driver also
1379 * requiring our device to be power up. Due to the lack of a
1380 * parent/child relationship we currently solve this with an late
1381 * suspend hook.
1382 *
1383 * FIXME: This should be solved with a special hdmi sink device or
1384 * similar so that power domains can be employed.
1385 */
1386 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1387 return 0;
1388
1389 return i915_drm_suspend_late(dev: &i915->drm, hibernation: false);
1390}
1391
1392static int i915_pm_poweroff_late(struct device *kdev)
1393{
1394 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1395
1396 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1397 return 0;
1398
1399 return i915_drm_suspend_late(dev: &i915->drm, hibernation: true);
1400}
1401
1402static int i915_pm_resume_early(struct device *kdev)
1403{
1404 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1405
1406 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1407 return 0;
1408
1409 return i915_drm_resume_early(dev: &i915->drm);
1410}
1411
1412static int i915_pm_resume(struct device *kdev)
1413{
1414 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1415
1416 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1417 return 0;
1418
1419 return i915_drm_resume(dev: &i915->drm);
1420}
1421
1422static void i915_pm_complete(struct device *kdev)
1423{
1424 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1425
1426 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1427 return;
1428
1429 i915_drm_complete(dev: &i915->drm);
1430}
1431
1432/* freeze: before creating the hibernation_image */
1433static int i915_pm_freeze(struct device *kdev)
1434{
1435 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1436 int ret;
1437
1438 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1439 ret = i915_drm_suspend(dev: &i915->drm);
1440 if (ret)
1441 return ret;
1442 }
1443
1444 ret = i915_gem_freeze(i915);
1445 if (ret)
1446 return ret;
1447
1448 return 0;
1449}
1450
1451static int i915_pm_freeze_late(struct device *kdev)
1452{
1453 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1454 int ret;
1455
1456 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1457 ret = i915_drm_suspend_late(dev: &i915->drm, hibernation: true);
1458 if (ret)
1459 return ret;
1460 }
1461
1462 ret = i915_gem_freeze_late(i915);
1463 if (ret)
1464 return ret;
1465
1466 return 0;
1467}
1468
1469/* thaw: called after creating the hibernation image, but before turning off. */
1470static int i915_pm_thaw_early(struct device *kdev)
1471{
1472 return i915_pm_resume_early(kdev);
1473}
1474
1475static int i915_pm_thaw(struct device *kdev)
1476{
1477 return i915_pm_resume(kdev);
1478}
1479
1480/* restore: called after loading the hibernation image. */
1481static int i915_pm_restore_early(struct device *kdev)
1482{
1483 return i915_pm_resume_early(kdev);
1484}
1485
1486static int i915_pm_restore(struct device *kdev)
1487{
1488 return i915_pm_resume(kdev);
1489}
1490
1491static int intel_runtime_suspend(struct device *kdev)
1492{
1493 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1494 struct intel_display *display = dev_priv->display;
1495 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1496 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1497 struct pci_dev *root_pdev;
1498 struct intel_gt *gt;
1499 int ret, i;
1500
1501 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1502 return -ENODEV;
1503
1504 drm_dbg(&dev_priv->drm, "Suspending device\n");
1505
1506 disable_rpm_wakeref_asserts(rpm);
1507
1508 /*
1509 * We are safe here against re-faults, since the fault handler takes
1510 * an RPM reference.
1511 */
1512 i915_gem_runtime_suspend(i915: dev_priv);
1513
1514 intel_pxp_runtime_suspend(pxp: dev_priv->pxp);
1515
1516 for_each_gt(gt, dev_priv, i)
1517 intel_gt_runtime_suspend(gt);
1518
1519 intel_irq_suspend(i915: dev_priv);
1520
1521 for_each_gt(gt, dev_priv, i)
1522 intel_uncore_suspend(uncore: gt->uncore);
1523
1524 intel_display_power_suspend(display);
1525
1526 ret = vlv_suspend_complete(i915: dev_priv);
1527 if (ret) {
1528 drm_err(&dev_priv->drm,
1529 "Runtime suspend failed, disabling it (%d)\n", ret);
1530 intel_uncore_runtime_resume(uncore: &dev_priv->uncore);
1531
1532 intel_irq_resume(i915: dev_priv);
1533
1534 for_each_gt(gt, dev_priv, i)
1535 intel_gt_runtime_resume(gt);
1536
1537 enable_rpm_wakeref_asserts(rpm);
1538
1539 return ret;
1540 }
1541
1542 enable_rpm_wakeref_asserts(rpm);
1543 intel_runtime_pm_driver_release(rpm);
1544
1545 if (intel_uncore_arm_unclaimed_mmio_detection(uncore: &dev_priv->uncore))
1546 drm_err(&dev_priv->drm,
1547 "Unclaimed access detected prior to suspending\n");
1548
1549 /*
1550 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1551 * This should be totally removed when we handle the pci states properly
1552 * on runtime PM.
1553 */
1554 root_pdev = pcie_find_root_port(dev: pdev);
1555 if (root_pdev)
1556 pci_d3cold_disable(dev: root_pdev);
1557
1558 /*
1559 * FIXME: We really should find a document that references the arguments
1560 * used below!
1561 */
1562 if (IS_BROADWELL(dev_priv)) {
1563 /*
1564 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1565 * being detected, and the call we do at intel_runtime_resume()
1566 * won't be able to restore them. Since PCI_D3hot matches the
1567 * actual specification and appears to be working, use it.
1568 */
1569 intel_opregion_notify_adapter(display, PCI_D3hot);
1570 } else {
1571 /*
1572 * current versions of firmware which depend on this opregion
1573 * notification have repurposed the D1 definition to mean
1574 * "runtime suspended" vs. what you would normally expect (D3)
1575 * to distinguish it from notifications that might be sent via
1576 * the suspend path.
1577 */
1578 intel_opregion_notify_adapter(display, PCI_D1);
1579 }
1580
1581 assert_forcewakes_inactive(uncore: &dev_priv->uncore);
1582
1583 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1584 intel_hpd_poll_enable(display);
1585
1586 drm_dbg(&dev_priv->drm, "Device suspended\n");
1587 return 0;
1588}
1589
1590static int intel_runtime_resume(struct device *kdev)
1591{
1592 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1593 struct intel_display *display = dev_priv->display;
1594 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1595 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1596 struct pci_dev *root_pdev;
1597 struct intel_gt *gt;
1598 int ret, i;
1599
1600 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1601 return -ENODEV;
1602
1603 drm_dbg(&dev_priv->drm, "Resuming device\n");
1604
1605 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1606 disable_rpm_wakeref_asserts(rpm);
1607
1608 intel_opregion_notify_adapter(display, PCI_D0);
1609
1610 root_pdev = pcie_find_root_port(dev: pdev);
1611 if (root_pdev)
1612 pci_d3cold_enable(dev: root_pdev);
1613
1614 if (intel_uncore_unclaimed_mmio(uncore: &dev_priv->uncore))
1615 drm_dbg(&dev_priv->drm,
1616 "Unclaimed access during suspend, bios?\n");
1617
1618 intel_display_power_resume(display);
1619
1620 ret = vlv_resume_prepare(i915: dev_priv, rpm_resume: true);
1621
1622 for_each_gt(gt, dev_priv, i)
1623 intel_uncore_runtime_resume(uncore: gt->uncore);
1624
1625 intel_irq_resume(i915: dev_priv);
1626
1627 /*
1628 * No point of rolling back things in case of an error, as the best
1629 * we can do is to hope that things will still work (and disable RPM).
1630 */
1631 for_each_gt(gt, dev_priv, i)
1632 intel_gt_runtime_resume(gt);
1633
1634 intel_pxp_runtime_resume(pxp: dev_priv->pxp);
1635
1636 /*
1637 * On VLV/CHV display interrupts are part of the display
1638 * power well, so hpd is reinitialized from there. For
1639 * everyone else do it here.
1640 */
1641 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1642 intel_hpd_init(display);
1643 intel_hpd_poll_disable(display);
1644 }
1645
1646 skl_watermark_ipc_update(display);
1647
1648 enable_rpm_wakeref_asserts(rpm);
1649
1650 if (ret)
1651 drm_err(&dev_priv->drm,
1652 "Runtime resume failed, disabling it (%d)\n", ret);
1653 else
1654 drm_dbg(&dev_priv->drm, "Device resumed\n");
1655
1656 return ret;
1657}
1658
1659const struct dev_pm_ops i915_pm_ops = {
1660 /*
1661 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1662 * PMSG_RESUME]
1663 */
1664 .prepare = i915_pm_prepare,
1665 .suspend = i915_pm_suspend,
1666 .suspend_late = i915_pm_suspend_late,
1667 .resume_early = i915_pm_resume_early,
1668 .resume = i915_pm_resume,
1669 .complete = i915_pm_complete,
1670
1671 /*
1672 * S4 event handlers
1673 * @freeze, @freeze_late : called (1) before creating the
1674 * hibernation image [PMSG_FREEZE] and
1675 * (2) after rebooting, before restoring
1676 * the image [PMSG_QUIESCE]
1677 * @thaw, @thaw_early : called (1) after creating the hibernation
1678 * image, before writing it [PMSG_THAW]
1679 * and (2) after failing to create or
1680 * restore the image [PMSG_RECOVER]
1681 * @poweroff, @poweroff_late: called after writing the hibernation
1682 * image, before rebooting [PMSG_HIBERNATE]
1683 * @restore, @restore_early : called after rebooting and restoring the
1684 * hibernation image [PMSG_RESTORE]
1685 */
1686 .freeze = i915_pm_freeze,
1687 .freeze_late = i915_pm_freeze_late,
1688 .thaw_early = i915_pm_thaw_early,
1689 .thaw = i915_pm_thaw,
1690 .poweroff = i915_pm_suspend,
1691 .poweroff_late = i915_pm_poweroff_late,
1692 .restore_early = i915_pm_restore_early,
1693 .restore = i915_pm_restore,
1694
1695 /* S0ix (via runtime suspend) event handlers */
1696 .runtime_suspend = intel_runtime_suspend,
1697 .runtime_resume = intel_runtime_resume,
1698};
1699
1700static const struct file_operations i915_driver_fops = {
1701 .owner = THIS_MODULE,
1702 .open = drm_open,
1703 .release = drm_release_noglobal,
1704 .unlocked_ioctl = drm_ioctl,
1705 .mmap = i915_gem_mmap,
1706 .poll = drm_poll,
1707 .read = drm_read,
1708 .compat_ioctl = i915_ioc32_compat_ioctl,
1709 .llseek = noop_llseek,
1710#ifdef CONFIG_PROC_FS
1711 .show_fdinfo = drm_show_fdinfo,
1712#endif
1713 .fop_flags = FOP_UNSIGNED_OFFSET,
1714};
1715
1716static int
1717i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1718 struct drm_file *file)
1719{
1720 return -ENODEV;
1721}
1722
1723static const struct drm_ioctl_desc i915_ioctls[] = {
1724 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1725 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1726 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1727 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1728 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1729 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1730 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1731 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1732 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1733 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1734 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1735 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1736 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1737 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1738 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1739 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1740 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1741 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1742 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1743 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1744 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1745 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1746 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1747 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1748 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1749 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1750 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1751 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1752 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1753 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1754 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1755 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1756 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1757 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1758 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1759 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1760 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1761 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1762 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1763 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_crtc_get_pipe_from_crtc_id_ioctl, 0),
1764 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1765 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1766 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1767 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1768 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1769 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1770 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1771 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1772 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1773 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1774 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1775 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1776 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1777 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1778 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1779 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1780 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1781 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1782 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1783};
1784
1785/*
1786 * Interface history:
1787 *
1788 * 1.1: Original.
1789 * 1.2: Add Power Management
1790 * 1.3: Add vblank support
1791 * 1.4: Fix cmdbuffer path, add heap destroy
1792 * 1.5: Add vblank pipe configuration
1793 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1794 * - Support vertical blank on secondary display pipe
1795 */
1796#define DRIVER_MAJOR 1
1797#define DRIVER_MINOR 6
1798#define DRIVER_PATCHLEVEL 0
1799
1800static const struct drm_driver i915_drm_driver = {
1801 /* Don't use MTRRs here; the Xserver or userspace app should
1802 * deal with them for Intel hardware.
1803 */
1804 .driver_features =
1805 DRIVER_GEM |
1806 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1807 DRIVER_SYNCOBJ_TIMELINE,
1808 .release = i915_driver_release,
1809 .open = i915_driver_open,
1810 .postclose = i915_driver_postclose,
1811 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo),
1812
1813 .gem_prime_import = i915_gem_prime_import,
1814
1815 .dumb_create = i915_gem_dumb_create,
1816 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1817
1818 INTEL_FBDEV_DRIVER_OPS,
1819
1820 .ioctls = i915_ioctls,
1821 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1822 .fops = &i915_driver_fops,
1823 .name = DRIVER_NAME,
1824 .desc = DRIVER_DESC,
1825 .major = DRIVER_MAJOR,
1826 .minor = DRIVER_MINOR,
1827 .patchlevel = DRIVER_PATCHLEVEL,
1828};
1829