1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/export.h>
29#include <linux/i2c.h>
30#include <linux/iopoll.h>
31#include <linux/log2.h>
32#include <linux/math.h>
33#include <linux/notifier.h>
34#include <linux/seq_buf.h>
35#include <linux/slab.h>
36#include <linux/sort.h>
37#include <linux/string_helpers.h>
38#include <linux/timekeeping.h>
39#include <linux/types.h>
40#include <asm/byteorder.h>
41
42#include <drm/display/drm_dp_helper.h>
43#include <drm/display/drm_dp_tunnel.h>
44#include <drm/display/drm_dsc_helper.h>
45#include <drm/display/drm_hdmi_helper.h>
46#include <drm/drm_atomic_helper.h>
47#include <drm/drm_crtc.h>
48#include <drm/drm_edid.h>
49#include <drm/drm_fixed.h>
50#include <drm/drm_print.h>
51#include <drm/drm_probe_helper.h>
52
53#include "g4x_dp.h"
54#include "i915_utils.h"
55#include "intel_alpm.h"
56#include "intel_atomic.h"
57#include "intel_audio.h"
58#include "intel_backlight.h"
59#include "intel_combo_phy_regs.h"
60#include "intel_connector.h"
61#include "intel_crtc.h"
62#include "intel_crtc_state_dump.h"
63#include "intel_cx0_phy.h"
64#include "intel_ddi.h"
65#include "intel_de.h"
66#include "intel_display_driver.h"
67#include "intel_display_regs.h"
68#include "intel_display_rpm.h"
69#include "intel_display_types.h"
70#include "intel_dp.h"
71#include "intel_dp_aux.h"
72#include "intel_dp_hdcp.h"
73#include "intel_dp_link_training.h"
74#include "intel_dp_mst.h"
75#include "intel_dp_test.h"
76#include "intel_dp_tunnel.h"
77#include "intel_dpio_phy.h"
78#include "intel_dpll.h"
79#include "intel_drrs.h"
80#include "intel_encoder.h"
81#include "intel_fifo_underrun.h"
82#include "intel_hdcp.h"
83#include "intel_hdmi.h"
84#include "intel_hotplug.h"
85#include "intel_hotplug_irq.h"
86#include "intel_lspcon.h"
87#include "intel_lvds.h"
88#include "intel_modeset_lock.h"
89#include "intel_panel.h"
90#include "intel_pch_display.h"
91#include "intel_pfit.h"
92#include "intel_pps.h"
93#include "intel_psr.h"
94#include "intel_quirks.h"
95#include "intel_tc.h"
96#include "intel_vdsc.h"
97#include "intel_vrr.h"
98
99/* DP DSC throughput values used for slice count calculations KPixels/s */
100#define DP_DSC_PEAK_PIXEL_RATE 2720000
101#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
102#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
103
104/* Max DSC line buffer depth supported by HW. */
105#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13
106
107/* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
108#define DP_DSC_FEC_OVERHEAD_FACTOR 1028530
109
110/* Constants for DP DSC configurations */
111static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
112
113/*
114 * With Single pipe configuration, HW is capable of supporting maximum of:
115 * 2 slices per line for ICL, BMG
116 * 4 slices per line for other platforms.
117 * For now consider a max of 2 slices per line, which works for all platforms.
118 * With this we can have max of 4 DSC Slices per pipe.
119 *
120 * For higher resolutions where 12 slice support is required with
121 * ultrajoiner, only then each pipe can support 3 slices.
122 *
123 * #TODO Split this better to use 4 slices/dsc engine where supported.
124 */
125static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4};
126
127/**
128 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
129 * @intel_dp: DP struct
130 *
131 * If a CPU or PCH DP output is attached to an eDP panel, this function
132 * will return true, and false otherwise.
133 *
134 * This function is not safe to use prior to encoder type being set.
135 */
136bool intel_dp_is_edp(struct intel_dp *intel_dp)
137{
138 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
139
140 return dig_port->base.type == INTEL_OUTPUT_EDP;
141}
142
143static void intel_dp_unset_edid(struct intel_dp *intel_dp);
144
145/* Is link rate UHBR and thus 128b/132b? */
146bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
147{
148 return drm_dp_is_uhbr_rate(link_rate: crtc_state->port_clock);
149}
150
151/**
152 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
153 * @rate: link rate in 10kbit/s units
154 *
155 * Returns the link symbol size in bits/symbol units depending on the link
156 * rate -> channel coding.
157 */
158int intel_dp_link_symbol_size(int rate)
159{
160 return drm_dp_is_uhbr_rate(link_rate: rate) ? 32 : 10;
161}
162
163/**
164 * intel_dp_link_symbol_clock - convert link rate to link symbol clock
165 * @rate: link rate in 10kbit/s units
166 *
167 * Returns the link symbol clock frequency in kHz units depending on the
168 * link rate and channel coding.
169 */
170int intel_dp_link_symbol_clock(int rate)
171{
172 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
173}
174
175static int max_dprx_rate(struct intel_dp *intel_dp)
176{
177 struct intel_display *display = to_intel_display(intel_dp);
178 int max_rate;
179
180 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
181 max_rate = drm_dp_tunnel_max_dprx_rate(tunnel: intel_dp->tunnel);
182 else
183 max_rate = drm_dp_bw_code_to_link_rate(link_bw: intel_dp->dpcd[DP_MAX_LINK_RATE]);
184
185 /*
186 * Some platforms + eDP panels may not reliably support HBR3
187 * due to signal integrity limitations, despite advertising it.
188 * Cap the link rate to HBR2 to avoid unstable configurations for the
189 * known machines.
190 */
191 if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, quirk: QUIRK_EDP_LIMIT_RATE_HBR2))
192 max_rate = min(max_rate, 540000);
193
194 return max_rate;
195}
196
197static int max_dprx_lane_count(struct intel_dp *intel_dp)
198{
199 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
200 return drm_dp_tunnel_max_dprx_lane_count(tunnel: intel_dp->tunnel);
201
202 return drm_dp_max_lane_count(dpcd: intel_dp->dpcd);
203}
204
205static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
206{
207 intel_dp->sink_rates[0] = 162000;
208 intel_dp->num_sink_rates = 1;
209}
210
211/* update sink rates from dpcd */
212static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
213{
214 static const int dp_rates[] = {
215 162000, 270000, 540000, 810000
216 };
217 int i, max_rate;
218 int max_lttpr_rate;
219
220 if (drm_dp_has_quirk(desc: &intel_dp->desc, quirk: DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
221 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
222 static const int quirk_rates[] = { 162000, 270000, 324000 };
223
224 memcpy(to: intel_dp->sink_rates, from: quirk_rates, len: sizeof(quirk_rates));
225 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
226
227 return;
228 }
229
230 /*
231 * Sink rates for 8b/10b.
232 */
233 max_rate = max_dprx_rate(intel_dp);
234 max_lttpr_rate = drm_dp_lttpr_max_link_rate(caps: intel_dp->lttpr_common_caps);
235 if (max_lttpr_rate)
236 max_rate = min(max_rate, max_lttpr_rate);
237
238 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
239 if (dp_rates[i] > max_rate)
240 break;
241 intel_dp->sink_rates[i] = dp_rates[i];
242 }
243
244 /*
245 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
246 * rates and 10 Gbps.
247 */
248 if (drm_dp_128b132b_supported(dpcd: intel_dp->dpcd)) {
249 u8 uhbr_rates = 0;
250
251 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
252
253 drm_dp_dpcd_readb(aux: &intel_dp->aux,
254 DP_128B132B_SUPPORTED_LINK_RATES, valuep: &uhbr_rates);
255
256 if (drm_dp_lttpr_count(cap: intel_dp->lttpr_common_caps)) {
257 /* We have a repeater */
258 if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
259 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
260 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
261 DP_PHY_REPEATER_128B132B_SUPPORTED) {
262 /* Repeater supports 128b/132b, valid UHBR rates */
263 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
264 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
265 } else {
266 /* Does not support 128b/132b */
267 uhbr_rates = 0;
268 }
269 }
270
271 if (uhbr_rates & DP_UHBR10)
272 intel_dp->sink_rates[i++] = 1000000;
273 if (uhbr_rates & DP_UHBR13_5)
274 intel_dp->sink_rates[i++] = 1350000;
275 if (uhbr_rates & DP_UHBR20)
276 intel_dp->sink_rates[i++] = 2000000;
277 }
278
279 intel_dp->num_sink_rates = i;
280}
281
282static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
283{
284 struct intel_display *display = to_intel_display(intel_dp);
285 struct intel_connector *connector = intel_dp->attached_connector;
286 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
287 struct intel_encoder *encoder = &intel_dig_port->base;
288
289 intel_dp_set_dpcd_sink_rates(intel_dp);
290
291 if (intel_dp->num_sink_rates)
292 return;
293
294 drm_err(display->drm,
295 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
296 connector->base.base.id, connector->base.name,
297 encoder->base.base.id, encoder->base.name);
298
299 intel_dp_set_default_sink_rates(intel_dp);
300}
301
302static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
303{
304 intel_dp->max_sink_lane_count = 1;
305}
306
307static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
308{
309 struct intel_display *display = to_intel_display(intel_dp);
310 struct intel_connector *connector = intel_dp->attached_connector;
311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
312 struct intel_encoder *encoder = &intel_dig_port->base;
313
314 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);
315
316 switch (intel_dp->max_sink_lane_count) {
317 case 1:
318 case 2:
319 case 4:
320 return;
321 }
322
323 drm_err(display->drm,
324 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
325 connector->base.base.id, connector->base.name,
326 encoder->base.base.id, encoder->base.name,
327 intel_dp->max_sink_lane_count);
328
329 intel_dp_set_default_max_sink_lane_count(intel_dp);
330}
331
332/* Get length of rates array potentially limited by max_rate. */
333static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
334{
335 int i;
336
337 /* Limit results by potentially reduced max rate */
338 for (i = 0; i < len; i++) {
339 if (rates[len - i - 1] <= max_rate)
340 return len - i;
341 }
342
343 return 0;
344}
345
346/* Get length of common rates array potentially limited by max_rate. */
347static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
348 int max_rate)
349{
350 return intel_dp_rate_limit_len(rates: intel_dp->common_rates,
351 len: intel_dp->num_common_rates, max_rate);
352}
353
354int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
355{
356 struct intel_display *display = to_intel_display(intel_dp);
357
358 if (drm_WARN_ON(display->drm,
359 index < 0 || index >= intel_dp->num_common_rates))
360 return 162000;
361
362 return intel_dp->common_rates[index];
363}
364
365/* Theoretical max between source and sink */
366int intel_dp_max_common_rate(struct intel_dp *intel_dp)
367{
368 return intel_dp_common_rate(intel_dp, index: intel_dp->num_common_rates - 1);
369}
370
371int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
372{
373 int vbt_max_lanes = intel_bios_dp_max_lane_count(devdata: dig_port->base.devdata);
374 int max_lanes = dig_port->max_lanes;
375
376 if (vbt_max_lanes)
377 max_lanes = min(max_lanes, vbt_max_lanes);
378
379 return max_lanes;
380}
381
382/* Theoretical max between source and sink */
383int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
384{
385 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
386 int source_max = intel_dp_max_source_lane_count(dig_port);
387 int sink_max = intel_dp->max_sink_lane_count;
388 int lane_max = intel_tc_port_max_lane_count(dig_port);
389 int lttpr_max = drm_dp_lttpr_max_lane_count(caps: intel_dp->lttpr_common_caps);
390
391 if (lttpr_max)
392 sink_max = min(sink_max, lttpr_max);
393
394 return min3(source_max, sink_max, lane_max);
395}
396
397static int forced_lane_count(struct intel_dp *intel_dp)
398{
399 return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));
400}
401
402int intel_dp_max_lane_count(struct intel_dp *intel_dp)
403{
404 int lane_count;
405
406 if (intel_dp->link.force_lane_count)
407 lane_count = forced_lane_count(intel_dp);
408 else
409 lane_count = intel_dp->link.max_lane_count;
410
411 switch (lane_count) {
412 case 1:
413 case 2:
414 case 4:
415 return lane_count;
416 default:
417 MISSING_CASE(lane_count);
418 return 1;
419 }
420}
421
422static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
423{
424 if (intel_dp->link.force_lane_count)
425 return forced_lane_count(intel_dp);
426
427 return 1;
428}
429
430/*
431 * The required data bandwidth for a mode with given pixel clock and bpp. This
432 * is the required net bandwidth independent of the data bandwidth efficiency.
433 *
434 * TODO: check if callers of this functions should use
435 * intel_dp_effective_data_rate() instead.
436 */
437int
438intel_dp_link_required(int pixel_clock, int bpp)
439{
440 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
441 return DIV_ROUND_UP(pixel_clock * bpp, 8);
442}
443
444/**
445 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
446 * @pixel_clock: pixel clock in kHz
447 * @bpp_x16: bits per pixel .4 fixed point format
448 * @bw_overhead: BW allocation overhead in 1ppm units
449 *
450 * Return the effective pixel data rate in kB/sec units taking into account
451 * the provided SSC, FEC, DSC BW allocation overhead.
452 */
453int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
454 int bw_overhead)
455{
456 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
457 1000000 * 16 * 8);
458}
459
460/**
461 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params
462 * @intel_dp: Intel DP object
463 * @max_dprx_rate: Maximum data rate of the DPRX
464 * @max_dprx_lanes: Maximum lane count of the DPRX
465 *
466 * Calculate the maximum data rate for the provided link parameters taking into
467 * account any BW limitations by a DP tunnel attached to @intel_dp.
468 *
469 * Returns the maximum data rate in kBps units.
470 */
471int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
472 int max_dprx_rate, int max_dprx_lanes)
473{
474 int max_rate = drm_dp_max_dprx_data_rate(max_link_rate: max_dprx_rate, max_lanes: max_dprx_lanes);
475
476 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
477 max_rate = min(max_rate,
478 drm_dp_tunnel_available_bw(intel_dp->tunnel));
479
480 return max_rate;
481}
482
483bool intel_dp_has_joiner(struct intel_dp *intel_dp)
484{
485 struct intel_display *display = to_intel_display(intel_dp);
486 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
487 struct intel_encoder *encoder = &intel_dig_port->base;
488
489 /* eDP MSO is not compatible with joiner */
490 if (intel_dp->mso_link_count)
491 return false;
492
493 return DISPLAY_VER(display) >= 12 ||
494 (DISPLAY_VER(display) == 11 &&
495 encoder->port != PORT_A);
496}
497
498static int dg2_max_source_rate(struct intel_dp *intel_dp)
499{
500 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
501}
502
503static int icl_max_source_rate(struct intel_dp *intel_dp)
504{
505 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
506
507 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))
508 return 540000;
509
510 return 810000;
511}
512
513static int ehl_max_source_rate(struct intel_dp *intel_dp)
514{
515 if (intel_dp_is_edp(intel_dp))
516 return 540000;
517
518 return 810000;
519}
520
521static int mtl_max_source_rate(struct intel_dp *intel_dp)
522{
523 struct intel_display *display = to_intel_display(intel_dp);
524 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
525
526 if (intel_encoder_is_c10phy(encoder))
527 return 810000;
528
529 if (DISPLAY_VERx100(display) == 1401)
530 return 1350000;
531
532 return 2000000;
533}
534
535static int vbt_max_link_rate(struct intel_dp *intel_dp)
536{
537 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
538 int max_rate;
539
540 max_rate = intel_bios_dp_max_link_rate(devdata: encoder->devdata);
541
542 if (intel_dp_is_edp(intel_dp)) {
543 struct intel_connector *connector = intel_dp->attached_connector;
544 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
545
546 if (max_rate && edp_max_rate)
547 max_rate = min(max_rate, edp_max_rate);
548 else if (edp_max_rate)
549 max_rate = edp_max_rate;
550 }
551
552 return max_rate;
553}
554
555static void
556intel_dp_set_source_rates(struct intel_dp *intel_dp)
557{
558 /* The values must be in increasing order */
559 static const int bmg_rates[] = {
560 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
561 810000, 1000000, 1350000,
562 };
563 static const int mtl_rates[] = {
564 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
565 810000, 1000000, 2000000,
566 };
567 static const int icl_rates[] = {
568 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
569 1000000, 1350000,
570 };
571 static const int bxt_rates[] = {
572 162000, 216000, 243000, 270000, 324000, 432000, 540000
573 };
574 static const int skl_rates[] = {
575 162000, 216000, 270000, 324000, 432000, 540000
576 };
577 static const int hsw_rates[] = {
578 162000, 270000, 540000
579 };
580 static const int g4x_rates[] = {
581 162000, 270000
582 };
583 struct intel_display *display = to_intel_display(intel_dp);
584 const int *source_rates;
585 int size, max_rate = 0, vbt_max_rate;
586
587 /* This should only be done once */
588 drm_WARN_ON(display->drm,
589 intel_dp->source_rates || intel_dp->num_source_rates);
590
591 if (DISPLAY_VER(display) >= 14) {
592 if (display->platform.battlemage) {
593 source_rates = bmg_rates;
594 size = ARRAY_SIZE(bmg_rates);
595 } else {
596 source_rates = mtl_rates;
597 size = ARRAY_SIZE(mtl_rates);
598 }
599 max_rate = mtl_max_source_rate(intel_dp);
600 } else if (DISPLAY_VER(display) >= 11) {
601 source_rates = icl_rates;
602 size = ARRAY_SIZE(icl_rates);
603 if (display->platform.dg2)
604 max_rate = dg2_max_source_rate(intel_dp);
605 else if (display->platform.alderlake_p || display->platform.alderlake_s ||
606 display->platform.dg1 || display->platform.rocketlake)
607 max_rate = 810000;
608 else if (display->platform.jasperlake || display->platform.elkhartlake)
609 max_rate = ehl_max_source_rate(intel_dp);
610 else
611 max_rate = icl_max_source_rate(intel_dp);
612 } else if (display->platform.geminilake || display->platform.broxton) {
613 source_rates = bxt_rates;
614 size = ARRAY_SIZE(bxt_rates);
615 } else if (DISPLAY_VER(display) == 9) {
616 source_rates = skl_rates;
617 size = ARRAY_SIZE(skl_rates);
618 } else if ((display->platform.haswell && !display->platform.haswell_ulx) ||
619 display->platform.broadwell) {
620 source_rates = hsw_rates;
621 size = ARRAY_SIZE(hsw_rates);
622 } else {
623 source_rates = g4x_rates;
624 size = ARRAY_SIZE(g4x_rates);
625 }
626
627 vbt_max_rate = vbt_max_link_rate(intel_dp);
628 if (max_rate && vbt_max_rate)
629 max_rate = min(max_rate, vbt_max_rate);
630 else if (vbt_max_rate)
631 max_rate = vbt_max_rate;
632
633 if (max_rate)
634 size = intel_dp_rate_limit_len(rates: source_rates, len: size, max_rate);
635
636 intel_dp->source_rates = source_rates;
637 intel_dp->num_source_rates = size;
638}
639
640static int intersect_rates(const int *source_rates, int source_len,
641 const int *sink_rates, int sink_len,
642 int *common_rates)
643{
644 int i = 0, j = 0, k = 0;
645
646 while (i < source_len && j < sink_len) {
647 if (source_rates[i] == sink_rates[j]) {
648 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
649 return k;
650 common_rates[k] = source_rates[i];
651 ++k;
652 ++i;
653 ++j;
654 } else if (source_rates[i] < sink_rates[j]) {
655 ++i;
656 } else {
657 ++j;
658 }
659 }
660 return k;
661}
662
663/* return index of rate in rates array, or -1 if not found */
664int intel_dp_rate_index(const int *rates, int len, int rate)
665{
666 int i;
667
668 for (i = 0; i < len; i++)
669 if (rate == rates[i])
670 return i;
671
672 return -1;
673}
674
675static int intel_dp_link_config_rate(struct intel_dp *intel_dp,
676 const struct intel_dp_link_config *lc)
677{
678 return intel_dp_common_rate(intel_dp, index: lc->link_rate_idx);
679}
680
681static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc)
682{
683 return 1 << lc->lane_count_exp;
684}
685
686static int intel_dp_link_config_bw(struct intel_dp *intel_dp,
687 const struct intel_dp_link_config *lc)
688{
689 return drm_dp_max_dprx_data_rate(max_link_rate: intel_dp_link_config_rate(intel_dp, lc),
690 max_lanes: intel_dp_link_config_lane_count(lc));
691}
692
693static int link_config_cmp_by_bw(const void *a, const void *b, const void *p)
694{
695 struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */
696 const struct intel_dp_link_config *lc_a = a;
697 const struct intel_dp_link_config *lc_b = b;
698 int bw_a = intel_dp_link_config_bw(intel_dp, lc: lc_a);
699 int bw_b = intel_dp_link_config_bw(intel_dp, lc: lc_b);
700
701 if (bw_a != bw_b)
702 return bw_a - bw_b;
703
704 return intel_dp_link_config_rate(intel_dp, lc: lc_a) -
705 intel_dp_link_config_rate(intel_dp, lc: lc_b);
706}
707
708static void intel_dp_link_config_init(struct intel_dp *intel_dp)
709{
710 struct intel_display *display = to_intel_display(intel_dp);
711 struct intel_dp_link_config *lc;
712 int num_common_lane_configs;
713 int i;
714 int j;
715
716 if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
717 return;
718
719 num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;
720
721 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >
722 ARRAY_SIZE(intel_dp->link.configs)))
723 return;
724
725 intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;
726
727 lc = &intel_dp->link.configs[0];
728 for (i = 0; i < intel_dp->num_common_rates; i++) {
729 for (j = 0; j < num_common_lane_configs; j++) {
730 lc->lane_count_exp = j;
731 lc->link_rate_idx = i;
732
733 lc++;
734 }
735 }
736
737 sort_r(base: intel_dp->link.configs, num: intel_dp->link.num_configs,
738 size: sizeof(intel_dp->link.configs[0]),
739 cmp_func: link_config_cmp_by_bw, NULL,
740 priv: intel_dp);
741}
742
743void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)
744{
745 struct intel_display *display = to_intel_display(intel_dp);
746 const struct intel_dp_link_config *lc;
747
748 if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))
749 idx = 0;
750
751 lc = &intel_dp->link.configs[idx];
752
753 *link_rate = intel_dp_link_config_rate(intel_dp, lc);
754 *lane_count = intel_dp_link_config_lane_count(lc);
755}
756
757int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count)
758{
759 int link_rate_idx = intel_dp_rate_index(rates: intel_dp->common_rates, len: intel_dp->num_common_rates,
760 rate: link_rate);
761 int lane_count_exp = ilog2(lane_count);
762 int i;
763
764 for (i = 0; i < intel_dp->link.num_configs; i++) {
765 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];
766
767 if (lc->lane_count_exp == lane_count_exp &&
768 lc->link_rate_idx == link_rate_idx)
769 return i;
770 }
771
772 return -1;
773}
774
775static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
776{
777 struct intel_display *display = to_intel_display(intel_dp);
778
779 drm_WARN_ON(display->drm,
780 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
781
782 intel_dp->num_common_rates = intersect_rates(source_rates: intel_dp->source_rates,
783 source_len: intel_dp->num_source_rates,
784 sink_rates: intel_dp->sink_rates,
785 sink_len: intel_dp->num_sink_rates,
786 common_rates: intel_dp->common_rates);
787
788 /* Paranoia, there should always be something in common. */
789 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {
790 intel_dp->common_rates[0] = 162000;
791 intel_dp->num_common_rates = 1;
792 }
793
794 intel_dp_link_config_init(intel_dp);
795}
796
797bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
798 u8 lane_count)
799{
800 /*
801 * FIXME: we need to synchronize the current link parameters with
802 * hardware readout. Currently fast link training doesn't work on
803 * boot-up.
804 */
805 if (link_rate == 0 ||
806 link_rate > intel_dp->link.max_rate)
807 return false;
808
809 if (lane_count == 0 ||
810 lane_count > intel_dp_max_lane_count(intel_dp))
811 return false;
812
813 return true;
814}
815
816u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
817{
818 return div_u64(dividend: mul_u32_u32(a: mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
819 divisor: 1000000U);
820}
821
822int intel_dp_bw_fec_overhead(bool fec_enabled)
823{
824 /*
825 * TODO: Calculate the actual overhead for a given mode.
826 * The hard-coded 1/0.972261=2.853% overhead factor
827 * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
828 * 0.453% DSC overhead. This is enough for a 3840 width mode,
829 * which has a DSC overhead of up to ~0.2%, but may not be
830 * enough for a 1024 width mode where this is ~0.8% (on a 4
831 * lane DP link, with 2 DSC slices and 8 bpp color depth).
832 */
833 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
834}
835
836static int
837small_joiner_ram_size_bits(struct intel_display *display)
838{
839 if (DISPLAY_VER(display) >= 13)
840 return 17280 * 8;
841 else if (DISPLAY_VER(display) >= 11)
842 return 7680 * 8;
843 else
844 return 6144 * 8;
845}
846
847static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp)
848{
849 u32 bits_per_pixel = bpp;
850 int i;
851
852 /* Error out if the max bpp is less than smallest allowed valid bpp */
853 if (bits_per_pixel < valid_dsc_bpp[0]) {
854 drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n",
855 bits_per_pixel, valid_dsc_bpp[0]);
856 return 0;
857 }
858
859 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
860 if (DISPLAY_VER(display) >= 13) {
861 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
862
863 /*
864 * According to BSpec, 27 is the max DSC output bpp,
865 * 8 is the min DSC output bpp.
866 * While we can still clamp higher bpp values to 27, saving bandwidth,
867 * if it is required to oompress up to bpp < 8, means we can't do
868 * that and probably means we can't fit the required mode, even with
869 * DSC enabled.
870 */
871 if (bits_per_pixel < 8) {
872 drm_dbg_kms(display->drm,
873 "Unsupported BPP %u, min 8\n",
874 bits_per_pixel);
875 return 0;
876 }
877 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
878 } else {
879 /* Find the nearest match in the array of known BPPs from VESA */
880 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
881 if (bits_per_pixel < valid_dsc_bpp[i + 1])
882 break;
883 }
884 drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n",
885 bits_per_pixel, valid_dsc_bpp[i]);
886
887 bits_per_pixel = valid_dsc_bpp[i];
888 }
889
890 return bits_per_pixel;
891}
892
893static int bigjoiner_interface_bits(struct intel_display *display)
894{
895 return DISPLAY_VER(display) >= 14 ? 36 : 24;
896}
897
898static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock,
899 int num_joined_pipes)
900{
901 u32 max_bpp;
902 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
903 int ppc = 2;
904 int num_big_joiners = num_joined_pipes / 2;
905
906 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /
907 intel_dp_mode_to_fec_clock(mode_clock);
908
909 max_bpp *= num_big_joiners;
910
911 return max_bpp;
912
913}
914
915static u32 small_joiner_ram_max_bpp(struct intel_display *display,
916 u32 mode_hdisplay,
917 int num_joined_pipes)
918{
919 u32 max_bpp;
920
921 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
922 max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay;
923
924 max_bpp *= num_joined_pipes;
925
926 return max_bpp;
927}
928
929static int ultrajoiner_ram_bits(void)
930{
931 return 4 * 72 * 512;
932}
933
934static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay)
935{
936 return ultrajoiner_ram_bits() / mode_hdisplay;
937}
938
939/* TODO: return a bpp_x16 value */
940static
941u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,
942 u32 mode_clock, u32 mode_hdisplay,
943 int num_joined_pipes)
944{
945 u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);
946
947 if (num_joined_pipes > 1)
948 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock,
949 num_joined_pipes));
950 if (num_joined_pipes == 4)
951 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay));
952
953 return max_bpp;
954}
955
956/* TODO: return a bpp_x16 value */
957u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
958 u32 link_clock, u32 lane_count,
959 u32 mode_clock, u32 mode_hdisplay,
960 int num_joined_pipes,
961 enum intel_output_format output_format,
962 u32 pipe_bpp,
963 u32 timeslots)
964{
965 u32 bits_per_pixel, joiner_max_bpp;
966
967 /*
968 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
969 * (LinkSymbolClock)* 8 * (TimeSlots / 64)
970 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
971 * for MST -> TimeSlots has to be calculated, based on mode requirements
972 *
973 * Due to FEC overhead, the available bw is reduced to 97.2261%.
974 * To support the given mode:
975 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
976 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
977 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
978 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
979 * (ModeClock / FEC Overhead)
980 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
981 * (ModeClock / FEC Overhead * 8)
982 */
983 bits_per_pixel = ((link_clock * lane_count) * timeslots) /
984 (intel_dp_mode_to_fec_clock(mode_clock) * 8);
985
986 /* Bandwidth required for 420 is half, that of 444 format */
987 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
988 bits_per_pixel *= 2;
989
990 /*
991 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
992 * supported PPS value can be 63.9375 and with the further
993 * mention that for 420, 422 formats, bpp should be programmed double
994 * the target bpp restricting our target bpp to be 31.9375 at max.
995 */
996 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
997 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
998
999 drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots "
1000 "total bw %u pixel clock %u\n",
1001 bits_per_pixel, timeslots,
1002 (link_clock * lane_count * 8),
1003 intel_dp_mode_to_fec_clock(mode_clock));
1004
1005 joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock,
1006 mode_hdisplay, num_joined_pipes);
1007 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
1008
1009 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bpp: bits_per_pixel, pipe_bpp);
1010
1011 return bits_per_pixel;
1012}
1013
1014u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
1015 int mode_clock, int mode_hdisplay,
1016 int num_joined_pipes)
1017{
1018 struct intel_display *display = to_intel_display(connector);
1019 u8 min_slice_count, i;
1020 int max_slice_width;
1021
1022 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
1023 min_slice_count = DIV_ROUND_UP(mode_clock,
1024 DP_DSC_MAX_ENC_THROUGHPUT_0);
1025 else
1026 min_slice_count = DIV_ROUND_UP(mode_clock,
1027 DP_DSC_MAX_ENC_THROUGHPUT_1);
1028
1029 /*
1030 * Due to some DSC engine BW limitations, we need to enable second
1031 * slice and VDSC engine, whenever we approach close enough to max CDCLK
1032 */
1033 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))
1034 min_slice_count = max_t(u8, min_slice_count, 2);
1035
1036 max_slice_width = drm_dp_dsc_sink_max_slice_width(dsc_dpcd: connector->dp.dsc_dpcd);
1037 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
1038 drm_dbg_kms(display->drm,
1039 "Unsupported slice width %d by DP DSC Sink device\n",
1040 max_slice_width);
1041 return 0;
1042 }
1043 /* Also take into account max slice width */
1044 min_slice_count = max_t(u8, min_slice_count,
1045 DIV_ROUND_UP(mode_hdisplay,
1046 max_slice_width));
1047
1048 /* Find the closest match to the valid slice count values */
1049 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
1050 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
1051
1052 /*
1053 * 3 DSC Slices per pipe need 3 DSC engines, which is supported only
1054 * with Ultrajoiner only for some platforms.
1055 */
1056 if (valid_dsc_slicecount[i] == 3 &&
1057 (!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4))
1058 continue;
1059
1060 if (test_slice_count >
1061 drm_dp_dsc_sink_max_slice_count(dsc_dpcd: connector->dp.dsc_dpcd, is_edp: false))
1062 break;
1063
1064 /*
1065 * Bigjoiner needs small joiner to be enabled.
1066 * So there should be at least 2 dsc slices per pipe,
1067 * whenever bigjoiner is enabled.
1068 */
1069 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2)
1070 continue;
1071
1072 if (mode_hdisplay % test_slice_count)
1073 continue;
1074
1075 if (min_slice_count <= test_slice_count)
1076 return test_slice_count;
1077 }
1078
1079 drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n",
1080 min_slice_count);
1081 return 0;
1082}
1083
1084static bool source_can_output(struct intel_dp *intel_dp,
1085 enum intel_output_format format)
1086{
1087 struct intel_display *display = to_intel_display(intel_dp);
1088
1089 switch (format) {
1090 case INTEL_OUTPUT_FORMAT_RGB:
1091 return true;
1092
1093 case INTEL_OUTPUT_FORMAT_YCBCR444:
1094 /*
1095 * No YCbCr output support on gmch platforms.
1096 * Also, ILK doesn't seem capable of DP YCbCr output.
1097 * The displayed image is severely corrupted. SNB+ is fine.
1098 */
1099 return !HAS_GMCH(display) && !display->platform.ironlake;
1100
1101 case INTEL_OUTPUT_FORMAT_YCBCR420:
1102 /* Platform < Gen 11 cannot output YCbCr420 format */
1103 return DISPLAY_VER(display) >= 11;
1104
1105 default:
1106 MISSING_CASE(format);
1107 return false;
1108 }
1109}
1110
1111static bool
1112dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
1113 enum intel_output_format sink_format)
1114{
1115 if (!drm_dp_is_branch(dpcd: intel_dp->dpcd))
1116 return false;
1117
1118 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1119 return intel_dp->dfp.rgb_to_ycbcr;
1120
1121 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1122 return intel_dp->dfp.rgb_to_ycbcr &&
1123 intel_dp->dfp.ycbcr_444_to_420;
1124
1125 return false;
1126}
1127
1128static bool
1129dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
1130 enum intel_output_format sink_format)
1131{
1132 if (!drm_dp_is_branch(dpcd: intel_dp->dpcd))
1133 return false;
1134
1135 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1136 return intel_dp->dfp.ycbcr_444_to_420;
1137
1138 return false;
1139}
1140
1141static bool
1142dfp_can_convert(struct intel_dp *intel_dp,
1143 enum intel_output_format output_format,
1144 enum intel_output_format sink_format)
1145{
1146 switch (output_format) {
1147 case INTEL_OUTPUT_FORMAT_RGB:
1148 return dfp_can_convert_from_rgb(intel_dp, sink_format);
1149 case INTEL_OUTPUT_FORMAT_YCBCR444:
1150 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1151 default:
1152 MISSING_CASE(output_format);
1153 return false;
1154 }
1155
1156 return false;
1157}
1158
1159static enum intel_output_format
1160intel_dp_output_format(struct intel_connector *connector,
1161 enum intel_output_format sink_format)
1162{
1163 struct intel_display *display = to_intel_display(connector);
1164 struct intel_dp *intel_dp = intel_attached_dp(connector);
1165 enum intel_output_format force_dsc_output_format =
1166 intel_dp->force_dsc_output_format;
1167 enum intel_output_format output_format;
1168 if (force_dsc_output_format) {
1169 if (source_can_output(intel_dp, format: force_dsc_output_format) &&
1170 (!drm_dp_is_branch(dpcd: intel_dp->dpcd) ||
1171 sink_format != force_dsc_output_format ||
1172 dfp_can_convert(intel_dp, output_format: force_dsc_output_format, sink_format)))
1173 return force_dsc_output_format;
1174
1175 drm_dbg_kms(display->drm, "Cannot force DSC output format\n");
1176 }
1177
1178 if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1179 dfp_can_convert_from_rgb(intel_dp, sink_format))
1180 output_format = INTEL_OUTPUT_FORMAT_RGB;
1181
1182 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1183 dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1184 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1185
1186 else
1187 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1188
1189 drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));
1190
1191 return output_format;
1192}
1193
1194int intel_dp_min_bpp(enum intel_output_format output_format)
1195{
1196 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1197 return intel_display_min_pipe_bpp();
1198 else
1199 return 8 * 3;
1200}
1201
1202int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1203{
1204 /*
1205 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1206 * format of the number of bytes per pixel will be half the number
1207 * of bytes of RGB pixel.
1208 */
1209 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1210 bpp /= 2;
1211
1212 return bpp;
1213}
1214
1215static enum intel_output_format
1216intel_dp_sink_format(struct intel_connector *connector,
1217 const struct drm_display_mode *mode)
1218{
1219 const struct drm_display_info *info = &connector->base.display_info;
1220
1221 if (drm_mode_is_420_only(display: info, mode))
1222 return INTEL_OUTPUT_FORMAT_YCBCR420;
1223
1224 return INTEL_OUTPUT_FORMAT_RGB;
1225}
1226
1227static int
1228intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1229 const struct drm_display_mode *mode)
1230{
1231 enum intel_output_format output_format, sink_format;
1232
1233 sink_format = intel_dp_sink_format(connector, mode);
1234
1235 output_format = intel_dp_output_format(connector, sink_format);
1236
1237 return intel_dp_output_bpp(output_format, bpp: intel_dp_min_bpp(output_format));
1238}
1239
1240static bool intel_dp_hdisplay_bad(struct intel_display *display,
1241 int hdisplay)
1242{
1243 /*
1244 * Older platforms don't like hdisplay==4096 with DP.
1245 *
1246 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1247 * and frame counter increment), but we don't get vblank interrupts,
1248 * and the pipe underruns immediately. The link also doesn't seem
1249 * to get trained properly.
1250 *
1251 * On CHV the vblank interrupts don't seem to disappear but
1252 * otherwise the symptoms are similar.
1253 *
1254 * TODO: confirm the behaviour on HSW+
1255 */
1256 return hdisplay == 4096 && !HAS_DDI(display);
1257}
1258
1259static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1260{
1261 struct intel_connector *connector = intel_dp->attached_connector;
1262 const struct drm_display_info *info = &connector->base.display_info;
1263 int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1264
1265 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1266 if (max_tmds_clock && info->max_tmds_clock)
1267 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1268
1269 return max_tmds_clock;
1270}
1271
1272static enum drm_mode_status
1273intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1274 int clock, int bpc,
1275 enum intel_output_format sink_format,
1276 bool respect_downstream_limits)
1277{
1278 int tmds_clock, min_tmds_clock, max_tmds_clock;
1279
1280 if (!respect_downstream_limits)
1281 return MODE_OK;
1282
1283 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1284
1285 min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1286 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1287
1288 if (min_tmds_clock && tmds_clock < min_tmds_clock)
1289 return MODE_CLOCK_LOW;
1290
1291 if (max_tmds_clock && tmds_clock > max_tmds_clock)
1292 return MODE_CLOCK_HIGH;
1293
1294 return MODE_OK;
1295}
1296
1297static enum drm_mode_status
1298intel_dp_mode_valid_downstream(struct intel_connector *connector,
1299 const struct drm_display_mode *mode,
1300 int target_clock)
1301{
1302 struct intel_dp *intel_dp = intel_attached_dp(connector);
1303 const struct drm_display_info *info = &connector->base.display_info;
1304 enum drm_mode_status status;
1305 enum intel_output_format sink_format;
1306
1307 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1308 if (intel_dp->dfp.pcon_max_frl_bw) {
1309 int target_bw;
1310 int max_frl_bw;
1311 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1312
1313 target_bw = bpp * target_clock;
1314
1315 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1316
1317 /* converting bw from Gbps to Kbps*/
1318 max_frl_bw = max_frl_bw * 1000000;
1319
1320 if (target_bw > max_frl_bw)
1321 return MODE_CLOCK_HIGH;
1322
1323 return MODE_OK;
1324 }
1325
1326 if (intel_dp->dfp.max_dotclock &&
1327 target_clock > intel_dp->dfp.max_dotclock)
1328 return MODE_CLOCK_HIGH;
1329
1330 sink_format = intel_dp_sink_format(connector, mode);
1331
1332 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1333 status = intel_dp_tmds_clock_valid(intel_dp, clock: target_clock,
1334 bpc: 8, sink_format, respect_downstream_limits: true);
1335
1336 if (status != MODE_OK) {
1337 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1338 !connector->base.ycbcr_420_allowed ||
1339 !drm_mode_is_420_also(display: info, mode))
1340 return status;
1341 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1342 status = intel_dp_tmds_clock_valid(intel_dp, clock: target_clock,
1343 bpc: 8, sink_format, respect_downstream_limits: true);
1344 if (status != MODE_OK)
1345 return status;
1346 }
1347
1348 return MODE_OK;
1349}
1350
1351static
1352bool intel_dp_needs_joiner(struct intel_dp *intel_dp,
1353 struct intel_connector *connector,
1354 int hdisplay, int clock,
1355 int num_joined_pipes)
1356{
1357 struct intel_display *display = to_intel_display(intel_dp);
1358 int hdisplay_limit;
1359
1360 if (!intel_dp_has_joiner(intel_dp))
1361 return false;
1362
1363 num_joined_pipes /= 2;
1364
1365 hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120;
1366
1367 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||
1368 hdisplay > num_joined_pipes * hdisplay_limit;
1369}
1370
1371int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
1372 struct intel_connector *connector,
1373 int hdisplay, int clock)
1374{
1375 struct intel_display *display = to_intel_display(intel_dp);
1376
1377 if (connector->force_joined_pipes)
1378 return connector->force_joined_pipes;
1379
1380 if (HAS_ULTRAJOINER(display) &&
1381 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, num_joined_pipes: 4))
1382 return 4;
1383
1384 if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) &&
1385 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, num_joined_pipes: 2))
1386 return 2;
1387
1388 return 1;
1389}
1390
1391bool intel_dp_has_dsc(const struct intel_connector *connector)
1392{
1393 struct intel_display *display = to_intel_display(connector);
1394
1395 if (!HAS_DSC(display))
1396 return false;
1397
1398 if (connector->mst.dp && !HAS_DSC_MST(display))
1399 return false;
1400
1401 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
1402 connector->panel.vbt.edp.dsc_disable)
1403 return false;
1404
1405 if (!drm_dp_sink_supports_dsc(dsc_dpcd: connector->dp.dsc_dpcd))
1406 return false;
1407
1408 return true;
1409}
1410
1411static enum drm_mode_status
1412intel_dp_mode_valid(struct drm_connector *_connector,
1413 const struct drm_display_mode *mode)
1414{
1415 struct intel_display *display = to_intel_display(_connector->dev);
1416 struct intel_connector *connector = to_intel_connector(_connector);
1417 struct intel_dp *intel_dp = intel_attached_dp(connector);
1418 enum intel_output_format sink_format, output_format;
1419 const struct drm_display_mode *fixed_mode;
1420 int target_clock = mode->clock;
1421 int max_rate, mode_rate, max_lanes, max_link_clock;
1422 int max_dotclk = display->cdclk.max_dotclk_freq;
1423 u16 dsc_max_compressed_bpp = 0;
1424 u8 dsc_slice_count = 0;
1425 enum drm_mode_status status;
1426 bool dsc = false;
1427 int num_joined_pipes;
1428
1429 status = intel_cpu_transcoder_mode_valid(display, mode);
1430 if (status != MODE_OK)
1431 return status;
1432
1433 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1434 return MODE_H_ILLEGAL;
1435
1436 if (mode->clock < 10000)
1437 return MODE_CLOCK_LOW;
1438
1439 fixed_mode = intel_panel_fixed_mode(connector, mode);
1440 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1441 status = intel_panel_mode_valid(connector, mode);
1442 if (status != MODE_OK)
1443 return status;
1444
1445 target_clock = fixed_mode->clock;
1446 }
1447
1448 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
1449 hdisplay: mode->hdisplay, clock: target_clock);
1450 max_dotclk *= num_joined_pipes;
1451
1452 sink_format = intel_dp_sink_format(connector, mode);
1453 output_format = intel_dp_output_format(connector, sink_format);
1454
1455 status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
1456 if (status != MODE_OK)
1457 return status;
1458
1459 if (target_clock > max_dotclk)
1460 return MODE_CLOCK_HIGH;
1461
1462 if (intel_dp_hdisplay_bad(display, hdisplay: mode->hdisplay))
1463 return MODE_H_ILLEGAL;
1464
1465 max_link_clock = intel_dp_max_link_rate(intel_dp);
1466 max_lanes = intel_dp_max_lane_count(intel_dp);
1467
1468 max_rate = intel_dp_max_link_data_rate(intel_dp, max_dprx_rate: max_link_clock, max_dprx_lanes: max_lanes);
1469
1470 mode_rate = intel_dp_link_required(pixel_clock: target_clock,
1471 bpp: intel_dp_mode_min_output_bpp(connector, mode));
1472
1473 if (intel_dp_has_dsc(connector)) {
1474 int pipe_bpp;
1475
1476 /*
1477 * TBD pass the connector BPC,
1478 * for now U8_MAX so that max BPC on that platform would be picked
1479 */
1480 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1481
1482 /*
1483 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1484 * integer value since we support only integer values of bpp.
1485 */
1486 if (intel_dp_is_edp(intel_dp)) {
1487 dsc_max_compressed_bpp =
1488 drm_edp_dsc_sink_output_bpp(dsc_dpcd: connector->dp.dsc_dpcd) >> 4;
1489 dsc_slice_count =
1490 drm_dp_dsc_sink_max_slice_count(dsc_dpcd: connector->dp.dsc_dpcd,
1491 is_edp: true);
1492 } else if (drm_dp_sink_supports_fec(fec_capable: connector->dp.fec_capability)) {
1493 dsc_max_compressed_bpp =
1494 intel_dp_dsc_get_max_compressed_bpp(display,
1495 link_clock: max_link_clock,
1496 lane_count: max_lanes,
1497 mode_clock: target_clock,
1498 mode_hdisplay: mode->hdisplay,
1499 num_joined_pipes,
1500 output_format,
1501 pipe_bpp, timeslots: 64);
1502 dsc_slice_count =
1503 intel_dp_dsc_get_slice_count(connector,
1504 mode_clock: target_clock,
1505 mode_hdisplay: mode->hdisplay,
1506 num_joined_pipes);
1507 }
1508
1509 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1510 }
1511
1512 if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
1513 return MODE_CLOCK_HIGH;
1514
1515 if (mode_rate > max_rate && !dsc)
1516 return MODE_CLOCK_HIGH;
1517
1518 status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1519 if (status != MODE_OK)
1520 return status;
1521
1522 return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
1523}
1524
1525bool intel_dp_source_supports_tps3(struct intel_display *display)
1526{
1527 return DISPLAY_VER(display) >= 9 ||
1528 display->platform.broadwell || display->platform.haswell;
1529}
1530
1531bool intel_dp_source_supports_tps4(struct intel_display *display)
1532{
1533 return DISPLAY_VER(display) >= 10;
1534}
1535
1536static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem)
1537{
1538 int i;
1539
1540 for (i = 0; i < nelem; i++)
1541 seq_buf_printf(s, fmt: "%s%d", i ? ", " : "", array[i]);
1542}
1543
1544static void intel_dp_print_rates(struct intel_dp *intel_dp)
1545{
1546 struct intel_display *display = to_intel_display(intel_dp);
1547 DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */
1548
1549 if (!drm_debug_enabled(DRM_UT_KMS))
1550 return;
1551
1552 seq_buf_print_array(s: &s, array: intel_dp->source_rates, nelem: intel_dp->num_source_rates);
1553 drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s));
1554
1555 seq_buf_clear(s: &s);
1556 seq_buf_print_array(s: &s, array: intel_dp->sink_rates, nelem: intel_dp->num_sink_rates);
1557 drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s));
1558
1559 seq_buf_clear(s: &s);
1560 seq_buf_print_array(s: &s, array: intel_dp->common_rates, nelem: intel_dp->num_common_rates);
1561 drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));
1562}
1563
1564static int forced_link_rate(struct intel_dp *intel_dp)
1565{
1566 int len = intel_dp_common_len_rate_limit(intel_dp, max_rate: intel_dp->link.force_rate);
1567
1568 if (len == 0)
1569 return intel_dp_common_rate(intel_dp, index: 0);
1570
1571 return intel_dp_common_rate(intel_dp, index: len - 1);
1572}
1573
1574int
1575intel_dp_max_link_rate(struct intel_dp *intel_dp)
1576{
1577 int len;
1578
1579 if (intel_dp->link.force_rate)
1580 return forced_link_rate(intel_dp);
1581
1582 len = intel_dp_common_len_rate_limit(intel_dp, max_rate: intel_dp->link.max_rate);
1583
1584 return intel_dp_common_rate(intel_dp, index: len - 1);
1585}
1586
1587static int
1588intel_dp_min_link_rate(struct intel_dp *intel_dp)
1589{
1590 if (intel_dp->link.force_rate)
1591 return forced_link_rate(intel_dp);
1592
1593 return intel_dp_common_rate(intel_dp, index: 0);
1594}
1595
1596int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1597{
1598 struct intel_display *display = to_intel_display(intel_dp);
1599 int i = intel_dp_rate_index(rates: intel_dp->sink_rates,
1600 len: intel_dp->num_sink_rates, rate);
1601
1602 if (drm_WARN_ON(display->drm, i < 0))
1603 i = 0;
1604
1605 return i;
1606}
1607
1608void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1609 u8 *link_bw, u8 *rate_select)
1610{
1611 struct intel_display *display = to_intel_display(intel_dp);
1612
1613 /* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */
1614 if (display->platform.g4x && port_clock == 268800)
1615 port_clock = 270000;
1616
1617 /* eDP 1.4 rate select method. */
1618 if (intel_dp->use_rate_select) {
1619 *link_bw = 0;
1620 *rate_select =
1621 intel_dp_rate_select(intel_dp, rate: port_clock);
1622 } else {
1623 *link_bw = drm_dp_link_rate_to_bw_code(link_rate: port_clock);
1624 *rate_select = 0;
1625 }
1626}
1627
1628bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1629{
1630 struct intel_connector *connector = intel_dp->attached_connector;
1631
1632 return connector->base.display_info.is_hdmi;
1633}
1634
1635static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1636 const struct intel_crtc_state *pipe_config)
1637{
1638 struct intel_display *display = to_intel_display(intel_dp);
1639 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1640
1641 if (DISPLAY_VER(display) >= 12)
1642 return true;
1643
1644 if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&
1645 !intel_crtc_has_type(crtc_state: pipe_config, type: INTEL_OUTPUT_DP_MST))
1646 return true;
1647
1648 return false;
1649}
1650
1651bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1652 const struct intel_connector *connector,
1653 const struct intel_crtc_state *pipe_config)
1654{
1655 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1656 drm_dp_sink_supports_fec(fec_capable: connector->dp.fec_capability);
1657}
1658
1659bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1660 const struct intel_connector *connector,
1661 const struct intel_crtc_state *crtc_state)
1662{
1663 if (!intel_dp_has_dsc(connector))
1664 return false;
1665
1666 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP) &&
1667 !intel_dp_supports_fec(intel_dp, connector, pipe_config: crtc_state))
1668 return false;
1669
1670 return intel_dsc_source_support(crtc_state);
1671}
1672
1673static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1674 const struct intel_crtc_state *crtc_state,
1675 int bpc, bool respect_downstream_limits)
1676{
1677 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1678
1679 /*
1680 * Current bpc could already be below 8bpc due to
1681 * FDI bandwidth constraints or other limits.
1682 * HDMI minimum is 8bpc however.
1683 */
1684 bpc = max(bpc, 8);
1685
1686 /*
1687 * We will never exceed downstream TMDS clock limits while
1688 * attempting deep color. If the user insists on forcing an
1689 * out of spec mode they will have to be satisfied with 8bpc.
1690 */
1691 if (!respect_downstream_limits)
1692 bpc = 8;
1693
1694 for (; bpc >= 8; bpc -= 2) {
1695 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1696 has_hdmi_sink: intel_dp_has_hdmi_sink(intel_dp)) &&
1697 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, sink_format: crtc_state->sink_format,
1698 respect_downstream_limits) == MODE_OK)
1699 return bpc;
1700 }
1701
1702 return -EINVAL;
1703}
1704
1705static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1706 const struct intel_crtc_state *crtc_state,
1707 bool respect_downstream_limits)
1708{
1709 struct intel_display *display = to_intel_display(intel_dp);
1710 struct intel_connector *connector = intel_dp->attached_connector;
1711 int bpp, bpc;
1712
1713 bpc = crtc_state->pipe_bpp / 3;
1714
1715 if (intel_dp->dfp.max_bpc)
1716 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1717
1718 if (intel_dp->dfp.min_tmds_clock) {
1719 int max_hdmi_bpc;
1720
1721 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1722 respect_downstream_limits);
1723 if (max_hdmi_bpc < 0)
1724 return 0;
1725
1726 bpc = min(bpc, max_hdmi_bpc);
1727 }
1728
1729 bpp = bpc * 3;
1730 if (intel_dp_is_edp(intel_dp)) {
1731 /* Get bpp from vbt only for panels that dont have bpp in edid */
1732 if (connector->base.display_info.bpc == 0 &&
1733 connector->panel.vbt.edp.bpp &&
1734 connector->panel.vbt.edp.bpp < bpp) {
1735 drm_dbg_kms(display->drm,
1736 "clamping bpp for eDP panel to BIOS-provided %i\n",
1737 connector->panel.vbt.edp.bpp);
1738 bpp = connector->panel.vbt.edp.bpp;
1739 }
1740 }
1741
1742 return bpp;
1743}
1744
1745static bool has_seamless_m_n(struct intel_connector *connector)
1746{
1747 struct intel_display *display = to_intel_display(connector);
1748
1749 /*
1750 * Seamless M/N reprogramming only implemented
1751 * for BDW+ double buffered M/N registers so far.
1752 */
1753 return HAS_DOUBLE_BUFFERED_M_N(display) &&
1754 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1755}
1756
1757static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1758 const struct drm_connector_state *conn_state)
1759{
1760 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1761 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1762
1763 /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1764 if (has_seamless_m_n(connector))
1765 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1766 else
1767 return adjusted_mode->crtc_clock;
1768}
1769
1770/* Optimize link config in order: max bpp, min clock, min lanes */
1771static int
1772intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1773 struct intel_crtc_state *pipe_config,
1774 const struct drm_connector_state *conn_state,
1775 const struct link_config_limits *limits)
1776{
1777 int bpp, i, lane_count, clock = intel_dp_mode_clock(crtc_state: pipe_config, conn_state);
1778 int mode_rate, link_rate, link_avail;
1779
1780 for (bpp = fxp_q4_to_int(val_q4: limits->link.max_bpp_x16);
1781 bpp >= fxp_q4_to_int(val_q4: limits->link.min_bpp_x16);
1782 bpp -= 2 * 3) {
1783 int link_bpp = intel_dp_output_bpp(output_format: pipe_config->output_format, bpp);
1784
1785 mode_rate = intel_dp_link_required(pixel_clock: clock, bpp: link_bpp);
1786
1787 for (i = 0; i < intel_dp->num_common_rates; i++) {
1788 link_rate = intel_dp_common_rate(intel_dp, index: i);
1789 if (link_rate < limits->min_rate ||
1790 link_rate > limits->max_rate)
1791 continue;
1792
1793 for (lane_count = limits->min_lane_count;
1794 lane_count <= limits->max_lane_count;
1795 lane_count <<= 1) {
1796 link_avail = intel_dp_max_link_data_rate(intel_dp,
1797 max_dprx_rate: link_rate,
1798 max_dprx_lanes: lane_count);
1799
1800
1801 if (mode_rate <= link_avail) {
1802 pipe_config->lane_count = lane_count;
1803 pipe_config->pipe_bpp = bpp;
1804 pipe_config->port_clock = link_rate;
1805
1806 return 0;
1807 }
1808 }
1809 }
1810 }
1811
1812 return -EINVAL;
1813}
1814
1815int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
1816{
1817 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1818 if (DISPLAY_VER(display) >= 12)
1819 return 12;
1820 if (DISPLAY_VER(display) == 11)
1821 return 10;
1822
1823 return intel_dp_dsc_min_src_input_bpc();
1824}
1825
1826int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1827 u8 max_req_bpc)
1828{
1829 struct intel_display *display = to_intel_display(connector);
1830 int i, num_bpc;
1831 u8 dsc_bpc[3] = {};
1832 int dsc_max_bpc;
1833
1834 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
1835
1836 if (!dsc_max_bpc)
1837 return dsc_max_bpc;
1838
1839 dsc_max_bpc = min(dsc_max_bpc, max_req_bpc);
1840
1841 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(dsc_dpc: connector->dp.dsc_dpcd,
1842 dsc_bpc);
1843 for (i = 0; i < num_bpc; i++) {
1844 if (dsc_max_bpc >= dsc_bpc[i])
1845 return dsc_bpc[i] * 3;
1846 }
1847
1848 return 0;
1849}
1850
1851static int intel_dp_source_dsc_version_minor(struct intel_display *display)
1852{
1853 return DISPLAY_VER(display) >= 14 ? 2 : 1;
1854}
1855
1856static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1857{
1858 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1859 DP_DSC_MINOR_SHIFT;
1860}
1861
1862static int intel_dp_get_slice_height(int vactive)
1863{
1864 int slice_height;
1865
1866 /*
1867 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1868 * lines is an optimal slice height, but any size can be used as long as
1869 * vertical active integer multiple and maximum vertical slice count
1870 * requirements are met.
1871 */
1872 for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1873 if (vactive % slice_height == 0)
1874 return slice_height;
1875
1876 /*
1877 * Highly unlikely we reach here as most of the resolutions will end up
1878 * finding appropriate slice_height in above loop but returning
1879 * slice_height as 2 here as it should work with all resolutions.
1880 */
1881 return 2;
1882}
1883
1884static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1885 struct intel_crtc_state *crtc_state)
1886{
1887 struct intel_display *display = to_intel_display(connector);
1888 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1889 int ret;
1890
1891 /*
1892 * RC_MODEL_SIZE is currently a constant across all configurations.
1893 *
1894 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1895 * DP_DSC_RC_BUF_SIZE for this.
1896 */
1897 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1898 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1899
1900 vdsc_cfg->slice_height = intel_dp_get_slice_height(vactive: vdsc_cfg->pic_height);
1901
1902 ret = intel_dsc_compute_params(pipe_config: crtc_state);
1903 if (ret)
1904 return ret;
1905
1906 vdsc_cfg->dsc_version_major =
1907 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1908 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1909 vdsc_cfg->dsc_version_minor =
1910 min(intel_dp_source_dsc_version_minor(display),
1911 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1912 if (vdsc_cfg->convert_rgb)
1913 vdsc_cfg->convert_rgb =
1914 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1915 DP_DSC_RGB;
1916
1917 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
1918 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
1919 if (!vdsc_cfg->line_buf_depth) {
1920 drm_dbg_kms(display->drm,
1921 "DSC Sink Line Buffer Depth invalid\n");
1922 return -EINVAL;
1923 }
1924
1925 vdsc_cfg->block_pred_enable =
1926 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1927 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1928
1929 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1930}
1931
1932static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1933 enum intel_output_format output_format)
1934{
1935 struct intel_display *display = to_intel_display(connector);
1936 u8 sink_dsc_format;
1937
1938 switch (output_format) {
1939 case INTEL_OUTPUT_FORMAT_RGB:
1940 sink_dsc_format = DP_DSC_RGB;
1941 break;
1942 case INTEL_OUTPUT_FORMAT_YCBCR444:
1943 sink_dsc_format = DP_DSC_YCbCr444;
1944 break;
1945 case INTEL_OUTPUT_FORMAT_YCBCR420:
1946 if (min(intel_dp_source_dsc_version_minor(display),
1947 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1948 return false;
1949 sink_dsc_format = DP_DSC_YCbCr420_Native;
1950 break;
1951 default:
1952 return false;
1953 }
1954
1955 return drm_dp_dsc_sink_supports_format(dsc_dpcd: connector->dp.dsc_dpcd, output_format: sink_dsc_format);
1956}
1957
1958static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock,
1959 u32 lane_count, u32 mode_clock,
1960 enum intel_output_format output_format,
1961 int timeslots)
1962{
1963 u32 available_bw, required_bw;
1964
1965 available_bw = (link_clock * lane_count * timeslots * 16) / 8;
1966 required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock));
1967
1968 return available_bw > required_bw;
1969}
1970
1971static int dsc_compute_link_config(struct intel_dp *intel_dp,
1972 struct intel_crtc_state *pipe_config,
1973 struct drm_connector_state *conn_state,
1974 const struct link_config_limits *limits,
1975 int dsc_bpp_x16,
1976 int timeslots)
1977{
1978 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1979 int link_rate, lane_count;
1980 int i;
1981
1982 for (i = 0; i < intel_dp->num_common_rates; i++) {
1983 link_rate = intel_dp_common_rate(intel_dp, index: i);
1984 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1985 continue;
1986
1987 for (lane_count = limits->min_lane_count;
1988 lane_count <= limits->max_lane_count;
1989 lane_count <<= 1) {
1990
1991 /*
1992 * FIXME: intel_dp_mtp_tu_compute_config() requires
1993 * ->lane_count and ->port_clock set before we know
1994 * they'll work. If we end up failing altogether,
1995 * they'll remain in crtc state. This shouldn't matter,
1996 * as we'd then bail out from compute config, but it's
1997 * just ugly.
1998 */
1999 pipe_config->lane_count = lane_count;
2000 pipe_config->port_clock = link_rate;
2001
2002 if (drm_dp_is_uhbr_rate(link_rate)) {
2003 int ret;
2004
2005 ret = intel_dp_mtp_tu_compute_config(intel_dp,
2006 crtc_state: pipe_config,
2007 conn_state,
2008 min_bpp_x16: dsc_bpp_x16,
2009 max_bpp_x16: dsc_bpp_x16,
2010 bpp_step_x16: 0, dsc: true);
2011 if (ret)
2012 continue;
2013 } else {
2014 if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_clock: link_rate,
2015 lane_count, mode_clock: adjusted_mode->clock,
2016 output_format: pipe_config->output_format,
2017 timeslots))
2018 continue;
2019 }
2020
2021 return 0;
2022 }
2023 }
2024
2025 return -EINVAL;
2026}
2027
2028static
2029u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
2030 const struct intel_crtc_state *pipe_config,
2031 int bpc)
2032{
2033 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(dsc_dpcd: connector->dp.dsc_dpcd);
2034
2035 if (max_bppx16)
2036 return max_bppx16;
2037 /*
2038 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
2039 * values as given in spec Table 2-157 DP v2.0
2040 */
2041 switch (pipe_config->output_format) {
2042 case INTEL_OUTPUT_FORMAT_RGB:
2043 case INTEL_OUTPUT_FORMAT_YCBCR444:
2044 return (3 * bpc) << 4;
2045 case INTEL_OUTPUT_FORMAT_YCBCR420:
2046 return (3 * (bpc / 2)) << 4;
2047 default:
2048 MISSING_CASE(pipe_config->output_format);
2049 break;
2050 }
2051
2052 return 0;
2053}
2054
2055int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config)
2056{
2057 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
2058 switch (pipe_config->output_format) {
2059 case INTEL_OUTPUT_FORMAT_RGB:
2060 case INTEL_OUTPUT_FORMAT_YCBCR444:
2061 return 8;
2062 case INTEL_OUTPUT_FORMAT_YCBCR420:
2063 return 6;
2064 default:
2065 MISSING_CASE(pipe_config->output_format);
2066 break;
2067 }
2068
2069 return 0;
2070}
2071
2072int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
2073 const struct intel_crtc_state *pipe_config,
2074 int bpc)
2075{
2076 return intel_dp_dsc_max_sink_compressed_bppx16(connector,
2077 pipe_config, bpc) >> 4;
2078}
2079
2080int intel_dp_dsc_min_src_compressed_bpp(void)
2081{
2082 /* Min Compressed bpp supported by source is 8 */
2083 return 8;
2084}
2085
2086static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
2087{
2088 struct intel_display *display = to_intel_display(intel_dp);
2089
2090 /*
2091 * Forcing DSC and using the platform's max compressed bpp is seen to cause
2092 * underruns. Since DSC isn't needed in these cases, limit the
2093 * max compressed bpp to 18, which is a safe value across platforms with different
2094 * pipe bpps.
2095 */
2096 if (intel_dp->force_dsc_en)
2097 return 18;
2098
2099 /*
2100 * Max Compressed bpp for Gen 13+ is 27bpp.
2101 * For earlier platform is 23bpp. (Bspec:49259).
2102 */
2103 if (DISPLAY_VER(display) < 13)
2104 return 23;
2105 else
2106 return 27;
2107}
2108
2109/*
2110 * Note: for pre-13 display you still need to check the validity of each step.
2111 */
2112int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector)
2113{
2114 struct intel_display *display = to_intel_display(connector);
2115 u8 incr = drm_dp_dsc_sink_bpp_incr(dsc_dpcd: connector->dp.dsc_dpcd);
2116
2117 if (DISPLAY_VER(display) < 14 || !incr)
2118 return fxp_q4_from_int(val_int: 1);
2119
2120 if (connector->mst.dp &&
2121 !connector->link.force_bpp_x16 && !connector->mst.dp->force_dsc_fractional_bpp_en)
2122 return fxp_q4_from_int(val_int: 1);
2123
2124 /* fxp q4 */
2125 return fxp_q4_from_int(val_int: 1) / incr;
2126}
2127
2128/*
2129 * Note: for bpp_x16 to be valid it must be also within the source/sink's
2130 * min..max bpp capability range.
2131 */
2132bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16)
2133{
2134 struct intel_display *display = to_intel_display(intel_dp);
2135 int i;
2136
2137 if (DISPLAY_VER(display) >= 13) {
2138 if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(val_q4: bpp_x16))
2139 return false;
2140
2141 return true;
2142 }
2143
2144 if (fxp_q4_to_frac(val_q4: bpp_x16))
2145 return false;
2146
2147 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
2148 if (fxp_q4_to_int(val_q4: bpp_x16) == valid_dsc_bpp[i])
2149 return true;
2150 }
2151
2152 return false;
2153}
2154
2155/*
2156 * Find the max compressed BPP we can find a link configuration for. The BPPs to
2157 * try depend on the source (platform) and sink.
2158 */
2159static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
2160 struct intel_crtc_state *pipe_config,
2161 struct drm_connector_state *conn_state,
2162 const struct link_config_limits *limits,
2163 int pipe_bpp,
2164 int timeslots)
2165{
2166 struct intel_display *display = to_intel_display(intel_dp);
2167 const struct intel_connector *connector = to_intel_connector(conn_state->connector);
2168 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2169 int output_bpp;
2170 int min_bpp_x16, max_bpp_x16, bpp_step_x16;
2171 int dsc_joiner_max_bpp;
2172 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state: pipe_config);
2173 int bpp_x16;
2174 int ret;
2175
2176 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock: adjusted_mode->clock,
2177 mode_hdisplay: adjusted_mode->hdisplay,
2178 num_joined_pipes);
2179 max_bpp_x16 = min(fxp_q4_from_int(dsc_joiner_max_bpp), limits->link.max_bpp_x16);
2180
2181 bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector);
2182
2183 /* Compressed BPP should be less than the Input DSC bpp */
2184 output_bpp = intel_dp_output_bpp(output_format: pipe_config->output_format, bpp: pipe_bpp);
2185 max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16);
2186
2187 drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16));
2188 min_bpp_x16 = round_up(limits->link.min_bpp_x16, bpp_step_x16);
2189 max_bpp_x16 = round_down(max_bpp_x16, bpp_step_x16);
2190
2191 for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) {
2192 if (!intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16))
2193 continue;
2194
2195 ret = dsc_compute_link_config(intel_dp,
2196 pipe_config,
2197 conn_state,
2198 limits,
2199 dsc_bpp_x16: bpp_x16,
2200 timeslots);
2201 if (ret == 0) {
2202 pipe_config->dsc.compressed_bpp_x16 = bpp_x16;
2203 if (intel_dp->force_dsc_fractional_bpp_en &&
2204 fxp_q4_to_frac(val_q4: bpp_x16))
2205 drm_dbg_kms(display->drm,
2206 "Forcing DSC fractional bpp\n");
2207
2208 return 0;
2209 }
2210 }
2211
2212 return -EINVAL;
2213}
2214
2215int intel_dp_dsc_min_src_input_bpc(void)
2216{
2217 /* Min DSC Input BPC for ICL+ is 8 */
2218 return 8;
2219}
2220
2221static
2222bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits,
2223 int pipe_bpp)
2224{
2225 return pipe_bpp >= limits->pipe.min_bpp &&
2226 pipe_bpp <= limits->pipe.max_bpp;
2227}
2228
2229static
2230int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2231 const struct link_config_limits *limits)
2232{
2233 struct intel_display *display = to_intel_display(intel_dp);
2234 int forced_bpp;
2235
2236 if (!intel_dp->force_dsc_bpc)
2237 return 0;
2238
2239 forced_bpp = intel_dp->force_dsc_bpc * 3;
2240
2241 if (is_dsc_pipe_bpp_sufficient(limits, pipe_bpp: forced_bpp)) {
2242 drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",
2243 intel_dp->force_dsc_bpc);
2244 return forced_bpp;
2245 }
2246
2247 drm_dbg_kms(display->drm,
2248 "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2249 intel_dp->force_dsc_bpc);
2250
2251 return 0;
2252}
2253
2254static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2255 struct intel_crtc_state *pipe_config,
2256 struct drm_connector_state *conn_state,
2257 const struct link_config_limits *limits,
2258 int timeslots)
2259{
2260 const struct intel_connector *connector =
2261 to_intel_connector(conn_state->connector);
2262 u8 dsc_bpc[3] = {};
2263 int forced_bpp, pipe_bpp;
2264 int num_bpc, i, ret;
2265
2266 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
2267
2268 if (forced_bpp) {
2269 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state,
2270 limits, pipe_bpp: forced_bpp, timeslots);
2271 if (ret == 0) {
2272 pipe_config->pipe_bpp = forced_bpp;
2273 return 0;
2274 }
2275 }
2276
2277 /*
2278 * Get the maximum DSC bpc that will be supported by any valid
2279 * link configuration and compressed bpp.
2280 */
2281 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(dsc_dpc: connector->dp.dsc_dpcd, dsc_bpc);
2282 for (i = 0; i < num_bpc; i++) {
2283 pipe_bpp = dsc_bpc[i] * 3;
2284 if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp)
2285 continue;
2286
2287 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state,
2288 limits, pipe_bpp, timeslots);
2289 if (ret == 0) {
2290 pipe_config->pipe_bpp = pipe_bpp;
2291 return 0;
2292 }
2293 }
2294
2295 return -EINVAL;
2296}
2297
2298static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2299 struct intel_crtc_state *pipe_config,
2300 struct drm_connector_state *conn_state,
2301 const struct link_config_limits *limits)
2302{
2303 struct intel_display *display = to_intel_display(intel_dp);
2304 struct intel_connector *connector =
2305 to_intel_connector(conn_state->connector);
2306 int pipe_bpp, forced_bpp;
2307 int dsc_min_bpp;
2308 int dsc_max_bpp;
2309
2310 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
2311
2312 if (forced_bpp) {
2313 pipe_bpp = forced_bpp;
2314 } else {
2315 int max_bpc = limits->pipe.max_bpp / 3;
2316
2317 /* For eDP use max bpp that can be supported with DSC. */
2318 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_req_bpc: max_bpc);
2319 if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {
2320 drm_dbg_kms(display->drm,
2321 "Computed BPC is not in DSC BPC limits\n");
2322 return -EINVAL;
2323 }
2324 }
2325 pipe_config->port_clock = limits->max_rate;
2326 pipe_config->lane_count = limits->max_lane_count;
2327
2328 dsc_min_bpp = fxp_q4_to_int_roundup(val_q4: limits->link.min_bpp_x16);
2329
2330 dsc_max_bpp = fxp_q4_to_int(val_q4: limits->link.max_bpp_x16);
2331
2332 /* Compressed BPP should be less than the Input DSC bpp */
2333 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2334
2335 pipe_config->dsc.compressed_bpp_x16 =
2336 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp));
2337
2338 pipe_config->pipe_bpp = pipe_bpp;
2339
2340 return 0;
2341}
2342
2343static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
2344 struct intel_crtc_state *crtc_state)
2345{
2346 if (crtc_state->fec_enable)
2347 return;
2348
2349 /*
2350 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.
2351 * Since, FEC is a bandwidth overhead, continue to not enable it for
2352 * eDP. Until, there is a good reason to do so.
2353 */
2354 if (intel_dp_is_edp(intel_dp))
2355 return;
2356
2357 if (intel_dp_is_uhbr(crtc_state))
2358 return;
2359
2360 crtc_state->fec_enable = true;
2361}
2362
2363int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2364 struct intel_crtc_state *pipe_config,
2365 struct drm_connector_state *conn_state,
2366 const struct link_config_limits *limits,
2367 int timeslots)
2368{
2369 struct intel_display *display = to_intel_display(intel_dp);
2370 const struct intel_connector *connector =
2371 to_intel_connector(conn_state->connector);
2372 const struct drm_display_mode *adjusted_mode =
2373 &pipe_config->hw.adjusted_mode;
2374 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state: pipe_config);
2375 bool is_mst = intel_crtc_has_type(crtc_state: pipe_config, type: INTEL_OUTPUT_DP_MST);
2376 int ret;
2377
2378 intel_dp_fec_compute_config(intel_dp, crtc_state: pipe_config);
2379
2380 if (!intel_dp_dsc_supports_format(connector, output_format: pipe_config->output_format))
2381 return -EINVAL;
2382
2383 /*
2384 * Link parameters, pipe bpp and compressed bpp have already been
2385 * figured out for DP MST DSC.
2386 */
2387 if (!is_mst) {
2388 if (intel_dp_is_edp(intel_dp))
2389 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2390 conn_state, limits);
2391 else
2392 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2393 conn_state, limits, timeslots);
2394 if (ret) {
2395 drm_dbg_kms(display->drm,
2396 "No Valid pipe bpp for given mode ret = %d\n", ret);
2397 return ret;
2398 }
2399 }
2400
2401 /* Calculate Slice count */
2402 if (intel_dp_is_edp(intel_dp)) {
2403 pipe_config->dsc.slice_count =
2404 drm_dp_dsc_sink_max_slice_count(dsc_dpcd: connector->dp.dsc_dpcd,
2405 is_edp: true);
2406 if (!pipe_config->dsc.slice_count) {
2407 drm_dbg_kms(display->drm,
2408 "Unsupported Slice Count %d\n",
2409 pipe_config->dsc.slice_count);
2410 return -EINVAL;
2411 }
2412 } else {
2413 u8 dsc_dp_slice_count;
2414
2415 dsc_dp_slice_count =
2416 intel_dp_dsc_get_slice_count(connector,
2417 mode_clock: adjusted_mode->crtc_clock,
2418 mode_hdisplay: adjusted_mode->crtc_hdisplay,
2419 num_joined_pipes);
2420 if (!dsc_dp_slice_count) {
2421 drm_dbg_kms(display->drm,
2422 "Compressed Slice Count not supported\n");
2423 return -EINVAL;
2424 }
2425
2426 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2427 }
2428 /*
2429 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2430 * is greater than the maximum Cdclock and if slice count is even
2431 * then we need to use 2 VDSC instances.
2432 * In case of Ultrajoiner along with 12 slices we need to use 3
2433 * VDSC instances.
2434 */
2435 if (pipe_config->joiner_pipes && num_joined_pipes == 4 &&
2436 pipe_config->dsc.slice_count == 12)
2437 pipe_config->dsc.num_streams = 3;
2438 else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
2439 pipe_config->dsc.num_streams = 2;
2440 else
2441 pipe_config->dsc.num_streams = 1;
2442
2443 ret = intel_dp_dsc_compute_params(connector, crtc_state: pipe_config);
2444 if (ret < 0) {
2445 drm_dbg_kms(display->drm,
2446 "Cannot compute valid DSC parameters for Input Bpp = %d"
2447 "Compressed BPP = " FXP_Q4_FMT "\n",
2448 pipe_config->pipe_bpp,
2449 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));
2450 return ret;
2451 }
2452
2453 pipe_config->dsc.compression_enable = true;
2454 drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "
2455 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
2456 pipe_config->pipe_bpp,
2457 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2458 pipe_config->dsc.slice_count);
2459
2460 return 0;
2461}
2462
2463/*
2464 * Calculate the output link min, max bpp values in limits based on the pipe bpp
2465 * range, crtc_state and dsc mode. Return true on success.
2466 */
2467static bool
2468intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2469 const struct intel_connector *connector,
2470 const struct intel_crtc_state *crtc_state,
2471 bool dsc,
2472 struct link_config_limits *limits)
2473{
2474 struct intel_display *display = to_intel_display(intel_dp);
2475 const struct drm_display_mode *adjusted_mode =
2476 &crtc_state->hw.adjusted_mode;
2477 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2478 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2479 int max_link_bpp_x16;
2480
2481 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2482 fxp_q4_from_int(limits->pipe.max_bpp));
2483
2484 if (!dsc) {
2485 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3));
2486
2487 if (max_link_bpp_x16 < fxp_q4_from_int(val_int: limits->pipe.min_bpp))
2488 return false;
2489
2490 limits->link.min_bpp_x16 = fxp_q4_from_int(val_int: limits->pipe.min_bpp);
2491 } else {
2492 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2493 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2494
2495 dsc_src_min_bpp = intel_dp_dsc_min_src_compressed_bpp();
2496 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config: crtc_state);
2497 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2498 limits->link.min_bpp_x16 = fxp_q4_from_int(val_int: dsc_min_bpp);
2499
2500 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2501 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2502 pipe_config: crtc_state,
2503 bpc: limits->pipe.max_bpp / 3);
2504 dsc_max_bpp = dsc_sink_max_bpp ?
2505 min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2506
2507 max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
2508 }
2509
2510 limits->link.max_bpp_x16 = max_link_bpp_x16;
2511
2512 drm_dbg_kms(display->drm,
2513 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
2514 encoder->base.base.id, encoder->base.name,
2515 crtc->base.base.id, crtc->base.name,
2516 adjusted_mode->crtc_clock,
2517 str_on_off(dsc),
2518 limits->max_lane_count,
2519 limits->max_rate,
2520 limits->pipe.max_bpp,
2521 FXP_Q4_ARGS(limits->link.max_bpp_x16));
2522
2523 return true;
2524}
2525
2526static void
2527intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp,
2528 struct link_config_limits *limits)
2529{
2530 struct intel_display *display = to_intel_display(intel_dp);
2531 int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc();
2532 int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
2533
2534 limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);
2535 limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);
2536}
2537
2538bool
2539intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2540 struct drm_connector_state *conn_state,
2541 struct intel_crtc_state *crtc_state,
2542 bool respect_downstream_limits,
2543 bool dsc,
2544 struct link_config_limits *limits)
2545{
2546 bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
2547 struct intel_connector *connector =
2548 to_intel_connector(conn_state->connector);
2549
2550 limits->min_rate = intel_dp_min_link_rate(intel_dp);
2551 limits->max_rate = intel_dp_max_link_rate(intel_dp);
2552
2553 limits->min_rate = min(limits->min_rate, limits->max_rate);
2554
2555 limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
2556 limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2557
2558 limits->pipe.min_bpp = intel_dp_in_hdr_mode(conn_state) ? 30 :
2559 intel_dp_min_bpp(output_format: crtc_state->output_format);
2560 if (is_mst) {
2561 /*
2562 * FIXME: If all the streams can't fit into the link with their
2563 * current pipe_bpp we should reduce pipe_bpp across the board
2564 * until things start to fit. Until then we limit to <= 8bpc
2565 * since that's what was hardcoded for all MST streams
2566 * previously. This hack should be removed once we have the
2567 * proper retry logic in place.
2568 */
2569 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
2570 } else {
2571 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2572 respect_downstream_limits);
2573 }
2574
2575 if (dsc)
2576 intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits);
2577
2578 if (is_mst || intel_dp->use_max_params) {
2579 /*
2580 * For MST we always configure max link bw - the spec doesn't
2581 * seem to suggest we should do otherwise.
2582 *
2583 * Use the maximum clock and number of lanes the eDP panel
2584 * advertizes being capable of in case the initial fast
2585 * optimal params failed us. The panels are generally
2586 * designed to support only a single clock and lane
2587 * configuration, and typically on older panels these
2588 * values correspond to the native resolution of the panel.
2589 */
2590 limits->min_lane_count = limits->max_lane_count;
2591 limits->min_rate = limits->max_rate;
2592 }
2593
2594 intel_dp_test_compute_config(intel_dp, pipe_config: crtc_state, limits);
2595
2596 return intel_dp_compute_config_link_bpp_limits(intel_dp,
2597 connector,
2598 crtc_state,
2599 dsc,
2600 limits);
2601}
2602
2603int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
2604{
2605 const struct drm_display_mode *adjusted_mode =
2606 &crtc_state->hw.adjusted_mode;
2607 int bpp = crtc_state->dsc.compression_enable ?
2608 fxp_q4_to_int_roundup(val_q4: crtc_state->dsc.compressed_bpp_x16) :
2609 crtc_state->pipe_bpp;
2610
2611 return intel_dp_link_required(pixel_clock: adjusted_mode->crtc_clock, bpp);
2612}
2613
2614bool intel_dp_joiner_needs_dsc(struct intel_display *display,
2615 int num_joined_pipes)
2616{
2617 /*
2618 * Pipe joiner needs compression up to display 12 due to bandwidth
2619 * limitation. DG2 onwards pipe joiner can be enabled without
2620 * compression.
2621 * Ultrajoiner always needs compression.
2622 */
2623 return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||
2624 num_joined_pipes == 4;
2625}
2626
2627static int
2628intel_dp_compute_link_config(struct intel_encoder *encoder,
2629 struct intel_crtc_state *pipe_config,
2630 struct drm_connector_state *conn_state,
2631 bool respect_downstream_limits)
2632{
2633 struct intel_display *display = to_intel_display(encoder);
2634 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2635 struct intel_connector *connector =
2636 to_intel_connector(conn_state->connector);
2637 const struct drm_display_mode *adjusted_mode =
2638 &pipe_config->hw.adjusted_mode;
2639 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2640 struct link_config_limits limits;
2641 bool dsc_needed, joiner_needs_dsc;
2642 int num_joined_pipes;
2643 int ret = 0;
2644
2645 if (pipe_config->fec_enable &&
2646 !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2647 return -EINVAL;
2648
2649 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
2650 hdisplay: adjusted_mode->crtc_hdisplay,
2651 clock: adjusted_mode->crtc_clock);
2652 if (num_joined_pipes > 1)
2653 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
2654
2655 joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
2656
2657 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2658 !intel_dp_compute_config_limits(intel_dp, conn_state, crtc_state: pipe_config,
2659 respect_downstream_limits,
2660 dsc: false,
2661 limits: &limits);
2662
2663 if (!dsc_needed) {
2664 /*
2665 * Optimize for slow and wide for everything, because there are some
2666 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2667 */
2668 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2669 conn_state, limits: &limits);
2670 if (!ret && intel_dp_is_uhbr(crtc_state: pipe_config))
2671 ret = intel_dp_mtp_tu_compute_config(intel_dp,
2672 crtc_state: pipe_config,
2673 conn_state,
2674 min_bpp_x16: fxp_q4_from_int(val_int: pipe_config->pipe_bpp),
2675 max_bpp_x16: fxp_q4_from_int(val_int: pipe_config->pipe_bpp),
2676 bpp_step_x16: 0, dsc: false);
2677 if (ret)
2678 dsc_needed = true;
2679 }
2680
2681 if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, crtc_state: pipe_config)) {
2682 drm_dbg_kms(display->drm, "DSC required but not available\n");
2683 return -EINVAL;
2684 }
2685
2686 if (dsc_needed) {
2687 drm_dbg_kms(display->drm,
2688 "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2689 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2690 str_yes_no(intel_dp->force_dsc_en));
2691
2692 if (!intel_dp_compute_config_limits(intel_dp, conn_state, crtc_state: pipe_config,
2693 respect_downstream_limits,
2694 dsc: true,
2695 limits: &limits))
2696 return -EINVAL;
2697
2698 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2699 conn_state, limits: &limits, timeslots: 64);
2700 if (ret < 0)
2701 return ret;
2702 }
2703
2704 drm_dbg_kms(display->drm,
2705 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
2706 pipe_config->lane_count, pipe_config->port_clock,
2707 pipe_config->pipe_bpp,
2708 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2709 intel_dp_config_required_rate(pipe_config),
2710 intel_dp_max_link_data_rate(intel_dp,
2711 pipe_config->port_clock,
2712 pipe_config->lane_count));
2713
2714 return 0;
2715}
2716
2717bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2718 const struct drm_connector_state *conn_state)
2719{
2720 const struct intel_digital_connector_state *intel_conn_state =
2721 to_intel_digital_connector_state(conn_state);
2722 const struct drm_display_mode *adjusted_mode =
2723 &crtc_state->hw.adjusted_mode;
2724
2725 /*
2726 * Our YCbCr output is always limited range.
2727 * crtc_state->limited_color_range only applies to RGB,
2728 * and it must never be set for YCbCr or we risk setting
2729 * some conflicting bits in TRANSCONF which will mess up
2730 * the colors on the monitor.
2731 */
2732 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2733 return false;
2734
2735 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2736 /*
2737 * See:
2738 * CEA-861-E - 5.1 Default Encoding Parameters
2739 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2740 */
2741 return crtc_state->pipe_bpp != 18 &&
2742 drm_default_rgb_quant_range(mode: adjusted_mode) ==
2743 HDMI_QUANTIZATION_RANGE_LIMITED;
2744 } else {
2745 return intel_conn_state->broadcast_rgb ==
2746 INTEL_BROADCAST_RGB_LIMITED;
2747 }
2748}
2749
2750static bool intel_dp_port_has_audio(struct intel_display *display, enum port port)
2751{
2752 if (display->platform.g4x)
2753 return false;
2754 if (DISPLAY_VER(display) < 12 && port == PORT_A)
2755 return false;
2756
2757 return true;
2758}
2759
2760static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2761 const struct drm_connector_state *conn_state,
2762 struct drm_dp_vsc_sdp *vsc)
2763{
2764 struct intel_display *display = to_intel_display(crtc_state);
2765
2766 if (crtc_state->has_panel_replay) {
2767 /*
2768 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2769 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2770 * Encoding/Colorimetry Format indication.
2771 */
2772 vsc->revision = 0x7;
2773 } else {
2774 /*
2775 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2776 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2777 * Colorimetry Format indication.
2778 */
2779 vsc->revision = 0x5;
2780 }
2781
2782 vsc->length = 0x13;
2783
2784 /* DP 1.4a spec, Table 2-120 */
2785 switch (crtc_state->output_format) {
2786 case INTEL_OUTPUT_FORMAT_YCBCR444:
2787 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2788 break;
2789 case INTEL_OUTPUT_FORMAT_YCBCR420:
2790 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2791 break;
2792 case INTEL_OUTPUT_FORMAT_RGB:
2793 default:
2794 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2795 }
2796
2797 switch (conn_state->colorspace) {
2798 case DRM_MODE_COLORIMETRY_BT709_YCC:
2799 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2800 break;
2801 case DRM_MODE_COLORIMETRY_XVYCC_601:
2802 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2803 break;
2804 case DRM_MODE_COLORIMETRY_XVYCC_709:
2805 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2806 break;
2807 case DRM_MODE_COLORIMETRY_SYCC_601:
2808 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2809 break;
2810 case DRM_MODE_COLORIMETRY_OPYCC_601:
2811 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2812 break;
2813 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2814 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2815 break;
2816 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2817 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2818 break;
2819 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2820 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2821 break;
2822 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2823 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2824 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2825 break;
2826 default:
2827 /*
2828 * RGB->YCBCR color conversion uses the BT.709
2829 * color space.
2830 */
2831 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2832 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2833 else
2834 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2835 break;
2836 }
2837
2838 vsc->bpc = crtc_state->pipe_bpp / 3;
2839
2840 /* only RGB pixelformat supports 6 bpc */
2841 drm_WARN_ON(display->drm,
2842 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2843
2844 /* all YCbCr are always limited range */
2845 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2846 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2847}
2848
2849static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
2850 struct intel_crtc_state *crtc_state)
2851{
2852 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
2853 const struct drm_display_mode *adjusted_mode =
2854 &crtc_state->hw.adjusted_mode;
2855
2856 if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
2857 return;
2858
2859 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
2860
2861 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
2862 as_sdp->length = 0x9;
2863 as_sdp->duration_incr_ms = 0;
2864 as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
2865
2866 if (crtc_state->cmrr.enable) {
2867 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
2868 as_sdp->target_rr = drm_mode_vrefresh(mode: adjusted_mode);
2869 as_sdp->target_rr_divider = true;
2870 } else {
2871 as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
2872 as_sdp->target_rr = 0;
2873 }
2874}
2875
2876static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2877 struct intel_crtc_state *crtc_state,
2878 const struct drm_connector_state *conn_state)
2879{
2880 struct drm_dp_vsc_sdp *vsc;
2881
2882 if ((!intel_dp->colorimetry_support ||
2883 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2884 !crtc_state->has_psr)
2885 return;
2886
2887 vsc = &crtc_state->infoframes.vsc;
2888
2889 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2890 vsc->sdp_type = DP_SDP_VSC;
2891
2892 /* Needs colorimetry */
2893 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2894 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2895 vsc);
2896 } else if (crtc_state->has_panel_replay) {
2897 /*
2898 * [Panel Replay without colorimetry info]
2899 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2900 * VSC SDP supporting 3D stereo + Panel Replay.
2901 */
2902 vsc->revision = 0x6;
2903 vsc->length = 0x10;
2904 } else if (crtc_state->has_sel_update) {
2905 /*
2906 * [PSR2 without colorimetry]
2907 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2908 * 3D stereo + PSR/PSR2 + Y-coordinate.
2909 */
2910 vsc->revision = 0x4;
2911 vsc->length = 0xe;
2912 } else {
2913 /*
2914 * [PSR1]
2915 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2916 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2917 * higher).
2918 */
2919 vsc->revision = 0x2;
2920 vsc->length = 0x8;
2921 }
2922}
2923
2924bool
2925intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
2926{
2927 struct hdr_output_metadata *hdr_metadata;
2928
2929 if (!conn_state->hdr_output_metadata)
2930 return false;
2931
2932 hdr_metadata = conn_state->hdr_output_metadata->data;
2933
2934 return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
2935}
2936
2937static void
2938intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2939 struct intel_crtc_state *crtc_state,
2940 const struct drm_connector_state *conn_state)
2941{
2942 struct intel_display *display = to_intel_display(intel_dp);
2943 int ret;
2944 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2945
2946 if (!conn_state->hdr_output_metadata)
2947 return;
2948
2949 ret = drm_hdmi_infoframe_set_hdr_metadata(frame: drm_infoframe, conn_state);
2950
2951 if (ret) {
2952 drm_dbg_kms(display->drm,
2953 "couldn't set HDR metadata in infoframe\n");
2954 return;
2955 }
2956
2957 crtc_state->infoframes.enable |=
2958 intel_hdmi_infoframe_enable(type: HDMI_PACKET_TYPE_GAMUT_METADATA);
2959}
2960
2961static bool can_enable_drrs(struct intel_connector *connector,
2962 const struct intel_crtc_state *pipe_config,
2963 const struct drm_display_mode *downclock_mode)
2964{
2965 struct intel_display *display = to_intel_display(connector);
2966
2967 if (pipe_config->vrr.enable)
2968 return false;
2969
2970 /*
2971 * DRRS and PSR can't be enable together, so giving preference to PSR
2972 * as it allows more power-savings by complete shutting down display,
2973 * so to guarantee this, intel_drrs_compute_config() must be called
2974 * after intel_psr_compute_config().
2975 */
2976 if (pipe_config->has_psr)
2977 return false;
2978
2979 /* FIXME missing FDI M2/N2 etc. */
2980 if (pipe_config->has_pch_encoder)
2981 return false;
2982
2983 if (!intel_cpu_transcoder_has_drrs(display, cpu_transcoder: pipe_config->cpu_transcoder))
2984 return false;
2985
2986 return downclock_mode &&
2987 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2988}
2989
2990static void
2991intel_dp_drrs_compute_config(struct intel_connector *connector,
2992 struct intel_crtc_state *pipe_config,
2993 int link_bpp_x16)
2994{
2995 struct intel_display *display = to_intel_display(connector);
2996 const struct drm_display_mode *downclock_mode =
2997 intel_panel_downclock_mode(connector, adjusted_mode: &pipe_config->hw.adjusted_mode);
2998 int pixel_clock;
2999
3000 /*
3001 * FIXME all joined pipes share the same transcoder.
3002 * Need to account for that when updating M/N live.
3003 */
3004 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
3005 pipe_config->update_m_n = true;
3006
3007 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
3008 if (intel_cpu_transcoder_has_m2_n2(display, transcoder: pipe_config->cpu_transcoder))
3009 intel_zero_m_n(m_n: &pipe_config->dp_m2_n2);
3010 return;
3011 }
3012
3013 if (display->platform.ironlake || display->platform.sandybridge ||
3014 display->platform.ivybridge)
3015 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
3016
3017 pipe_config->has_drrs = true;
3018
3019 pixel_clock = downclock_mode->clock;
3020 if (pipe_config->splitter.enable)
3021 pixel_clock /= pipe_config->splitter.link_count;
3022
3023 intel_link_compute_m_n(bpp: link_bpp_x16, nlanes: pipe_config->lane_count, pixel_clock,
3024 link_clock: pipe_config->port_clock,
3025 bw_overhead: intel_dp_bw_fec_overhead(fec_enabled: pipe_config->fec_enable),
3026 m_n: &pipe_config->dp_m2_n2);
3027
3028 /* FIXME: abstract this better */
3029 if (pipe_config->splitter.enable)
3030 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
3031}
3032
3033static bool intel_dp_has_audio(struct intel_encoder *encoder,
3034 const struct drm_connector_state *conn_state)
3035{
3036 struct intel_display *display = to_intel_display(encoder);
3037 const struct intel_digital_connector_state *intel_conn_state =
3038 to_intel_digital_connector_state(conn_state);
3039 struct intel_connector *connector =
3040 to_intel_connector(conn_state->connector);
3041
3042 if (!intel_dp_port_has_audio(display, port: encoder->port))
3043 return false;
3044
3045 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
3046 return connector->base.display_info.has_audio;
3047 else
3048 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
3049}
3050
3051static int
3052intel_dp_compute_output_format(struct intel_encoder *encoder,
3053 struct intel_crtc_state *crtc_state,
3054 struct drm_connector_state *conn_state,
3055 bool respect_downstream_limits)
3056{
3057 struct intel_display *display = to_intel_display(encoder);
3058 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3059 struct intel_connector *connector = intel_dp->attached_connector;
3060 const struct drm_display_info *info = &connector->base.display_info;
3061 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
3062 bool ycbcr_420_only;
3063 int ret;
3064
3065 ycbcr_420_only = drm_mode_is_420_only(display: info, mode: adjusted_mode);
3066
3067 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
3068 drm_dbg_kms(display->drm,
3069 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
3070 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
3071 } else {
3072 crtc_state->sink_format = intel_dp_sink_format(connector, mode: adjusted_mode);
3073 }
3074
3075 crtc_state->output_format = intel_dp_output_format(connector, sink_format: crtc_state->sink_format);
3076
3077 ret = intel_dp_compute_link_config(encoder, pipe_config: crtc_state, conn_state,
3078 respect_downstream_limits);
3079 if (ret) {
3080 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3081 !connector->base.ycbcr_420_allowed ||
3082 !drm_mode_is_420_also(display: info, mode: adjusted_mode))
3083 return ret;
3084
3085 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
3086 crtc_state->output_format = intel_dp_output_format(connector,
3087 sink_format: crtc_state->sink_format);
3088 ret = intel_dp_compute_link_config(encoder, pipe_config: crtc_state, conn_state,
3089 respect_downstream_limits);
3090 }
3091
3092 return ret;
3093}
3094
3095void
3096intel_dp_audio_compute_config(struct intel_encoder *encoder,
3097 struct intel_crtc_state *pipe_config,
3098 struct drm_connector_state *conn_state)
3099{
3100 pipe_config->has_audio =
3101 intel_dp_has_audio(encoder, conn_state) &&
3102 intel_audio_compute_config(encoder, crtc_state: pipe_config, conn_state);
3103
3104 pipe_config->sdp_split_enable = pipe_config->has_audio &&
3105 intel_dp_is_uhbr(crtc_state: pipe_config);
3106}
3107
3108void
3109intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
3110 struct intel_encoder *encoder,
3111 const struct intel_crtc_state *crtc_state)
3112{
3113 struct intel_connector *connector;
3114 struct intel_digital_connector_state *conn_state;
3115 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3116 int i;
3117
3118 if (intel_dp->needs_modeset_retry)
3119 return;
3120
3121 intel_dp->needs_modeset_retry = true;
3122
3123 if (!intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST)) {
3124 intel_connector_queue_modeset_retry_work(connector: intel_dp->attached_connector);
3125
3126 return;
3127 }
3128
3129 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
3130 if (!conn_state->base.crtc)
3131 continue;
3132
3133 if (connector->mst.dp == intel_dp)
3134 intel_connector_queue_modeset_retry_work(connector);
3135 }
3136}
3137
3138int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
3139 const struct drm_connector_state *conn_state)
3140{
3141 struct intel_display *display = to_intel_display(crtc_state);
3142 const struct drm_display_mode *adjusted_mode =
3143 &crtc_state->hw.adjusted_mode;
3144 struct intel_connector *connector = to_intel_connector(conn_state->connector);
3145 int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
3146 /*
3147 * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and
3148 * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b
3149 */
3150 int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5;
3151 bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
3152 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
3153 int min_hblank;
3154 int max_lane_count = 4;
3155 int hactive_sym_cycles, htotal_sym_cycles;
3156 int dsc_slices = 0;
3157 int link_bpp_x16;
3158
3159 if (DISPLAY_VER(display) < 30)
3160 return 0;
3161
3162 /* MIN_HBLANK should be set only for 8b/10b MST or for 128b/132b SST/MST */
3163 if (!is_mst && !intel_dp_is_uhbr(crtc_state))
3164 return 0;
3165
3166 if (crtc_state->dsc.compression_enable) {
3167 dsc_slices = intel_dp_dsc_get_slice_count(connector,
3168 mode_clock: adjusted_mode->crtc_clock,
3169 mode_hdisplay: adjusted_mode->crtc_hdisplay,
3170 num_joined_pipes);
3171 if (!dsc_slices) {
3172 drm_dbg(display->drm, "failed to calculate dsc slice count\n");
3173 return -EINVAL;
3174 }
3175 }
3176
3177 if (crtc_state->dsc.compression_enable)
3178 link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
3179 else
3180 link_bpp_x16 = fxp_q4_from_int(val_int: intel_dp_output_bpp(output_format: crtc_state->output_format,
3181 bpp: crtc_state->pipe_bpp));
3182
3183 /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
3184 hactive_sym_cycles = drm_dp_link_symbol_cycles(lane_count: max_lane_count,
3185 pixels: adjusted_mode->hdisplay,
3186 dsc_slice_count: dsc_slices,
3187 bpp_x16: link_bpp_x16,
3188 symbol_size, is_mst);
3189 htotal_sym_cycles = adjusted_mode->htotal * hactive_sym_cycles /
3190 adjusted_mode->hdisplay;
3191
3192 min_hblank = htotal_sym_cycles - hactive_sym_cycles;
3193 /* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */
3194 min_hblank = max(min_hblank, min_sym_cycles);
3195
3196 /*
3197 * adjust the BlankingStart/BlankingEnd framing control from
3198 * the calculated value
3199 */
3200 min_hblank = min_hblank - 2;
3201
3202 /*
3203 * min_hblank formula is undergoing a change, to avoid underrun use the
3204 * recomended value in spec to compare with the calculated one and use the
3205 * minimum value
3206 */
3207 if (intel_dp_is_uhbr(crtc_state)) {
3208 /*
3209 * Note: Bspec requires a min_hblank of 2 for YCBCR420
3210 * with compressed bpp 6, but the minimum compressed bpp
3211 * supported by the driver is 8.
3212 */
3213 drm_WARN_ON(display->drm,
3214 (crtc_state->dsc.compression_enable &&
3215 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
3216 crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8)));
3217 min_hblank = min(3, min_hblank);
3218 } else {
3219 min_hblank = min(10, min_hblank);
3220 }
3221
3222 crtc_state->min_hblank = min_hblank;
3223
3224 return 0;
3225}
3226
3227int
3228intel_dp_compute_config(struct intel_encoder *encoder,
3229 struct intel_crtc_state *pipe_config,
3230 struct drm_connector_state *conn_state)
3231{
3232 struct intel_display *display = to_intel_display(encoder);
3233 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
3234 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
3235 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3236 const struct drm_display_mode *fixed_mode;
3237 struct intel_connector *connector = intel_dp->attached_connector;
3238 int ret = 0, link_bpp_x16;
3239
3240 fixed_mode = intel_panel_fixed_mode(connector, mode: adjusted_mode);
3241 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
3242 ret = intel_panel_compute_config(connector, adjusted_mode);
3243 if (ret)
3244 return ret;
3245 }
3246
3247 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
3248 return -EINVAL;
3249
3250 if (!connector->base.interlace_allowed &&
3251 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
3252 return -EINVAL;
3253
3254 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
3255 return -EINVAL;
3256
3257 if (intel_dp_hdisplay_bad(display, hdisplay: adjusted_mode->crtc_hdisplay))
3258 return -EINVAL;
3259
3260 /*
3261 * Try to respect downstream TMDS clock limits first, if
3262 * that fails assume the user might know something we don't.
3263 */
3264 ret = intel_dp_compute_output_format(encoder, crtc_state: pipe_config, conn_state, respect_downstream_limits: true);
3265 if (ret)
3266 ret = intel_dp_compute_output_format(encoder, crtc_state: pipe_config, conn_state, respect_downstream_limits: false);
3267 if (ret)
3268 return ret;
3269
3270 if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
3271 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3272 ret = intel_pfit_compute_config(crtc_state: pipe_config, conn_state);
3273 if (ret)
3274 return ret;
3275 }
3276
3277 pipe_config->limited_color_range =
3278 intel_dp_limited_color_range(crtc_state: pipe_config, conn_state);
3279
3280 if (intel_dp_is_uhbr(crtc_state: pipe_config)) {
3281 /* 128b/132b SST also needs this */
3282 pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
3283 } else {
3284 pipe_config->enhanced_framing =
3285 drm_dp_enhanced_frame_cap(dpcd: intel_dp->dpcd);
3286 }
3287
3288 if (pipe_config->dsc.compression_enable)
3289 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
3290 else
3291 link_bpp_x16 = fxp_q4_from_int(val_int: intel_dp_output_bpp(output_format: pipe_config->output_format,
3292 bpp: pipe_config->pipe_bpp));
3293
3294 if (intel_dp->mso_link_count) {
3295 int n = intel_dp->mso_link_count;
3296 int overlap = intel_dp->mso_pixel_overlap;
3297
3298 pipe_config->splitter.enable = true;
3299 pipe_config->splitter.link_count = n;
3300 pipe_config->splitter.pixel_overlap = overlap;
3301
3302 drm_dbg_kms(display->drm,
3303 "MSO link count %d, pixel overlap %d\n",
3304 n, overlap);
3305
3306 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
3307 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
3308 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
3309 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
3310 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
3311 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
3312 adjusted_mode->crtc_clock /= n;
3313 }
3314
3315 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
3316
3317 if (!intel_dp_is_uhbr(crtc_state: pipe_config)) {
3318 intel_link_compute_m_n(bpp: link_bpp_x16,
3319 nlanes: pipe_config->lane_count,
3320 pixel_clock: adjusted_mode->crtc_clock,
3321 link_clock: pipe_config->port_clock,
3322 bw_overhead: intel_dp_bw_fec_overhead(fec_enabled: pipe_config->fec_enable),
3323 m_n: &pipe_config->dp_m_n);
3324 }
3325
3326 ret = intel_dp_compute_min_hblank(crtc_state: pipe_config, conn_state);
3327 if (ret)
3328 return ret;
3329
3330 /* FIXME: abstract this better */
3331 if (pipe_config->splitter.enable)
3332 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
3333
3334 intel_vrr_compute_config(crtc_state: pipe_config, conn_state);
3335 intel_dp_compute_as_sdp(intel_dp, crtc_state: pipe_config);
3336 intel_psr_compute_config(intel_dp, crtc_state: pipe_config, conn_state);
3337 intel_alpm_lobf_compute_config(intel_dp, crtc_state: pipe_config, conn_state);
3338 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
3339 intel_dp_compute_vsc_sdp(intel_dp, crtc_state: pipe_config, conn_state);
3340 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, crtc_state: pipe_config, conn_state);
3341
3342 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
3343 crtc_state: pipe_config);
3344}
3345
3346void intel_dp_set_link_params(struct intel_dp *intel_dp,
3347 int link_rate, int lane_count)
3348{
3349 memset(s: intel_dp->train_set, c: 0, n: sizeof(intel_dp->train_set));
3350 intel_dp->link.active = false;
3351 intel_dp->needs_modeset_retry = false;
3352 intel_dp->link_rate = link_rate;
3353 intel_dp->lane_count = lane_count;
3354}
3355
3356void intel_dp_reset_link_params(struct intel_dp *intel_dp)
3357{
3358 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
3359 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
3360 intel_dp->link.mst_probed_lane_count = 0;
3361 intel_dp->link.mst_probed_rate = 0;
3362 intel_dp->link.retrain_disabled = false;
3363 intel_dp->link.seq_train_failures = 0;
3364}
3365
3366/* Enable backlight PWM and backlight PP control. */
3367void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3368 const struct drm_connector_state *conn_state)
3369{
3370 struct intel_display *display = to_intel_display(crtc_state);
3371 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3372
3373 if (!intel_dp_is_edp(intel_dp))
3374 return;
3375
3376 drm_dbg_kms(display->drm, "\n");
3377
3378 intel_backlight_enable(crtc_state, conn_state);
3379 intel_pps_backlight_on(intel_dp);
3380}
3381
3382/* Disable backlight PP control and backlight PWM. */
3383void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3384{
3385 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3386 struct intel_display *display = to_intel_display(intel_dp);
3387
3388 if (!intel_dp_is_edp(intel_dp))
3389 return;
3390
3391 drm_dbg_kms(display->drm, "\n");
3392
3393 intel_pps_backlight_off(intel_dp);
3394 intel_backlight_disable(old_conn_state);
3395}
3396
3397static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3398{
3399 /*
3400 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3401 * be capable of signalling downstream hpd with a long pulse.
3402 * Whether or not that means D3 is safe to use is not clear,
3403 * but let's assume so until proven otherwise.
3404 *
3405 * FIXME should really check all downstream ports...
3406 */
3407 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3408 drm_dp_is_branch(dpcd: intel_dp->dpcd) &&
3409 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3410}
3411
3412static int
3413write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3414{
3415 int err;
3416 u8 val;
3417
3418 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, valuep: &val);
3419 if (err < 0)
3420 return err;
3421
3422 if (set)
3423 val |= flag;
3424 else
3425 val &= ~flag;
3426
3427 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, value: val);
3428}
3429
3430static void
3431intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3432 bool enable)
3433{
3434 struct intel_display *display = to_intel_display(connector);
3435
3436 if (write_dsc_decompression_flag(aux: connector->dp.dsc_decompression_aux,
3437 DP_DECOMPRESSION_EN, set: enable) < 0)
3438 drm_dbg_kms(display->drm,
3439 "Failed to %s sink decompression state\n",
3440 str_enable_disable(enable));
3441}
3442
3443static void
3444intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3445 bool enable)
3446{
3447 struct intel_display *display = to_intel_display(connector);
3448 struct drm_dp_aux *aux = connector->mst.port ?
3449 connector->mst.port->passthrough_aux : NULL;
3450
3451 if (!aux)
3452 return;
3453
3454 if (write_dsc_decompression_flag(aux,
3455 DP_DSC_PASSTHROUGH_EN, set: enable) < 0)
3456 drm_dbg_kms(display->drm,
3457 "Failed to %s sink compression passthrough state\n",
3458 str_enable_disable(enable));
3459}
3460
3461static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3462 const struct intel_connector *connector,
3463 bool for_get_ref)
3464{
3465 struct intel_display *display = to_intel_display(state);
3466 struct drm_connector *_connector_iter;
3467 struct drm_connector_state *old_conn_state;
3468 struct drm_connector_state *new_conn_state;
3469 int ref_count = 0;
3470 int i;
3471
3472 /*
3473 * On SST the decompression AUX device won't be shared, each connector
3474 * uses for this its own AUX targeting the sink device.
3475 */
3476 if (!connector->mst.dp)
3477 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3478
3479 for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3480 old_conn_state, new_conn_state, i) {
3481 const struct intel_connector *
3482 connector_iter = to_intel_connector(_connector_iter);
3483
3484 if (connector_iter->mst.dp != connector->mst.dp)
3485 continue;
3486
3487 if (!connector_iter->dp.dsc_decompression_enabled)
3488 continue;
3489
3490 drm_WARN_ON(display->drm,
3491 (for_get_ref && !new_conn_state->crtc) ||
3492 (!for_get_ref && !old_conn_state->crtc));
3493
3494 if (connector_iter->dp.dsc_decompression_aux ==
3495 connector->dp.dsc_decompression_aux)
3496 ref_count++;
3497 }
3498
3499 return ref_count;
3500}
3501
3502static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3503 struct intel_connector *connector)
3504{
3505 bool ret = intel_dp_dsc_aux_ref_count(state, connector, for_get_ref: true) == 0;
3506
3507 connector->dp.dsc_decompression_enabled = true;
3508
3509 return ret;
3510}
3511
3512static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3513 struct intel_connector *connector)
3514{
3515 connector->dp.dsc_decompression_enabled = false;
3516
3517 return intel_dp_dsc_aux_ref_count(state, connector, for_get_ref: false) == 0;
3518}
3519
3520/**
3521 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3522 * @state: atomic state
3523 * @connector: connector to enable the decompression for
3524 * @new_crtc_state: new state for the CRTC driving @connector
3525 *
3526 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3527 * register of the appropriate sink/branch device. On SST this is always the
3528 * sink device, whereas on MST based on each device's DSC capabilities it's
3529 * either the last branch device (enabling decompression in it) or both the
3530 * last branch device (enabling passthrough in it) and the sink device
3531 * (enabling decompression in it).
3532 */
3533void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3534 struct intel_connector *connector,
3535 const struct intel_crtc_state *new_crtc_state)
3536{
3537 struct intel_display *display = to_intel_display(state);
3538
3539 if (!new_crtc_state->dsc.compression_enable)
3540 return;
3541
3542 if (drm_WARN_ON(display->drm,
3543 !connector->dp.dsc_decompression_aux ||
3544 connector->dp.dsc_decompression_enabled))
3545 return;
3546
3547 if (!intel_dp_dsc_aux_get_ref(state, connector))
3548 return;
3549
3550 intel_dp_sink_set_dsc_passthrough(connector, enable: true);
3551 intel_dp_sink_set_dsc_decompression(connector, enable: true);
3552}
3553
3554/**
3555 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3556 * @state: atomic state
3557 * @connector: connector to disable the decompression for
3558 * @old_crtc_state: old state for the CRTC driving @connector
3559 *
3560 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3561 * register of the appropriate sink/branch device, corresponding to the
3562 * sequence in intel_dp_sink_enable_decompression().
3563 */
3564void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3565 struct intel_connector *connector,
3566 const struct intel_crtc_state *old_crtc_state)
3567{
3568 struct intel_display *display = to_intel_display(state);
3569
3570 if (!old_crtc_state->dsc.compression_enable)
3571 return;
3572
3573 if (drm_WARN_ON(display->drm,
3574 !connector->dp.dsc_decompression_aux ||
3575 !connector->dp.dsc_decompression_enabled))
3576 return;
3577
3578 if (!intel_dp_dsc_aux_put_ref(state, connector))
3579 return;
3580
3581 intel_dp_sink_set_dsc_decompression(connector, enable: false);
3582 intel_dp_sink_set_dsc_passthrough(connector, enable: false);
3583}
3584
3585static void
3586intel_dp_init_source_oui(struct intel_dp *intel_dp)
3587{
3588 struct intel_display *display = to_intel_display(intel_dp);
3589 u8 oui[] = { 0x00, 0xaa, 0x01 };
3590 u8 buf[3] = {};
3591
3592 if (READ_ONCE(intel_dp->oui_valid))
3593 return;
3594
3595 WRITE_ONCE(intel_dp->oui_valid, true);
3596
3597 /*
3598 * During driver init, we want to be careful and avoid changing the source OUI if it's
3599 * already set to what we want, so as to avoid clearing any state by accident
3600 */
3601 if (drm_dp_dpcd_read(aux: &intel_dp->aux, DP_SOURCE_OUI, buffer: buf, size: sizeof(buf)) < 0)
3602 drm_dbg_kms(display->drm, "Failed to read source OUI\n");
3603
3604 if (memcmp(oui, buf, sizeof(oui)) == 0) {
3605 /* Assume the OUI was written now. */
3606 intel_dp->last_oui_write = jiffies;
3607 return;
3608 }
3609
3610 if (drm_dp_dpcd_write(aux: &intel_dp->aux, DP_SOURCE_OUI, buffer: oui, size: sizeof(oui)) < 0) {
3611 drm_dbg_kms(display->drm, "Failed to write source OUI\n");
3612 WRITE_ONCE(intel_dp->oui_valid, false);
3613 }
3614
3615 intel_dp->last_oui_write = jiffies;
3616}
3617
3618void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp)
3619{
3620 WRITE_ONCE(intel_dp->oui_valid, false);
3621}
3622
3623void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3624{
3625 struct intel_display *display = to_intel_display(intel_dp);
3626 struct intel_connector *connector = intel_dp->attached_connector;
3627
3628 drm_dbg_kms(display->drm,
3629 "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3630 connector->base.base.id, connector->base.name,
3631 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3632
3633 wait_remaining_ms_from_jiffies(timestamp_jiffies: intel_dp->last_oui_write,
3634 to_wait_ms: connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3635}
3636
3637/* If the device supports it, try to set the power state appropriately */
3638void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3639{
3640 struct intel_display *display = to_intel_display(intel_dp);
3641 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3642 int ret, i;
3643
3644 /* Should have a valid DPCD by this point */
3645 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3646 return;
3647
3648 if (mode != DP_SET_POWER_D0) {
3649 if (downstream_hpd_needs_d0(intel_dp))
3650 return;
3651
3652 ret = drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_SET_POWER, value: mode);
3653 } else {
3654 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3655
3656 intel_lspcon_resume(dig_port);
3657
3658 /* Write the source OUI as early as possible */
3659 intel_dp_init_source_oui(intel_dp);
3660
3661 /*
3662 * When turning on, we need to retry for 1ms to give the sink
3663 * time to wake up.
3664 */
3665 for (i = 0; i < 3; i++) {
3666 ret = drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_SET_POWER, value: mode);
3667 if (ret == 1)
3668 break;
3669 msleep(msecs: 1);
3670 }
3671
3672 if (ret == 1 && intel_lspcon_active(dig_port))
3673 intel_lspcon_wait_pcon_mode(dig_port);
3674 }
3675
3676 if (ret != 1)
3677 drm_dbg_kms(display->drm,
3678 "[ENCODER:%d:%s] Set power to %s failed\n",
3679 encoder->base.base.id, encoder->base.name,
3680 mode == DP_SET_POWER_D0 ? "D0" : "D3");
3681}
3682
3683static bool
3684intel_dp_get_dpcd(struct intel_dp *intel_dp);
3685
3686/**
3687 * intel_dp_sync_state - sync the encoder state during init/resume
3688 * @encoder: intel encoder to sync
3689 * @crtc_state: state for the CRTC connected to the encoder
3690 *
3691 * Sync any state stored in the encoder wrt. HW state during driver init
3692 * and system resume.
3693 */
3694void intel_dp_sync_state(struct intel_encoder *encoder,
3695 const struct intel_crtc_state *crtc_state)
3696{
3697 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3698 bool dpcd_updated = false;
3699
3700 /*
3701 * Don't clobber DPCD if it's been already read out during output
3702 * setup (eDP) or detect.
3703 */
3704 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3705 intel_dp_get_dpcd(intel_dp);
3706 dpcd_updated = true;
3707 }
3708
3709 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
3710
3711 if (crtc_state) {
3712 intel_dp_reset_link_params(intel_dp);
3713 intel_dp_set_link_params(intel_dp, link_rate: crtc_state->port_clock, lane_count: crtc_state->lane_count);
3714 intel_dp->link.active = true;
3715 }
3716}
3717
3718bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3719 struct intel_crtc_state *crtc_state)
3720{
3721 struct intel_display *display = to_intel_display(encoder);
3722 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3723 bool fastset = true;
3724
3725 /*
3726 * If BIOS has set an unsupported or non-standard link rate for some
3727 * reason force an encoder recompute and full modeset.
3728 */
3729 if (intel_dp_rate_index(rates: intel_dp->source_rates, len: intel_dp->num_source_rates,
3730 rate: crtc_state->port_clock) < 0) {
3731 drm_dbg_kms(display->drm,
3732 "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3733 encoder->base.base.id, encoder->base.name);
3734 crtc_state->uapi.connectors_changed = true;
3735 fastset = false;
3736 }
3737
3738 /*
3739 * FIXME hack to force full modeset when DSC is being used.
3740 *
3741 * As long as we do not have full state readout and config comparison
3742 * of crtc_state->dsc, we have no way to ensure reliable fastset.
3743 * Remove once we have readout for DSC.
3744 */
3745 if (crtc_state->dsc.compression_enable) {
3746 drm_dbg_kms(display->drm,
3747 "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3748 encoder->base.base.id, encoder->base.name);
3749 crtc_state->uapi.mode_changed = true;
3750 fastset = false;
3751 }
3752
3753 if (CAN_PANEL_REPLAY(intel_dp)) {
3754 drm_dbg_kms(display->drm,
3755 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
3756 encoder->base.base.id, encoder->base.name);
3757 crtc_state->uapi.mode_changed = true;
3758 fastset = false;
3759 }
3760
3761 return fastset;
3762}
3763
3764static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3765{
3766 struct intel_display *display = to_intel_display(intel_dp);
3767
3768 /* Clear the cached register set to avoid using stale values */
3769
3770 memset(s: intel_dp->pcon_dsc_dpcd, c: 0, n: sizeof(intel_dp->pcon_dsc_dpcd));
3771
3772 if (!drm_dp_is_branch(dpcd: intel_dp->dpcd))
3773 return;
3774
3775 if (drm_dp_dpcd_read(aux: &intel_dp->aux, DP_PCON_DSC_ENCODER,
3776 buffer: intel_dp->pcon_dsc_dpcd,
3777 size: sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3778 drm_err(display->drm, "Failed to read DPCD register 0x%x\n",
3779 DP_PCON_DSC_ENCODER);
3780
3781 drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3782 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3783}
3784
3785static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3786{
3787 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3788 int i;
3789
3790 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3791 if (frl_bw_mask & (1 << i))
3792 return bw_gbps[i];
3793 }
3794 return 0;
3795}
3796
3797static int intel_dp_pcon_set_frl_mask(int max_frl)
3798{
3799 switch (max_frl) {
3800 case 48:
3801 return DP_PCON_FRL_BW_MASK_48GBPS;
3802 case 40:
3803 return DP_PCON_FRL_BW_MASK_40GBPS;
3804 case 32:
3805 return DP_PCON_FRL_BW_MASK_32GBPS;
3806 case 24:
3807 return DP_PCON_FRL_BW_MASK_24GBPS;
3808 case 18:
3809 return DP_PCON_FRL_BW_MASK_18GBPS;
3810 case 9:
3811 return DP_PCON_FRL_BW_MASK_9GBPS;
3812 }
3813
3814 return 0;
3815}
3816
3817static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3818{
3819 struct intel_connector *connector = intel_dp->attached_connector;
3820 const struct drm_display_info *info = &connector->base.display_info;
3821 int max_frl_rate;
3822 int max_lanes, rate_per_lane;
3823 int max_dsc_lanes, dsc_rate_per_lane;
3824
3825 max_lanes = info->hdmi.max_lanes;
3826 rate_per_lane = info->hdmi.max_frl_rate_per_lane;
3827 max_frl_rate = max_lanes * rate_per_lane;
3828
3829 if (info->hdmi.dsc_cap.v_1p2) {
3830 max_dsc_lanes = info->hdmi.dsc_cap.max_lanes;
3831 dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane;
3832 if (max_dsc_lanes && dsc_rate_per_lane)
3833 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3834 }
3835
3836 return max_frl_rate;
3837}
3838
3839static bool
3840intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3841 u8 max_frl_bw_mask, u8 *frl_trained_mask)
3842{
3843 if (drm_dp_pcon_hdmi_link_active(aux: &intel_dp->aux) &&
3844 drm_dp_pcon_hdmi_link_mode(aux: &intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3845 *frl_trained_mask >= max_frl_bw_mask)
3846 return true;
3847
3848 return false;
3849}
3850
3851static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3852{
3853 struct intel_display *display = to_intel_display(intel_dp);
3854#define TIMEOUT_FRL_READY_MS 500
3855#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3856 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3857 u8 max_frl_bw_mask = 0, frl_trained_mask;
3858 bool is_active;
3859
3860 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3861 drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3862
3863 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3864 drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",
3865 max_edid_frl_bw);
3866
3867 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3868
3869 if (max_frl_bw <= 0)
3870 return -EINVAL;
3871
3872 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl: max_frl_bw);
3873 drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3874
3875 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, frl_trained_mask: &frl_trained_mask))
3876 goto frl_trained;
3877
3878 ret = drm_dp_pcon_frl_prepare(aux: &intel_dp->aux, enable_frl_ready_hpd: false);
3879 if (ret < 0)
3880 return ret;
3881 /* Wait for PCON to be FRL Ready */
3882 ret = poll_timeout_us(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux),
3883 is_active,
3884 1000, TIMEOUT_FRL_READY_MS * 1000, false);
3885 if (ret)
3886 return ret;
3887
3888 ret = drm_dp_pcon_frl_configure_1(aux: &intel_dp->aux, max_frl_gbps: max_frl_bw,
3889 DP_PCON_ENABLE_SEQUENTIAL_LINK);
3890 if (ret < 0)
3891 return ret;
3892 ret = drm_dp_pcon_frl_configure_2(aux: &intel_dp->aux, max_frl_mask: max_frl_bw_mask,
3893 DP_PCON_FRL_LINK_TRAIN_NORMAL);
3894 if (ret < 0)
3895 return ret;
3896 ret = drm_dp_pcon_frl_enable(aux: &intel_dp->aux);
3897 if (ret < 0)
3898 return ret;
3899 /*
3900 * Wait for FRL to be completed
3901 * Check if the HDMI Link is up and active.
3902 */
3903 ret = poll_timeout_us(is_active = intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3904 is_active,
3905 1000, TIMEOUT_HDMI_LINK_ACTIVE_MS * 1000, false);
3906 if (ret)
3907 return ret;
3908
3909frl_trained:
3910 drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3911 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_bw_mask: frl_trained_mask);
3912 intel_dp->frl.is_trained = true;
3913 drm_dbg(display->drm, "FRL trained with : %d Gbps\n",
3914 intel_dp->frl.trained_rate_gbps);
3915
3916 return 0;
3917}
3918
3919static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3920{
3921 if (drm_dp_is_branch(dpcd: intel_dp->dpcd) &&
3922 intel_dp_has_hdmi_sink(intel_dp) &&
3923 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3924 return true;
3925
3926 return false;
3927}
3928
3929static
3930int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3931{
3932 int ret;
3933 u8 buf = 0;
3934
3935 /* Set PCON source control mode */
3936 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3937
3938 ret = drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf);
3939 if (ret < 0)
3940 return ret;
3941
3942 /* Set HDMI LINK ENABLE */
3943 buf |= DP_PCON_ENABLE_HDMI_LINK;
3944 ret = drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf);
3945 if (ret < 0)
3946 return ret;
3947
3948 return 0;
3949}
3950
3951void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3952{
3953 struct intel_display *display = to_intel_display(intel_dp);
3954
3955 /*
3956 * Always go for FRL training if:
3957 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3958 * -sink is HDMI2.1
3959 */
3960 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3961 !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3962 intel_dp->frl.is_trained)
3963 return;
3964
3965 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3966 int ret, mode;
3967
3968 drm_dbg(display->drm,
3969 "Couldn't set FRL mode, continuing with TMDS mode\n");
3970 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3971 mode = drm_dp_pcon_hdmi_link_mode(aux: &intel_dp->aux, NULL);
3972
3973 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3974 drm_dbg(display->drm,
3975 "Issue with PCON, cannot set TMDS mode\n");
3976 } else {
3977 drm_dbg(display->drm, "FRL training Completed\n");
3978 }
3979}
3980
3981static int
3982intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3983{
3984 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3985
3986 return intel_hdmi_dsc_get_slice_height(vactive);
3987}
3988
3989static int
3990intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3991 const struct intel_crtc_state *crtc_state)
3992{
3993 struct intel_connector *connector = intel_dp->attached_connector;
3994 const struct drm_display_info *info = &connector->base.display_info;
3995 int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice;
3996 int hdmi_max_slices = info->hdmi.dsc_cap.max_slices;
3997 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(pcon_dsc_dpcd: intel_dp->pcon_dsc_dpcd);
3998 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(pcon_dsc_dpcd: intel_dp->pcon_dsc_dpcd);
3999
4000 return intel_hdmi_dsc_get_num_slices(crtc_state, src_max_slices: pcon_max_slices,
4001 src_max_slice_width: pcon_max_slice_width,
4002 hdmi_max_slices, hdmi_throughput);
4003}
4004
4005static int
4006intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
4007 const struct intel_crtc_state *crtc_state,
4008 int num_slices, int slice_width)
4009{
4010 struct intel_connector *connector = intel_dp->attached_connector;
4011 const struct drm_display_info *info = &connector->base.display_info;
4012 int output_format = crtc_state->output_format;
4013 bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp;
4014 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(pcon_dsc_dpcd: intel_dp->pcon_dsc_dpcd);
4015 int hdmi_max_chunk_bytes =
4016 info->hdmi.dsc_cap.total_chunk_kbytes * 1024;
4017
4018 return intel_hdmi_dsc_get_bpp(src_fractional_bpp: pcon_fractional_bpp, slice_width,
4019 num_slices, output_format, hdmi_all_bpp,
4020 hdmi_max_chunk_bytes);
4021}
4022
4023void
4024intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
4025 const struct intel_crtc_state *crtc_state)
4026{
4027 struct intel_display *display = to_intel_display(intel_dp);
4028 struct intel_connector *connector = intel_dp->attached_connector;
4029 const struct drm_display_info *info;
4030 u8 pps_param[6];
4031 int slice_height;
4032 int slice_width;
4033 int num_slices;
4034 int bits_per_pixel;
4035 int ret;
4036 bool hdmi_is_dsc_1_2;
4037
4038 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
4039 return;
4040
4041 if (!connector)
4042 return;
4043
4044 info = &connector->base.display_info;
4045
4046 hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2;
4047
4048 if (!drm_dp_pcon_enc_is_dsc_1_2(pcon_dsc_dpcd: intel_dp->pcon_dsc_dpcd) ||
4049 !hdmi_is_dsc_1_2)
4050 return;
4051
4052 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
4053 if (!slice_height)
4054 return;
4055
4056 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
4057 if (!num_slices)
4058 return;
4059
4060 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
4061 num_slices);
4062
4063 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
4064 num_slices, slice_width);
4065 if (!bits_per_pixel)
4066 return;
4067
4068 pps_param[0] = slice_height & 0xFF;
4069 pps_param[1] = slice_height >> 8;
4070 pps_param[2] = slice_width & 0xFF;
4071 pps_param[3] = slice_width >> 8;
4072 pps_param[4] = bits_per_pixel & 0xFF;
4073 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
4074
4075 ret = drm_dp_pcon_pps_override_param(aux: &intel_dp->aux, pps_param);
4076 if (ret < 0)
4077 drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");
4078}
4079
4080void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
4081 const struct intel_crtc_state *crtc_state)
4082{
4083 struct intel_display *display = to_intel_display(intel_dp);
4084 bool ycbcr444_to_420 = false;
4085 bool rgb_to_ycbcr = false;
4086 u8 tmp;
4087
4088 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
4089 return;
4090
4091 if (!drm_dp_is_branch(dpcd: intel_dp->dpcd))
4092 return;
4093
4094 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
4095
4096 if (drm_dp_dpcd_writeb(aux: &intel_dp->aux,
4097 DP_PROTOCOL_CONVERTER_CONTROL_0, value: tmp) != 1)
4098 drm_dbg_kms(display->drm,
4099 "Failed to %s protocol converter HDMI mode\n",
4100 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
4101
4102 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
4103 switch (crtc_state->output_format) {
4104 case INTEL_OUTPUT_FORMAT_YCBCR420:
4105 break;
4106 case INTEL_OUTPUT_FORMAT_YCBCR444:
4107 ycbcr444_to_420 = true;
4108 break;
4109 case INTEL_OUTPUT_FORMAT_RGB:
4110 rgb_to_ycbcr = true;
4111 ycbcr444_to_420 = true;
4112 break;
4113 default:
4114 MISSING_CASE(crtc_state->output_format);
4115 break;
4116 }
4117 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
4118 switch (crtc_state->output_format) {
4119 case INTEL_OUTPUT_FORMAT_YCBCR444:
4120 break;
4121 case INTEL_OUTPUT_FORMAT_RGB:
4122 rgb_to_ycbcr = true;
4123 break;
4124 default:
4125 MISSING_CASE(crtc_state->output_format);
4126 break;
4127 }
4128 }
4129
4130 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
4131
4132 if (drm_dp_dpcd_writeb(aux: &intel_dp->aux,
4133 DP_PROTOCOL_CONVERTER_CONTROL_1, value: tmp) != 1)
4134 drm_dbg_kms(display->drm,
4135 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
4136 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
4137
4138 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
4139
4140 if (drm_dp_pcon_convert_rgb_to_ycbcr(aux: &intel_dp->aux, color_spc: tmp) < 0)
4141 drm_dbg_kms(display->drm,
4142 "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
4143 str_enable_disable(tmp));
4144}
4145
4146static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4147{
4148 u8 dprx = 0;
4149
4150 if (drm_dp_dpcd_readb(aux: &intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4151 valuep: &dprx) != 1)
4152 return false;
4153 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4154}
4155
4156static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
4157 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
4158{
4159 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, buffer: dsc_dpcd,
4160 DP_DSC_RECEIVER_CAP_SIZE) < 0) {
4161 drm_err(aux->drm_dev,
4162 "Failed to read DPCD register 0x%x\n",
4163 DP_DSC_SUPPORT);
4164 return;
4165 }
4166
4167 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
4168 DP_DSC_RECEIVER_CAP_SIZE,
4169 dsc_dpcd);
4170}
4171
4172void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
4173{
4174 struct intel_display *display = to_intel_display(connector);
4175
4176 /*
4177 * Clear the cached register set to avoid using stale values
4178 * for the sinks that do not support DSC.
4179 */
4180 memset(s: connector->dp.dsc_dpcd, c: 0, n: sizeof(connector->dp.dsc_dpcd));
4181
4182 /* Clear fec_capable to avoid using stale values */
4183 connector->dp.fec_capability = 0;
4184
4185 if (dpcd_rev < DP_DPCD_REV_14)
4186 return;
4187
4188 intel_dp_read_dsc_dpcd(aux: connector->dp.dsc_decompression_aux,
4189 dsc_dpcd: connector->dp.dsc_dpcd);
4190
4191 if (drm_dp_dpcd_readb(aux: connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
4192 valuep: &connector->dp.fec_capability) < 0) {
4193 drm_err(display->drm, "Failed to read FEC DPCD register\n");
4194 return;
4195 }
4196
4197 drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
4198 connector->dp.fec_capability);
4199}
4200
4201static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
4202{
4203 if (edp_dpcd_rev < DP_EDP_14)
4204 return;
4205
4206 intel_dp_read_dsc_dpcd(aux: connector->dp.dsc_decompression_aux, dsc_dpcd: connector->dp.dsc_dpcd);
4207}
4208
4209static void
4210intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
4211{
4212 struct intel_display *display = to_intel_display(intel_dp);
4213
4214 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4215 if (!HAS_DSC(display))
4216 return;
4217
4218 if (intel_dp_is_edp(intel_dp))
4219 intel_edp_get_dsc_sink_cap(edp_dpcd_rev: intel_dp->edp_dpcd[0],
4220 connector);
4221 else
4222 intel_dp_get_dsc_sink_cap(dpcd_rev: intel_dp->dpcd[DP_DPCD_REV],
4223 connector);
4224}
4225
4226static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
4227 struct drm_display_mode *mode)
4228{
4229 struct intel_display *display = to_intel_display(connector);
4230 struct intel_dp *intel_dp = intel_attached_dp(connector);
4231 int n = intel_dp->mso_link_count;
4232 int overlap = intel_dp->mso_pixel_overlap;
4233
4234 if (!mode || !n)
4235 return;
4236
4237 mode->hdisplay = (mode->hdisplay - overlap) * n;
4238 mode->hsync_start = (mode->hsync_start - overlap) * n;
4239 mode->hsync_end = (mode->hsync_end - overlap) * n;
4240 mode->htotal = (mode->htotal - overlap) * n;
4241 mode->clock *= n;
4242
4243 drm_mode_set_name(mode);
4244
4245 drm_dbg_kms(display->drm,
4246 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
4247 connector->base.base.id, connector->base.name,
4248 DRM_MODE_ARG(mode));
4249}
4250
4251void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
4252{
4253 struct intel_display *display = to_intel_display(encoder);
4254 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4255 struct intel_connector *connector = intel_dp->attached_connector;
4256
4257 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
4258 /*
4259 * This is a big fat ugly hack.
4260 *
4261 * Some machines in UEFI boot mode provide us a VBT that has 18
4262 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4263 * unknown we fail to light up. Yet the same BIOS boots up with
4264 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4265 * max, not what it tells us to use.
4266 *
4267 * Note: This will still be broken if the eDP panel is not lit
4268 * up by the BIOS, and thus we can't get the mode at module
4269 * load.
4270 */
4271 drm_dbg_kms(display->drm,
4272 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4273 pipe_bpp, connector->panel.vbt.edp.bpp);
4274 connector->panel.vbt.edp.bpp = pipe_bpp;
4275 }
4276}
4277
4278static void intel_edp_mso_init(struct intel_dp *intel_dp)
4279{
4280 struct intel_display *display = to_intel_display(intel_dp);
4281 struct intel_connector *connector = intel_dp->attached_connector;
4282 struct drm_display_info *info = &connector->base.display_info;
4283 u8 mso;
4284
4285 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
4286 return;
4287
4288 if (drm_dp_dpcd_readb(aux: &intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, valuep: &mso) != 1) {
4289 drm_err(display->drm, "Failed to read MSO cap\n");
4290 return;
4291 }
4292
4293 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
4294 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
4295 if (mso % 2 || mso > drm_dp_max_lane_count(dpcd: intel_dp->dpcd)) {
4296 drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);
4297 mso = 0;
4298 }
4299
4300 if (mso) {
4301 drm_dbg_kms(display->drm,
4302 "Sink MSO %ux%u configuration, pixel overlap %u\n",
4303 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
4304 info->mso_pixel_overlap);
4305 if (!HAS_MSO(display)) {
4306 drm_err(display->drm,
4307 "No source MSO support, disabling\n");
4308 mso = 0;
4309 }
4310 }
4311
4312 intel_dp->mso_link_count = mso;
4313 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
4314}
4315
4316static void
4317intel_edp_set_data_override_rates(struct intel_dp *intel_dp)
4318{
4319 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4320 int *sink_rates = intel_dp->sink_rates;
4321 int i, count = 0;
4322
4323 for (i = 0; i < intel_dp->num_sink_rates; i++) {
4324 if (intel_bios_encoder_reject_edp_rate(devdata: encoder->devdata,
4325 rate: intel_dp->sink_rates[i]))
4326 continue;
4327
4328 sink_rates[count++] = intel_dp->sink_rates[i];
4329 }
4330 intel_dp->num_sink_rates = count;
4331}
4332
4333static void
4334intel_edp_set_sink_rates(struct intel_dp *intel_dp)
4335{
4336 struct intel_display *display = to_intel_display(intel_dp);
4337
4338 intel_dp->num_sink_rates = 0;
4339
4340 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4341 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4342 int i;
4343
4344 drm_dp_dpcd_read(aux: &intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4345 buffer: sink_rates, size: sizeof(sink_rates));
4346
4347 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4348 int rate;
4349
4350 /* Value read multiplied by 200kHz gives the per-lane
4351 * link rate in kHz. The source rates are, however,
4352 * stored in terms of LS_Clk kHz. The full conversion
4353 * back to symbols is
4354 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4355 */
4356 rate = le16_to_cpu(sink_rates[i]) * 200 / 10;
4357
4358 if (rate == 0)
4359 break;
4360
4361 /*
4362 * Some platforms cannot reliably drive HBR3 rates due to PHY limitations,
4363 * even if the sink advertises support. Reject any sink rates above HBR2 on
4364 * the known machines for stable output.
4365 */
4366 if (rate > 540000 &&
4367 intel_has_quirk(display, quirk: QUIRK_EDP_LIMIT_RATE_HBR2))
4368 break;
4369
4370 intel_dp->sink_rates[i] = rate;
4371 }
4372 intel_dp->num_sink_rates = i;
4373 }
4374
4375 /*
4376 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4377 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4378 */
4379 if (intel_dp->num_sink_rates)
4380 intel_dp->use_rate_select = true;
4381 else
4382 intel_dp_set_sink_rates(intel_dp);
4383
4384 intel_edp_set_data_override_rates(intel_dp);
4385}
4386
4387static bool
4388intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
4389{
4390 struct intel_display *display = to_intel_display(intel_dp);
4391
4392 /* this function is meant to be called only once */
4393 drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4394
4395 if (drm_dp_read_dpcd_caps(aux: &intel_dp->aux, dpcd: intel_dp->dpcd) != 0)
4396 return false;
4397
4398 drm_dp_read_desc(aux: &intel_dp->aux, desc: &intel_dp->desc,
4399 is_branch: drm_dp_is_branch(dpcd: intel_dp->dpcd));
4400 intel_init_dpcd_quirks(intel_dp, ident: &intel_dp->desc.ident);
4401
4402 intel_dp->colorimetry_support =
4403 intel_dp_get_colorimetry_status(intel_dp);
4404
4405 /*
4406 * Read the eDP display control registers.
4407 *
4408 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4409 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4410 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4411 * method). The display control registers should read zero if they're
4412 * not supported anyway.
4413 */
4414 if (drm_dp_dpcd_read(aux: &intel_dp->aux, DP_EDP_DPCD_REV,
4415 buffer: intel_dp->edp_dpcd, size: sizeof(intel_dp->edp_dpcd)) ==
4416 sizeof(intel_dp->edp_dpcd)) {
4417 drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",
4418 (int)sizeof(intel_dp->edp_dpcd),
4419 intel_dp->edp_dpcd);
4420
4421 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
4422 }
4423
4424 /*
4425 * If needed, program our source OUI so we can make various Intel-specific AUX services
4426 * available (such as HDR backlight controls)
4427 */
4428 intel_dp_init_source_oui(intel_dp);
4429
4430 /*
4431 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4432 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4433 */
4434 intel_psr_init_dpcd(intel_dp);
4435
4436 intel_edp_set_sink_rates(intel_dp);
4437 intel_dp_set_max_sink_lane_count(intel_dp);
4438
4439 /* Read the eDP DSC DPCD registers */
4440 intel_dp_detect_dsc_caps(intel_dp, connector);
4441
4442 return true;
4443}
4444
4445static bool
4446intel_dp_has_sink_count(struct intel_dp *intel_dp)
4447{
4448 if (!intel_dp->attached_connector)
4449 return false;
4450
4451 return drm_dp_read_sink_count_cap(connector: &intel_dp->attached_connector->base,
4452 dpcd: intel_dp->dpcd,
4453 desc: &intel_dp->desc);
4454}
4455
4456void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
4457{
4458 intel_dp_set_sink_rates(intel_dp);
4459 intel_dp_set_max_sink_lane_count(intel_dp);
4460 intel_dp_set_common_rates(intel_dp);
4461}
4462
4463static bool
4464intel_dp_get_dpcd(struct intel_dp *intel_dp)
4465{
4466 int ret;
4467
4468 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
4469 return false;
4470
4471 /*
4472 * Don't clobber cached eDP rates. Also skip re-reading
4473 * the OUI/ID since we know it won't change.
4474 */
4475 if (!intel_dp_is_edp(intel_dp)) {
4476 drm_dp_read_desc(aux: &intel_dp->aux, desc: &intel_dp->desc,
4477 is_branch: drm_dp_is_branch(dpcd: intel_dp->dpcd));
4478
4479 intel_init_dpcd_quirks(intel_dp, ident: &intel_dp->desc.ident);
4480
4481 intel_dp->colorimetry_support =
4482 intel_dp_get_colorimetry_status(intel_dp);
4483
4484 intel_dp_update_sink_caps(intel_dp);
4485 }
4486
4487 if (intel_dp_has_sink_count(intel_dp)) {
4488 ret = drm_dp_read_sink_count(aux: &intel_dp->aux);
4489 if (ret < 0)
4490 return false;
4491
4492 /*
4493 * Sink count can change between short pulse hpd hence
4494 * a member variable in intel_dp will track any changes
4495 * between short pulse interrupts.
4496 */
4497 intel_dp->sink_count = ret;
4498
4499 /*
4500 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4501 * a dongle is present but no display. Unless we require to know
4502 * if a dongle is present or not, we don't need to update
4503 * downstream port information. So, an early return here saves
4504 * time from performing other operations which are not required.
4505 */
4506 if (!intel_dp->sink_count)
4507 return false;
4508 }
4509
4510 return drm_dp_read_downstream_info(aux: &intel_dp->aux, dpcd: intel_dp->dpcd,
4511 downstream_ports: intel_dp->downstream_ports) == 0;
4512}
4513
4514static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode)
4515{
4516 if (mst_mode == DRM_DP_MST)
4517 return "MST";
4518 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG)
4519 return "SST w/ sideband messaging";
4520 else
4521 return "SST";
4522}
4523
4524static enum drm_dp_mst_mode
4525intel_dp_mst_mode_choose(struct intel_dp *intel_dp,
4526 enum drm_dp_mst_mode sink_mst_mode)
4527{
4528 struct intel_display *display = to_intel_display(intel_dp);
4529
4530 if (!display->params.enable_dp_mst)
4531 return DRM_DP_SST;
4532
4533 if (!intel_dp_mst_source_support(intel_dp))
4534 return DRM_DP_SST;
4535
4536 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG &&
4537 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))
4538 return DRM_DP_SST;
4539
4540 return sink_mst_mode;
4541}
4542
4543static enum drm_dp_mst_mode
4544intel_dp_mst_detect(struct intel_dp *intel_dp)
4545{
4546 struct intel_display *display = to_intel_display(intel_dp);
4547 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4548 enum drm_dp_mst_mode sink_mst_mode;
4549 enum drm_dp_mst_mode mst_detect;
4550
4551 sink_mst_mode = drm_dp_read_mst_cap(aux: &intel_dp->aux, dpcd: intel_dp->dpcd);
4552
4553 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);
4554
4555 drm_dbg_kms(display->drm,
4556 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",
4557 encoder->base.base.id, encoder->base.name,
4558 str_yes_no(intel_dp_mst_source_support(intel_dp)),
4559 intel_dp_mst_mode_str(sink_mst_mode),
4560 str_yes_no(display->params.enable_dp_mst),
4561 intel_dp_mst_mode_str(mst_detect));
4562
4563 return mst_detect;
4564}
4565
4566static void
4567intel_dp_mst_configure(struct intel_dp *intel_dp)
4568{
4569 if (!intel_dp_mst_source_support(intel_dp))
4570 return;
4571
4572 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;
4573
4574 if (intel_dp->is_mst)
4575 intel_dp_mst_prepare_probe(intel_dp);
4576
4577 drm_dp_mst_topology_mgr_set_mst(mgr: &intel_dp->mst.mgr, mst_state: intel_dp->is_mst);
4578
4579 /* Avoid stale info on the next detect cycle. */
4580 intel_dp->mst_detect = DRM_DP_SST;
4581}
4582
4583static void
4584intel_dp_mst_disconnect(struct intel_dp *intel_dp)
4585{
4586 struct intel_display *display = to_intel_display(intel_dp);
4587
4588 if (!intel_dp->is_mst)
4589 return;
4590
4591 drm_dbg_kms(display->drm,
4592 "MST device may have disappeared %d vs %d\n",
4593 intel_dp->is_mst, intel_dp->mst.mgr.mst_state);
4594 intel_dp->is_mst = false;
4595 drm_dp_mst_topology_mgr_set_mst(mgr: &intel_dp->mst.mgr, mst_state: intel_dp->is_mst);
4596}
4597
4598static bool
4599intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4600{
4601 struct intel_display *display = to_intel_display(intel_dp);
4602
4603 /*
4604 * Display WA for HSD #13013007775: mtl/arl/lnl
4605 * Read the sink count and link service IRQ registers in separate
4606 * transactions to prevent disconnecting the sink on a TBT link
4607 * inadvertently.
4608 */
4609 if (IS_DISPLAY_VER(display, 14, 20) && !display->platform.battlemage) {
4610 if (drm_dp_dpcd_read(aux: &intel_dp->aux, DP_SINK_COUNT_ESI, buffer: esi, size: 3) != 3)
4611 return false;
4612
4613 /* DP_SINK_COUNT_ESI + 3 == DP_LINK_SERVICE_IRQ_VECTOR_ESI0 */
4614 return drm_dp_dpcd_readb(aux: &intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0,
4615 valuep: &esi[3]) == 1;
4616 }
4617
4618 return drm_dp_dpcd_read(aux: &intel_dp->aux, DP_SINK_COUNT_ESI, buffer: esi, size: 4) == 4;
4619}
4620
4621static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4622{
4623 int retry;
4624
4625 for (retry = 0; retry < 3; retry++) {
4626 if (drm_dp_dpcd_write(aux: &intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4627 buffer: &esi[1], size: 3) == 3)
4628 return true;
4629 }
4630
4631 return false;
4632}
4633
4634bool
4635intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4636 const struct drm_connector_state *conn_state)
4637{
4638 /*
4639 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4640 * of Color Encoding Format and Content Color Gamut], in order to
4641 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4642 */
4643 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4644 return true;
4645
4646 switch (conn_state->colorspace) {
4647 case DRM_MODE_COLORIMETRY_SYCC_601:
4648 case DRM_MODE_COLORIMETRY_OPYCC_601:
4649 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4650 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4651 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4652 return true;
4653 default:
4654 break;
4655 }
4656
4657 return false;
4658}
4659
4660static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
4661 struct dp_sdp *sdp, size_t size)
4662{
4663 size_t length = sizeof(struct dp_sdp);
4664
4665 if (size < length)
4666 return -ENOSPC;
4667
4668 memset(s: sdp, c: 0, n: size);
4669
4670 /* Prepare AS (Adaptive Sync) SDP Header */
4671 sdp->sdp_header.HB0 = 0;
4672 sdp->sdp_header.HB1 = as_sdp->sdp_type;
4673 sdp->sdp_header.HB2 = 0x02;
4674 sdp->sdp_header.HB3 = as_sdp->length;
4675
4676 /* Fill AS (Adaptive Sync) SDP Payload */
4677 sdp->db[0] = as_sdp->mode;
4678 sdp->db[1] = as_sdp->vtotal & 0xFF;
4679 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
4680 sdp->db[3] = as_sdp->target_rr & 0xFF;
4681 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
4682
4683 if (as_sdp->target_rr_divider)
4684 sdp->db[4] |= 0x20;
4685
4686 return length;
4687}
4688
4689static ssize_t
4690intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display,
4691 const struct hdmi_drm_infoframe *drm_infoframe,
4692 struct dp_sdp *sdp,
4693 size_t size)
4694{
4695 size_t length = sizeof(struct dp_sdp);
4696 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4697 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4698 ssize_t len;
4699
4700 if (size < length)
4701 return -ENOSPC;
4702
4703 memset(s: sdp, c: 0, n: size);
4704
4705 len = hdmi_drm_infoframe_pack_only(frame: drm_infoframe, buffer: buf, size: sizeof(buf));
4706 if (len < 0) {
4707 drm_dbg_kms(display->drm,
4708 "buffer size is smaller than hdr metadata infoframe\n");
4709 return -ENOSPC;
4710 }
4711
4712 if (len != infoframe_size) {
4713 drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");
4714 return -ENOSPC;
4715 }
4716
4717 /*
4718 * Set up the infoframe sdp packet for HDR static metadata.
4719 * Prepare VSC Header for SU as per DP 1.4a spec,
4720 * Table 2-100 and Table 2-101
4721 */
4722
4723 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4724 sdp->sdp_header.HB0 = 0;
4725 /*
4726 * Packet Type 80h + Non-audio INFOFRAME Type value
4727 * HDMI_INFOFRAME_TYPE_DRM: 0x87
4728 * - 80h + Non-audio INFOFRAME Type value
4729 * - InfoFrame Type: 0x07
4730 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4731 */
4732 sdp->sdp_header.HB1 = drm_infoframe->type;
4733 /*
4734 * Least Significant Eight Bits of (Data Byte Count – 1)
4735 * infoframe_size - 1
4736 */
4737 sdp->sdp_header.HB2 = 0x1D;
4738 /* INFOFRAME SDP Version Number */
4739 sdp->sdp_header.HB3 = (0x13 << 2);
4740 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4741 sdp->db[0] = drm_infoframe->version;
4742 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4743 sdp->db[1] = drm_infoframe->length;
4744 /*
4745 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4746 * HDMI_INFOFRAME_HEADER_SIZE
4747 */
4748 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4749 memcpy(to: &sdp->db[2], from: &buf[HDMI_INFOFRAME_HEADER_SIZE],
4750 HDMI_DRM_INFOFRAME_SIZE);
4751
4752 /*
4753 * Size of DP infoframe sdp packet for HDR static metadata consists of
4754 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4755 * - Two Data Blocks: 2 bytes
4756 * CTA Header Byte2 (INFOFRAME Version Number)
4757 * CTA Header Byte3 (Length of INFOFRAME)
4758 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4759 *
4760 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4761 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4762 * will pad rest of the size.
4763 */
4764 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4765}
4766
4767static void intel_write_dp_sdp(struct intel_encoder *encoder,
4768 const struct intel_crtc_state *crtc_state,
4769 unsigned int type)
4770{
4771 struct intel_display *display = to_intel_display(encoder);
4772 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4773 struct dp_sdp sdp = {};
4774 ssize_t len;
4775
4776 if ((crtc_state->infoframes.enable &
4777 intel_hdmi_infoframe_enable(type)) == 0)
4778 return;
4779
4780 switch (type) {
4781 case DP_SDP_VSC:
4782 len = drm_dp_vsc_sdp_pack(vsc: &crtc_state->infoframes.vsc, sdp: &sdp);
4783 break;
4784 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4785 len = intel_dp_hdr_metadata_infoframe_sdp_pack(display,
4786 drm_infoframe: &crtc_state->infoframes.drm.drm,
4787 sdp: &sdp, size: sizeof(sdp));
4788 break;
4789 case DP_SDP_ADAPTIVE_SYNC:
4790 len = intel_dp_as_sdp_pack(as_sdp: &crtc_state->infoframes.as_sdp, sdp: &sdp,
4791 size: sizeof(sdp));
4792 break;
4793 default:
4794 MISSING_CASE(type);
4795 return;
4796 }
4797
4798 if (drm_WARN_ON(display->drm, len < 0))
4799 return;
4800
4801 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4802}
4803
4804void intel_dp_set_infoframes(struct intel_encoder *encoder,
4805 bool enable,
4806 const struct intel_crtc_state *crtc_state,
4807 const struct drm_connector_state *conn_state)
4808{
4809 struct intel_display *display = to_intel_display(encoder);
4810 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
4811 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4812 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4813 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4814
4815 if (HAS_AS_SDP(display))
4816 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
4817
4818 u32 val = intel_de_read(display, reg) & ~dip_enable;
4819
4820 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4821 if (!enable && HAS_DSC(display))
4822 val &= ~VDIP_ENABLE_PPS;
4823
4824 /*
4825 * This routine disables VSC DIP if the function is called
4826 * to disable SDP or if it does not have PSR
4827 */
4828 if (!enable || !crtc_state->has_psr)
4829 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4830
4831 intel_de_write(display, reg, val);
4832 intel_de_posting_read(display, reg);
4833
4834 if (!enable)
4835 return;
4836
4837 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4838 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
4839
4840 intel_write_dp_sdp(encoder, crtc_state, type: HDMI_PACKET_TYPE_GAMUT_METADATA);
4841}
4842
4843static
4844int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
4845 const void *buffer, size_t size)
4846{
4847 const struct dp_sdp *sdp = buffer;
4848
4849 if (size < sizeof(struct dp_sdp))
4850 return -EINVAL;
4851
4852 memset(s: as_sdp, c: 0, n: sizeof(*as_sdp));
4853
4854 if (sdp->sdp_header.HB0 != 0)
4855 return -EINVAL;
4856
4857 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
4858 return -EINVAL;
4859
4860 if (sdp->sdp_header.HB2 != 0x02)
4861 return -EINVAL;
4862
4863 if ((sdp->sdp_header.HB3 & 0x3F) != 9)
4864 return -EINVAL;
4865
4866 as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
4867 as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
4868 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
4869 as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
4870 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
4871
4872 return 0;
4873}
4874
4875static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4876 const void *buffer, size_t size)
4877{
4878 const struct dp_sdp *sdp = buffer;
4879
4880 if (size < sizeof(struct dp_sdp))
4881 return -EINVAL;
4882
4883 memset(s: vsc, c: 0, n: sizeof(*vsc));
4884
4885 if (sdp->sdp_header.HB0 != 0)
4886 return -EINVAL;
4887
4888 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4889 return -EINVAL;
4890
4891 vsc->sdp_type = sdp->sdp_header.HB1;
4892 vsc->revision = sdp->sdp_header.HB2;
4893 vsc->length = sdp->sdp_header.HB3;
4894
4895 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4896 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||
4897 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {
4898 /*
4899 * - HB2 = 0x2, HB3 = 0x8
4900 * VSC SDP supporting 3D stereo + PSR
4901 * - HB2 = 0x4, HB3 = 0xe
4902 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4903 * first scan line of the SU region (applies to eDP v1.4b
4904 * and higher).
4905 * - HB2 = 0x6, HB3 = 0x10
4906 * VSC SDP supporting 3D stereo + Panel Replay.
4907 */
4908 return 0;
4909 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4910 /*
4911 * - HB2 = 0x5, HB3 = 0x13
4912 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4913 * Format.
4914 */
4915 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4916 vsc->colorimetry = sdp->db[16] & 0xf;
4917 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4918
4919 switch (sdp->db[17] & 0x7) {
4920 case 0x0:
4921 vsc->bpc = 6;
4922 break;
4923 case 0x1:
4924 vsc->bpc = 8;
4925 break;
4926 case 0x2:
4927 vsc->bpc = 10;
4928 break;
4929 case 0x3:
4930 vsc->bpc = 12;
4931 break;
4932 case 0x4:
4933 vsc->bpc = 16;
4934 break;
4935 default:
4936 MISSING_CASE(sdp->db[17] & 0x7);
4937 return -EINVAL;
4938 }
4939
4940 vsc->content_type = sdp->db[18] & 0x7;
4941 } else {
4942 return -EINVAL;
4943 }
4944
4945 return 0;
4946}
4947
4948static void
4949intel_read_dp_as_sdp(struct intel_encoder *encoder,
4950 struct intel_crtc_state *crtc_state,
4951 struct drm_dp_as_sdp *as_sdp)
4952{
4953 struct intel_display *display = to_intel_display(encoder);
4954 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4955 unsigned int type = DP_SDP_ADAPTIVE_SYNC;
4956 struct dp_sdp sdp = {};
4957 int ret;
4958
4959 if ((crtc_state->infoframes.enable &
4960 intel_hdmi_infoframe_enable(type)) == 0)
4961 return;
4962
4963 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4964 sizeof(sdp));
4965
4966 ret = intel_dp_as_sdp_unpack(as_sdp, buffer: &sdp, size: sizeof(sdp));
4967 if (ret)
4968 drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");
4969}
4970
4971static int
4972intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4973 const void *buffer, size_t size)
4974{
4975 int ret;
4976
4977 const struct dp_sdp *sdp = buffer;
4978
4979 if (size < sizeof(struct dp_sdp))
4980 return -EINVAL;
4981
4982 if (sdp->sdp_header.HB0 != 0)
4983 return -EINVAL;
4984
4985 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4986 return -EINVAL;
4987
4988 /*
4989 * Least Significant Eight Bits of (Data Byte Count – 1)
4990 * 1Dh (i.e., Data Byte Count = 30 bytes).
4991 */
4992 if (sdp->sdp_header.HB2 != 0x1D)
4993 return -EINVAL;
4994
4995 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4996 if ((sdp->sdp_header.HB3 & 0x3) != 0)
4997 return -EINVAL;
4998
4999 /* INFOFRAME SDP Version Number */
5000 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
5001 return -EINVAL;
5002
5003 /* CTA Header Byte 2 (INFOFRAME Version Number) */
5004 if (sdp->db[0] != 1)
5005 return -EINVAL;
5006
5007 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5008 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
5009 return -EINVAL;
5010
5011 ret = hdmi_drm_infoframe_unpack_only(frame: drm_infoframe, buffer: &sdp->db[2],
5012 HDMI_DRM_INFOFRAME_SIZE);
5013
5014 return ret;
5015}
5016
5017static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
5018 struct intel_crtc_state *crtc_state,
5019 struct drm_dp_vsc_sdp *vsc)
5020{
5021 struct intel_display *display = to_intel_display(encoder);
5022 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5023 unsigned int type = DP_SDP_VSC;
5024 struct dp_sdp sdp = {};
5025 int ret;
5026
5027 if ((crtc_state->infoframes.enable &
5028 intel_hdmi_infoframe_enable(type)) == 0)
5029 return;
5030
5031 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
5032
5033 ret = intel_dp_vsc_sdp_unpack(vsc, buffer: &sdp, size: sizeof(sdp));
5034
5035 if (ret)
5036 drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");
5037}
5038
5039static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
5040 struct intel_crtc_state *crtc_state,
5041 struct hdmi_drm_infoframe *drm_infoframe)
5042{
5043 struct intel_display *display = to_intel_display(encoder);
5044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5045 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
5046 struct dp_sdp sdp = {};
5047 int ret;
5048
5049 if ((crtc_state->infoframes.enable &
5050 intel_hdmi_infoframe_enable(type)) == 0)
5051 return;
5052
5053 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5054 sizeof(sdp));
5055
5056 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, buffer: &sdp,
5057 size: sizeof(sdp));
5058
5059 if (ret)
5060 drm_dbg_kms(display->drm,
5061 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
5062}
5063
5064void intel_read_dp_sdp(struct intel_encoder *encoder,
5065 struct intel_crtc_state *crtc_state,
5066 unsigned int type)
5067{
5068 switch (type) {
5069 case DP_SDP_VSC:
5070 intel_read_dp_vsc_sdp(encoder, crtc_state,
5071 vsc: &crtc_state->infoframes.vsc);
5072 break;
5073 case HDMI_PACKET_TYPE_GAMUT_METADATA:
5074 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
5075 drm_infoframe: &crtc_state->infoframes.drm.drm);
5076 break;
5077 case DP_SDP_ADAPTIVE_SYNC:
5078 intel_read_dp_as_sdp(encoder, crtc_state,
5079 as_sdp: &crtc_state->infoframes.as_sdp);
5080 break;
5081 default:
5082 MISSING_CASE(type);
5083 break;
5084 }
5085}
5086
5087static bool intel_dp_link_ok(struct intel_dp *intel_dp,
5088 u8 link_status[DP_LINK_STATUS_SIZE])
5089{
5090 struct intel_display *display = to_intel_display(intel_dp);
5091 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5092 bool uhbr = intel_dp->link_rate >= 1000000;
5093 bool ok;
5094
5095 if (uhbr)
5096 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
5097 lane_count: intel_dp->lane_count);
5098 else
5099 ok = drm_dp_channel_eq_ok(link_status, lane_count: intel_dp->lane_count);
5100
5101 if (ok)
5102 return true;
5103
5104 intel_dp_dump_link_status(intel_dp, dp_phy: DP_PHY_DPRX, link_status);
5105 drm_dbg_kms(display->drm,
5106 "[ENCODER:%d:%s] %s link not ok, retraining\n",
5107 encoder->base.base.id, encoder->base.name,
5108 uhbr ? "128b/132b" : "8b/10b");
5109
5110 return false;
5111}
5112
5113static void
5114intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
5115{
5116 bool handled = false;
5117
5118 drm_dp_mst_hpd_irq_handle_event(mgr: &intel_dp->mst.mgr, esi, ack, handled: &handled);
5119
5120 if (esi[1] & DP_CP_IRQ) {
5121 intel_hdcp_handle_cp_irq(connector: intel_dp->attached_connector);
5122 ack[1] |= DP_CP_IRQ;
5123 }
5124}
5125
5126static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
5127{
5128 struct intel_display *display = to_intel_display(intel_dp);
5129 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5130 u8 link_status[DP_LINK_STATUS_SIZE] = {};
5131 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
5132
5133 if (drm_dp_dpcd_read(aux: &intel_dp->aux, DP_LANE0_1_STATUS_ESI, buffer: link_status,
5134 size: esi_link_status_size) != esi_link_status_size) {
5135 drm_err(display->drm,
5136 "[ENCODER:%d:%s] Failed to read link status\n",
5137 encoder->base.base.id, encoder->base.name);
5138 return false;
5139 }
5140
5141 return intel_dp_link_ok(intel_dp, link_status);
5142}
5143
5144/**
5145 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
5146 * @intel_dp: Intel DP struct
5147 *
5148 * Read any pending MST interrupts, call MST core to handle these and ack the
5149 * interrupts. Check if the main and AUX link state is ok.
5150 *
5151 * Returns:
5152 * - %true if pending interrupts were serviced (or no interrupts were
5153 * pending) w/o detecting an error condition.
5154 * - %false if an error condition - like AUX failure or a loss of link - is
5155 * detected, or another condition - like a DP tunnel BW state change - needs
5156 * servicing from the hotplug work.
5157 */
5158static bool
5159intel_dp_check_mst_status(struct intel_dp *intel_dp)
5160{
5161 struct intel_display *display = to_intel_display(intel_dp);
5162 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5163 struct intel_encoder *encoder = &dig_port->base;
5164 bool link_ok = true;
5165 bool reprobe_needed = false;
5166
5167 for (;;) {
5168 u8 esi[4] = {};
5169 u8 ack[4] = {};
5170
5171 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
5172 drm_dbg_kms(display->drm,
5173 "failed to get ESI - device may have failed\n");
5174 link_ok = false;
5175
5176 break;
5177 }
5178
5179 drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);
5180
5181 if (intel_dp_mst_active_streams(intel_dp) > 0 && link_ok &&
5182 esi[3] & LINK_STATUS_CHANGED) {
5183 if (!intel_dp_mst_link_status(intel_dp))
5184 link_ok = false;
5185 ack[3] |= LINK_STATUS_CHANGED;
5186 }
5187
5188 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
5189
5190 if (esi[3] & DP_TUNNELING_IRQ) {
5191 if (drm_dp_tunnel_handle_irq(mgr: display->dp_tunnel_mgr,
5192 aux: &intel_dp->aux))
5193 reprobe_needed = true;
5194 ack[3] |= DP_TUNNELING_IRQ;
5195 }
5196
5197 if (mem_is_zero(s: ack, n: sizeof(ack)))
5198 break;
5199
5200 if (!intel_dp_ack_sink_irq_esi(intel_dp, esi: ack))
5201 drm_dbg_kms(display->drm, "Failed to ack ESI\n");
5202
5203 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
5204 drm_dp_mst_hpd_irq_send_new_request(mgr: &intel_dp->mst.mgr);
5205 }
5206
5207 if (!link_ok || intel_dp->link.force_retrain)
5208 intel_encoder_link_check_queue_work(encoder, delay_ms: 0);
5209
5210 return !reprobe_needed;
5211}
5212
5213static void
5214intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
5215{
5216 bool is_active;
5217 u8 buf = 0;
5218
5219 is_active = drm_dp_pcon_hdmi_link_active(aux: &intel_dp->aux);
5220 if (intel_dp->frl.is_trained && !is_active) {
5221 if (drm_dp_dpcd_readb(aux: &intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, valuep: &buf) < 0)
5222 return;
5223
5224 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
5225 if (drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf) < 0)
5226 return;
5227
5228 drm_dp_pcon_hdmi_frl_link_error_count(aux: &intel_dp->aux, connector: &intel_dp->attached_connector->base);
5229
5230 intel_dp->frl.is_trained = false;
5231
5232 /* Restart FRL training or fall back to TMDS mode */
5233 intel_dp_check_frl_training(intel_dp);
5234 }
5235}
5236
5237static bool
5238intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5239{
5240 u8 link_status[DP_LINK_STATUS_SIZE];
5241
5242 if (!intel_dp->link.active)
5243 return false;
5244
5245 /*
5246 * While PSR source HW is enabled, it will control main-link sending
5247 * frames, enabling and disabling it so trying to do a retrain will fail
5248 * as the link would or not be on or it could mix training patterns
5249 * and frame data at the same time causing retrain to fail.
5250 * Also when exiting PSR, HW will retrain the link anyways fixing
5251 * any link status error.
5252 */
5253 if (intel_psr_enabled(intel_dp))
5254 return false;
5255
5256 if (intel_dp->link.force_retrain)
5257 return true;
5258
5259 if (drm_dp_dpcd_read_phy_link_status(aux: &intel_dp->aux, dp_phy: DP_PHY_DPRX,
5260 link_status) < 0)
5261 return false;
5262
5263 /*
5264 * Validate the cached values of intel_dp->link_rate and
5265 * intel_dp->lane_count before attempting to retrain.
5266 *
5267 * FIXME would be nice to user the crtc state here, but since
5268 * we need to call this from the short HPD handler that seems
5269 * a bit hard.
5270 */
5271 if (!intel_dp_link_params_valid(intel_dp, link_rate: intel_dp->link_rate,
5272 lane_count: intel_dp->lane_count))
5273 return false;
5274
5275 if (intel_dp->link.retrain_disabled)
5276 return false;
5277
5278 if (intel_dp->link.seq_train_failures)
5279 return true;
5280
5281 /* Retrain if link not ok */
5282 return !intel_dp_link_ok(intel_dp, link_status) &&
5283 !intel_psr_link_ok(intel_dp);
5284}
5285
5286bool intel_dp_has_connector(struct intel_dp *intel_dp,
5287 const struct drm_connector_state *conn_state)
5288{
5289 struct intel_display *display = to_intel_display(intel_dp);
5290 struct intel_encoder *encoder;
5291 enum pipe pipe;
5292
5293 if (!conn_state->best_encoder)
5294 return false;
5295
5296 /* SST */
5297 encoder = &dp_to_dig_port(intel_dp)->base;
5298 if (conn_state->best_encoder == &encoder->base)
5299 return true;
5300
5301 /* MST */
5302 for_each_pipe(display, pipe) {
5303 encoder = &intel_dp->mst.stream_encoders[pipe]->base;
5304 if (conn_state->best_encoder == &encoder->base)
5305 return true;
5306 }
5307
5308 return false;
5309}
5310
5311static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state)
5312{
5313 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5314 struct intel_display *display = to_intel_display(connector);
5315
5316 drm_modeset_lock_assert_held(lock: &display->drm->mode_config.connection_mutex);
5317
5318 if (!conn_state->commit)
5319 return;
5320
5321 drm_WARN_ON(display->drm,
5322 !wait_for_completion_timeout(&conn_state->commit->hw_done,
5323 msecs_to_jiffies(5000)));
5324}
5325
5326int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5327 struct drm_modeset_acquire_ctx *ctx,
5328 u8 *pipe_mask)
5329{
5330 struct intel_display *display = to_intel_display(intel_dp);
5331 struct drm_connector_list_iter conn_iter;
5332 struct intel_connector *connector;
5333 int ret = 0;
5334
5335 *pipe_mask = 0;
5336
5337 drm_connector_list_iter_begin(dev: display->drm, iter: &conn_iter);
5338 for_each_intel_connector_iter(connector, &conn_iter) {
5339 struct drm_connector_state *conn_state =
5340 connector->base.state;
5341 struct intel_crtc_state *crtc_state;
5342 struct intel_crtc *crtc;
5343
5344 if (!intel_dp_has_connector(intel_dp, conn_state))
5345 continue;
5346
5347 crtc = to_intel_crtc(conn_state->crtc);
5348 if (!crtc)
5349 continue;
5350
5351 ret = drm_modeset_lock(lock: &crtc->base.mutex, ctx);
5352 if (ret)
5353 break;
5354
5355 crtc_state = to_intel_crtc_state(crtc->base.state);
5356
5357 drm_WARN_ON(display->drm,
5358 !intel_crtc_has_dp_encoder(crtc_state));
5359
5360 if (!crtc_state->hw.active)
5361 continue;
5362
5363 wait_for_connector_hw_done(conn_state);
5364
5365 *pipe_mask |= BIT(crtc->pipe);
5366 }
5367 drm_connector_list_iter_end(iter: &conn_iter);
5368
5369 return ret;
5370}
5371
5372void intel_dp_flush_connector_commits(struct intel_connector *connector)
5373{
5374 wait_for_connector_hw_done(conn_state: connector->base.state);
5375}
5376
5377static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5378{
5379 struct intel_connector *connector = intel_dp->attached_connector;
5380
5381 return connector->base.status == connector_status_connected ||
5382 intel_dp->is_mst;
5383}
5384
5385static int intel_dp_retrain_link(struct intel_encoder *encoder,
5386 struct drm_modeset_acquire_ctx *ctx)
5387{
5388 struct intel_display *display = to_intel_display(encoder);
5389 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5390 u8 pipe_mask;
5391 int ret;
5392
5393 if (!intel_dp_is_connected(intel_dp))
5394 return 0;
5395
5396 ret = drm_modeset_lock(lock: &display->drm->mode_config.connection_mutex,
5397 ctx);
5398 if (ret)
5399 return ret;
5400
5401 if (!intel_dp_needs_link_retrain(intel_dp))
5402 return 0;
5403
5404 ret = intel_dp_get_active_pipes(intel_dp, ctx, pipe_mask: &pipe_mask);
5405 if (ret)
5406 return ret;
5407
5408 if (pipe_mask == 0)
5409 return 0;
5410
5411 if (!intel_dp_needs_link_retrain(intel_dp))
5412 return 0;
5413
5414 drm_dbg_kms(display->drm,
5415 "[ENCODER:%d:%s] retraining link (forced %s)\n",
5416 encoder->base.base.id, encoder->base.name,
5417 str_yes_no(intel_dp->link.force_retrain));
5418
5419 ret = intel_modeset_commit_pipes(display, pipe_mask, ctx);
5420 if (ret == -EDEADLK)
5421 return ret;
5422
5423 intel_dp->link.force_retrain = false;
5424
5425 if (ret)
5426 drm_dbg_kms(display->drm,
5427 "[ENCODER:%d:%s] link retraining failed: %pe\n",
5428 encoder->base.base.id, encoder->base.name,
5429 ERR_PTR(ret));
5430
5431 return ret;
5432}
5433
5434void intel_dp_link_check(struct intel_encoder *encoder)
5435{
5436 struct drm_modeset_acquire_ctx ctx;
5437 int ret;
5438
5439 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
5440 ret = intel_dp_retrain_link(encoder, ctx: &ctx);
5441}
5442
5443void intel_dp_check_link_state(struct intel_dp *intel_dp)
5444{
5445 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5446 struct intel_encoder *encoder = &dig_port->base;
5447
5448 if (!intel_dp_is_connected(intel_dp))
5449 return;
5450
5451 if (!intel_dp_needs_link_retrain(intel_dp))
5452 return;
5453
5454 intel_encoder_link_check_queue_work(encoder, delay_ms: 0);
5455}
5456
5457static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5458{
5459 struct intel_display *display = to_intel_display(intel_dp);
5460 u8 val;
5461
5462 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5463 return;
5464
5465 if (drm_dp_dpcd_readb(aux: &intel_dp->aux,
5466 DP_DEVICE_SERVICE_IRQ_VECTOR, valuep: &val) != 1 || !val)
5467 return;
5468
5469 drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, value: val);
5470
5471 if (val & DP_AUTOMATED_TEST_REQUEST)
5472 intel_dp_test_request(intel_dp);
5473
5474 if (val & DP_CP_IRQ)
5475 intel_hdcp_handle_cp_irq(connector: intel_dp->attached_connector);
5476
5477 if (val & DP_SINK_SPECIFIC_IRQ)
5478 drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");
5479}
5480
5481static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5482{
5483 struct intel_display *display = to_intel_display(intel_dp);
5484 bool reprobe_needed = false;
5485 u8 val;
5486
5487 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5488 return false;
5489
5490 if (drm_dp_dpcd_readb(aux: &intel_dp->aux,
5491 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, valuep: &val) != 1 || !val)
5492 return false;
5493
5494 if ((val & DP_TUNNELING_IRQ) &&
5495 drm_dp_tunnel_handle_irq(mgr: display->dp_tunnel_mgr,
5496 aux: &intel_dp->aux))
5497 reprobe_needed = true;
5498
5499 if (drm_dp_dpcd_writeb(aux: &intel_dp->aux,
5500 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, value: val) != 1)
5501 return reprobe_needed;
5502
5503 if (val & HDMI_LINK_STATUS_CHANGED)
5504 intel_dp_handle_hdmi_link_status_change(intel_dp);
5505
5506 return reprobe_needed;
5507}
5508
5509/*
5510 * According to DP spec
5511 * 5.1.2:
5512 * 1. Read DPCD
5513 * 2. Configure link according to Receiver Capabilities
5514 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5515 * 4. Check link status on receipt of hot-plug interrupt
5516 *
5517 * intel_dp_short_pulse - handles short pulse interrupts
5518 * when full detection is not required.
5519 * Returns %true if short pulse is handled and full detection
5520 * is NOT required and %false otherwise.
5521 */
5522static bool
5523intel_dp_short_pulse(struct intel_dp *intel_dp)
5524{
5525 u8 old_sink_count = intel_dp->sink_count;
5526 bool reprobe_needed = false;
5527 bool ret;
5528
5529 intel_dp_test_reset(intel_dp);
5530
5531 /*
5532 * Now read the DPCD to see if it's actually running
5533 * If the current value of sink count doesn't match with
5534 * the value that was stored earlier or dpcd read failed
5535 * we need to do full detection
5536 */
5537 ret = intel_dp_get_dpcd(intel_dp);
5538
5539 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5540 /* No need to proceed if we are going to do full detect */
5541 return false;
5542 }
5543
5544 intel_dp_check_device_service_irq(intel_dp);
5545 reprobe_needed = intel_dp_check_link_service_irq(intel_dp);
5546
5547 /* Handle CEC interrupts, if any */
5548 drm_dp_cec_irq(aux: &intel_dp->aux);
5549
5550 intel_dp_check_link_state(intel_dp);
5551
5552 intel_psr_short_pulse(intel_dp);
5553
5554 if (intel_alpm_get_error(intel_dp)) {
5555 intel_alpm_disable(intel_dp);
5556 intel_dp->alpm_parameters.sink_alpm_error = true;
5557 }
5558
5559 if (intel_dp_test_short_pulse(intel_dp))
5560 reprobe_needed = true;
5561
5562 return !reprobe_needed;
5563}
5564
5565/* XXX this is probably wrong for multiple downstream ports */
5566static enum drm_connector_status
5567intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5568{
5569 struct intel_display *display = to_intel_display(intel_dp);
5570 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5571 u8 *dpcd = intel_dp->dpcd;
5572 u8 type;
5573
5574 if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))
5575 return connector_status_connected;
5576
5577 intel_lspcon_resume(dig_port);
5578
5579 if (!intel_dp_get_dpcd(intel_dp))
5580 return connector_status_disconnected;
5581
5582 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);
5583
5584 /* if there's no downstream port, we're done */
5585 if (!drm_dp_is_branch(dpcd))
5586 return connector_status_connected;
5587
5588 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5589 if (intel_dp_has_sink_count(intel_dp) &&
5590 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5591 return intel_dp->sink_count ?
5592 connector_status_connected : connector_status_disconnected;
5593 }
5594
5595 if (intel_dp->mst_detect == DRM_DP_MST)
5596 return connector_status_connected;
5597
5598 /* If no HPD, poke DDC gently */
5599 if (drm_probe_ddc(adapter: &intel_dp->aux.ddc))
5600 return connector_status_connected;
5601
5602 /* Well we tried, say unknown for unreliable port types */
5603 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5604 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5605 if (type == DP_DS_PORT_TYPE_VGA ||
5606 type == DP_DS_PORT_TYPE_NON_EDID)
5607 return connector_status_unknown;
5608 } else {
5609 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5610 DP_DWN_STRM_PORT_TYPE_MASK;
5611 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5612 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5613 return connector_status_unknown;
5614 }
5615
5616 /* Anything else is out of spec, warn and ignore */
5617 drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");
5618 return connector_status_disconnected;
5619}
5620
5621static enum drm_connector_status
5622edp_detect(struct intel_dp *intel_dp)
5623{
5624 return connector_status_connected;
5625}
5626
5627void intel_digital_port_lock(struct intel_encoder *encoder)
5628{
5629 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5630
5631 if (dig_port->lock)
5632 dig_port->lock(dig_port);
5633}
5634
5635void intel_digital_port_unlock(struct intel_encoder *encoder)
5636{
5637 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5638
5639 if (dig_port->unlock)
5640 dig_port->unlock(dig_port);
5641}
5642
5643/*
5644 * intel_digital_port_connected_locked - is the specified port connected?
5645 * @encoder: intel_encoder
5646 *
5647 * In cases where there's a connector physically connected but it can't be used
5648 * by our hardware we also return false, since the rest of the driver should
5649 * pretty much treat the port as disconnected. This is relevant for type-C
5650 * (starting on ICL) where there's ownership involved.
5651 *
5652 * The caller must hold the lock acquired by calling intel_digital_port_lock()
5653 * when calling this function.
5654 *
5655 * Return %true if port is connected, %false otherwise.
5656 */
5657bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5658{
5659 struct intel_display *display = to_intel_display(encoder);
5660 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5661 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5662 bool is_connected = false;
5663 intel_wakeref_t wakeref;
5664
5665 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5666 poll_timeout_us(is_connected = dig_port->connected(encoder),
5667 is_connected || is_glitch_free,
5668 30, 4000, false);
5669 }
5670
5671 return is_connected;
5672}
5673
5674bool intel_digital_port_connected(struct intel_encoder *encoder)
5675{
5676 bool ret;
5677
5678 intel_digital_port_lock(encoder);
5679 ret = intel_digital_port_connected_locked(encoder);
5680 intel_digital_port_unlock(encoder);
5681
5682 return ret;
5683}
5684
5685static const struct drm_edid *
5686intel_dp_get_edid(struct intel_dp *intel_dp)
5687{
5688 struct intel_connector *connector = intel_dp->attached_connector;
5689 const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5690
5691 /* Use panel fixed edid if we have one */
5692 if (fixed_edid) {
5693 /* invalid edid */
5694 if (IS_ERR(ptr: fixed_edid))
5695 return NULL;
5696
5697 return drm_edid_dup(drm_edid: fixed_edid);
5698 }
5699
5700 return drm_edid_read_ddc(connector: &connector->base, adapter: &intel_dp->aux.ddc);
5701}
5702
5703static void
5704intel_dp_update_dfp(struct intel_dp *intel_dp,
5705 const struct drm_edid *drm_edid)
5706{
5707 struct intel_display *display = to_intel_display(intel_dp);
5708 struct intel_connector *connector = intel_dp->attached_connector;
5709
5710 intel_dp->dfp.max_bpc =
5711 drm_dp_downstream_max_bpc(dpcd: intel_dp->dpcd,
5712 port_cap: intel_dp->downstream_ports, drm_edid);
5713
5714 intel_dp->dfp.max_dotclock =
5715 drm_dp_downstream_max_dotclock(dpcd: intel_dp->dpcd,
5716 port_cap: intel_dp->downstream_ports);
5717
5718 intel_dp->dfp.min_tmds_clock =
5719 drm_dp_downstream_min_tmds_clock(dpcd: intel_dp->dpcd,
5720 port_cap: intel_dp->downstream_ports,
5721 drm_edid);
5722 intel_dp->dfp.max_tmds_clock =
5723 drm_dp_downstream_max_tmds_clock(dpcd: intel_dp->dpcd,
5724 port_cap: intel_dp->downstream_ports,
5725 drm_edid);
5726
5727 intel_dp->dfp.pcon_max_frl_bw =
5728 drm_dp_get_pcon_max_frl_bw(dpcd: intel_dp->dpcd,
5729 port_cap: intel_dp->downstream_ports);
5730
5731 drm_dbg_kms(display->drm,
5732 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5733 connector->base.base.id, connector->base.name,
5734 intel_dp->dfp.max_bpc,
5735 intel_dp->dfp.max_dotclock,
5736 intel_dp->dfp.min_tmds_clock,
5737 intel_dp->dfp.max_tmds_clock,
5738 intel_dp->dfp.pcon_max_frl_bw);
5739
5740 intel_dp_get_pcon_dsc_cap(intel_dp);
5741}
5742
5743static bool
5744intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5745{
5746 if (source_can_output(intel_dp, format: INTEL_OUTPUT_FORMAT_YCBCR420) &&
5747 (!drm_dp_is_branch(dpcd: intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5748 return true;
5749
5750 if (source_can_output(intel_dp, format: INTEL_OUTPUT_FORMAT_RGB) &&
5751 dfp_can_convert_from_rgb(intel_dp, sink_format: INTEL_OUTPUT_FORMAT_YCBCR420))
5752 return true;
5753
5754 if (source_can_output(intel_dp, format: INTEL_OUTPUT_FORMAT_YCBCR444) &&
5755 dfp_can_convert_from_ycbcr444(intel_dp, sink_format: INTEL_OUTPUT_FORMAT_YCBCR420))
5756 return true;
5757
5758 return false;
5759}
5760
5761static void
5762intel_dp_update_420(struct intel_dp *intel_dp)
5763{
5764 struct intel_display *display = to_intel_display(intel_dp);
5765 struct intel_connector *connector = intel_dp->attached_connector;
5766
5767 intel_dp->dfp.ycbcr420_passthrough =
5768 drm_dp_downstream_420_passthrough(dpcd: intel_dp->dpcd,
5769 port_cap: intel_dp->downstream_ports);
5770 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5771 intel_dp->dfp.ycbcr_444_to_420 =
5772 intel_lspcon_active(dig_port: dp_to_dig_port(intel_dp)) ||
5773 drm_dp_downstream_444_to_420_conversion(dpcd: intel_dp->dpcd,
5774 port_cap: intel_dp->downstream_ports);
5775 intel_dp->dfp.rgb_to_ycbcr =
5776 drm_dp_downstream_rgb_to_ycbcr_conversion(dpcd: intel_dp->dpcd,
5777 port_cap: intel_dp->downstream_ports,
5778 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5779
5780 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5781
5782 drm_dbg_kms(display->drm,
5783 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5784 connector->base.base.id, connector->base.name,
5785 str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5786 str_yes_no(connector->base.ycbcr_420_allowed),
5787 str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5788}
5789
5790static void
5791intel_dp_set_edid(struct intel_dp *intel_dp)
5792{
5793 struct intel_display *display = to_intel_display(intel_dp);
5794 struct intel_connector *connector = intel_dp->attached_connector;
5795 const struct drm_edid *drm_edid;
5796 bool vrr_capable;
5797
5798 intel_dp_unset_edid(intel_dp);
5799 drm_edid = intel_dp_get_edid(intel_dp);
5800 connector->detect_edid = drm_edid;
5801
5802 /* Below we depend on display info having been updated */
5803 drm_edid_connector_update(connector: &connector->base, edid: drm_edid);
5804
5805 vrr_capable = intel_vrr_is_capable(connector);
5806 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5807 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5808 drm_connector_set_vrr_capable_property(connector: &connector->base, capable: vrr_capable);
5809
5810 intel_dp_update_dfp(intel_dp, drm_edid);
5811 intel_dp_update_420(intel_dp);
5812
5813 drm_dp_cec_attach(aux: &intel_dp->aux,
5814 source_physical_address: connector->base.display_info.source_physical_address);
5815}
5816
5817static void
5818intel_dp_unset_edid(struct intel_dp *intel_dp)
5819{
5820 struct intel_connector *connector = intel_dp->attached_connector;
5821
5822 drm_dp_cec_unset_edid(aux: &intel_dp->aux);
5823 drm_edid_free(drm_edid: connector->detect_edid);
5824 connector->detect_edid = NULL;
5825
5826 intel_dp->dfp.max_bpc = 0;
5827 intel_dp->dfp.max_dotclock = 0;
5828 intel_dp->dfp.min_tmds_clock = 0;
5829 intel_dp->dfp.max_tmds_clock = 0;
5830
5831 intel_dp->dfp.pcon_max_frl_bw = 0;
5832
5833 intel_dp->dfp.ycbcr_444_to_420 = false;
5834 connector->base.ycbcr_420_allowed = false;
5835
5836 drm_connector_set_vrr_capable_property(connector: &connector->base,
5837 capable: false);
5838}
5839
5840static void
5841intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
5842{
5843 struct intel_display *display = to_intel_display(intel_dp);
5844
5845 intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
5846 drm_dp_as_sdp_supported(aux: &intel_dp->aux, dpcd: intel_dp->dpcd);
5847}
5848
5849static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
5850{
5851 struct intel_connector *connector = intel_dp->attached_connector;
5852
5853 if (intel_dp_is_edp(intel_dp))
5854 return false;
5855
5856 if (force_on_external)
5857 return true;
5858
5859 if (intel_dp->is_mst)
5860 return false;
5861
5862 return drm_edid_has_quirk(connector: &connector->base, quirk: DRM_EDID_QUIRK_DP_DPCD_PROBE);
5863}
5864
5865void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external)
5866{
5867 drm_dp_dpcd_set_probe(aux: &intel_dp->aux,
5868 enable: intel_dp_needs_dpcd_probe(intel_dp, force_on_external));
5869}
5870
5871static int
5872intel_dp_detect(struct drm_connector *_connector,
5873 struct drm_modeset_acquire_ctx *ctx,
5874 bool force)
5875{
5876 struct intel_display *display = to_intel_display(_connector->dev);
5877 struct intel_connector *connector = to_intel_connector(_connector);
5878 struct intel_dp *intel_dp = intel_attached_dp(connector);
5879 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5880 struct intel_encoder *encoder = &dig_port->base;
5881 enum drm_connector_status status;
5882 int ret;
5883
5884 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
5885 connector->base.base.id, connector->base.name);
5886 drm_WARN_ON(display->drm,
5887 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
5888
5889 if (!intel_display_device_enabled(display))
5890 return connector_status_disconnected;
5891
5892 if (!intel_display_driver_check_access(display))
5893 return connector->base.status;
5894
5895 intel_dp_flush_connector_commits(connector);
5896
5897 intel_pps_vdd_on(intel_dp);
5898
5899 /* Can't disconnect eDP */
5900 if (intel_dp_is_edp(intel_dp))
5901 status = edp_detect(intel_dp);
5902 else if (intel_digital_port_connected(encoder))
5903 status = intel_dp_detect_dpcd(intel_dp);
5904 else
5905 status = connector_status_disconnected;
5906
5907 if (status != connector_status_disconnected &&
5908 !intel_dp_mst_verify_dpcd_state(intel_dp))
5909 /*
5910 * This requires retrying detection for instance to re-enable
5911 * the MST mode that got reset via a long HPD pulse. The retry
5912 * will happen either via the hotplug handler's retry logic,
5913 * ensured by setting the connector here to SST/disconnected,
5914 * or via a userspace connector probing in response to the
5915 * hotplug uevent sent when removing the MST connectors.
5916 */
5917 status = connector_status_disconnected;
5918
5919 if (status == connector_status_disconnected) {
5920 intel_dp_test_reset(intel_dp);
5921 memset(s: connector->dp.dsc_dpcd, c: 0, n: sizeof(connector->dp.dsc_dpcd));
5922 intel_dp->psr.sink_panel_replay_support = false;
5923 intel_dp->psr.sink_panel_replay_su_support = false;
5924
5925 intel_dp_mst_disconnect(intel_dp);
5926
5927 intel_dp_tunnel_disconnect(intel_dp);
5928
5929 goto out_unset_edid;
5930 }
5931
5932 intel_dp_init_source_oui(intel_dp);
5933
5934 ret = intel_dp_tunnel_detect(intel_dp, ctx);
5935 if (ret == -EDEADLK) {
5936 status = ret;
5937
5938 goto out_vdd_off;
5939 }
5940
5941 if (ret == 1)
5942 connector->base.epoch_counter++;
5943
5944 if (!intel_dp_is_edp(intel_dp))
5945 intel_psr_init_dpcd(intel_dp);
5946
5947 intel_dp_detect_dsc_caps(intel_dp, connector);
5948
5949 intel_dp_detect_sdp_caps(intel_dp);
5950
5951 if (intel_dp->reset_link_params) {
5952 intel_dp_reset_link_params(intel_dp);
5953 intel_dp->reset_link_params = false;
5954 }
5955
5956 intel_dp_mst_configure(intel_dp);
5957
5958 intel_dp_print_rates(intel_dp);
5959
5960 if (intel_dp->is_mst) {
5961 /*
5962 * If we are in MST mode then this connector
5963 * won't appear connected or have anything
5964 * with EDID on it
5965 */
5966 status = connector_status_disconnected;
5967 goto out_unset_edid;
5968 }
5969
5970 /*
5971 * Some external monitors do not signal loss of link synchronization
5972 * with an IRQ_HPD, so force a link status check.
5973 *
5974 * TODO: this probably became redundant, so remove it: the link state
5975 * is rechecked/recovered now after modesets, where the loss of
5976 * synchronization tends to occur.
5977 */
5978 if (!intel_dp_is_edp(intel_dp))
5979 intel_dp_check_link_state(intel_dp);
5980
5981 /*
5982 * Clearing NACK and defer counts to get their exact values
5983 * while reading EDID which are required by Compliance tests
5984 * 4.2.2.4 and 4.2.2.5
5985 */
5986 intel_dp->aux.i2c_nack_count = 0;
5987 intel_dp->aux.i2c_defer_count = 0;
5988
5989 intel_dp_set_edid(intel_dp);
5990 if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
5991 status = connector_status_connected;
5992
5993 intel_dp_check_device_service_irq(intel_dp);
5994
5995out_unset_edid:
5996 if (status != connector_status_connected && !intel_dp->is_mst)
5997 intel_dp_unset_edid(intel_dp);
5998
5999 intel_dp_dpcd_set_probe(intel_dp, force_on_external: false);
6000
6001 if (!intel_dp_is_edp(intel_dp))
6002 drm_dp_set_subconnector_property(connector: &connector->base,
6003 status,
6004 dpcd: intel_dp->dpcd,
6005 port_cap: intel_dp->downstream_ports);
6006out_vdd_off:
6007 intel_pps_vdd_off(intel_dp);
6008
6009 return status;
6010}
6011
6012static void
6013intel_dp_force(struct drm_connector *_connector)
6014{
6015 struct intel_connector *connector = to_intel_connector(_connector);
6016 struct intel_display *display = to_intel_display(connector);
6017 struct intel_dp *intel_dp = intel_attached_dp(connector);
6018
6019 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
6020 connector->base.base.id, connector->base.name);
6021
6022 if (!intel_display_driver_check_access(display))
6023 return;
6024
6025 intel_dp_unset_edid(intel_dp);
6026
6027 if (connector->base.status != connector_status_connected)
6028 return;
6029
6030 intel_dp_set_edid(intel_dp);
6031
6032 intel_dp_dpcd_set_probe(intel_dp, force_on_external: false);
6033}
6034
6035static int intel_dp_get_modes(struct drm_connector *_connector)
6036{
6037 struct intel_display *display = to_intel_display(_connector->dev);
6038 struct intel_connector *connector = to_intel_connector(_connector);
6039 struct intel_dp *intel_dp = intel_attached_dp(connector);
6040 int num_modes;
6041
6042 /* drm_edid_connector_update() done in ->detect() or ->force() */
6043 num_modes = drm_edid_connector_add_modes(connector: &connector->base);
6044
6045 /* Also add fixed mode, which may or may not be present in EDID */
6046 if (intel_dp_is_edp(intel_dp))
6047 num_modes += intel_panel_get_modes(connector);
6048
6049 if (num_modes)
6050 return num_modes;
6051
6052 if (!connector->detect_edid) {
6053 struct drm_display_mode *mode;
6054
6055 mode = drm_dp_downstream_mode(dev: display->drm,
6056 dpcd: intel_dp->dpcd,
6057 port_cap: intel_dp->downstream_ports);
6058 if (mode) {
6059 drm_mode_probed_add(connector: &connector->base, mode);
6060 num_modes++;
6061 }
6062 }
6063
6064 return num_modes;
6065}
6066
6067static int
6068intel_dp_connector_register(struct drm_connector *_connector)
6069{
6070 struct intel_connector *connector = to_intel_connector(_connector);
6071 struct intel_display *display = to_intel_display(connector);
6072 struct intel_dp *intel_dp = intel_attached_dp(connector);
6073 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6074 int ret;
6075
6076 ret = intel_connector_register(connector: &connector->base);
6077 if (ret)
6078 return ret;
6079
6080 drm_dbg_kms(display->drm, "registering %s bus for %s\n",
6081 intel_dp->aux.name, connector->base.kdev->kobj.name);
6082
6083 intel_dp->aux.dev = connector->base.kdev;
6084 ret = drm_dp_aux_register(aux: &intel_dp->aux);
6085 if (!ret)
6086 drm_dp_cec_register_connector(aux: &intel_dp->aux, connector: &connector->base);
6087
6088 if (!intel_bios_encoder_is_lspcon(devdata: dig_port->base.devdata))
6089 return ret;
6090
6091 /*
6092 * ToDo: Clean this up to handle lspcon init and resume more
6093 * efficiently and streamlined.
6094 */
6095 if (intel_lspcon_init(dig_port)) {
6096 if (intel_lspcon_detect_hdr_capability(dig_port))
6097 drm_connector_attach_hdr_output_metadata_property(connector: &connector->base);
6098 }
6099
6100 return ret;
6101}
6102
6103static void
6104intel_dp_connector_unregister(struct drm_connector *_connector)
6105{
6106 struct intel_connector *connector = to_intel_connector(_connector);
6107 struct intel_dp *intel_dp = intel_attached_dp(connector);
6108
6109 drm_dp_cec_unregister_connector(aux: &intel_dp->aux);
6110 drm_dp_aux_unregister(aux: &intel_dp->aux);
6111 intel_connector_unregister(connector: &connector->base);
6112}
6113
6114void intel_dp_connector_sync_state(struct intel_connector *connector,
6115 const struct intel_crtc_state *crtc_state)
6116{
6117 struct intel_display *display = to_intel_display(connector);
6118
6119 if (crtc_state && crtc_state->dsc.compression_enable) {
6120 drm_WARN_ON(display->drm,
6121 !connector->dp.dsc_decompression_aux);
6122 connector->dp.dsc_decompression_enabled = true;
6123 } else {
6124 connector->dp.dsc_decompression_enabled = false;
6125 }
6126}
6127
6128void intel_dp_encoder_flush_work(struct drm_encoder *_encoder)
6129{
6130 struct intel_encoder *encoder = to_intel_encoder(_encoder);
6131 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6132 struct intel_dp *intel_dp = &dig_port->dp;
6133
6134 intel_encoder_link_check_flush_work(encoder);
6135
6136 intel_dp_mst_encoder_cleanup(dig_port);
6137
6138 intel_dp_tunnel_destroy(intel_dp);
6139
6140 intel_pps_vdd_off_sync(intel_dp);
6141
6142 /*
6143 * Ensure power off delay is respected on module remove, so that we can
6144 * reduce delays at driver probe. See pps_init_timestamps().
6145 */
6146 intel_pps_wait_power_cycle(intel_dp);
6147
6148 intel_dp_aux_fini(intel_dp);
6149}
6150
6151void intel_dp_encoder_suspend(struct intel_encoder *encoder)
6152{
6153 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6154
6155 intel_pps_vdd_off_sync(intel_dp);
6156
6157 intel_dp_tunnel_suspend(intel_dp);
6158}
6159
6160void intel_dp_encoder_shutdown(struct intel_encoder *encoder)
6161{
6162 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6163
6164 intel_pps_wait_power_cycle(intel_dp);
6165}
6166
6167static int intel_modeset_tile_group(struct intel_atomic_state *state,
6168 int tile_group_id)
6169{
6170 struct intel_display *display = to_intel_display(state);
6171 struct drm_connector_list_iter conn_iter;
6172 struct intel_connector *connector;
6173 int ret = 0;
6174
6175 drm_connector_list_iter_begin(dev: display->drm, iter: &conn_iter);
6176 for_each_intel_connector_iter(connector, &conn_iter) {
6177 struct drm_connector_state *conn_state;
6178 struct intel_crtc_state *crtc_state;
6179 struct intel_crtc *crtc;
6180
6181 if (!connector->base.has_tile ||
6182 connector->base.tile_group->id != tile_group_id)
6183 continue;
6184
6185 conn_state = drm_atomic_get_connector_state(state: &state->base,
6186 connector: &connector->base);
6187 if (IS_ERR(ptr: conn_state)) {
6188 ret = PTR_ERR(ptr: conn_state);
6189 break;
6190 }
6191
6192 crtc = to_intel_crtc(conn_state->crtc);
6193
6194 if (!crtc)
6195 continue;
6196
6197 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6198 crtc_state->uapi.mode_changed = true;
6199
6200 ret = drm_atomic_add_affected_planes(state: &state->base, crtc: &crtc->base);
6201 if (ret)
6202 break;
6203 }
6204 drm_connector_list_iter_end(iter: &conn_iter);
6205
6206 return ret;
6207}
6208
6209static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6210{
6211 struct intel_display *display = to_intel_display(state);
6212 struct intel_crtc *crtc;
6213
6214 if (transcoders == 0)
6215 return 0;
6216
6217 for_each_intel_crtc(display->drm, crtc) {
6218 struct intel_crtc_state *crtc_state;
6219 int ret;
6220
6221 crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
6222 if (IS_ERR(ptr: crtc_state))
6223 return PTR_ERR(ptr: crtc_state);
6224
6225 if (!crtc_state->hw.enable)
6226 continue;
6227
6228 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
6229 continue;
6230
6231 crtc_state->uapi.mode_changed = true;
6232
6233 ret = drm_atomic_add_affected_connectors(state: &state->base, crtc: &crtc->base);
6234 if (ret)
6235 return ret;
6236
6237 ret = drm_atomic_add_affected_planes(state: &state->base, crtc: &crtc->base);
6238 if (ret)
6239 return ret;
6240
6241 transcoders &= ~BIT(crtc_state->cpu_transcoder);
6242 }
6243
6244 drm_WARN_ON(display->drm, transcoders != 0);
6245
6246 return 0;
6247}
6248
6249static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
6250 struct drm_connector *_connector)
6251{
6252 struct intel_connector *connector = to_intel_connector(_connector);
6253 const struct drm_connector_state *old_conn_state =
6254 drm_atomic_get_old_connector_state(state: &state->base, connector: &connector->base);
6255 const struct intel_crtc_state *old_crtc_state;
6256 struct intel_crtc *crtc;
6257 u8 transcoders;
6258
6259 crtc = to_intel_crtc(old_conn_state->crtc);
6260 if (!crtc)
6261 return 0;
6262
6263 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6264
6265 if (!old_crtc_state->hw.active)
6266 return 0;
6267
6268 transcoders = old_crtc_state->sync_mode_slaves_mask;
6269 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6270 transcoders |= BIT(old_crtc_state->master_transcoder);
6271
6272 return intel_modeset_affected_transcoders(state,
6273 transcoders);
6274}
6275
6276static int intel_dp_connector_atomic_check(struct drm_connector *_connector,
6277 struct drm_atomic_state *_state)
6278{
6279 struct intel_connector *connector = to_intel_connector(_connector);
6280 struct intel_display *display = to_intel_display(connector);
6281 struct intel_atomic_state *state = to_intel_atomic_state(_state);
6282 struct drm_connector_state *conn_state =
6283 drm_atomic_get_new_connector_state(state: _state, connector: &connector->base);
6284 struct intel_dp *intel_dp = enc_to_intel_dp(encoder: connector->encoder);
6285 int ret;
6286
6287 ret = intel_digital_connector_atomic_check(conn: &connector->base, state: &state->base);
6288 if (ret)
6289 return ret;
6290
6291 if (intel_dp_mst_source_support(intel_dp)) {
6292 ret = drm_dp_mst_root_conn_atomic_check(new_conn_state: conn_state, mgr: &intel_dp->mst.mgr);
6293 if (ret)
6294 return ret;
6295 }
6296
6297 if (!intel_connector_needs_modeset(state, connector: &connector->base))
6298 return 0;
6299
6300 ret = intel_dp_tunnel_atomic_check_state(state,
6301 intel_dp,
6302 connector);
6303 if (ret)
6304 return ret;
6305
6306 /*
6307 * We don't enable port sync on BDW due to missing w/as and
6308 * due to not having adjusted the modeset sequence appropriately.
6309 */
6310 if (DISPLAY_VER(display) < 9)
6311 return 0;
6312
6313 if (connector->base.has_tile) {
6314 ret = intel_modeset_tile_group(state, tile_group_id: connector->base.tile_group->id);
6315 if (ret)
6316 return ret;
6317 }
6318
6319 return intel_modeset_synced_crtcs(state, connector: &connector->base);
6320}
6321
6322static void intel_dp_oob_hotplug_event(struct drm_connector *_connector,
6323 enum drm_connector_status hpd_state)
6324{
6325 struct intel_connector *connector = to_intel_connector(_connector);
6326 struct intel_display *display = to_intel_display(connector);
6327 struct intel_encoder *encoder = intel_attached_encoder(connector);
6328 bool hpd_high = hpd_state == connector_status_connected;
6329 unsigned int hpd_pin = encoder->hpd_pin;
6330 bool need_work = false;
6331
6332 spin_lock_irq(lock: &display->irq.lock);
6333 if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {
6334 display->hotplug.event_bits |= BIT(hpd_pin);
6335
6336 __assign_bit(hpd_pin,
6337 &display->hotplug.oob_hotplug_last_state,
6338 hpd_high);
6339 need_work = true;
6340 }
6341 spin_unlock_irq(lock: &display->irq.lock);
6342
6343 if (need_work)
6344 intel_hpd_schedule_detection(display);
6345}
6346
6347static const struct drm_connector_funcs intel_dp_connector_funcs = {
6348 .force = intel_dp_force,
6349 .fill_modes = drm_helper_probe_single_connector_modes,
6350 .atomic_get_property = intel_digital_connector_atomic_get_property,
6351 .atomic_set_property = intel_digital_connector_atomic_set_property,
6352 .late_register = intel_dp_connector_register,
6353 .early_unregister = intel_dp_connector_unregister,
6354 .destroy = intel_connector_destroy,
6355 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6356 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6357 .oob_hotplug_event = intel_dp_oob_hotplug_event,
6358};
6359
6360static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6361 .detect_ctx = intel_dp_detect,
6362 .get_modes = intel_dp_get_modes,
6363 .mode_valid = intel_dp_mode_valid,
6364 .atomic_check = intel_dp_connector_atomic_check,
6365};
6366
6367enum irqreturn
6368intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6369{
6370 struct intel_display *display = to_intel_display(dig_port);
6371 struct intel_dp *intel_dp = &dig_port->dp;
6372 u8 dpcd[DP_RECEIVER_CAP_SIZE];
6373
6374 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6375 (long_hpd ||
6376 intel_display_rpm_suspended(display) ||
6377 !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6378 /*
6379 * vdd off can generate a long/short pulse on eDP which
6380 * would require vdd on to handle it, and thus we
6381 * would end up in an endless cycle of
6382 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6383 */
6384 drm_dbg_kms(display->drm,
6385 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6386 long_hpd ? "long" : "short",
6387 dig_port->base.base.base.id,
6388 dig_port->base.base.name);
6389 return IRQ_HANDLED;
6390 }
6391
6392 drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6393 dig_port->base.base.base.id,
6394 dig_port->base.base.name,
6395 long_hpd ? "long" : "short");
6396
6397 /*
6398 * TBT DP tunnels require the GFX driver to read out the DPRX caps in
6399 * response to long HPD pulses. The DP hotplug handler does that,
6400 * however the hotplug handler may be blocked by another
6401 * connector's/encoder's hotplug handler. Since the TBT CM may not
6402 * complete the DP tunnel BW request for the latter connector/encoder
6403 * waiting for this encoder's DPRX read, perform a dummy read here.
6404 */
6405 if (long_hpd) {
6406 intel_dp_dpcd_set_probe(intel_dp, force_on_external: true);
6407
6408 intel_dp_read_dprx_caps(intel_dp, dpcd);
6409
6410 intel_dp->reset_link_params = true;
6411 intel_dp_invalidate_source_oui(intel_dp);
6412
6413 return IRQ_NONE;
6414 }
6415
6416 if (intel_dp->is_mst) {
6417 if (!intel_dp_check_mst_status(intel_dp))
6418 return IRQ_NONE;
6419 } else if (!intel_dp_short_pulse(intel_dp)) {
6420 return IRQ_NONE;
6421 }
6422
6423 return IRQ_HANDLED;
6424}
6425
6426static bool _intel_dp_is_port_edp(struct intel_display *display,
6427 const struct intel_bios_encoder_data *devdata,
6428 enum port port)
6429{
6430 /*
6431 * eDP not supported on g4x. so bail out early just
6432 * for a bit extra safety in case the VBT is bonkers.
6433 */
6434 if (DISPLAY_VER(display) < 5)
6435 return false;
6436
6437 if (DISPLAY_VER(display) < 9 && port == PORT_A)
6438 return true;
6439
6440 return devdata && intel_bios_encoder_supports_edp(devdata);
6441}
6442
6443bool intel_dp_is_port_edp(struct intel_display *display, enum port port)
6444{
6445 const struct intel_bios_encoder_data *devdata =
6446 intel_bios_encoder_data_lookup(display, port);
6447
6448 return _intel_dp_is_port_edp(display, devdata, port);
6449}
6450
6451bool
6452intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)
6453{
6454 struct intel_display *display = to_intel_display(encoder);
6455 enum port port = encoder->port;
6456
6457 if (intel_bios_encoder_is_lspcon(devdata: encoder->devdata))
6458 return false;
6459
6460 if (DISPLAY_VER(display) >= 11)
6461 return true;
6462
6463 if (port == PORT_A)
6464 return false;
6465
6466 if (display->platform.haswell || display->platform.broadwell ||
6467 DISPLAY_VER(display) >= 9)
6468 return true;
6469
6470 return false;
6471}
6472
6473static void
6474intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *_connector)
6475{
6476 struct intel_connector *connector = to_intel_connector(_connector);
6477 struct intel_display *display = to_intel_display(intel_dp);
6478 enum port port = dp_to_dig_port(intel_dp)->base.port;
6479
6480 if (!intel_dp_is_edp(intel_dp))
6481 drm_connector_attach_dp_subconnector_property(connector: &connector->base);
6482
6483 if (!display->platform.g4x && port != PORT_A)
6484 intel_attach_force_audio_property(connector: &connector->base);
6485
6486 intel_attach_broadcast_rgb_property(connector: &connector->base);
6487 if (HAS_GMCH(display))
6488 drm_connector_attach_max_bpc_property(connector: &connector->base, min: 6, max: 10);
6489 else if (DISPLAY_VER(display) >= 5)
6490 drm_connector_attach_max_bpc_property(connector: &connector->base, min: 6, max: 12);
6491
6492 /* Register HDMI colorspace for case of lspcon */
6493 if (intel_bios_encoder_is_lspcon(devdata: dp_to_dig_port(intel_dp)->base.devdata)) {
6494 drm_connector_attach_content_type_property(dev: &connector->base);
6495 intel_attach_hdmi_colorspace_property(connector: &connector->base);
6496 } else {
6497 intel_attach_dp_colorspace_property(connector: &connector->base);
6498 }
6499
6500 if (intel_dp_has_gamut_metadata_dip(encoder: &dp_to_dig_port(intel_dp)->base))
6501 drm_connector_attach_hdr_output_metadata_property(connector: &connector->base);
6502
6503 if (HAS_VRR(display))
6504 drm_connector_attach_vrr_capable_property(connector: &connector->base);
6505}
6506
6507static void
6508intel_edp_add_properties(struct intel_dp *intel_dp)
6509{
6510 struct intel_display *display = to_intel_display(intel_dp);
6511 struct intel_connector *connector = intel_dp->attached_connector;
6512 const struct drm_display_mode *fixed_mode =
6513 intel_panel_preferred_fixed_mode(connector);
6514
6515 intel_attach_scaling_mode_property(connector: &connector->base);
6516
6517 drm_connector_set_panel_orientation_with_quirk(connector: &connector->base,
6518 panel_orientation: display->vbt.orientation,
6519 width: fixed_mode->hdisplay,
6520 height: fixed_mode->vdisplay);
6521}
6522
6523static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6524 struct intel_connector *connector)
6525{
6526 struct intel_display *display = to_intel_display(intel_dp);
6527 enum pipe pipe = INVALID_PIPE;
6528
6529 if (display->platform.valleyview || display->platform.cherryview)
6530 pipe = vlv_pps_backlight_initial_pipe(intel_dp);
6531
6532 intel_backlight_setup(connector, pipe);
6533}
6534
6535static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6536 struct intel_connector *connector)
6537{
6538 struct intel_display *display = to_intel_display(intel_dp);
6539 struct drm_display_mode *fixed_mode;
6540 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6541 bool has_dpcd;
6542 const struct drm_edid *drm_edid;
6543
6544 if (!intel_dp_is_edp(intel_dp))
6545 return true;
6546
6547 /*
6548 * On IBX/CPT we may get here with LVDS already registered. Since the
6549 * driver uses the only internal power sequencer available for both
6550 * eDP and LVDS bail out early in this case to prevent interfering
6551 * with an already powered-on LVDS power sequencer.
6552 */
6553 if (intel_get_lvds_encoder(display)) {
6554 drm_WARN_ON(display->drm,
6555 !(HAS_PCH_IBX(display) || HAS_PCH_CPT(display)));
6556 drm_info(display->drm,
6557 "LVDS was detected, not registering eDP\n");
6558
6559 return false;
6560 }
6561
6562 intel_bios_init_panel_early(display, panel: &connector->panel,
6563 devdata: encoder->devdata);
6564
6565 if (!intel_pps_init(intel_dp)) {
6566 drm_info(display->drm,
6567 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6568 encoder->base.base.id, encoder->base.name);
6569 /*
6570 * The BIOS may have still enabled VDD on the PPS even
6571 * though it's unusable. Make sure we turn it back off
6572 * and to release the power domain references/etc.
6573 */
6574 goto out_vdd_off;
6575 }
6576
6577 /*
6578 * Enable HPD sense for live status check.
6579 * intel_hpd_irq_setup() will turn it off again
6580 * if it's no longer needed later.
6581 *
6582 * The DPCD probe below will make sure VDD is on.
6583 */
6584 intel_hpd_enable_detection(encoder);
6585
6586 intel_alpm_init(intel_dp);
6587
6588 /* Cache DPCD and EDID for edp. */
6589 has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
6590
6591 if (!has_dpcd) {
6592 /* if this fails, presume the device is a ghost */
6593 drm_info(display->drm,
6594 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6595 encoder->base.base.id, encoder->base.name);
6596 goto out_vdd_off;
6597 }
6598
6599 /*
6600 * VBT and straps are liars. Also check HPD as that seems
6601 * to be the most reliable piece of information available.
6602 *
6603 * ... expect on devices that forgot to hook HPD up for eDP
6604 * (eg. Acer Chromebook C710), so we'll check it only if multiple
6605 * ports are attempting to use the same AUX CH, according to VBT.
6606 */
6607 if (intel_bios_dp_has_shared_aux_ch(devdata: encoder->devdata)) {
6608 /*
6609 * If this fails, presume the DPCD answer came
6610 * from some other port using the same AUX CH.
6611 *
6612 * FIXME maybe cleaner to check this before the
6613 * DPCD read? Would need sort out the VDD handling...
6614 */
6615 if (!intel_digital_port_connected(encoder)) {
6616 drm_info(display->drm,
6617 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6618 encoder->base.base.id, encoder->base.name);
6619 goto out_vdd_off;
6620 }
6621
6622 /*
6623 * Unfortunately even the HPD based detection fails on
6624 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6625 * back to checking for a VGA branch device. Only do this
6626 * on known affected platforms to minimize false positives.
6627 */
6628 if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(dpcd: intel_dp->dpcd) &&
6629 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6630 DP_DWN_STRM_PORT_TYPE_ANALOG) {
6631 drm_info(display->drm,
6632 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6633 encoder->base.base.id, encoder->base.name);
6634 goto out_vdd_off;
6635 }
6636 }
6637
6638 mutex_lock(lock: &display->drm->mode_config.mutex);
6639 drm_edid = drm_edid_read_ddc(connector: &connector->base, adapter: connector->base.ddc);
6640 if (!drm_edid) {
6641 /* Fallback to EDID from ACPI OpRegion, if any */
6642 drm_edid = intel_opregion_get_edid(connector);
6643 if (drm_edid)
6644 drm_dbg_kms(display->drm,
6645 "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6646 connector->base.base.id, connector->base.name);
6647 }
6648 if (drm_edid) {
6649 if (drm_edid_connector_update(connector: &connector->base, edid: drm_edid) ||
6650 !drm_edid_connector_add_modes(connector: &connector->base)) {
6651 drm_edid_connector_update(connector: &connector->base, NULL);
6652 drm_edid_free(drm_edid);
6653 drm_edid = ERR_PTR(error: -EINVAL);
6654 }
6655 } else {
6656 drm_edid = ERR_PTR(error: -ENOENT);
6657 }
6658
6659 intel_bios_init_panel_late(display, panel: &connector->panel, devdata: encoder->devdata,
6660 drm_edid: IS_ERR(ptr: drm_edid) ? NULL : drm_edid);
6661
6662 intel_panel_add_edid_fixed_modes(connector, use_alt_fixed_modes: true);
6663
6664 /* MSO requires information from the EDID */
6665 intel_edp_mso_init(intel_dp);
6666
6667 /* multiply the mode clock and horizontal timings for MSO */
6668 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head)
6669 intel_edp_mso_mode_fixup(connector, mode: fixed_mode);
6670
6671 /* fallback to VBT if available for eDP */
6672 if (!intel_panel_preferred_fixed_mode(connector))
6673 intel_panel_add_vbt_lfp_fixed_mode(connector);
6674
6675 mutex_unlock(lock: &display->drm->mode_config.mutex);
6676
6677 if (!intel_panel_preferred_fixed_mode(connector)) {
6678 drm_info(display->drm,
6679 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6680 encoder->base.base.id, encoder->base.name);
6681 goto out_vdd_off;
6682 }
6683
6684 intel_panel_init(connector, fixed_edid: drm_edid);
6685
6686 intel_edp_backlight_setup(intel_dp, connector);
6687
6688 intel_edp_add_properties(intel_dp);
6689
6690 intel_pps_init_late(intel_dp);
6691
6692 return true;
6693
6694out_vdd_off:
6695 intel_pps_vdd_off_sync(intel_dp);
6696 intel_bios_fini_panel(panel: &connector->panel);
6697
6698 return false;
6699}
6700
6701bool
6702intel_dp_init_connector(struct intel_digital_port *dig_port,
6703 struct intel_connector *connector)
6704{
6705 struct intel_display *display = to_intel_display(dig_port);
6706 struct intel_dp *intel_dp = &dig_port->dp;
6707 struct intel_encoder *encoder = &dig_port->base;
6708 struct drm_device *dev = encoder->base.dev;
6709 enum port port = encoder->port;
6710 int type;
6711
6712 if (drm_WARN(dev, dig_port->max_lanes < 1,
6713 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6714 dig_port->max_lanes, encoder->base.base.id,
6715 encoder->base.name))
6716 return false;
6717
6718 intel_dp->reset_link_params = true;
6719
6720 /* Preserve the current hw state. */
6721 intel_dp->DP = intel_de_read(display, reg: intel_dp->output_reg);
6722 intel_dp->attached_connector = connector;
6723
6724 if (_intel_dp_is_port_edp(display, devdata: encoder->devdata, port)) {
6725 /*
6726 * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,
6727 * although in theory it could work on TypeC legacy ports.
6728 */
6729 drm_WARN_ON(dev, intel_encoder_is_tc(encoder) &&
6730 DISPLAY_VER(display) < 30);
6731 type = DRM_MODE_CONNECTOR_eDP;
6732 encoder->type = INTEL_OUTPUT_EDP;
6733
6734 /* eDP only on port B and/or C on vlv/chv */
6735 if (drm_WARN_ON(dev, (display->platform.valleyview ||
6736 display->platform.cherryview) &&
6737 port != PORT_B && port != PORT_C))
6738 return false;
6739 } else {
6740 type = DRM_MODE_CONNECTOR_DisplayPort;
6741 }
6742
6743 intel_dp_set_default_sink_rates(intel_dp);
6744 intel_dp_set_default_max_sink_lane_count(intel_dp);
6745
6746 if (display->platform.valleyview || display->platform.cherryview)
6747 vlv_pps_pipe_init(intel_dp);
6748
6749 intel_dp_aux_init(intel_dp);
6750 connector->dp.dsc_decompression_aux = &intel_dp->aux;
6751
6752 drm_dbg_kms(display->drm,
6753 "Adding %s connector on [ENCODER:%d:%s]\n",
6754 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6755 encoder->base.base.id, encoder->base.name);
6756
6757 drm_connector_init_with_ddc(dev, connector: &connector->base, funcs: &intel_dp_connector_funcs,
6758 connector_type: type, ddc: &intel_dp->aux.ddc);
6759 drm_connector_helper_add(connector: &connector->base, funcs: &intel_dp_connector_helper_funcs);
6760
6761 if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12)
6762 connector->base.interlace_allowed = true;
6763
6764 if (type != DRM_MODE_CONNECTOR_eDP)
6765 connector->polled = DRM_CONNECTOR_POLL_HPD;
6766 connector->base.polled = connector->polled;
6767
6768 intel_connector_attach_encoder(connector, encoder);
6769
6770 if (HAS_DDI(display))
6771 connector->get_hw_state = intel_ddi_connector_get_hw_state;
6772 else
6773 connector->get_hw_state = intel_connector_get_hw_state;
6774 connector->sync_state = intel_dp_connector_sync_state;
6775
6776 if (!intel_edp_init_connector(intel_dp, connector)) {
6777 intel_dp_aux_fini(intel_dp);
6778 goto fail;
6779 }
6780
6781 intel_dp_set_source_rates(intel_dp);
6782 intel_dp_set_common_rates(intel_dp);
6783 intel_dp_reset_link_params(intel_dp);
6784
6785 /* init MST on ports that can support it */
6786 intel_dp_mst_encoder_init(dig_port, conn_id: connector->base.base.id);
6787
6788 intel_dp_add_properties(intel_dp, connector: &connector->base);
6789
6790 if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
6791 int ret = intel_dp_hdcp_init(dig_port, intel_connector: connector);
6792 if (ret)
6793 drm_dbg_kms(display->drm,
6794 "HDCP init failed, skipping.\n");
6795 }
6796
6797 intel_dp->frl.is_trained = false;
6798 intel_dp->frl.trained_rate_gbps = 0;
6799
6800 intel_psr_init(intel_dp);
6801
6802 return true;
6803
6804fail:
6805 intel_display_power_flush_work(display);
6806 drm_connector_cleanup(connector: &connector->base);
6807
6808 return false;
6809}
6810
6811void intel_dp_mst_suspend(struct intel_display *display)
6812{
6813 struct intel_encoder *encoder;
6814
6815 if (!HAS_DISPLAY(display))
6816 return;
6817
6818 for_each_intel_encoder(display->drm, encoder) {
6819 struct intel_dp *intel_dp;
6820
6821 if (encoder->type != INTEL_OUTPUT_DDI)
6822 continue;
6823
6824 intel_dp = enc_to_intel_dp(encoder);
6825
6826 if (!intel_dp_mst_source_support(intel_dp))
6827 continue;
6828
6829 if (intel_dp->is_mst)
6830 drm_dp_mst_topology_mgr_suspend(mgr: &intel_dp->mst.mgr);
6831 }
6832}
6833
6834void intel_dp_mst_resume(struct intel_display *display)
6835{
6836 struct intel_encoder *encoder;
6837
6838 if (!HAS_DISPLAY(display))
6839 return;
6840
6841 for_each_intel_encoder(display->drm, encoder) {
6842 struct intel_dp *intel_dp;
6843 int ret;
6844
6845 if (encoder->type != INTEL_OUTPUT_DDI)
6846 continue;
6847
6848 intel_dp = enc_to_intel_dp(encoder);
6849
6850 if (!intel_dp_mst_source_support(intel_dp))
6851 continue;
6852
6853 ret = drm_dp_mst_topology_mgr_resume(mgr: &intel_dp->mst.mgr, sync: true);
6854 if (ret) {
6855 intel_dp->is_mst = false;
6856 drm_dp_mst_topology_mgr_set_mst(mgr: &intel_dp->mst.mgr, mst_state: false);
6857 }
6858 }
6859}
6860