1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include <linux/iopoll.h>
29#include <linux/seq_buf.h>
30#include <linux/string_helpers.h>
31
32#include <drm/display/drm_dp_helper.h>
33#include <drm/display/drm_scdc_helper.h>
34#include <drm/drm_print.h>
35#include <drm/drm_privacy_screen_consumer.h>
36
37#include "i915_reg.h"
38#include "i915_utils.h"
39#include "icl_dsi.h"
40#include "intel_alpm.h"
41#include "intel_audio.h"
42#include "intel_audio_regs.h"
43#include "intel_backlight.h"
44#include "intel_combo_phy.h"
45#include "intel_combo_phy_regs.h"
46#include "intel_connector.h"
47#include "intel_crtc.h"
48#include "intel_cx0_phy.h"
49#include "intel_cx0_phy_regs.h"
50#include "intel_ddi.h"
51#include "intel_ddi_buf_trans.h"
52#include "intel_de.h"
53#include "intel_display_power.h"
54#include "intel_display_regs.h"
55#include "intel_display_types.h"
56#include "intel_dkl_phy.h"
57#include "intel_dkl_phy_regs.h"
58#include "intel_dp.h"
59#include "intel_dp_aux.h"
60#include "intel_dp_link_training.h"
61#include "intel_dp_mst.h"
62#include "intel_dp_test.h"
63#include "intel_dp_tunnel.h"
64#include "intel_dpio_phy.h"
65#include "intel_dsi.h"
66#include "intel_encoder.h"
67#include "intel_fdi.h"
68#include "intel_fifo_underrun.h"
69#include "intel_gmbus.h"
70#include "intel_hdcp.h"
71#include "intel_hdmi.h"
72#include "intel_hotplug.h"
73#include "intel_hti.h"
74#include "intel_lspcon.h"
75#include "intel_mg_phy_regs.h"
76#include "intel_modeset_lock.h"
77#include "intel_panel.h"
78#include "intel_pfit.h"
79#include "intel_pps.h"
80#include "intel_psr.h"
81#include "intel_quirks.h"
82#include "intel_snps_phy.h"
83#include "intel_step.h"
84#include "intel_tc.h"
85#include "intel_vdsc.h"
86#include "intel_vdsc_regs.h"
87#include "intel_vrr.h"
88#include "skl_scaler.h"
89#include "skl_universal_plane.h"
90
91static const u8 index_to_dp_signal_levels[] = {
92 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
93 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
94 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
95 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
96 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
97 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
98 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
99 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
100 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
101 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
102};
103
104static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
105 const struct intel_ddi_buf_trans *trans)
106{
107 int level;
108
109 level = intel_bios_hdmi_level_shift(devdata: encoder->devdata);
110 if (level < 0)
111 level = trans->hdmi_default_entry;
112
113 return level;
114}
115
116static bool has_buf_trans_select(struct intel_display *display)
117{
118 return DISPLAY_VER(display) < 10 && !display->platform.broxton;
119}
120
121static bool has_iboost(struct intel_display *display)
122{
123 return DISPLAY_VER(display) == 9 && !display->platform.broxton;
124}
125
126/*
127 * Starting with Haswell, DDI port buffers must be programmed with correct
128 * values in advance. This function programs the correct values for
129 * DP/eDP/FDI use cases.
130 */
131void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
132 const struct intel_crtc_state *crtc_state)
133{
134 struct intel_display *display = to_intel_display(encoder);
135 u32 iboost_bit = 0;
136 int i, n_entries;
137 enum port port = encoder->port;
138 const struct intel_ddi_buf_trans *trans;
139
140 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
141 if (drm_WARN_ON_ONCE(display->drm, !trans))
142 return;
143
144 /* If we're boosting the current, set bit 31 of trans1 */
145 if (has_iboost(display) &&
146 intel_bios_dp_boost_level(devdata: encoder->devdata))
147 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
148
149 for (i = 0; i < n_entries; i++) {
150 intel_de_write(display, DDI_BUF_TRANS_LO(port, i),
151 val: trans->entries[i].hsw.trans1 | iboost_bit);
152 intel_de_write(display, DDI_BUF_TRANS_HI(port, i),
153 val: trans->entries[i].hsw.trans2);
154 }
155}
156
157/*
158 * Starting with Haswell, DDI port buffers must be programmed with correct
159 * values in advance. This function programs the correct values for
160 * HDMI/DVI use cases.
161 */
162static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
163 const struct intel_crtc_state *crtc_state)
164{
165 struct intel_display *display = to_intel_display(encoder);
166 int level = intel_ddi_level(encoder, crtc_state, lane: 0);
167 u32 iboost_bit = 0;
168 int n_entries;
169 enum port port = encoder->port;
170 const struct intel_ddi_buf_trans *trans;
171
172 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
173 if (drm_WARN_ON_ONCE(display->drm, !trans))
174 return;
175
176 /* If we're boosting the current, set bit 31 of trans1 */
177 if (has_iboost(display) &&
178 intel_bios_hdmi_boost_level(devdata: encoder->devdata))
179 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
180
181 /* Entry 9 is for HDMI: */
182 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9),
183 val: trans->entries[level].hsw.trans1 | iboost_bit);
184 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9),
185 val: trans->entries[level].hsw.trans2);
186}
187
188static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)
189{
190 if (DISPLAY_VER(display) >= 14)
191 return XELPDP_PORT_BUF_CTL1(display, port);
192 else
193 return DDI_BUF_CTL(port);
194}
195
196void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port)
197{
198 /*
199 * Bspec's platform specific timeouts:
200 * MTL+ : 100 us
201 * BXT : fixed 16 us
202 * HSW-ADL: 8 us
203 *
204 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short
205 */
206 if (display->platform.broxton) {
207 udelay(usec: 16);
208 return;
209 }
210
211 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
212 if (intel_de_wait_for_set(display, reg: intel_ddi_buf_status_reg(display, port),
213 DDI_BUF_IS_IDLE, timeout_ms: 10))
214 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n",
215 port_name(port));
216}
217
218static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
219{
220 struct intel_display *display = to_intel_display(encoder);
221 enum port port = encoder->port;
222
223 /*
224 * Bspec's platform specific timeouts:
225 * MTL+ : 10000 us
226 * DG2 : 1200 us
227 * TGL-ADL combo PHY: 1000 us
228 * TGL-ADL TypeC PHY: 3000 us
229 * HSW-ICL : fixed 518 us
230 */
231 if (DISPLAY_VER(display) < 10) {
232 usleep_range(min: 518, max: 1000);
233 return;
234 }
235
236 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
237 if (intel_de_wait_for_clear(display, reg: intel_ddi_buf_status_reg(display, port),
238 DDI_BUF_IS_IDLE, timeout_ms: 10))
239 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n",
240 port_name(port));
241}
242
243static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll)
244{
245 switch (pll->info->id) {
246 case DPLL_ID_WRPLL1:
247 return PORT_CLK_SEL_WRPLL1;
248 case DPLL_ID_WRPLL2:
249 return PORT_CLK_SEL_WRPLL2;
250 case DPLL_ID_SPLL:
251 return PORT_CLK_SEL_SPLL;
252 case DPLL_ID_LCPLL_810:
253 return PORT_CLK_SEL_LCPLL_810;
254 case DPLL_ID_LCPLL_1350:
255 return PORT_CLK_SEL_LCPLL_1350;
256 case DPLL_ID_LCPLL_2700:
257 return PORT_CLK_SEL_LCPLL_2700;
258 default:
259 MISSING_CASE(pll->info->id);
260 return PORT_CLK_SEL_NONE;
261 }
262}
263
264static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
265 const struct intel_crtc_state *crtc_state)
266{
267 const struct intel_dpll *pll = crtc_state->intel_dpll;
268 int clock = crtc_state->port_clock;
269 const enum intel_dpll_id id = pll->info->id;
270
271 switch (id) {
272 default:
273 /*
274 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
275 * here, so do warn if this get passed in
276 */
277 MISSING_CASE(id);
278 return DDI_CLK_SEL_NONE;
279 case DPLL_ID_ICL_TBTPLL:
280 switch (clock) {
281 case 162000:
282 return DDI_CLK_SEL_TBT_162;
283 case 270000:
284 return DDI_CLK_SEL_TBT_270;
285 case 540000:
286 return DDI_CLK_SEL_TBT_540;
287 case 810000:
288 return DDI_CLK_SEL_TBT_810;
289 default:
290 MISSING_CASE(clock);
291 return DDI_CLK_SEL_NONE;
292 }
293 case DPLL_ID_ICL_MGPLL1:
294 case DPLL_ID_ICL_MGPLL2:
295 case DPLL_ID_ICL_MGPLL3:
296 case DPLL_ID_ICL_MGPLL4:
297 case DPLL_ID_TGL_MGPLL5:
298 case DPLL_ID_TGL_MGPLL6:
299 return DDI_CLK_SEL_MG;
300 }
301}
302
303static u32 ddi_buf_phy_link_rate(int port_clock)
304{
305 switch (port_clock) {
306 case 162000:
307 return DDI_BUF_PHY_LINK_RATE(0);
308 case 216000:
309 return DDI_BUF_PHY_LINK_RATE(4);
310 case 243000:
311 return DDI_BUF_PHY_LINK_RATE(5);
312 case 270000:
313 return DDI_BUF_PHY_LINK_RATE(1);
314 case 324000:
315 return DDI_BUF_PHY_LINK_RATE(6);
316 case 432000:
317 return DDI_BUF_PHY_LINK_RATE(7);
318 case 540000:
319 return DDI_BUF_PHY_LINK_RATE(2);
320 case 810000:
321 return DDI_BUF_PHY_LINK_RATE(3);
322 default:
323 MISSING_CASE(port_clock);
324 return DDI_BUF_PHY_LINK_RATE(0);
325 }
326}
327
328static int dp_phy_lane_stagger_delay(int port_clock)
329{
330 /*
331 * Return the number of symbol clocks delay used to stagger the
332 * assertion/desassertion of the port lane enables. The target delay
333 * time is 100 ns or greater, return the number of symbols specific to
334 * the provided port_clock (aka link clock) corresponding to this delay
335 * time, i.e. so that
336 *
337 * number_of_symbols * duration_of_one_symbol >= 100 ns
338 *
339 * The delay must be applied only on TypeC DP outputs, for everything else
340 * the delay must be set to 0.
341 *
342 * Return the number of link symbols per 100 ns:
343 * port_clock (10 kHz) -> bits / 100 us
344 * / symbol_size -> symbols / 100 us
345 * / 1000 -> symbols / 100 ns
346 */
347 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000);
348}
349
350static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
351 const struct intel_crtc_state *crtc_state)
352{
353 struct intel_display *display = to_intel_display(encoder);
354 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
355 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
356
357 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
358 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) |
359 DDI_BUF_TRANS_SELECT(0);
360
361 if (dig_port->lane_reversal)
362 intel_dp->DP |= DDI_BUF_PORT_REVERSAL;
363 if (dig_port->ddi_a_4_lanes)
364 intel_dp->DP |= DDI_A_4_LANES;
365
366 if (DISPLAY_VER(display) >= 14) {
367 if (intel_dp_is_uhbr(crtc_state))
368 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
369 else
370 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
371 }
372
373 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {
374 intel_dp->DP |= ddi_buf_phy_link_rate(port_clock: crtc_state->port_clock);
375 if (!intel_tc_port_in_tbt_alt_mode(dig_port))
376 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
377 }
378
379 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) {
380 int delay = dp_phy_lane_stagger_delay(port_clock: crtc_state->port_clock);
381
382 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay);
383 }
384}
385
386static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port)
387{
388 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
389
390 switch (val) {
391 case DDI_CLK_SEL_NONE:
392 return 0;
393 case DDI_CLK_SEL_TBT_162:
394 return 162000;
395 case DDI_CLK_SEL_TBT_270:
396 return 270000;
397 case DDI_CLK_SEL_TBT_540:
398 return 540000;
399 case DDI_CLK_SEL_TBT_810:
400 return 810000;
401 default:
402 MISSING_CASE(val);
403 return 0;
404 }
405}
406
407static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
408{
409 /* CRT dotclock is determined via other means */
410 if (pipe_config->has_pch_encoder)
411 return;
412
413 pipe_config->hw.adjusted_mode.crtc_clock =
414 intel_crtc_dotclock(pipe_config);
415}
416
417void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
418 const struct drm_connector_state *conn_state)
419{
420 struct intel_display *display = to_intel_display(crtc_state);
421 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
422 u32 temp;
423
424 if (!intel_crtc_has_dp_encoder(crtc_state))
425 return;
426
427 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
428
429 temp = DP_MSA_MISC_SYNC_CLOCK;
430
431 switch (crtc_state->pipe_bpp) {
432 case 18:
433 temp |= DP_MSA_MISC_6_BPC;
434 break;
435 case 24:
436 temp |= DP_MSA_MISC_8_BPC;
437 break;
438 case 30:
439 temp |= DP_MSA_MISC_10_BPC;
440 break;
441 case 36:
442 temp |= DP_MSA_MISC_12_BPC;
443 break;
444 default:
445 MISSING_CASE(crtc_state->pipe_bpp);
446 break;
447 }
448
449 /* nonsense combination */
450 drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
451 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
452
453 if (crtc_state->limited_color_range)
454 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
455
456 /*
457 * As per DP 1.2 spec section 2.3.4.3 while sending
458 * YCBCR 444 signals we should program MSA MISC1/0 fields with
459 * colorspace information.
460 */
461 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
462 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
463
464 /*
465 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
466 * of Color Encoding Format and Content Color Gamut] while sending
467 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
468 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
469 */
470 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
471 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
472
473 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder),
474 val: temp);
475}
476
477static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
478{
479 if (master_transcoder == TRANSCODER_EDP)
480 return 0;
481 else
482 return master_transcoder + 1;
483}
484
485static void
486intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state,
487 bool enable)
488{
489 struct intel_display *display = to_intel_display(crtc_state);
490 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
491 u32 val = 0;
492
493 if (!HAS_DP20(display))
494 return;
495
496 if (enable && intel_dp_is_uhbr(crtc_state))
497 val = TRANS_DP2_128B132B_CHANNEL_CODING;
498
499 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val);
500}
501
502/*
503 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
504 *
505 * Only intended to be used by intel_ddi_enable_transcoder_func() and
506 * intel_ddi_config_transcoder_func().
507 */
508static u32
509intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
510 const struct intel_crtc_state *crtc_state)
511{
512 struct intel_display *display = to_intel_display(crtc_state);
513 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
514 enum pipe pipe = crtc->pipe;
515 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
516 enum port port = encoder->port;
517 u32 temp;
518
519 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
520 temp = TRANS_DDI_FUNC_ENABLE;
521 if (DISPLAY_VER(display) >= 12)
522 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
523 else
524 temp |= TRANS_DDI_SELECT_PORT(port);
525
526 switch (crtc_state->pipe_bpp) {
527 default:
528 MISSING_CASE(crtc_state->pipe_bpp);
529 fallthrough;
530 case 18:
531 temp |= TRANS_DDI_BPC_6;
532 break;
533 case 24:
534 temp |= TRANS_DDI_BPC_8;
535 break;
536 case 30:
537 temp |= TRANS_DDI_BPC_10;
538 break;
539 case 36:
540 temp |= TRANS_DDI_BPC_12;
541 break;
542 }
543
544 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
545 temp |= TRANS_DDI_PVSYNC;
546 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
547 temp |= TRANS_DDI_PHSYNC;
548
549 if (cpu_transcoder == TRANSCODER_EDP) {
550 switch (pipe) {
551 default:
552 MISSING_CASE(pipe);
553 fallthrough;
554 case PIPE_A:
555 /* On Haswell, can only use the always-on power well for
556 * eDP when not using the panel fitter, and when not
557 * using motion blur mitigation (which we don't
558 * support). */
559 if (crtc_state->pch_pfit.force_thru)
560 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
561 else
562 temp |= TRANS_DDI_EDP_INPUT_A_ON;
563 break;
564 case PIPE_B:
565 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
566 break;
567 case PIPE_C:
568 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
569 break;
570 }
571 }
572
573 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) {
574 if (crtc_state->has_hdmi_sink)
575 temp |= TRANS_DDI_MODE_SELECT_HDMI;
576 else
577 temp |= TRANS_DDI_MODE_SELECT_DVI;
578
579 if (crtc_state->hdmi_scrambling)
580 temp |= TRANS_DDI_HDMI_SCRAMBLING;
581 if (crtc_state->hdmi_high_tmds_clock_ratio)
582 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
583 if (DISPLAY_VER(display) >= 14)
584 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
585 } else if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_ANALOG)) {
586 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
587 temp |= (crtc_state->fdi_lanes - 1) << 1;
588 } else if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST) ||
589 intel_dp_is_uhbr(crtc_state)) {
590 if (intel_dp_is_uhbr(crtc_state))
591 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
592 else
593 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
594 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
595
596 if (DISPLAY_VER(display) >= 12) {
597 enum transcoder master;
598
599 master = crtc_state->mst_master_transcoder;
600 if (drm_WARN_ON(display->drm,
601 master == INVALID_TRANSCODER))
602 master = TRANSCODER_A;
603 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
604 }
605 } else {
606 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
607 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
608 }
609
610 if (IS_DISPLAY_VER(display, 8, 10) &&
611 crtc_state->master_transcoder != INVALID_TRANSCODER) {
612 u8 master_select =
613 bdw_trans_port_sync_master_select(master_transcoder: crtc_state->master_transcoder);
614
615 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
616 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
617 }
618
619 return temp;
620}
621
622void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
623 const struct intel_crtc_state *crtc_state)
624{
625 struct intel_display *display = to_intel_display(crtc_state);
626 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
627
628 if (DISPLAY_VER(display) >= 11) {
629 enum transcoder master_transcoder = crtc_state->master_transcoder;
630 u32 ctl2 = 0;
631
632 if (master_transcoder != INVALID_TRANSCODER) {
633 u8 master_select =
634 bdw_trans_port_sync_master_select(master_transcoder);
635
636 ctl2 |= PORT_SYNC_MODE_ENABLE |
637 PORT_SYNC_MODE_MASTER_SELECT(master_select);
638 }
639
640 intel_de_write(display,
641 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
642 val: ctl2);
643 }
644
645 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
646 val: intel_ddi_transcoder_func_reg_val_get(encoder,
647 crtc_state));
648}
649
650/*
651 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
652 * bit for the DDI function and enables the DP2 configuration. Called for all
653 * transcoder types.
654 */
655void
656intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
657 const struct intel_crtc_state *crtc_state)
658{
659 struct intel_display *display = to_intel_display(crtc_state);
660 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
661 u32 ctl;
662
663 intel_ddi_config_transcoder_dp2(crtc_state, enable: true);
664
665 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
666 ctl &= ~TRANS_DDI_FUNC_ENABLE;
667 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
668 val: ctl);
669}
670
671/*
672 * Disable the DDI function and port syncing.
673 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port,
674 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master
675 * transcoders these are done later in intel_ddi_post_disable_dp().
676 */
677void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
678{
679 struct intel_display *display = to_intel_display(crtc_state);
680 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
681 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
682 u32 ctl;
683
684 if (DISPLAY_VER(display) >= 11)
685 intel_de_write(display,
686 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
687 val: 0);
688
689 ctl = intel_de_read(display,
690 TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
691
692 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
693
694 ctl &= ~TRANS_DDI_FUNC_ENABLE;
695
696 if (IS_DISPLAY_VER(display, 8, 10))
697 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
698 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
699
700 if (DISPLAY_VER(display) >= 12) {
701 if (!intel_dp_mst_is_master_trans(crtc_state)) {
702 ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
703 TRANS_DDI_MODE_SELECT_MASK);
704 }
705 } else {
706 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
707 }
708
709 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
710 val: ctl);
711
712 if (intel_dp_mst_is_slave_trans(crtc_state))
713 intel_ddi_config_transcoder_dp2(crtc_state, enable: false);
714
715 if (intel_has_quirk(display, quirk: QUIRK_INCREASE_DDI_DISABLED_TIME) &&
716 intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) {
717 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n");
718 /* Quirk time at 100ms for reliable operation */
719 msleep(msecs: 100);
720 }
721}
722
723int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
724 enum transcoder cpu_transcoder,
725 bool enable, u32 hdcp_mask)
726{
727 struct intel_display *display = to_intel_display(intel_encoder);
728 intel_wakeref_t wakeref;
729 int ret = 0;
730
731 wakeref = intel_display_power_get_if_enabled(display,
732 domain: intel_encoder->power_domain);
733 if (drm_WARN_ON(display->drm, !wakeref))
734 return -ENXIO;
735
736 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
737 clear: hdcp_mask, set: enable ? hdcp_mask : 0);
738 intel_display_power_put(display, domain: intel_encoder->power_domain, wakeref);
739 return ret;
740}
741
742bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
743{
744 struct intel_display *display = to_intel_display(intel_connector);
745 struct intel_encoder *encoder = intel_attached_encoder(connector: intel_connector);
746 int type = intel_connector->base.connector_type;
747 enum port port = encoder->port;
748 enum transcoder cpu_transcoder;
749 intel_wakeref_t wakeref;
750 enum pipe pipe = 0;
751 u32 ddi_mode;
752 bool ret;
753
754 wakeref = intel_display_power_get_if_enabled(display,
755 domain: encoder->power_domain);
756 if (!wakeref)
757 return false;
758
759 /* Note: This returns false for DP MST primary encoders. */
760 if (!encoder->get_hw_state(encoder, &pipe)) {
761 ret = false;
762 goto out;
763 }
764
765 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)
766 cpu_transcoder = TRANSCODER_EDP;
767 else
768 cpu_transcoder = (enum transcoder) pipe;
769
770 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &
771 TRANS_DDI_MODE_SELECT_MASK;
772
773 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI ||
774 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) {
775 ret = type == DRM_MODE_CONNECTOR_HDMIA;
776 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {
777 ret = type == DRM_MODE_CONNECTOR_VGA;
778 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
779 ret = type == DRM_MODE_CONNECTOR_eDP ||
780 type == DRM_MODE_CONNECTOR_DisplayPort;
781 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
782 /*
783 * encoder->get_hw_state() should have bailed out on MST. This
784 * must be SST and non-eDP.
785 */
786 ret = type == DRM_MODE_CONNECTOR_DisplayPort;
787 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) {
788 /* encoder->get_hw_state() should have bailed out on MST. */
789 ret = false;
790 } else {
791 ret = false;
792 }
793
794out:
795 intel_display_power_put(display, domain: encoder->power_domain, wakeref);
796
797 return ret;
798}
799
800static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
801 u8 *pipe_mask, bool *is_dp_mst)
802{
803 struct intel_display *display = to_intel_display(encoder);
804 enum port port = encoder->port;
805 intel_wakeref_t wakeref;
806 enum pipe p;
807 u32 tmp;
808 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0;
809
810 *pipe_mask = 0;
811 *is_dp_mst = false;
812
813 wakeref = intel_display_power_get_if_enabled(display,
814 domain: encoder->power_domain);
815 if (!wakeref)
816 return;
817
818 tmp = intel_de_read(display, DDI_BUF_CTL(port));
819 if (!(tmp & DDI_BUF_CTL_ENABLE))
820 goto out;
821
822 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) {
823 tmp = intel_de_read(display,
824 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP));
825
826 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
827 default:
828 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
829 fallthrough;
830 case TRANS_DDI_EDP_INPUT_A_ON:
831 case TRANS_DDI_EDP_INPUT_A_ONOFF:
832 *pipe_mask = BIT(PIPE_A);
833 break;
834 case TRANS_DDI_EDP_INPUT_B_ONOFF:
835 *pipe_mask = BIT(PIPE_B);
836 break;
837 case TRANS_DDI_EDP_INPUT_C_ONOFF:
838 *pipe_mask = BIT(PIPE_C);
839 break;
840 }
841
842 goto out;
843 }
844
845 for_each_pipe(display, p) {
846 enum transcoder cpu_transcoder = (enum transcoder)p;
847 u32 port_mask, ddi_select, ddi_mode;
848 intel_wakeref_t trans_wakeref;
849
850 trans_wakeref = intel_display_power_get_if_enabled(display,
851 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
852 if (!trans_wakeref)
853 continue;
854
855 if (DISPLAY_VER(display) >= 12) {
856 port_mask = TGL_TRANS_DDI_PORT_MASK;
857 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
858 } else {
859 port_mask = TRANS_DDI_PORT_MASK;
860 ddi_select = TRANS_DDI_SELECT_PORT(port);
861 }
862
863 tmp = intel_de_read(display,
864 TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
865 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
866 wakeref: trans_wakeref);
867
868 if ((tmp & port_mask) != ddi_select)
869 continue;
870
871 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK;
872
873 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)
874 mst_pipe_mask |= BIT(p);
875 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))
876 dp128b132b_pipe_mask |= BIT(p);
877
878 *pipe_mask |= BIT(p);
879 }
880
881 if (!*pipe_mask)
882 drm_dbg_kms(display->drm,
883 "No pipe for [ENCODER:%d:%s] found\n",
884 encoder->base.base.id, encoder->base.name);
885
886 if (!mst_pipe_mask && dp128b132b_pipe_mask) {
887 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
888
889 /*
890 * If we don't have 8b/10b MST, but have more than one
891 * transcoder in 128b/132b mode, we know it must be 128b/132b
892 * MST.
893 *
894 * Otherwise, we fall back to checking the current MST
895 * state. It's not accurate for hardware takeover at probe, but
896 * we don't expect MST to have been enabled at that point, and
897 * can assume it's SST.
898 */
899 if (hweight8(dp128b132b_pipe_mask) > 1 ||
900 intel_dp_mst_active_streams(intel_dp))
901 mst_pipe_mask = dp128b132b_pipe_mask;
902 }
903
904 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
905 drm_dbg_kms(display->drm,
906 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
907 encoder->base.base.id, encoder->base.name,
908 *pipe_mask);
909 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
910 }
911
912 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
913 drm_dbg_kms(display->drm,
914 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n",
915 encoder->base.base.id, encoder->base.name,
916 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask);
917 else
918 *is_dp_mst = mst_pipe_mask;
919
920out:
921 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) {
922 tmp = intel_de_read(display, BXT_PHY_CTL(port));
923 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
924 BXT_PHY_LANE_POWERDOWN_ACK |
925 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
926 drm_err(display->drm,
927 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
928 encoder->base.base.id, encoder->base.name, tmp);
929 }
930
931 intel_display_power_put(display, domain: encoder->power_domain, wakeref);
932}
933
934bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
935 enum pipe *pipe)
936{
937 u8 pipe_mask;
938 bool is_mst;
939
940 intel_ddi_get_encoder_pipes(encoder, pipe_mask: &pipe_mask, is_dp_mst: &is_mst);
941
942 if (is_mst || !pipe_mask)
943 return false;
944
945 *pipe = ffs(pipe_mask) - 1;
946
947 return true;
948}
949
950static enum intel_display_power_domain
951intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
952 const struct intel_crtc_state *crtc_state)
953{
954 struct intel_display *display = to_intel_display(dig_port);
955
956 /*
957 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
958 * DC states enabled at the same time, while for driver initiated AUX
959 * transfers we need the same AUX IOs to be powered but with DC states
960 * disabled. Accordingly use the AUX_IO_<port> power domain here which
961 * leaves DC states enabled.
962 *
963 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
964 * AUX IO to be enabled, but all these require DC_OFF to be enabled as
965 * well, so we can acquire a wider AUX_<port> power domain reference
966 * instead of a specific AUX_IO_<port> reference without powering up any
967 * extra wells.
968 */
969 if (intel_psr_needs_aux_io_power(encoder: &dig_port->base, crtc_state))
970 return intel_display_power_aux_io_domain(display, aux_ch: dig_port->aux_ch);
971 else if (DISPLAY_VER(display) < 14 &&
972 (intel_crtc_has_dp_encoder(crtc_state) ||
973 intel_encoder_is_tc(encoder: &dig_port->base)))
974 return intel_aux_power_domain(dig_port);
975 else
976 return POWER_DOMAIN_INVALID;
977}
978
979static void
980main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
981 const struct intel_crtc_state *crtc_state)
982{
983 struct intel_display *display = to_intel_display(dig_port);
984 enum intel_display_power_domain domain =
985 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
986
987 drm_WARN_ON(display->drm, dig_port->aux_wakeref);
988
989 if (domain == POWER_DOMAIN_INVALID)
990 return;
991
992 dig_port->aux_wakeref = intel_display_power_get(display, domain);
993}
994
995static void
996main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
997 const struct intel_crtc_state *crtc_state)
998{
999 struct intel_display *display = to_intel_display(dig_port);
1000 enum intel_display_power_domain domain =
1001 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
1002 intel_wakeref_t wf;
1003
1004 wf = fetch_and_zero(&dig_port->aux_wakeref);
1005 if (!wf)
1006 return;
1007
1008 intel_display_power_put(display, domain, wakeref: wf);
1009}
1010
1011static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
1012 struct intel_crtc_state *crtc_state)
1013{
1014 struct intel_display *display = to_intel_display(encoder);
1015 struct intel_digital_port *dig_port;
1016
1017 /*
1018 * TODO: Add support for MST encoders. Atm, the following should never
1019 * happen since fake-MST encoders don't set their get_power_domains()
1020 * hook.
1021 */
1022 if (drm_WARN_ON(display->drm,
1023 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
1024 return;
1025
1026 dig_port = enc_to_dig_port(encoder);
1027
1028 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
1029 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
1030 dig_port->ddi_io_wakeref = intel_display_power_get(display,
1031 domain: dig_port->ddi_io_power_domain);
1032 }
1033
1034 main_link_aux_power_domain_get(dig_port, crtc_state);
1035}
1036
1037void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
1038 const struct intel_crtc_state *crtc_state)
1039{
1040 struct intel_display *display = to_intel_display(crtc_state);
1041 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1042 enum phy phy = intel_encoder_to_phy(encoder);
1043 u32 val;
1044
1045 if (cpu_transcoder == TRANSCODER_EDP)
1046 return;
1047
1048 if (DISPLAY_VER(display) >= 13)
1049 val = TGL_TRANS_CLK_SEL_PORT(phy);
1050 else if (DISPLAY_VER(display) >= 12)
1051 val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
1052 else
1053 val = TRANS_CLK_SEL_PORT(encoder->port);
1054
1055 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);
1056}
1057
1058void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
1059{
1060 struct intel_display *display = to_intel_display(crtc_state);
1061 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1062 u32 val;
1063
1064 if (cpu_transcoder == TRANSCODER_EDP)
1065 return;
1066
1067 if (DISPLAY_VER(display) >= 12)
1068 val = TGL_TRANS_CLK_SEL_DISABLED;
1069 else
1070 val = TRANS_CLK_SEL_DISABLED;
1071
1072 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);
1073}
1074
1075static void _skl_ddi_set_iboost(struct intel_display *display,
1076 enum port port, u8 iboost)
1077{
1078 u32 tmp;
1079
1080 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0);
1081 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1082 if (iboost)
1083 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1084 else
1085 tmp |= BALANCE_LEG_DISABLE(port);
1086 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, val: tmp);
1087}
1088
1089static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1090 const struct intel_crtc_state *crtc_state,
1091 int level)
1092{
1093 struct intel_display *display = to_intel_display(encoder);
1094 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1095 u8 iboost;
1096
1097 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI))
1098 iboost = intel_bios_hdmi_boost_level(devdata: encoder->devdata);
1099 else
1100 iboost = intel_bios_dp_boost_level(devdata: encoder->devdata);
1101
1102 if (iboost == 0) {
1103 const struct intel_ddi_buf_trans *trans;
1104 int n_entries;
1105
1106 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1107 if (drm_WARN_ON_ONCE(display->drm, !trans))
1108 return;
1109
1110 iboost = trans->entries[level].hsw.i_boost;
1111 }
1112
1113 /* Make sure that the requested I_boost is valid */
1114 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1115 drm_err(display->drm, "Invalid I_boost value %u\n", iboost);
1116 return;
1117 }
1118
1119 _skl_ddi_set_iboost(display, port: encoder->port, iboost);
1120
1121 if (encoder->port == PORT_A && dig_port->max_lanes == 4)
1122 _skl_ddi_set_iboost(display, port: PORT_E, iboost);
1123}
1124
1125static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
1126 const struct intel_crtc_state *crtc_state)
1127{
1128 struct intel_display *display = to_intel_display(intel_dp);
1129 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1130 int n_entries;
1131
1132 encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1133
1134 if (drm_WARN_ON(display->drm, n_entries < 1))
1135 n_entries = 1;
1136 if (drm_WARN_ON(display->drm,
1137 n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1138 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1139
1140 return index_to_dp_signal_levels[n_entries - 1] &
1141 DP_TRAIN_VOLTAGE_SWING_MASK;
1142}
1143
1144/*
1145 * We assume that the full set of pre-emphasis values can be
1146 * used on all DDI platforms. Should that change we need to
1147 * rethink this code.
1148 */
1149static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1150{
1151 return DP_TRAIN_PRE_EMPH_LEVEL_3;
1152}
1153
1154static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
1155 int lane)
1156{
1157 if (crtc_state->port_clock > 600000)
1158 return 0;
1159
1160 if (crtc_state->lane_count == 4)
1161 return lane >= 1 ? LOADGEN_SELECT : 0;
1162 else
1163 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
1164}
1165
1166static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1167 const struct intel_crtc_state *crtc_state)
1168{
1169 struct intel_display *display = to_intel_display(encoder);
1170 const struct intel_ddi_buf_trans *trans;
1171 enum phy phy = intel_encoder_to_phy(encoder);
1172 int n_entries, ln;
1173 u32 val;
1174
1175 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1176 if (drm_WARN_ON_ONCE(display->drm, !trans))
1177 return;
1178
1179 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_EDP)) {
1180 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1181
1182 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1183 intel_dp->hobl_active = is_hobl_buf_trans(table: trans);
1184 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), clear: val,
1185 set: intel_dp->hobl_active ? val : 0);
1186 }
1187
1188 /* Set PORT_TX_DW5 */
1189 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
1190 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1191 COEFF_POLARITY | CURSOR_PROGRAM |
1192 TAP2_DISABLE | TAP3_DISABLE);
1193 val |= SCALING_MODE_SEL(0x2);
1194 val |= RTERM_SELECT(0x6);
1195 val |= TAP3_DISABLE;
1196 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
1197
1198 /* Program PORT_TX_DW2 */
1199 for (ln = 0; ln < 4; ln++) {
1200 int level = intel_ddi_level(encoder, crtc_state, lane: ln);
1201
1202 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy),
1203 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
1204 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
1205 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
1206 RCOMP_SCALAR(0x98));
1207 }
1208
1209 /* Program PORT_TX_DW4 */
1210 /* We cannot write to GRP. It would overwrite individual loadgen. */
1211 for (ln = 0; ln < 4; ln++) {
1212 int level = intel_ddi_level(encoder, crtc_state, lane: ln);
1213
1214 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),
1215 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
1216 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
1217 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
1218 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
1219 }
1220
1221 /* Program PORT_TX_DW7 */
1222 for (ln = 0; ln < 4; ln++) {
1223 int level = intel_ddi_level(encoder, crtc_state, lane: ln);
1224
1225 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy),
1226 N_SCALAR_MASK,
1227 N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
1228 }
1229}
1230
1231static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
1232 const struct intel_crtc_state *crtc_state)
1233{
1234 struct intel_display *display = to_intel_display(encoder);
1235 enum phy phy = intel_encoder_to_phy(encoder);
1236 u32 val;
1237 int ln;
1238
1239 /*
1240 * 1. If port type is eDP or DP,
1241 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1242 * else clear to 0b.
1243 */
1244 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
1245 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI))
1246 val &= ~COMMON_KEEPER_EN;
1247 else
1248 val |= COMMON_KEEPER_EN;
1249 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);
1250
1251 /* 2. Program loadgen select */
1252 /*
1253 * Program PORT_TX_DW4 depending on Bit rate and used lanes
1254 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1255 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1256 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1257 */
1258 for (ln = 0; ln < 4; ln++) {
1259 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),
1260 LOADGEN_SELECT,
1261 set: icl_combo_phy_loadgen_select(crtc_state, lane: ln));
1262 }
1263
1264 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1265 intel_de_rmw(display, ICL_PORT_CL_DW5(phy),
1266 clear: 0, SUS_CLOCK_CONFIG);
1267
1268 /* 4. Clear training enable to change swing values */
1269 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
1270 val &= ~TX_TRAINING_EN;
1271 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
1272
1273 /* 5. Program swing and de-emphasis */
1274 icl_ddi_combo_vswing_program(encoder, crtc_state);
1275
1276 /* 6. Set training enable to trigger update */
1277 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
1278 val |= TX_TRAINING_EN;
1279 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
1280}
1281
1282static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
1283 const struct intel_crtc_state *crtc_state)
1284{
1285 struct intel_display *display = to_intel_display(encoder);
1286 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1287 const struct intel_ddi_buf_trans *trans;
1288 int n_entries, ln;
1289
1290 if (intel_tc_port_in_tbt_alt_mode(dig_port: enc_to_dig_port(encoder)))
1291 return;
1292
1293 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1294 if (drm_WARN_ON_ONCE(display->drm, !trans))
1295 return;
1296
1297 for (ln = 0; ln < 2; ln++) {
1298 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port),
1299 CRI_USE_FS32, set: 0);
1300 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port),
1301 CRI_USE_FS32, set: 0);
1302 }
1303
1304 /* Program MG_TX_SWINGCTRL with values from vswing table */
1305 for (ln = 0; ln < 2; ln++) {
1306 int level;
1307
1308 level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+0);
1309
1310 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port),
1311 CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1312 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1313
1314 level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+1);
1315
1316 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port),
1317 CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1318 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1319 }
1320
1321 /* Program MG_TX_DRVCTRL with values from vswing table */
1322 for (ln = 0; ln < 2; ln++) {
1323 int level;
1324
1325 level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+0);
1326
1327 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port),
1328 CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1329 CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1330 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1331 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1332 CRI_TXDEEMPH_OVERRIDE_EN);
1333
1334 level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+1);
1335
1336 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port),
1337 CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1338 CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1339 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1340 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1341 CRI_TXDEEMPH_OVERRIDE_EN);
1342
1343 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1344 }
1345
1346 /*
1347 * Program MG_CLKHUB<LN, port being used> with value from frequency table
1348 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1349 * values from table for which TX1 and TX2 enabled.
1350 */
1351 for (ln = 0; ln < 2; ln++) {
1352 intel_de_rmw(display, MG_CLKHUB(ln, tc_port),
1353 CFG_LOW_RATE_LKREN_EN,
1354 set: crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
1355 }
1356
1357 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1358 for (ln = 0; ln < 2; ln++) {
1359 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port),
1360 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1361 CFG_AMI_CK_DIV_OVERRIDE_EN,
1362 set: crtc_state->port_clock > 500000 ?
1363 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1364 CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1365
1366 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port),
1367 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1368 CFG_AMI_CK_DIV_OVERRIDE_EN,
1369 set: crtc_state->port_clock > 500000 ?
1370 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1371 CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1372 }
1373
1374 /* Program MG_TX_PISO_READLOAD with values from vswing table */
1375 for (ln = 0; ln < 2; ln++) {
1376 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port),
1377 clear: 0, CRI_CALCINIT);
1378 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port),
1379 clear: 0, CRI_CALCINIT);
1380 }
1381}
1382
1383static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
1384 const struct intel_crtc_state *crtc_state)
1385{
1386 struct intel_display *display = to_intel_display(encoder);
1387 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1388 const struct intel_ddi_buf_trans *trans;
1389 int n_entries, ln;
1390
1391 if (intel_tc_port_in_tbt_alt_mode(dig_port: enc_to_dig_port(encoder)))
1392 return;
1393
1394 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1395 if (drm_WARN_ON_ONCE(display->drm, !trans))
1396 return;
1397
1398 for (ln = 0; ln < 2; ln++) {
1399 int level;
1400
1401 /* Wa_16011342517:adl-p */
1402 if (display->platform.alderlake_p &&
1403 IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) {
1404 if ((intel_encoder_is_hdmi(encoder) &&
1405 crtc_state->port_clock == 594000) ||
1406 (intel_encoder_is_dp(encoder) &&
1407 crtc_state->port_clock == 162000)) {
1408 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1409 LOADGEN_SHARING_PMD_DISABLE, set: 1);
1410 } else {
1411 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1412 LOADGEN_SHARING_PMD_DISABLE, set: 0);
1413 }
1414 }
1415
1416 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), val: 0);
1417
1418 level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+0);
1419
1420 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),
1421 DKL_TX_PRESHOOT_COEFF_MASK |
1422 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1423 DKL_TX_VSWING_CONTROL_MASK,
1424 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1425 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1426 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1427
1428 level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+1);
1429
1430 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),
1431 DKL_TX_PRESHOOT_COEFF_MASK |
1432 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1433 DKL_TX_VSWING_CONTROL_MASK,
1434 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1435 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1436 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1437
1438 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1439 DKL_TX_DP20BITMODE, set: 0);
1440
1441 if (display->platform.alderlake_p) {
1442 u32 val;
1443
1444 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) {
1445 if (ln == 0) {
1446 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1447 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
1448 } else {
1449 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
1450 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
1451 }
1452 } else {
1453 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1454 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
1455 }
1456
1457 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1458 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
1459 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
1460 set: val);
1461 }
1462 }
1463}
1464
1465static int translate_signal_level(struct intel_dp *intel_dp,
1466 u8 signal_levels)
1467{
1468 struct intel_display *display = to_intel_display(intel_dp);
1469 int i;
1470
1471 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1472 if (index_to_dp_signal_levels[i] == signal_levels)
1473 return i;
1474 }
1475
1476 drm_WARN(display->drm, 1,
1477 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1478 signal_levels);
1479
1480 return 0;
1481}
1482
1483static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1484 const struct intel_crtc_state *crtc_state,
1485 int lane)
1486{
1487 u8 train_set = intel_dp->train_set[lane];
1488
1489 if (intel_dp_is_uhbr(crtc_state)) {
1490 return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
1491 } else {
1492 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1493 DP_TRAIN_PRE_EMPHASIS_MASK);
1494
1495 return translate_signal_level(intel_dp, signal_levels);
1496 }
1497}
1498
1499int intel_ddi_level(struct intel_encoder *encoder,
1500 const struct intel_crtc_state *crtc_state,
1501 int lane)
1502{
1503 struct intel_display *display = to_intel_display(encoder);
1504 const struct intel_ddi_buf_trans *trans;
1505 int level, n_entries;
1506
1507 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1508 if (drm_WARN_ON_ONCE(display->drm, !trans))
1509 return 0;
1510
1511 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI))
1512 level = intel_ddi_hdmi_level(encoder, trans);
1513 else
1514 level = intel_ddi_dp_level(intel_dp: enc_to_intel_dp(encoder), crtc_state,
1515 lane);
1516
1517 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries))
1518 level = n_entries - 1;
1519
1520 return level;
1521}
1522
1523static void
1524hsw_set_signal_levels(struct intel_encoder *encoder,
1525 const struct intel_crtc_state *crtc_state)
1526{
1527 struct intel_display *display = to_intel_display(encoder);
1528 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1529 int level = intel_ddi_level(encoder, crtc_state, lane: 0);
1530 enum port port = encoder->port;
1531 u32 signal_levels;
1532
1533 if (has_iboost(display))
1534 skl_ddi_set_iboost(encoder, crtc_state, level);
1535
1536 /* HDMI ignores the rest */
1537 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI))
1538 return;
1539
1540 signal_levels = DDI_BUF_TRANS_SELECT(level);
1541
1542 drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1543 signal_levels);
1544
1545 intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1546 intel_dp->DP |= signal_levels;
1547
1548 intel_de_write(display, DDI_BUF_CTL(port), val: intel_dp->DP);
1549 intel_de_posting_read(display, DDI_BUF_CTL(port));
1550}
1551
1552static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg,
1553 u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1554{
1555 mutex_lock(lock: &display->dpll.lock);
1556
1557 intel_de_rmw(display, reg, clear: clk_sel_mask, set: clk_sel);
1558
1559 /*
1560 * "This step and the step before must be
1561 * done with separate register writes."
1562 */
1563 intel_de_rmw(display, reg, clear: clk_off, set: 0);
1564
1565 mutex_unlock(lock: &display->dpll.lock);
1566}
1567
1568static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg,
1569 u32 clk_off)
1570{
1571 mutex_lock(lock: &display->dpll.lock);
1572
1573 intel_de_rmw(display, reg, clear: 0, set: clk_off);
1574
1575 mutex_unlock(lock: &display->dpll.lock);
1576}
1577
1578static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg,
1579 u32 clk_off)
1580{
1581 return !(intel_de_read(display, reg) & clk_off);
1582}
1583
1584static struct intel_dpll *
1585_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
1586 u32 clk_sel_mask, u32 clk_sel_shift)
1587{
1588 enum intel_dpll_id id;
1589
1590 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
1591
1592 return intel_get_dpll_by_id(display, id);
1593}
1594
1595static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1596 const struct intel_crtc_state *crtc_state)
1597{
1598 struct intel_display *display = to_intel_display(encoder);
1599 const struct intel_dpll *pll = crtc_state->intel_dpll;
1600 enum phy phy = intel_encoder_to_phy(encoder);
1601
1602 if (drm_WARN_ON(display->drm, !pll))
1603 return;
1604
1605 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy),
1606 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1607 clk_sel: pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1608 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1609}
1610
1611static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1612{
1613 struct intel_display *display = to_intel_display(encoder);
1614 enum phy phy = intel_encoder_to_phy(encoder);
1615
1616 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy),
1617 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1618}
1619
1620static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1621{
1622 struct intel_display *display = to_intel_display(encoder);
1623 enum phy phy = intel_encoder_to_phy(encoder);
1624
1625 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy),
1626 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1627}
1628
1629static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1630{
1631 struct intel_display *display = to_intel_display(encoder);
1632 enum phy phy = intel_encoder_to_phy(encoder);
1633
1634 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),
1635 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1636 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1637}
1638
1639static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1640 const struct intel_crtc_state *crtc_state)
1641{
1642 struct intel_display *display = to_intel_display(encoder);
1643 const struct intel_dpll *pll = crtc_state->intel_dpll;
1644 enum phy phy = intel_encoder_to_phy(encoder);
1645
1646 if (drm_WARN_ON(display->drm, !pll))
1647 return;
1648
1649 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,
1650 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1651 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1652 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1653}
1654
1655static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1656{
1657 struct intel_display *display = to_intel_display(encoder);
1658 enum phy phy = intel_encoder_to_phy(encoder);
1659
1660 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,
1661 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1662}
1663
1664static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1665{
1666 struct intel_display *display = to_intel_display(encoder);
1667 enum phy phy = intel_encoder_to_phy(encoder);
1668
1669 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,
1670 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1671}
1672
1673static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1674{
1675 struct intel_display *display = to_intel_display(encoder);
1676 enum phy phy = intel_encoder_to_phy(encoder);
1677
1678 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
1679 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1680 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1681}
1682
1683static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1684 const struct intel_crtc_state *crtc_state)
1685{
1686 struct intel_display *display = to_intel_display(encoder);
1687 const struct intel_dpll *pll = crtc_state->intel_dpll;
1688 enum phy phy = intel_encoder_to_phy(encoder);
1689
1690 if (drm_WARN_ON(display->drm, !pll))
1691 return;
1692
1693 /*
1694 * If we fail this, something went very wrong: first 2 PLLs should be
1695 * used by first 2 phys and last 2 PLLs by last phys
1696 */
1697 if (drm_WARN_ON(display->drm,
1698 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1699 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1700 return;
1701
1702 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy),
1703 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1704 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1705 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1706}
1707
1708static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1709{
1710 struct intel_display *display = to_intel_display(encoder);
1711 enum phy phy = intel_encoder_to_phy(encoder);
1712
1713 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy),
1714 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1715}
1716
1717static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1718{
1719 struct intel_display *display = to_intel_display(encoder);
1720 enum phy phy = intel_encoder_to_phy(encoder);
1721
1722 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy),
1723 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1724}
1725
1726static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1727{
1728 struct intel_display *display = to_intel_display(encoder);
1729 enum phy phy = intel_encoder_to_phy(encoder);
1730 enum intel_dpll_id id;
1731 u32 val;
1732
1733 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
1734 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1735 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1736 id = val;
1737
1738 /*
1739 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1740 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1741 * bit for phy C and D.
1742 */
1743 if (phy >= PHY_C)
1744 id += DPLL_ID_DG1_DPLL2;
1745
1746 return intel_get_dpll_by_id(display, id);
1747}
1748
1749static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1750 const struct intel_crtc_state *crtc_state)
1751{
1752 struct intel_display *display = to_intel_display(encoder);
1753 const struct intel_dpll *pll = crtc_state->intel_dpll;
1754 enum phy phy = intel_encoder_to_phy(encoder);
1755
1756 if (drm_WARN_ON(display->drm, !pll))
1757 return;
1758
1759 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,
1760 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1761 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1762 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1763}
1764
1765static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1766{
1767 struct intel_display *display = to_intel_display(encoder);
1768 enum phy phy = intel_encoder_to_phy(encoder);
1769
1770 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,
1771 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1772}
1773
1774static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1775{
1776 struct intel_display *display = to_intel_display(encoder);
1777 enum phy phy = intel_encoder_to_phy(encoder);
1778
1779 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,
1780 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1781}
1782
1783struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1784{
1785 struct intel_display *display = to_intel_display(encoder);
1786 enum phy phy = intel_encoder_to_phy(encoder);
1787
1788 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
1789 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1790 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1791}
1792
1793static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1794 const struct intel_crtc_state *crtc_state)
1795{
1796 struct intel_display *display = to_intel_display(encoder);
1797 const struct intel_dpll *pll = crtc_state->intel_dpll;
1798 enum port port = encoder->port;
1799
1800 if (drm_WARN_ON(display->drm, !pll))
1801 return;
1802
1803 /*
1804 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1805 * MG does not exist, but the programming is required to ungate DDIC and DDID."
1806 */
1807 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1808
1809 icl_ddi_combo_enable_clock(encoder, crtc_state);
1810}
1811
1812static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1813{
1814 struct intel_display *display = to_intel_display(encoder);
1815 enum port port = encoder->port;
1816
1817 icl_ddi_combo_disable_clock(encoder);
1818
1819 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1820}
1821
1822static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1823{
1824 struct intel_display *display = to_intel_display(encoder);
1825 enum port port = encoder->port;
1826 u32 tmp;
1827
1828 tmp = intel_de_read(display, DDI_CLK_SEL(port));
1829
1830 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1831 return false;
1832
1833 return icl_ddi_combo_is_clock_enabled(encoder);
1834}
1835
1836static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1837 const struct intel_crtc_state *crtc_state)
1838{
1839 struct intel_display *display = to_intel_display(encoder);
1840 const struct intel_dpll *pll = crtc_state->intel_dpll;
1841 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1842 enum port port = encoder->port;
1843
1844 if (drm_WARN_ON(display->drm, !pll))
1845 return;
1846
1847 intel_de_write(display, DDI_CLK_SEL(port),
1848 val: icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1849
1850 mutex_lock(lock: &display->dpll.lock);
1851
1852 intel_de_rmw(display, ICL_DPCLKA_CFGCR0,
1853 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), set: 0);
1854
1855 mutex_unlock(lock: &display->dpll.lock);
1856}
1857
1858static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1859{
1860 struct intel_display *display = to_intel_display(encoder);
1861 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1862 enum port port = encoder->port;
1863
1864 mutex_lock(lock: &display->dpll.lock);
1865
1866 intel_de_rmw(display, ICL_DPCLKA_CFGCR0,
1867 clear: 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1868
1869 mutex_unlock(lock: &display->dpll.lock);
1870
1871 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1872}
1873
1874static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1875{
1876 struct intel_display *display = to_intel_display(encoder);
1877 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1878 enum port port = encoder->port;
1879 u32 tmp;
1880
1881 tmp = intel_de_read(display, DDI_CLK_SEL(port));
1882
1883 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1884 return false;
1885
1886 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
1887
1888 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1889}
1890
1891static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1892{
1893 struct intel_display *display = to_intel_display(encoder);
1894 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1895 enum port port = encoder->port;
1896 enum intel_dpll_id id;
1897 u32 tmp;
1898
1899 tmp = intel_de_read(display, DDI_CLK_SEL(port));
1900
1901 switch (tmp & DDI_CLK_SEL_MASK) {
1902 case DDI_CLK_SEL_TBT_162:
1903 case DDI_CLK_SEL_TBT_270:
1904 case DDI_CLK_SEL_TBT_540:
1905 case DDI_CLK_SEL_TBT_810:
1906 id = DPLL_ID_ICL_TBTPLL;
1907 break;
1908 case DDI_CLK_SEL_MG:
1909 id = icl_tc_port_to_pll_id(tc_port);
1910 break;
1911 default:
1912 MISSING_CASE(tmp);
1913 fallthrough;
1914 case DDI_CLK_SEL_NONE:
1915 return NULL;
1916 }
1917
1918 return intel_get_dpll_by_id(display, id);
1919}
1920
1921static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1922{
1923 struct intel_display *display = to_intel_display(encoder->base.dev);
1924 enum intel_dpll_id id;
1925
1926 switch (encoder->port) {
1927 case PORT_A:
1928 id = DPLL_ID_SKL_DPLL0;
1929 break;
1930 case PORT_B:
1931 id = DPLL_ID_SKL_DPLL1;
1932 break;
1933 case PORT_C:
1934 id = DPLL_ID_SKL_DPLL2;
1935 break;
1936 default:
1937 MISSING_CASE(encoder->port);
1938 return NULL;
1939 }
1940
1941 return intel_get_dpll_by_id(display, id);
1942}
1943
1944static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1945 const struct intel_crtc_state *crtc_state)
1946{
1947 struct intel_display *display = to_intel_display(encoder);
1948 const struct intel_dpll *pll = crtc_state->intel_dpll;
1949 enum port port = encoder->port;
1950
1951 if (drm_WARN_ON(display->drm, !pll))
1952 return;
1953
1954 mutex_lock(lock: &display->dpll.lock);
1955
1956 intel_de_rmw(display, DPLL_CTRL2,
1957 DPLL_CTRL2_DDI_CLK_OFF(port) |
1958 DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1959 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1960 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1961
1962 mutex_unlock(lock: &display->dpll.lock);
1963}
1964
1965static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1966{
1967 struct intel_display *display = to_intel_display(encoder);
1968 enum port port = encoder->port;
1969
1970 mutex_lock(lock: &display->dpll.lock);
1971
1972 intel_de_rmw(display, DPLL_CTRL2,
1973 clear: 0, DPLL_CTRL2_DDI_CLK_OFF(port));
1974
1975 mutex_unlock(lock: &display->dpll.lock);
1976}
1977
1978static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1979{
1980 struct intel_display *display = to_intel_display(encoder);
1981 enum port port = encoder->port;
1982
1983 /*
1984 * FIXME Not sure if the override affects both
1985 * the PLL selection and the CLK_OFF bit.
1986 */
1987 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1988}
1989
1990static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1991{
1992 struct intel_display *display = to_intel_display(encoder);
1993 enum port port = encoder->port;
1994 enum intel_dpll_id id;
1995 u32 tmp;
1996
1997 tmp = intel_de_read(display, DPLL_CTRL2);
1998
1999 /*
2000 * FIXME Not sure if the override affects both
2001 * the PLL selection and the CLK_OFF bit.
2002 */
2003 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
2004 return NULL;
2005
2006 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
2007 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
2008
2009 return intel_get_dpll_by_id(display, id);
2010}
2011
2012void hsw_ddi_enable_clock(struct intel_encoder *encoder,
2013 const struct intel_crtc_state *crtc_state)
2014{
2015 struct intel_display *display = to_intel_display(encoder);
2016 const struct intel_dpll *pll = crtc_state->intel_dpll;
2017 enum port port = encoder->port;
2018
2019 if (drm_WARN_ON(display->drm, !pll))
2020 return;
2021
2022 intel_de_write(display, PORT_CLK_SEL(port), val: hsw_pll_to_ddi_pll_sel(pll));
2023}
2024
2025void hsw_ddi_disable_clock(struct intel_encoder *encoder)
2026{
2027 struct intel_display *display = to_intel_display(encoder);
2028 enum port port = encoder->port;
2029
2030 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2031}
2032
2033bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
2034{
2035 struct intel_display *display = to_intel_display(encoder);
2036 enum port port = encoder->port;
2037
2038 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
2039}
2040
2041static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
2042{
2043 struct intel_display *display = to_intel_display(encoder);
2044 enum port port = encoder->port;
2045 enum intel_dpll_id id;
2046 u32 tmp;
2047
2048 tmp = intel_de_read(display, PORT_CLK_SEL(port));
2049
2050 switch (tmp & PORT_CLK_SEL_MASK) {
2051 case PORT_CLK_SEL_WRPLL1:
2052 id = DPLL_ID_WRPLL1;
2053 break;
2054 case PORT_CLK_SEL_WRPLL2:
2055 id = DPLL_ID_WRPLL2;
2056 break;
2057 case PORT_CLK_SEL_SPLL:
2058 id = DPLL_ID_SPLL;
2059 break;
2060 case PORT_CLK_SEL_LCPLL_810:
2061 id = DPLL_ID_LCPLL_810;
2062 break;
2063 case PORT_CLK_SEL_LCPLL_1350:
2064 id = DPLL_ID_LCPLL_1350;
2065 break;
2066 case PORT_CLK_SEL_LCPLL_2700:
2067 id = DPLL_ID_LCPLL_2700;
2068 break;
2069 default:
2070 MISSING_CASE(tmp);
2071 fallthrough;
2072 case PORT_CLK_SEL_NONE:
2073 return NULL;
2074 }
2075
2076 return intel_get_dpll_by_id(display, id);
2077}
2078
2079void intel_ddi_enable_clock(struct intel_encoder *encoder,
2080 const struct intel_crtc_state *crtc_state)
2081{
2082 if (encoder->enable_clock)
2083 encoder->enable_clock(encoder, crtc_state);
2084}
2085
2086void intel_ddi_disable_clock(struct intel_encoder *encoder)
2087{
2088 if (encoder->disable_clock)
2089 encoder->disable_clock(encoder);
2090}
2091
2092void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2093{
2094 struct intel_display *display = to_intel_display(encoder);
2095 u32 port_mask;
2096 bool ddi_clk_needed;
2097
2098 /*
2099 * In case of DP MST, we sanitize the primary encoder only, not the
2100 * virtual ones.
2101 */
2102 if (encoder->type == INTEL_OUTPUT_DP_MST)
2103 return;
2104
2105 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2106 u8 pipe_mask;
2107 bool is_mst;
2108
2109 intel_ddi_get_encoder_pipes(encoder, pipe_mask: &pipe_mask, is_dp_mst: &is_mst);
2110 /*
2111 * In the unlikely case that BIOS enables DP in MST mode, just
2112 * warn since our MST HW readout is incomplete.
2113 */
2114 if (drm_WARN_ON(display->drm, is_mst))
2115 return;
2116 }
2117
2118 port_mask = BIT(encoder->port);
2119 ddi_clk_needed = encoder->base.crtc;
2120
2121 if (encoder->type == INTEL_OUTPUT_DSI) {
2122 struct intel_encoder *other_encoder;
2123
2124 port_mask = intel_dsi_encoder_ports(encoder);
2125 /*
2126 * Sanity check that we haven't incorrectly registered another
2127 * encoder using any of the ports of this DSI encoder.
2128 */
2129 for_each_intel_encoder(display->drm, other_encoder) {
2130 if (other_encoder == encoder)
2131 continue;
2132
2133 if (drm_WARN_ON(display->drm,
2134 port_mask & BIT(other_encoder->port)))
2135 return;
2136 }
2137 /*
2138 * For DSI we keep the ddi clocks gated
2139 * except during enable/disable sequence.
2140 */
2141 ddi_clk_needed = false;
2142 }
2143
2144 if (ddi_clk_needed || !encoder->is_clock_enabled ||
2145 !encoder->is_clock_enabled(encoder))
2146 return;
2147
2148 drm_dbg_kms(display->drm,
2149 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2150 encoder->base.base.id, encoder->base.name);
2151
2152 encoder->disable_clock(encoder);
2153}
2154
2155static void
2156tgl_dkl_phy_check_and_rewrite(struct intel_display *display,
2157 enum tc_port tc_port, u32 ln0, u32 ln1)
2158{
2159 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))
2160 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), val: ln0);
2161 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))
2162 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), val: ln1);
2163}
2164
2165static void
2166icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2167 const struct intel_crtc_state *crtc_state)
2168{
2169 struct intel_display *display = to_intel_display(crtc_state);
2170 enum tc_port tc_port = intel_encoder_to_tc(encoder: &dig_port->base);
2171 enum intel_tc_pin_assignment pin_assignment;
2172 u32 ln0, ln1;
2173 u8 width;
2174
2175 if (DISPLAY_VER(display) >= 14)
2176 return;
2177
2178 if (!intel_encoder_is_tc(encoder: &dig_port->base) ||
2179 intel_tc_port_in_tbt_alt_mode(dig_port))
2180 return;
2181
2182 if (DISPLAY_VER(display) >= 12) {
2183 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));
2184 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));
2185 } else {
2186 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));
2187 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));
2188 }
2189
2190 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2191 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2192
2193 /* DPPATC */
2194 pin_assignment = intel_tc_port_get_pin_assignment(dig_port);
2195 width = crtc_state->lane_count;
2196
2197 switch (pin_assignment) {
2198 case INTEL_TC_PIN_ASSIGNMENT_NONE:
2199 drm_WARN_ON(display->drm,
2200 !intel_tc_port_in_legacy_mode(dig_port));
2201 if (width == 1) {
2202 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2203 } else {
2204 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2205 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2206 }
2207 break;
2208 case INTEL_TC_PIN_ASSIGNMENT_A:
2209 if (width == 4) {
2210 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2211 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2212 }
2213 break;
2214 case INTEL_TC_PIN_ASSIGNMENT_B:
2215 if (width == 2) {
2216 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2217 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2218 }
2219 break;
2220 case INTEL_TC_PIN_ASSIGNMENT_C:
2221 case INTEL_TC_PIN_ASSIGNMENT_E:
2222 if (width == 1) {
2223 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2224 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2225 } else {
2226 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2227 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2228 }
2229 break;
2230 case INTEL_TC_PIN_ASSIGNMENT_D:
2231 case INTEL_TC_PIN_ASSIGNMENT_F:
2232 if (width == 1) {
2233 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2234 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2235 } else {
2236 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2237 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2238 }
2239 break;
2240 default:
2241 MISSING_CASE(pin_assignment);
2242 }
2243
2244 if (DISPLAY_VER(display) >= 12) {
2245 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), val: ln0);
2246 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), val: ln1);
2247 /* WA_14018221282 */
2248 if (IS_DISPLAY_VER(display, 12, 13))
2249 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);
2250
2251 } else {
2252 intel_de_write(display, MG_DP_MODE(0, tc_port), val: ln0);
2253 intel_de_write(display, MG_DP_MODE(1, tc_port), val: ln1);
2254 }
2255}
2256
2257static enum transcoder
2258tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2259{
2260 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST))
2261 return crtc_state->mst_master_transcoder;
2262 else
2263 return crtc_state->cpu_transcoder;
2264}
2265
2266i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2267 const struct intel_crtc_state *crtc_state)
2268{
2269 struct intel_display *display = to_intel_display(encoder);
2270
2271 if (DISPLAY_VER(display) >= 12)
2272 return TGL_DP_TP_CTL(display,
2273 tgl_dp_tp_transcoder(crtc_state));
2274 else
2275 return DP_TP_CTL(encoder->port);
2276}
2277
2278static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2279 const struct intel_crtc_state *crtc_state)
2280{
2281 struct intel_display *display = to_intel_display(encoder);
2282
2283 if (DISPLAY_VER(display) >= 12)
2284 return TGL_DP_TP_STATUS(display,
2285 tgl_dp_tp_transcoder(crtc_state));
2286 else
2287 return DP_TP_STATUS(encoder->port);
2288}
2289
2290void intel_ddi_clear_act_sent(struct intel_encoder *encoder,
2291 const struct intel_crtc_state *crtc_state)
2292{
2293 struct intel_display *display = to_intel_display(encoder);
2294
2295 intel_de_write(display, reg: dp_tp_status_reg(encoder, crtc_state),
2296 DP_TP_STATUS_ACT_SENT);
2297}
2298
2299void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder,
2300 const struct intel_crtc_state *crtc_state)
2301{
2302 struct intel_display *display = to_intel_display(encoder);
2303
2304 if (intel_de_wait_for_set(display, reg: dp_tp_status_reg(encoder, crtc_state),
2305 DP_TP_STATUS_ACT_SENT, timeout_ms: 1))
2306 drm_err(display->drm, "Timed out waiting for ACT sent\n");
2307}
2308
2309static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2310 const struct intel_crtc_state *crtc_state,
2311 bool enable)
2312{
2313 struct intel_display *display = to_intel_display(intel_dp);
2314
2315 if (!crtc_state->vrr.enable)
2316 return;
2317
2318 if (drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_DOWNSPREAD_CTRL,
2319 value: enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2320 drm_dbg_kms(display->drm,
2321 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2322 str_enable_disable(enable));
2323}
2324
2325static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2326 const struct intel_crtc_state *crtc_state,
2327 bool enable)
2328{
2329 struct intel_display *display = to_intel_display(intel_dp);
2330
2331 if (!crtc_state->fec_enable)
2332 return;
2333
2334 if (drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_FEC_CONFIGURATION,
2335 value: enable ? DP_FEC_READY : 0) <= 0)
2336 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n",
2337 str_enabled_disabled(enable));
2338
2339 if (enable &&
2340 drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_FEC_STATUS,
2341 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0)
2342 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n");
2343}
2344
2345static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled)
2346{
2347 struct intel_display *display = to_intel_display(aux->drm_dev);
2348 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED;
2349 u8 status = 0;
2350 int ret, err;
2351
2352 ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status),
2353 err || (status & mask),
2354 10 * 1000, 200 * 1000, false);
2355
2356 /* Either can be non-zero, but not both */
2357 ret = ret ?: err;
2358 if (ret) {
2359 drm_dbg_kms(display->drm,
2360 "Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n",
2361 str_enabled_disabled(enabled), ret, status);
2362 return ret;
2363 }
2364
2365 return 0;
2366}
2367
2368int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
2369 const struct intel_crtc_state *crtc_state,
2370 bool enabled)
2371{
2372 struct intel_display *display = to_intel_display(encoder);
2373 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2374 int ret;
2375
2376 if (!crtc_state->fec_enable)
2377 return 0;
2378
2379 if (enabled)
2380 ret = intel_de_wait_for_set(display, reg: dp_tp_status_reg(encoder, crtc_state),
2381 DP_TP_STATUS_FEC_ENABLE_LIVE, timeout_ms: 1);
2382 else
2383 ret = intel_de_wait_for_clear(display, reg: dp_tp_status_reg(encoder, crtc_state),
2384 DP_TP_STATUS_FEC_ENABLE_LIVE, timeout_ms: 1);
2385
2386 if (ret) {
2387 drm_err(display->drm,
2388 "Timeout waiting for FEC live state to get %s\n",
2389 str_enabled_disabled(enabled));
2390 return ret;
2391 }
2392 /*
2393 * At least the Synoptics MST hub doesn't set the detected flag for
2394 * FEC decoding disabling so skip waiting for that.
2395 */
2396 if (enabled) {
2397 ret = wait_for_fec_detected(aux: &intel_dp->aux, enabled);
2398 if (ret)
2399 return ret;
2400 }
2401
2402 return 0;
2403}
2404
2405static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2406 const struct intel_crtc_state *crtc_state)
2407{
2408 struct intel_display *display = to_intel_display(encoder);
2409 int i;
2410 int ret;
2411
2412 if (!crtc_state->fec_enable)
2413 return;
2414
2415 intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
2416 clear: 0, DP_TP_CTL_FEC_ENABLE);
2417
2418 if (DISPLAY_VER(display) < 30)
2419 return;
2420
2421 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled: true);
2422 if (!ret)
2423 return;
2424
2425 for (i = 0; i < 3; i++) {
2426 drm_dbg_kms(display->drm, "Retry FEC enabling\n");
2427
2428 intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
2429 DP_TP_CTL_FEC_ENABLE, set: 0);
2430
2431 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled: false);
2432 if (ret)
2433 continue;
2434
2435 intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
2436 clear: 0, DP_TP_CTL_FEC_ENABLE);
2437
2438 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled: true);
2439 if (!ret)
2440 return;
2441 }
2442
2443 drm_err(display->drm, "Failed to enable FEC after retries\n");
2444}
2445
2446static void intel_ddi_disable_fec(struct intel_encoder *encoder,
2447 const struct intel_crtc_state *crtc_state)
2448{
2449 struct intel_display *display = to_intel_display(encoder);
2450
2451 if (!crtc_state->fec_enable)
2452 return;
2453
2454 intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
2455 DP_TP_CTL_FEC_ENABLE, set: 0);
2456 intel_de_posting_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
2457}
2458
2459static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2460 const struct intel_crtc_state *crtc_state)
2461{
2462 struct intel_display *display = to_intel_display(encoder);
2463 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2464
2465 if (intel_encoder_is_combo(encoder)) {
2466 enum phy phy = intel_encoder_to_phy(encoder);
2467
2468 intel_combo_phy_power_up_lanes(display, phy, is_dsi: false,
2469 lane_count: crtc_state->lane_count,
2470 lane_reversal: dig_port->lane_reversal);
2471 }
2472}
2473
2474/*
2475 * Splitter enable for eDP MSO is limited to certain pipes, on certain
2476 * platforms.
2477 */
2478static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display)
2479{
2480 if (DISPLAY_VER(display) > 20)
2481 return ~0;
2482 else if (display->platform.alderlake_p)
2483 return BIT(PIPE_A) | BIT(PIPE_B);
2484 else
2485 return BIT(PIPE_A);
2486}
2487
2488static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2489 struct intel_crtc_state *pipe_config)
2490{
2491 struct intel_display *display = to_intel_display(pipe_config);
2492 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2493 enum pipe pipe = crtc->pipe;
2494 u32 dss1;
2495
2496 if (!HAS_MSO(display))
2497 return;
2498
2499 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
2500
2501 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2502 if (!pipe_config->splitter.enable)
2503 return;
2504
2505 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) {
2506 pipe_config->splitter.enable = false;
2507 return;
2508 }
2509
2510 switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2511 default:
2512 drm_WARN(display->drm, true,
2513 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2514 fallthrough;
2515 case SPLITTER_CONFIGURATION_2_SEGMENT:
2516 pipe_config->splitter.link_count = 2;
2517 break;
2518 case SPLITTER_CONFIGURATION_4_SEGMENT:
2519 pipe_config->splitter.link_count = 4;
2520 break;
2521 }
2522
2523 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2524}
2525
2526static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2527{
2528 struct intel_display *display = to_intel_display(crtc_state);
2529 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2530 enum pipe pipe = crtc->pipe;
2531 u32 dss1 = 0;
2532
2533 if (!HAS_MSO(display))
2534 return;
2535
2536 if (crtc_state->splitter.enable) {
2537 dss1 |= SPLITTER_ENABLE;
2538 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2539 if (crtc_state->splitter.link_count == 2)
2540 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2541 else
2542 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2543 }
2544
2545 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe),
2546 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2547 OVERLAP_PIXELS_MASK, set: dss1);
2548}
2549
2550static void
2551mtl_ddi_enable_d2d(struct intel_encoder *encoder)
2552{
2553 struct intel_display *display = to_intel_display(encoder);
2554 enum port port = encoder->port;
2555 i915_reg_t reg;
2556 u32 set_bits, wait_bits;
2557 int ret;
2558
2559 if (DISPLAY_VER(display) < 14)
2560 return;
2561
2562 if (DISPLAY_VER(display) >= 20) {
2563 reg = DDI_BUF_CTL(port);
2564 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
2565 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
2566 } else {
2567 reg = XELPDP_PORT_BUF_CTL1(display, port);
2568 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
2569 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
2570 }
2571
2572 intel_de_rmw(display, reg, clear: 0, set: set_bits);
2573
2574 ret = intel_de_wait_custom(display, reg,
2575 mask: wait_bits, value: wait_bits,
2576 fast_timeout_us: 100, slow_timeout_ms: 0, NULL);
2577 if (ret) {
2578 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
2579 port_name(port));
2580 }
2581}
2582
2583static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
2584 const struct intel_crtc_state *crtc_state)
2585{
2586 struct intel_display *display = to_intel_display(encoder);
2587 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2588 enum port port = encoder->port;
2589 u32 val = 0;
2590
2591 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
2592
2593 if (intel_dp_is_uhbr(crtc_state))
2594 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
2595 else
2596 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT;
2597
2598 if (dig_port->lane_reversal)
2599 val |= XELPDP_PORT_REVERSAL;
2600
2601 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
2602 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK,
2603 set: val);
2604}
2605
2606static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
2607{
2608 struct intel_display *display = to_intel_display(encoder);
2609 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2610 u32 val;
2611
2612 val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
2613 XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
2614 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
2615 XELPDP_PORT_BUF_IO_SELECT_TBT, set: val);
2616}
2617
2618static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2619 struct intel_encoder *encoder,
2620 const struct intel_crtc_state *crtc_state,
2621 const struct drm_connector_state *conn_state)
2622{
2623 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2624 bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
2625 bool transparent_mode;
2626 int ret;
2627
2628 intel_dp_set_link_params(intel_dp,
2629 link_rate: crtc_state->port_clock,
2630 lane_count: crtc_state->lane_count);
2631
2632 /*
2633 * We only configure what the register value will be here. Actual
2634 * enabling happens during link training farther down.
2635 */
2636 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2637
2638 /*
2639 * 1. Enable Power Wells
2640 *
2641 * This was handled at the beginning of intel_atomic_commit_tail(),
2642 * before we called down into this function.
2643 */
2644
2645 /* 2. PMdemand was already set */
2646
2647 /* 3. Select Thunderbolt */
2648 mtl_port_buf_ctl_io_selection(encoder);
2649
2650 /* 4. Enable Panel Power if PPS is required */
2651 intel_pps_on(intel_dp);
2652
2653 /* 5. Enable the port PLL */
2654 intel_ddi_enable_clock(encoder, crtc_state);
2655
2656 /*
2657 * 6.a Configure Transcoder Clock Select to direct the Port clock to the
2658 * Transcoder.
2659 */
2660 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2661
2662 /*
2663 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings.
2664 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2665 * Transport Select
2666 */
2667 intel_ddi_config_transcoder_func(encoder, crtc_state);
2668
2669 /*
2670 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2671 */
2672 intel_ddi_mso_configure(crtc_state);
2673
2674 if (!is_mst)
2675 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2676
2677 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp);
2678 drm_dp_lttpr_wake_timeout_setup(aux: &intel_dp->aux, transparent_mode);
2679
2680 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2681 if (!is_mst)
2682 intel_dp_sink_enable_decompression(state,
2683 to_intel_connector(conn_state->connector),
2684 new_crtc_state: crtc_state);
2685
2686 /*
2687 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2688 * in the FEC_CONFIGURATION register to 1 before initiating link
2689 * training
2690 */
2691 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, enable: true);
2692
2693 intel_dp_check_frl_training(intel_dp);
2694 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2695
2696 /*
2697 * 6. The rest of the below are substeps under the bspec's "Enable and
2698 * Train Display Port" step. Note that steps that are specific to
2699 * MST will be handled by intel_mst_pre_enable_dp() before/after it
2700 * calls into this function. Also intel_mst_pre_enable_dp() only calls
2701 * us when active_mst_links==0, so any steps designated for "single
2702 * stream or multi-stream master transcoder" can just be performed
2703 * unconditionally here.
2704 *
2705 * mtl_ddi_prepare_link_retrain() that is called by
2706 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h,
2707 * 6.i and 6.j
2708 *
2709 * 6.k Follow DisplayPort specification training sequence (see notes for
2710 * failure handling)
2711 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2712 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2713 * (timeout after 800 us)
2714 */
2715 intel_dp_start_link_train(state, intel_dp, crtc_state);
2716
2717 /* 6.n Set DP_TP_CTL link training to Normal */
2718 if (!is_trans_port_sync_mode(state: crtc_state))
2719 intel_dp_stop_link_train(intel_dp, crtc_state);
2720
2721 /* 6.o Configure and enable FEC if needed */
2722 intel_ddi_enable_fec(encoder, crtc_state);
2723
2724 /* 7.a 128b/132b SST. */
2725 if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
2726 /* VCPID 1, start slot 0 for 128b/132b, tu slots */
2727 ret = drm_dp_dpcd_write_payload(aux: &intel_dp->aux, vcpid: 1, start_time_slot: 0, time_slot_count: crtc_state->dp_m_n.tu);
2728 if (ret < 0)
2729 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
2730 }
2731
2732 if (!is_mst)
2733 intel_dsc_dp_pps_write(encoder, crtc_state);
2734}
2735
2736static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2737 struct intel_encoder *encoder,
2738 const struct intel_crtc_state *crtc_state,
2739 const struct drm_connector_state *conn_state)
2740{
2741 struct intel_display *display = to_intel_display(encoder);
2742 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2743 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2744 bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
2745 int ret;
2746
2747 intel_dp_set_link_params(intel_dp,
2748 link_rate: crtc_state->port_clock,
2749 lane_count: crtc_state->lane_count);
2750
2751 /*
2752 * We only configure what the register value will be here. Actual
2753 * enabling happens during link training farther down.
2754 */
2755 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2756
2757 /*
2758 * 1. Enable Power Wells
2759 *
2760 * This was handled at the beginning of intel_atomic_commit_tail(),
2761 * before we called down into this function.
2762 */
2763
2764 /* 2. Enable Panel Power if PPS is required */
2765 intel_pps_on(intel_dp);
2766
2767 /*
2768 * 3. For non-TBT Type-C ports, set FIA lane count
2769 * (DFLEXDPSP.DPX4TXLATC)
2770 *
2771 * This was done before tgl_ddi_pre_enable_dp by
2772 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2773 */
2774
2775 /*
2776 * 4. Enable the port PLL.
2777 *
2778 * The PLL enabling itself was already done before this function by
2779 * hsw_crtc_enable()->intel_enable_dpll(). We need only
2780 * configure the PLL to port mapping here.
2781 */
2782 intel_ddi_enable_clock(encoder, crtc_state);
2783
2784 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2785 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2786 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
2787 dig_port->ddi_io_wakeref = intel_display_power_get(display,
2788 domain: dig_port->ddi_io_power_domain);
2789 }
2790
2791 /* 6. Program DP_MODE */
2792 icl_program_mg_dp_mode(dig_port, crtc_state);
2793
2794 /*
2795 * 7. The rest of the below are substeps under the bspec's "Enable and
2796 * Train Display Port" step. Note that steps that are specific to
2797 * MST will be handled by intel_mst_pre_enable_dp() before/after it
2798 * calls into this function. Also intel_mst_pre_enable_dp() only calls
2799 * us when active_mst_links==0, so any steps designated for "single
2800 * stream or multi-stream master transcoder" can just be performed
2801 * unconditionally here.
2802 */
2803
2804 /*
2805 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2806 * Transcoder.
2807 */
2808 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2809
2810 /*
2811 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2812 * Transport Select
2813 */
2814 intel_ddi_config_transcoder_func(encoder, crtc_state);
2815
2816 /*
2817 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2818 * selected
2819 *
2820 * This will be handled by the intel_dp_start_link_train() farther
2821 * down this function.
2822 */
2823
2824 /* 7.e Configure voltage swing and related IO settings */
2825 encoder->set_signal_levels(encoder, crtc_state);
2826
2827 /*
2828 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2829 * the used lanes of the DDI.
2830 */
2831 intel_ddi_power_up_lanes(encoder, crtc_state);
2832
2833 /*
2834 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2835 */
2836 intel_ddi_mso_configure(crtc_state);
2837
2838 if (!is_mst)
2839 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2840
2841 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2842 if (!is_mst)
2843 intel_dp_sink_enable_decompression(state,
2844 to_intel_connector(conn_state->connector),
2845 new_crtc_state: crtc_state);
2846 /*
2847 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2848 * in the FEC_CONFIGURATION register to 1 before initiating link
2849 * training
2850 */
2851 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, enable: true);
2852
2853 intel_dp_check_frl_training(intel_dp);
2854 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2855
2856 /*
2857 * 7.i Follow DisplayPort specification training sequence (see notes for
2858 * failure handling)
2859 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2860 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2861 * (timeout after 800 us)
2862 */
2863 intel_dp_start_link_train(state, intel_dp, crtc_state);
2864
2865 /* 7.k Set DP_TP_CTL link training to Normal */
2866 if (!is_trans_port_sync_mode(state: crtc_state))
2867 intel_dp_stop_link_train(intel_dp, crtc_state);
2868
2869 /* 7.l Configure and enable FEC if needed */
2870 intel_ddi_enable_fec(encoder, crtc_state);
2871
2872 if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
2873 /* VCPID 1, start slot 0 for 128b/132b, tu slots */
2874 ret = drm_dp_dpcd_write_payload(aux: &intel_dp->aux, vcpid: 1, start_time_slot: 0, time_slot_count: crtc_state->dp_m_n.tu);
2875 if (ret < 0)
2876 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
2877 }
2878
2879 if (!is_mst)
2880 intel_dsc_dp_pps_write(encoder, crtc_state);
2881}
2882
2883static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2884 struct intel_encoder *encoder,
2885 const struct intel_crtc_state *crtc_state,
2886 const struct drm_connector_state *conn_state)
2887{
2888 struct intel_display *display = to_intel_display(encoder);
2889 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2890 enum port port = encoder->port;
2891 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2892 bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
2893
2894 if (DISPLAY_VER(display) < 11)
2895 drm_WARN_ON(display->drm,
2896 is_mst && (port == PORT_A || port == PORT_E));
2897 else
2898 drm_WARN_ON(display->drm, is_mst && port == PORT_A);
2899
2900 intel_dp_set_link_params(intel_dp,
2901 link_rate: crtc_state->port_clock,
2902 lane_count: crtc_state->lane_count);
2903
2904 /*
2905 * We only configure what the register value will be here. Actual
2906 * enabling happens during link training farther down.
2907 */
2908 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2909
2910 intel_pps_on(intel_dp);
2911
2912 intel_ddi_enable_clock(encoder, crtc_state);
2913
2914 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2915 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
2916 dig_port->ddi_io_wakeref = intel_display_power_get(display,
2917 domain: dig_port->ddi_io_power_domain);
2918 }
2919
2920 icl_program_mg_dp_mode(dig_port, crtc_state);
2921
2922 if (has_buf_trans_select(display))
2923 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2924
2925 encoder->set_signal_levels(encoder, crtc_state);
2926
2927 intel_ddi_power_up_lanes(encoder, crtc_state);
2928
2929 if (!is_mst)
2930 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2931 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2932 if (!is_mst)
2933 intel_dp_sink_enable_decompression(state,
2934 to_intel_connector(conn_state->connector),
2935 new_crtc_state: crtc_state);
2936 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, enable: true);
2937 intel_dp_start_link_train(state, intel_dp, crtc_state);
2938 if ((port != PORT_A || DISPLAY_VER(display) >= 9) &&
2939 !is_trans_port_sync_mode(state: crtc_state))
2940 intel_dp_stop_link_train(intel_dp, crtc_state);
2941
2942 intel_ddi_enable_fec(encoder, crtc_state);
2943
2944 if (!is_mst) {
2945 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2946 intel_dsc_dp_pps_write(encoder, crtc_state);
2947 }
2948}
2949
2950static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2951 struct intel_encoder *encoder,
2952 const struct intel_crtc_state *crtc_state,
2953 const struct drm_connector_state *conn_state)
2954{
2955 struct intel_display *display = to_intel_display(encoder);
2956
2957 if (HAS_DP20(display))
2958 intel_dp_128b132b_sdp_crc16(intel_dp: enc_to_intel_dp(encoder),
2959 crtc_state);
2960
2961 /* Panel replay has to be enabled in sink dpcd before link training. */
2962 intel_psr_panel_replay_enable_sink(intel_dp: enc_to_intel_dp(encoder));
2963
2964 if (DISPLAY_VER(display) >= 14)
2965 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2966 else if (DISPLAY_VER(display) >= 12)
2967 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2968 else
2969 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2970
2971 /* MST will call a setting of MSA after an allocating of Virtual Channel
2972 * from MST encoder pre_enable callback.
2973 */
2974 if (!intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST))
2975 intel_ddi_set_dp_msa(crtc_state, conn_state);
2976}
2977
2978static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2979 struct intel_encoder *encoder,
2980 const struct intel_crtc_state *crtc_state,
2981 const struct drm_connector_state *conn_state)
2982{
2983 struct intel_display *display = to_intel_display(encoder);
2984 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2985 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2986
2987 intel_dp_dual_mode_set_tmds_output(hdmi: intel_hdmi, enable: true);
2988 intel_ddi_enable_clock(encoder, crtc_state);
2989
2990 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
2991 dig_port->ddi_io_wakeref = intel_display_power_get(display,
2992 domain: dig_port->ddi_io_power_domain);
2993
2994 icl_program_mg_dp_mode(dig_port, crtc_state);
2995
2996 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2997
2998 dig_port->set_infoframes(encoder,
2999 crtc_state->has_infoframe,
3000 crtc_state, conn_state);
3001}
3002
3003/*
3004 * Note: Also called from the ->pre_enable of the first active MST stream
3005 * encoder on its primary encoder.
3006 *
3007 * When called from DP MST code:
3008 *
3009 * - conn_state will be NULL
3010 *
3011 * - encoder will be the primary encoder (i.e. mst->primary)
3012 *
3013 * - the main connector associated with this port won't be active or linked to a
3014 * crtc
3015 *
3016 * - crtc_state will be the state of the first stream to be activated on this
3017 * port, and it may not be the same stream that will be deactivated last, but
3018 * each stream should have a state that is identical when it comes to the DP
3019 * link parameters.
3020 */
3021static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3022 struct intel_encoder *encoder,
3023 const struct intel_crtc_state *crtc_state,
3024 const struct drm_connector_state *conn_state)
3025{
3026 struct intel_display *display = to_intel_display(state);
3027 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3028 enum pipe pipe = crtc->pipe;
3029
3030 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder);
3031
3032 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
3033
3034 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) {
3035 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3036 conn_state);
3037 } else {
3038 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3039
3040 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3041 conn_state);
3042
3043 /* FIXME precompute everything properly */
3044 /* FIXME how do we turn infoframes off again? */
3045 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(intel_dp: &dig_port->dp))
3046 dig_port->set_infoframes(encoder,
3047 crtc_state->has_infoframe,
3048 crtc_state, conn_state);
3049 }
3050}
3051
3052static void
3053mtl_ddi_disable_d2d(struct intel_encoder *encoder)
3054{
3055 struct intel_display *display = to_intel_display(encoder);
3056 enum port port = encoder->port;
3057 i915_reg_t reg;
3058 u32 clr_bits, wait_bits;
3059 int ret;
3060
3061 if (DISPLAY_VER(display) < 14)
3062 return;
3063
3064 if (DISPLAY_VER(display) >= 20) {
3065 reg = DDI_BUF_CTL(port);
3066 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3067 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
3068 } else {
3069 reg = XELPDP_PORT_BUF_CTL1(display, port);
3070 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
3071 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
3072 }
3073
3074 intel_de_rmw(display, reg, clear: clr_bits, set: 0);
3075
3076 ret = intel_de_wait_custom(display, reg,
3077 mask: wait_bits, value: 0,
3078 fast_timeout_us: 100, slow_timeout_ms: 0, NULL);
3079 if (ret)
3080 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
3081 port_name(port));
3082}
3083
3084static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl)
3085{
3086 struct intel_display *display = to_intel_display(encoder);
3087 enum port port = encoder->port;
3088
3089 intel_de_write(display, DDI_BUF_CTL(port), val: buf_ctl | DDI_BUF_CTL_ENABLE);
3090 intel_de_posting_read(display, DDI_BUF_CTL(port));
3091
3092 intel_wait_ddi_buf_active(encoder);
3093}
3094
3095static void intel_ddi_buf_disable(struct intel_encoder *encoder,
3096 const struct intel_crtc_state *crtc_state)
3097{
3098 struct intel_display *display = to_intel_display(encoder);
3099 enum port port = encoder->port;
3100
3101 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, set: 0);
3102
3103 if (DISPLAY_VER(display) >= 14)
3104 intel_wait_ddi_buf_idle(display, port);
3105
3106 mtl_ddi_disable_d2d(encoder);
3107
3108 if (intel_crtc_has_dp_encoder(crtc_state)) {
3109 intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
3110 DP_TP_CTL_ENABLE, set: 0);
3111 }
3112
3113 intel_ddi_disable_fec(encoder, crtc_state);
3114
3115 if (DISPLAY_VER(display) < 14)
3116 intel_wait_ddi_buf_idle(display, port);
3117
3118 intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled: false);
3119}
3120
3121static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3122 struct intel_encoder *encoder,
3123 const struct intel_crtc_state *old_crtc_state,
3124 const struct drm_connector_state *old_conn_state)
3125{
3126 struct intel_display *display = to_intel_display(encoder);
3127 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3128 struct intel_dp *intel_dp = &dig_port->dp;
3129 intel_wakeref_t wakeref;
3130 bool is_mst = intel_crtc_has_type(crtc_state: old_crtc_state,
3131 type: INTEL_OUTPUT_DP_MST);
3132
3133 if (!is_mst)
3134 intel_dp_set_infoframes(encoder, enable: false,
3135 crtc_state: old_crtc_state, conn_state: old_conn_state);
3136
3137 /*
3138 * Power down sink before disabling the port, otherwise we end
3139 * up getting interrupts from the sink on detecting link loss.
3140 */
3141 intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3142
3143 if (DISPLAY_VER(display) >= 12) {
3144 if (is_mst || intel_dp_is_uhbr(crtc_state: old_crtc_state)) {
3145 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3146
3147 intel_de_rmw(display,
3148 TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
3149 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK,
3150 set: 0);
3151 }
3152 } else {
3153 if (!is_mst)
3154 intel_ddi_disable_transcoder_clock(crtc_state: old_crtc_state);
3155 }
3156
3157 intel_ddi_buf_disable(encoder, crtc_state: old_crtc_state);
3158
3159 intel_dp_sink_set_fec_ready(intel_dp, crtc_state: old_crtc_state, enable: false);
3160
3161 intel_ddi_config_transcoder_dp2(crtc_state: old_crtc_state, enable: false);
3162
3163 /*
3164 * From TGL spec: "If single stream or multi-stream master transcoder:
3165 * Configure Transcoder Clock select to direct no clock to the
3166 * transcoder"
3167 */
3168 if (DISPLAY_VER(display) >= 12)
3169 intel_ddi_disable_transcoder_clock(crtc_state: old_crtc_state);
3170
3171 intel_pps_vdd_on(intel_dp);
3172 intel_pps_off(intel_dp);
3173
3174 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
3175
3176 if (wakeref)
3177 intel_display_power_put(display,
3178 domain: dig_port->ddi_io_power_domain,
3179 wakeref);
3180
3181 intel_ddi_disable_clock(encoder);
3182
3183 /* De-select Thunderbolt */
3184 if (DISPLAY_VER(display) >= 14)
3185 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
3186 XELPDP_PORT_BUF_IO_SELECT_TBT, set: 0);
3187}
3188
3189static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3190 struct intel_encoder *encoder,
3191 const struct intel_crtc_state *old_crtc_state,
3192 const struct drm_connector_state *old_conn_state)
3193{
3194 struct intel_display *display = to_intel_display(encoder);
3195 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3196 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3197 intel_wakeref_t wakeref;
3198
3199 dig_port->set_infoframes(encoder, false,
3200 old_crtc_state, old_conn_state);
3201
3202 if (DISPLAY_VER(display) < 12)
3203 intel_ddi_disable_transcoder_clock(crtc_state: old_crtc_state);
3204
3205 intel_ddi_buf_disable(encoder, crtc_state: old_crtc_state);
3206
3207 if (DISPLAY_VER(display) >= 12)
3208 intel_ddi_disable_transcoder_clock(crtc_state: old_crtc_state);
3209
3210 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
3211 if (wakeref)
3212 intel_display_power_put(display,
3213 domain: dig_port->ddi_io_power_domain,
3214 wakeref);
3215
3216 intel_ddi_disable_clock(encoder);
3217
3218 intel_dp_dual_mode_set_tmds_output(hdmi: intel_hdmi, enable: false);
3219}
3220
3221static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
3222 struct intel_encoder *encoder,
3223 const struct intel_crtc_state *old_crtc_state,
3224 const struct drm_connector_state *old_conn_state)
3225{
3226 struct intel_display *display = to_intel_display(encoder);
3227 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3228 struct intel_crtc *pipe_crtc;
3229 bool is_hdmi = intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_HDMI);
3230 int i;
3231
3232 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
3233 const struct intel_crtc_state *old_pipe_crtc_state =
3234 intel_atomic_get_old_crtc_state(state, crtc: pipe_crtc);
3235
3236 intel_crtc_vblank_off(crtc_state: old_pipe_crtc_state);
3237 }
3238
3239 intel_disable_transcoder(old_crtc_state);
3240
3241 /* 128b/132b SST */
3242 if (!is_hdmi && intel_dp_is_uhbr(crtc_state: old_crtc_state)) {
3243 /* VCPID 1, start slot 0 for 128b/132b, clear */
3244 drm_dp_dpcd_write_payload(aux: &intel_dp->aux, vcpid: 1, start_time_slot: 0, time_slot_count: 0);
3245
3246 intel_ddi_clear_act_sent(encoder, crtc_state: old_crtc_state);
3247
3248 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),
3249 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, set: 0);
3250
3251 intel_ddi_wait_for_act_sent(encoder, crtc_state: old_crtc_state);
3252 drm_dp_dpcd_poll_act_handled(aux: &intel_dp->aux, timeout_ms: 0);
3253 }
3254
3255 intel_vrr_transcoder_disable(crtc_state: old_crtc_state);
3256
3257 intel_ddi_disable_transcoder_func(crtc_state: old_crtc_state);
3258
3259 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
3260 const struct intel_crtc_state *old_pipe_crtc_state =
3261 intel_atomic_get_old_crtc_state(state, crtc: pipe_crtc);
3262
3263 intel_dsc_disable(crtc_state: old_pipe_crtc_state);
3264
3265 if (DISPLAY_VER(display) >= 9)
3266 skl_scaler_disable(old_crtc_state: old_pipe_crtc_state);
3267 else
3268 ilk_pfit_disable(old_crtc_state: old_pipe_crtc_state);
3269 }
3270}
3271
3272/*
3273 * Note: Also called from the ->post_disable of the last active MST stream
3274 * encoder on its primary encoder. See also the comment for
3275 * intel_ddi_pre_enable().
3276 */
3277static void intel_ddi_post_disable(struct intel_atomic_state *state,
3278 struct intel_encoder *encoder,
3279 const struct intel_crtc_state *old_crtc_state,
3280 const struct drm_connector_state *old_conn_state)
3281{
3282 if (!intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_DP_MST))
3283 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state,
3284 old_conn_state);
3285
3286 /*
3287 * When called from DP MST code:
3288 * - old_conn_state will be NULL
3289 * - encoder will be the main encoder (ie. mst->primary)
3290 * - the main connector associated with this port
3291 * won't be active or linked to a crtc
3292 * - old_crtc_state will be the state of the last stream to
3293 * be deactivated on this port, and it may not be the same
3294 * stream that was activated last, but each stream
3295 * should have a state that is identical when it comes to
3296 * the DP link parameters
3297 */
3298
3299 if (intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_HDMI))
3300 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3301 old_conn_state);
3302 else
3303 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3304 old_conn_state);
3305}
3306
3307/*
3308 * Note: Also called from the ->post_pll_disable of the last active MST stream
3309 * encoder on its primary encoder. See also the comment for
3310 * intel_ddi_pre_enable().
3311 */
3312static void intel_ddi_post_pll_disable(struct intel_atomic_state *state,
3313 struct intel_encoder *encoder,
3314 const struct intel_crtc_state *old_crtc_state,
3315 const struct drm_connector_state *old_conn_state)
3316{
3317 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3318
3319 main_link_aux_power_domain_put(dig_port, crtc_state: old_crtc_state);
3320
3321 if (intel_encoder_is_tc(encoder))
3322 intel_tc_port_put_link(dig_port);
3323}
3324
3325static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3326 struct intel_encoder *encoder,
3327 const struct intel_crtc_state *crtc_state)
3328{
3329 const struct drm_connector_state *conn_state;
3330 struct drm_connector *conn;
3331 int i;
3332
3333 if (!crtc_state->sync_mode_slaves_mask)
3334 return;
3335
3336 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3337 struct intel_encoder *slave_encoder =
3338 to_intel_encoder(conn_state->best_encoder);
3339 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3340 const struct intel_crtc_state *slave_crtc_state;
3341
3342 if (!slave_crtc)
3343 continue;
3344
3345 slave_crtc_state =
3346 intel_atomic_get_new_crtc_state(state, crtc: slave_crtc);
3347
3348 if (slave_crtc_state->master_transcoder !=
3349 crtc_state->cpu_transcoder)
3350 continue;
3351
3352 intel_dp_stop_link_train(intel_dp: enc_to_intel_dp(encoder: slave_encoder),
3353 crtc_state: slave_crtc_state);
3354 }
3355
3356 usleep_range(min: 200, max: 400);
3357
3358 intel_dp_stop_link_train(intel_dp: enc_to_intel_dp(encoder),
3359 crtc_state);
3360}
3361
3362static void intel_ddi_enable_dp(struct intel_atomic_state *state,
3363 struct intel_encoder *encoder,
3364 const struct intel_crtc_state *crtc_state,
3365 const struct drm_connector_state *conn_state)
3366{
3367 struct intel_display *display = to_intel_display(encoder);
3368 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3369 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3370 enum port port = encoder->port;
3371
3372 if (port == PORT_A && DISPLAY_VER(display) < 9)
3373 intel_dp_stop_link_train(intel_dp, crtc_state);
3374
3375 drm_connector_update_privacy_screen(connector_state: conn_state);
3376 intel_edp_backlight_on(crtc_state, conn_state);
3377
3378 intel_panel_prepare(crtc_state, conn_state);
3379
3380 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(intel_dp: &dig_port->dp))
3381 intel_dp_set_infoframes(encoder, enable: true, crtc_state, conn_state);
3382
3383 trans_port_sync_stop_link_train(state, encoder, crtc_state);
3384}
3385
3386static i915_reg_t
3387gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port)
3388{
3389 static const enum transcoder trans[] = {
3390 [PORT_A] = TRANSCODER_EDP,
3391 [PORT_B] = TRANSCODER_A,
3392 [PORT_C] = TRANSCODER_B,
3393 [PORT_D] = TRANSCODER_C,
3394 [PORT_E] = TRANSCODER_A,
3395 };
3396
3397 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9);
3398
3399 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E))
3400 port = PORT_A;
3401
3402 return CHICKEN_TRANS(display, trans[port]);
3403}
3404
3405static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
3406 struct intel_encoder *encoder,
3407 const struct intel_crtc_state *crtc_state,
3408 const struct drm_connector_state *conn_state)
3409{
3410 struct intel_display *display = to_intel_display(encoder);
3411 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3412 struct drm_connector *connector = conn_state->connector;
3413 enum port port = encoder->port;
3414 u32 buf_ctl = 0;
3415
3416 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3417 high_tmds_clock_ratio: crtc_state->hdmi_high_tmds_clock_ratio,
3418 scrambling: crtc_state->hdmi_scrambling))
3419 drm_dbg_kms(display->drm,
3420 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3421 connector->base.id, connector->name);
3422
3423 if (has_buf_trans_select(display))
3424 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
3425
3426 /* e. Enable D2D Link for C10/C20 Phy */
3427 mtl_ddi_enable_d2d(encoder);
3428
3429 encoder->set_signal_levels(encoder, crtc_state);
3430
3431 /* Display WA #1143: skl,kbl,cfl */
3432 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {
3433 /*
3434 * For some reason these chicken bits have been
3435 * stuffed into a transcoder register, event though
3436 * the bits affect a specific DDI port rather than
3437 * a specific transcoder.
3438 */
3439 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);
3440 u32 val;
3441
3442 val = intel_de_read(display, reg);
3443
3444 if (port == PORT_E)
3445 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3446 DDIE_TRAINING_OVERRIDE_VALUE;
3447 else
3448 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3449 DDI_TRAINING_OVERRIDE_VALUE;
3450
3451 intel_de_write(display, reg, val);
3452 intel_de_posting_read(display, reg);
3453
3454 udelay(usec: 1);
3455
3456 if (port == PORT_E)
3457 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3458 DDIE_TRAINING_OVERRIDE_VALUE);
3459 else
3460 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3461 DDI_TRAINING_OVERRIDE_VALUE);
3462
3463 intel_de_write(display, reg, val);
3464 }
3465
3466 intel_ddi_power_up_lanes(encoder, crtc_state);
3467
3468 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3469 * are ignored so nothing special needs to be done besides
3470 * enabling the port.
3471 *
3472 * On ADL_P the PHY link rate and lane count must be programmed but
3473 * these are both 0 for HDMI.
3474 *
3475 * But MTL onwards HDMI2.1 is supported and in TMDS mode this
3476 * is filled with lane count, already set in the crtc_state.
3477 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
3478 */
3479 if (dig_port->lane_reversal)
3480 buf_ctl |= DDI_BUF_PORT_REVERSAL;
3481 if (dig_port->ddi_a_4_lanes)
3482 buf_ctl |= DDI_A_4_LANES;
3483
3484 if (DISPLAY_VER(display) >= 14) {
3485 u32 port_buf = 0;
3486
3487 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
3488
3489 if (dig_port->lane_reversal)
3490 port_buf |= XELPDP_PORT_REVERSAL;
3491
3492 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
3493 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, set: port_buf);
3494
3495 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
3496
3497 if (DISPLAY_VER(display) >= 20)
3498 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3499 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {
3500 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port));
3501 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
3502 }
3503
3504 intel_ddi_buf_enable(encoder, buf_ctl);
3505}
3506
3507static void intel_ddi_enable(struct intel_atomic_state *state,
3508 struct intel_encoder *encoder,
3509 const struct intel_crtc_state *crtc_state,
3510 const struct drm_connector_state *conn_state)
3511{
3512 struct intel_display *display = to_intel_display(encoder);
3513 struct intel_crtc *pipe_crtc;
3514 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3515 bool is_hdmi = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI);
3516 int i;
3517
3518 /* 128b/132b SST */
3519 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
3520 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
3521 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
3522
3523 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
3524 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
3525 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
3526 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
3527 }
3528
3529 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3530
3531 intel_vrr_transcoder_enable(crtc_state);
3532
3533 /* 128b/132b SST */
3534 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
3535 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3536
3537 intel_ddi_clear_act_sent(encoder, crtc_state);
3538
3539 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), clear: 0,
3540 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
3541
3542 intel_ddi_wait_for_act_sent(encoder, crtc_state);
3543 drm_dp_dpcd_poll_act_handled(aux: &intel_dp->aux, timeout_ms: 0);
3544 }
3545
3546 intel_enable_transcoder(new_crtc_state: crtc_state);
3547
3548 intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled: true);
3549
3550 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) {
3551 const struct intel_crtc_state *pipe_crtc_state =
3552 intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
3553
3554 intel_crtc_vblank_on(crtc_state: pipe_crtc_state);
3555 }
3556
3557 if (is_hdmi)
3558 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);
3559 else
3560 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
3561
3562 intel_hdcp_enable(state, encoder, pipe_config: crtc_state, conn_state);
3563
3564}
3565
3566static void intel_ddi_disable_dp(struct intel_atomic_state *state,
3567 struct intel_encoder *encoder,
3568 const struct intel_crtc_state *old_crtc_state,
3569 const struct drm_connector_state *old_conn_state)
3570{
3571 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3572 struct intel_connector *connector =
3573 to_intel_connector(old_conn_state->connector);
3574
3575 intel_dp->link.active = false;
3576
3577 intel_panel_unprepare(old_conn_state);
3578 intel_psr_disable(intel_dp, old_crtc_state);
3579 intel_alpm_disable(intel_dp);
3580 intel_edp_backlight_off(conn_state: old_conn_state);
3581 /* Disable the decompression in DP Sink */
3582 intel_dp_sink_disable_decompression(state,
3583 connector, old_crtc_state);
3584 /* Disable Ignore_MSA bit in DP Sink */
3585 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, crtc_state: old_crtc_state,
3586 enable: false);
3587}
3588
3589static void intel_ddi_disable_hdmi(struct intel_atomic_state *state,
3590 struct intel_encoder *encoder,
3591 const struct intel_crtc_state *old_crtc_state,
3592 const struct drm_connector_state *old_conn_state)
3593{
3594 struct intel_display *display = to_intel_display(encoder);
3595 struct drm_connector *connector = old_conn_state->connector;
3596
3597 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3598 high_tmds_clock_ratio: false, scrambling: false))
3599 drm_dbg_kms(display->drm,
3600 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3601 connector->base.id, connector->name);
3602}
3603
3604static void intel_ddi_disable(struct intel_atomic_state *state,
3605 struct intel_encoder *encoder,
3606 const struct intel_crtc_state *old_crtc_state,
3607 const struct drm_connector_state *old_conn_state)
3608{
3609 intel_tc_port_link_cancel_reset_work(dig_port: enc_to_dig_port(encoder));
3610
3611 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3612
3613 if (intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_HDMI))
3614 intel_ddi_disable_hdmi(state, encoder, old_crtc_state,
3615 old_conn_state);
3616 else
3617 intel_ddi_disable_dp(state, encoder, old_crtc_state,
3618 old_conn_state);
3619}
3620
3621static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3622 struct intel_encoder *encoder,
3623 const struct intel_crtc_state *crtc_state,
3624 const struct drm_connector_state *conn_state)
3625{
3626 intel_ddi_set_dp_msa(crtc_state, conn_state);
3627
3628 intel_dp_set_infoframes(encoder, enable: true, crtc_state, conn_state);
3629
3630 intel_backlight_update(state, encoder, crtc_state, conn_state);
3631 drm_connector_update_privacy_screen(connector_state: conn_state);
3632}
3633
3634static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder,
3635 const struct intel_crtc_state *crtc_state,
3636 const struct drm_connector_state *conn_state)
3637{
3638 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state);
3639}
3640
3641void intel_ddi_update_pipe(struct intel_atomic_state *state,
3642 struct intel_encoder *encoder,
3643 const struct intel_crtc_state *crtc_state,
3644 const struct drm_connector_state *conn_state)
3645{
3646
3647 if (!intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI) &&
3648 !intel_encoder_is_mst(encoder))
3649 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3650 conn_state);
3651
3652 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI))
3653 intel_ddi_update_pipe_hdmi(encoder, crtc_state,
3654 conn_state);
3655
3656 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3657}
3658
3659void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
3660 struct intel_encoder *encoder,
3661 struct intel_crtc *crtc)
3662{
3663 struct intel_display *display = to_intel_display(encoder);
3664 const struct intel_crtc_state *crtc_state =
3665 intel_atomic_get_new_crtc_state(state, crtc);
3666 struct intel_crtc *pipe_crtc;
3667
3668 /* FIXME: Add MTL pll_mgr */
3669 if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
3670 return;
3671
3672 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
3673 intel_crtc_joined_pipe_mask(crtc_state))
3674 intel_dpll_update_active(state, crtc: pipe_crtc, encoder);
3675}
3676
3677/*
3678 * Note: Also called from the ->pre_pll_enable of the first active MST stream
3679 * encoder on its primary encoder. See also the comment for
3680 * intel_ddi_pre_enable().
3681 */
3682static void
3683intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3684 struct intel_encoder *encoder,
3685 const struct intel_crtc_state *crtc_state,
3686 const struct drm_connector_state *conn_state)
3687{
3688 struct intel_display *display = to_intel_display(encoder);
3689 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3690 bool is_tc_port = intel_encoder_is_tc(encoder);
3691
3692 if (is_tc_port) {
3693 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3694
3695 intel_tc_port_get_link(dig_port, required_lanes: crtc_state->lane_count);
3696 intel_ddi_update_active_dpll(state, encoder, crtc);
3697 }
3698
3699 main_link_aux_power_domain_get(dig_port, crtc_state);
3700
3701 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
3702 /*
3703 * Program the lane count for static/dynamic connections on
3704 * Type-C ports. Skip this step for TBT.
3705 */
3706 intel_tc_port_set_fia_lane_count(dig_port, required_lanes: crtc_state->lane_count);
3707 else if (display->platform.geminilake || display->platform.broxton)
3708 bxt_dpio_phy_set_lane_optim_mask(encoder,
3709 lane_lat_optim_mask: crtc_state->lane_lat_optim_mask);
3710}
3711
3712static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
3713{
3714 struct intel_display *display = to_intel_display(encoder);
3715 enum tc_port tc_port = intel_encoder_to_tc(encoder);
3716 int ln;
3717
3718 for (ln = 0; ln < 2; ln++)
3719 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),
3720 DKL_PCS_DW5_CORE_SOFTRESET, set: 0);
3721}
3722
3723static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3724 const struct intel_crtc_state *crtc_state)
3725{
3726 struct intel_display *display = to_intel_display(crtc_state);
3727 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3728 struct intel_encoder *encoder = &dig_port->base;
3729 u32 dp_tp_ctl;
3730
3731 /*
3732 * TODO: To train with only a different voltage swing entry is not
3733 * necessary disable and enable port
3734 */
3735 dp_tp_ctl = intel_de_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
3736
3737 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);
3738
3739 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
3740 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3741 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST) ||
3742 intel_dp_is_uhbr(crtc_state)) {
3743 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3744 } else {
3745 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3746 if (crtc_state->enhanced_framing)
3747 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3748 }
3749 intel_de_write(display, reg: dp_tp_ctl_reg(encoder, crtc_state), val: dp_tp_ctl);
3750 intel_de_posting_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
3751
3752 /* 6.f Enable D2D Link */
3753 mtl_ddi_enable_d2d(encoder);
3754
3755 /* 6.g Configure voltage swing and related IO settings */
3756 encoder->set_signal_levels(encoder, crtc_state);
3757
3758 /* 6.h Configure PORT_BUF_CTL1 */
3759 mtl_port_buf_ctl_program(encoder, crtc_state);
3760
3761 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
3762 if (DISPLAY_VER(display) >= 20)
3763 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3764
3765 intel_ddi_buf_enable(encoder, buf_ctl: intel_dp->DP);
3766 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3767
3768 /*
3769 * 6.k If AUX-Less ALPM is going to be enabled:
3770 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here
3771 */
3772 intel_alpm_port_configure(intel_dp, crtc_state);
3773
3774 /*
3775 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE
3776 * register
3777 */
3778 intel_lnl_mac_transmit_lfps(encoder, crtc_state);
3779}
3780
3781static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3782 const struct intel_crtc_state *crtc_state)
3783{
3784 struct intel_display *display = to_intel_display(intel_dp);
3785 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3786 struct intel_encoder *encoder = &dig_port->base;
3787 u32 dp_tp_ctl;
3788
3789 dp_tp_ctl = intel_de_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
3790
3791 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);
3792
3793 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3794 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST) ||
3795 intel_dp_is_uhbr(crtc_state)) {
3796 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3797 } else {
3798 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3799 if (crtc_state->enhanced_framing)
3800 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3801 }
3802 intel_de_write(display, reg: dp_tp_ctl_reg(encoder, crtc_state), val: dp_tp_ctl);
3803 intel_de_posting_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
3804
3805 if (display->platform.alderlake_p &&
3806 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
3807 adlp_tbt_to_dp_alt_switch_wa(encoder);
3808
3809 intel_ddi_buf_enable(encoder, buf_ctl: intel_dp->DP);
3810 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3811}
3812
3813static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3814 const struct intel_crtc_state *crtc_state,
3815 u8 dp_train_pat)
3816{
3817 struct intel_display *display = to_intel_display(intel_dp);
3818 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3819 u32 temp;
3820
3821 temp = intel_de_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
3822
3823 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3824 switch (intel_dp_training_pattern_symbol(pattern: dp_train_pat)) {
3825 case DP_TRAINING_PATTERN_DISABLE:
3826 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3827 break;
3828 case DP_TRAINING_PATTERN_1:
3829 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3830 break;
3831 case DP_TRAINING_PATTERN_2:
3832 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3833 break;
3834 case DP_TRAINING_PATTERN_3:
3835 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3836 break;
3837 case DP_TRAINING_PATTERN_4:
3838 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3839 break;
3840 }
3841
3842 intel_de_write(display, reg: dp_tp_ctl_reg(encoder, crtc_state), val: temp);
3843}
3844
3845static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3846 const struct intel_crtc_state *crtc_state)
3847{
3848 struct intel_display *display = to_intel_display(intel_dp);
3849 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3850 enum port port = encoder->port;
3851
3852 intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
3853 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE);
3854
3855 /*
3856 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3857 * reason we need to set idle transmission mode is to work around a HW
3858 * issue where we enable the pipe while not in idle link-training mode.
3859 * In this case there is requirement to wait for a minimum number of
3860 * idle patterns to be sent.
3861 */
3862 if (port == PORT_A && DISPLAY_VER(display) < 12)
3863 return;
3864
3865 if (intel_de_wait_for_set(display,
3866 reg: dp_tp_status_reg(encoder, crtc_state),
3867 DP_TP_STATUS_IDLE_DONE, timeout_ms: 2))
3868 drm_err(display->drm,
3869 "Timed out waiting for DP idle patterns\n");
3870}
3871
3872static bool intel_ddi_is_audio_enabled(struct intel_display *display,
3873 enum transcoder cpu_transcoder)
3874{
3875 if (cpu_transcoder == TRANSCODER_EDP)
3876 return false;
3877
3878 if (!intel_display_power_is_enabled(display, domain: POWER_DOMAIN_AUDIO_MMIO))
3879 return false;
3880
3881 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) &
3882 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3883}
3884
3885static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3886{
3887 if (crtc_state->port_clock > 594000)
3888 return 2;
3889 else
3890 return 0;
3891}
3892
3893static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3894{
3895 if (crtc_state->port_clock > 594000)
3896 return 3;
3897 else
3898 return 0;
3899}
3900
3901static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3902{
3903 if (crtc_state->port_clock > 594000)
3904 return 1;
3905 else
3906 return 0;
3907}
3908
3909void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state)
3910{
3911 struct intel_display *display = to_intel_display(crtc_state);
3912
3913 if (DISPLAY_VER(display) >= 14)
3914 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
3915 else if (DISPLAY_VER(display) >= 12)
3916 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state);
3917 else if (display->platform.jasperlake || display->platform.elkhartlake)
3918 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state);
3919 else if (DISPLAY_VER(display) >= 11)
3920 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
3921}
3922
3923static enum transcoder bdw_transcoder_master_readout(struct intel_display *display,
3924 enum transcoder cpu_transcoder)
3925{
3926 u32 master_select;
3927
3928 if (DISPLAY_VER(display) >= 11) {
3929 u32 ctl2 = intel_de_read(display,
3930 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder));
3931
3932 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3933 return INVALID_TRANSCODER;
3934
3935 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3936 } else {
3937 u32 ctl = intel_de_read(display,
3938 TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3939
3940 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3941 return INVALID_TRANSCODER;
3942
3943 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3944 }
3945
3946 if (master_select == 0)
3947 return TRANSCODER_EDP;
3948 else
3949 return master_select - 1;
3950}
3951
3952static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3953{
3954 struct intel_display *display = to_intel_display(crtc_state);
3955 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3956 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3957 enum transcoder cpu_transcoder;
3958
3959 crtc_state->master_transcoder =
3960 bdw_transcoder_master_readout(display, cpu_transcoder: crtc_state->cpu_transcoder);
3961
3962 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) {
3963 enum intel_display_power_domain power_domain;
3964 intel_wakeref_t trans_wakeref;
3965
3966 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3967 trans_wakeref = intel_display_power_get_if_enabled(display,
3968 domain: power_domain);
3969
3970 if (!trans_wakeref)
3971 continue;
3972
3973 if (bdw_transcoder_master_readout(display, cpu_transcoder) ==
3974 crtc_state->cpu_transcoder)
3975 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3976
3977 intel_display_power_put(display, domain: power_domain, wakeref: trans_wakeref);
3978 }
3979
3980 drm_WARN_ON(display->drm,
3981 crtc_state->master_transcoder != INVALID_TRANSCODER &&
3982 crtc_state->sync_mode_slaves_mask);
3983}
3984
3985static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder,
3986 struct intel_crtc_state *crtc_state,
3987 u32 ddi_func_ctl)
3988{
3989 struct intel_display *display = to_intel_display(encoder);
3990
3991 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI);
3992 if (DISPLAY_VER(display) >= 14)
3993 crtc_state->lane_count =
3994 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3995 else
3996 crtc_state->lane_count = 4;
3997}
3998
3999static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder,
4000 struct intel_crtc_state *crtc_state,
4001 u32 ddi_func_ctl)
4002{
4003 crtc_state->has_hdmi_sink = true;
4004
4005 crtc_state->infoframes.enable |=
4006 intel_hdmi_infoframes_enabled(encoder, crtc_state);
4007
4008 if (crtc_state->infoframes.enable)
4009 crtc_state->has_infoframe = true;
4010
4011 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING)
4012 crtc_state->hdmi_scrambling = true;
4013 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4014 crtc_state->hdmi_high_tmds_clock_ratio = true;
4015
4016 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl);
4017}
4018
4019static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder,
4020 struct intel_crtc_state *crtc_state,
4021 u32 ddi_func_ctl)
4022{
4023 struct intel_display *display = to_intel_display(encoder);
4024
4025 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4026 crtc_state->enhanced_framing =
4027 intel_de_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state)) &
4028 DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4029}
4030
4031static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder,
4032 struct intel_crtc_state *crtc_state,
4033 u32 ddi_func_ctl)
4034{
4035 struct intel_display *display = to_intel_display(encoder);
4036 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4037 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4038 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4039
4040 if (encoder->type == INTEL_OUTPUT_EDP)
4041 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP);
4042 else
4043 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP);
4044 crtc_state->lane_count =
4045 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4046
4047 if (DISPLAY_VER(display) >= 12 &&
4048 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)
4049 crtc_state->mst_master_transcoder =
4050 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
4051
4052 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, m_n: &crtc_state->dp_m_n);
4053 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, m_n: &crtc_state->dp_m2_n2);
4054
4055 crtc_state->enhanced_framing =
4056 intel_de_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state)) &
4057 DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4058
4059 if (DISPLAY_VER(display) >= 11)
4060 crtc_state->fec_enable =
4061 intel_de_read(display,
4062 reg: dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
4063
4064 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(intel_dp: &dig_port->dp))
4065 crtc_state->infoframes.enable |=
4066 intel_lspcon_infoframes_enabled(encoder, pipe_config: crtc_state);
4067 else
4068 crtc_state->infoframes.enable |=
4069 intel_hdmi_infoframes_enabled(encoder, crtc_state);
4070}
4071
4072static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder,
4073 struct intel_crtc_state *crtc_state,
4074 u32 ddi_func_ctl)
4075{
4076 struct intel_display *display = to_intel_display(encoder);
4077 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4078 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4079
4080 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4081 crtc_state->lane_count =
4082 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4083
4084 if (DISPLAY_VER(display) >= 12)
4085 crtc_state->mst_master_transcoder =
4086 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
4087
4088 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, m_n: &crtc_state->dp_m_n);
4089
4090 if (DISPLAY_VER(display) >= 11)
4091 crtc_state->fec_enable =
4092 intel_de_read(display,
4093 reg: dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
4094
4095 crtc_state->infoframes.enable |=
4096 intel_hdmi_infoframes_enabled(encoder, crtc_state);
4097}
4098
4099static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
4100 struct intel_crtc_state *pipe_config)
4101{
4102 struct intel_display *display = to_intel_display(encoder);
4103 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4104 u32 ddi_func_ctl, ddi_mode, flags = 0;
4105
4106 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
4107 if (ddi_func_ctl & TRANS_DDI_PHSYNC)
4108 flags |= DRM_MODE_FLAG_PHSYNC;
4109 else
4110 flags |= DRM_MODE_FLAG_NHSYNC;
4111 if (ddi_func_ctl & TRANS_DDI_PVSYNC)
4112 flags |= DRM_MODE_FLAG_PVSYNC;
4113 else
4114 flags |= DRM_MODE_FLAG_NVSYNC;
4115
4116 pipe_config->hw.adjusted_mode.flags |= flags;
4117
4118 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) {
4119 case TRANS_DDI_BPC_6:
4120 pipe_config->pipe_bpp = 18;
4121 break;
4122 case TRANS_DDI_BPC_8:
4123 pipe_config->pipe_bpp = 24;
4124 break;
4125 case TRANS_DDI_BPC_10:
4126 pipe_config->pipe_bpp = 30;
4127 break;
4128 case TRANS_DDI_BPC_12:
4129 pipe_config->pipe_bpp = 36;
4130 break;
4131 default:
4132 break;
4133 }
4134
4135 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK;
4136
4137 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) {
4138 intel_ddi_read_func_ctl_hdmi(encoder, crtc_state: pipe_config, ddi_func_ctl);
4139 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) {
4140 intel_ddi_read_func_ctl_dvi(encoder, crtc_state: pipe_config, ddi_func_ctl);
4141 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {
4142 intel_ddi_read_func_ctl_fdi(encoder, crtc_state: pipe_config, ddi_func_ctl);
4143 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
4144 intel_ddi_read_func_ctl_dp_sst(encoder, crtc_state: pipe_config, ddi_func_ctl);
4145 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) {
4146 intel_ddi_read_func_ctl_dp_mst(encoder, crtc_state: pipe_config, ddi_func_ctl);
4147 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
4148 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4149
4150 /*
4151 * If this is true, we know we're being called from mst stream
4152 * encoder's ->get_config().
4153 */
4154 if (intel_dp_mst_active_streams(intel_dp))
4155 intel_ddi_read_func_ctl_dp_mst(encoder, crtc_state: pipe_config, ddi_func_ctl);
4156 else
4157 intel_ddi_read_func_ctl_dp_sst(encoder, crtc_state: pipe_config, ddi_func_ctl);
4158 }
4159}
4160
4161/*
4162 * Note: Also called from the ->get_config of the MST stream encoders on their
4163 * primary encoder, via the platform specific hooks here. See also the comment
4164 * for intel_ddi_pre_enable().
4165 */
4166static void intel_ddi_get_config(struct intel_encoder *encoder,
4167 struct intel_crtc_state *pipe_config)
4168{
4169 struct intel_display *display = to_intel_display(encoder);
4170 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4171
4172 /* XXX: DSI transcoder paranoia */
4173 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)))
4174 return;
4175
4176 intel_ddi_read_func_ctl(encoder, pipe_config);
4177
4178 intel_ddi_mso_get_config(encoder, pipe_config);
4179
4180 pipe_config->has_audio =
4181 intel_ddi_is_audio_enabled(display, cpu_transcoder);
4182
4183 if (encoder->type == INTEL_OUTPUT_EDP)
4184 intel_edp_fixup_vbt_bpp(encoder, pipe_bpp: pipe_config->pipe_bpp);
4185
4186 ddi_dotclock_get(pipe_config);
4187
4188 if (display->platform.geminilake || display->platform.broxton)
4189 pipe_config->lane_lat_optim_mask =
4190 bxt_dpio_phy_get_lane_lat_optim_mask(encoder);
4191
4192 intel_ddi_compute_min_voltage_level(crtc_state: pipe_config);
4193
4194 intel_hdmi_read_gcp_infoframe(encoder, crtc_state: pipe_config);
4195
4196 intel_read_infoframe(encoder, crtc_state: pipe_config,
4197 type: HDMI_INFOFRAME_TYPE_AVI,
4198 frame: &pipe_config->infoframes.avi);
4199 intel_read_infoframe(encoder, crtc_state: pipe_config,
4200 type: HDMI_INFOFRAME_TYPE_SPD,
4201 frame: &pipe_config->infoframes.spd);
4202 intel_read_infoframe(encoder, crtc_state: pipe_config,
4203 type: HDMI_INFOFRAME_TYPE_VENDOR,
4204 frame: &pipe_config->infoframes.hdmi);
4205 intel_read_infoframe(encoder, crtc_state: pipe_config,
4206 type: HDMI_INFOFRAME_TYPE_DRM,
4207 frame: &pipe_config->infoframes.drm);
4208
4209 if (DISPLAY_VER(display) >= 8)
4210 bdw_get_trans_port_sync_config(crtc_state: pipe_config);
4211
4212 intel_psr_get_config(encoder, pipe_config);
4213
4214 intel_read_dp_sdp(encoder, crtc_state: pipe_config, type: HDMI_PACKET_TYPE_GAMUT_METADATA);
4215 intel_read_dp_sdp(encoder, crtc_state: pipe_config, DP_SDP_VSC);
4216 intel_read_dp_sdp(encoder, crtc_state: pipe_config, DP_SDP_ADAPTIVE_SYNC);
4217
4218 intel_audio_codec_get_config(encoder, crtc_state: pipe_config);
4219}
4220
4221void intel_ddi_get_clock(struct intel_encoder *encoder,
4222 struct intel_crtc_state *crtc_state,
4223 struct intel_dpll *pll)
4224{
4225 struct intel_display *display = to_intel_display(encoder);
4226 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
4227 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
4228 bool pll_active;
4229
4230 if (drm_WARN_ON(display->drm, !pll))
4231 return;
4232
4233 port_dpll->pll = pll;
4234 pll_active = intel_dpll_get_hw_state(display, pll, dpll_hw_state: &port_dpll->hw_state);
4235 drm_WARN_ON(display->drm, !pll_active);
4236
4237 icl_set_active_port_dpll(crtc_state, port_dpll_id);
4238
4239 crtc_state->port_clock = intel_dpll_get_freq(display, pll: crtc_state->intel_dpll,
4240 dpll_hw_state: &crtc_state->dpll_hw_state);
4241}
4242
4243static void mtl_ddi_get_config(struct intel_encoder *encoder,
4244 struct intel_crtc_state *crtc_state)
4245{
4246 intel_cx0pll_readout_hw_state(encoder, pll_state: &crtc_state->dpll_hw_state.cx0pll);
4247
4248 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
4249 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
4250 else
4251 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, pll_state: &crtc_state->dpll_hw_state.cx0pll);
4252
4253 intel_ddi_get_config(encoder, pipe_config: crtc_state);
4254}
4255
4256static void dg2_ddi_get_config(struct intel_encoder *encoder,
4257 struct intel_crtc_state *crtc_state)
4258{
4259 intel_mpllb_readout_hw_state(encoder, pll_state: &crtc_state->dpll_hw_state.mpllb);
4260 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, pll_state: &crtc_state->dpll_hw_state.mpllb);
4261
4262 intel_ddi_get_config(encoder, pipe_config: crtc_state);
4263}
4264
4265static void adls_ddi_get_config(struct intel_encoder *encoder,
4266 struct intel_crtc_state *crtc_state)
4267{
4268 intel_ddi_get_clock(encoder, crtc_state, pll: adls_ddi_get_pll(encoder));
4269 intel_ddi_get_config(encoder, pipe_config: crtc_state);
4270}
4271
4272static void rkl_ddi_get_config(struct intel_encoder *encoder,
4273 struct intel_crtc_state *crtc_state)
4274{
4275 intel_ddi_get_clock(encoder, crtc_state, pll: rkl_ddi_get_pll(encoder));
4276 intel_ddi_get_config(encoder, pipe_config: crtc_state);
4277}
4278
4279static void dg1_ddi_get_config(struct intel_encoder *encoder,
4280 struct intel_crtc_state *crtc_state)
4281{
4282 intel_ddi_get_clock(encoder, crtc_state, pll: dg1_ddi_get_pll(encoder));
4283 intel_ddi_get_config(encoder, pipe_config: crtc_state);
4284}
4285
4286static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
4287 struct intel_crtc_state *crtc_state)
4288{
4289 intel_ddi_get_clock(encoder, crtc_state, pll: icl_ddi_combo_get_pll(encoder));
4290 intel_ddi_get_config(encoder, pipe_config: crtc_state);
4291}
4292
4293static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
4294{
4295 return pll->info->id == DPLL_ID_ICL_TBTPLL;
4296}
4297
4298static enum icl_port_dpll_id
4299icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
4300 const struct intel_crtc_state *crtc_state)
4301{
4302 struct intel_display *display = to_intel_display(encoder);
4303 const struct intel_dpll *pll = crtc_state->intel_dpll;
4304
4305 if (drm_WARN_ON(display->drm, !pll))
4306 return ICL_PORT_DPLL_DEFAULT;
4307
4308 if (icl_ddi_tc_pll_is_tbt(pll))
4309 return ICL_PORT_DPLL_DEFAULT;
4310 else
4311 return ICL_PORT_DPLL_MG_PHY;
4312}
4313
4314enum icl_port_dpll_id
4315intel_ddi_port_pll_type(struct intel_encoder *encoder,
4316 const struct intel_crtc_state *crtc_state)
4317{
4318 if (!encoder->port_pll_type)
4319 return ICL_PORT_DPLL_DEFAULT;
4320
4321 return encoder->port_pll_type(encoder, crtc_state);
4322}
4323
4324static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
4325 struct intel_crtc_state *crtc_state,
4326 struct intel_dpll *pll)
4327{
4328 struct intel_display *display = to_intel_display(encoder);
4329 enum icl_port_dpll_id port_dpll_id;
4330 struct icl_port_dpll *port_dpll;
4331 bool pll_active;
4332
4333 if (drm_WARN_ON(display->drm, !pll))
4334 return;
4335
4336 if (icl_ddi_tc_pll_is_tbt(pll))
4337 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
4338 else
4339 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
4340
4341 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
4342
4343 port_dpll->pll = pll;
4344 pll_active = intel_dpll_get_hw_state(display, pll, dpll_hw_state: &port_dpll->hw_state);
4345 drm_WARN_ON(display->drm, !pll_active);
4346
4347 icl_set_active_port_dpll(crtc_state, port_dpll_id);
4348
4349 if (icl_ddi_tc_pll_is_tbt(pll: crtc_state->intel_dpll))
4350 crtc_state->port_clock = icl_calc_tbt_pll_link(display, port: encoder->port);
4351 else
4352 crtc_state->port_clock = intel_dpll_get_freq(display, pll: crtc_state->intel_dpll,
4353 dpll_hw_state: &crtc_state->dpll_hw_state);
4354}
4355
4356static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
4357 struct intel_crtc_state *crtc_state)
4358{
4359 icl_ddi_tc_get_clock(encoder, crtc_state, pll: icl_ddi_tc_get_pll(encoder));
4360 intel_ddi_get_config(encoder, pipe_config: crtc_state);
4361}
4362
4363static void bxt_ddi_get_config(struct intel_encoder *encoder,
4364 struct intel_crtc_state *crtc_state)
4365{
4366 intel_ddi_get_clock(encoder, crtc_state, pll: bxt_ddi_get_pll(encoder));
4367 intel_ddi_get_config(encoder, pipe_config: crtc_state);
4368}
4369
4370static void skl_ddi_get_config(struct intel_encoder *encoder,
4371 struct intel_crtc_state *crtc_state)
4372{
4373 intel_ddi_get_clock(encoder, crtc_state, pll: skl_ddi_get_pll(encoder));
4374 intel_ddi_get_config(encoder, pipe_config: crtc_state);
4375}
4376
4377void hsw_ddi_get_config(struct intel_encoder *encoder,
4378 struct intel_crtc_state *crtc_state)
4379{
4380 intel_ddi_get_clock(encoder, crtc_state, pll: hsw_ddi_get_pll(encoder));
4381 intel_ddi_get_config(encoder, pipe_config: crtc_state);
4382}
4383
4384static void intel_ddi_sync_state(struct intel_encoder *encoder,
4385 const struct intel_crtc_state *crtc_state)
4386{
4387 if (intel_encoder_is_tc(encoder))
4388 intel_tc_port_sanitize_mode(dig_port: enc_to_dig_port(encoder),
4389 crtc_state);
4390
4391 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) ||
4392 (!crtc_state && intel_encoder_is_dp(encoder)))
4393 intel_dp_sync_state(encoder, crtc_state);
4394}
4395
4396static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
4397 struct intel_crtc_state *crtc_state)
4398{
4399 struct intel_display *display = to_intel_display(encoder);
4400 bool fastset = true;
4401
4402 if (intel_encoder_is_tc(encoder)) {
4403 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
4404 encoder->base.base.id, encoder->base.name);
4405 crtc_state->uapi.mode_changed = true;
4406 fastset = false;
4407 }
4408
4409 if (intel_crtc_has_dp_encoder(crtc_state) &&
4410 !intel_dp_initial_fastset_check(encoder, crtc_state))
4411 fastset = false;
4412
4413 return fastset;
4414}
4415
4416static enum intel_output_type
4417intel_ddi_compute_output_type(struct intel_encoder *encoder,
4418 struct intel_crtc_state *crtc_state,
4419 struct drm_connector_state *conn_state)
4420{
4421 switch (conn_state->connector->connector_type) {
4422 case DRM_MODE_CONNECTOR_HDMIA:
4423 return INTEL_OUTPUT_HDMI;
4424 case DRM_MODE_CONNECTOR_eDP:
4425 return INTEL_OUTPUT_EDP;
4426 case DRM_MODE_CONNECTOR_DisplayPort:
4427 return INTEL_OUTPUT_DP;
4428 default:
4429 MISSING_CASE(conn_state->connector->connector_type);
4430 return INTEL_OUTPUT_UNUSED;
4431 }
4432}
4433
4434static int intel_ddi_compute_config(struct intel_encoder *encoder,
4435 struct intel_crtc_state *pipe_config,
4436 struct drm_connector_state *conn_state)
4437{
4438 struct intel_display *display = to_intel_display(encoder);
4439 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4440 enum port port = encoder->port;
4441 int ret;
4442
4443 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)
4444 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4445
4446 if (intel_crtc_has_type(crtc_state: pipe_config, type: INTEL_OUTPUT_HDMI)) {
4447 pipe_config->has_hdmi_sink =
4448 intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state: pipe_config, conn_state);
4449
4450 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4451 } else {
4452 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4453 }
4454
4455 if (ret)
4456 return ret;
4457
4458 if (display->platform.haswell && crtc->pipe == PIPE_A &&
4459 pipe_config->cpu_transcoder == TRANSCODER_EDP)
4460 pipe_config->pch_pfit.force_thru =
4461 pipe_config->pch_pfit.enabled ||
4462 pipe_config->crc_enabled;
4463
4464 if (display->platform.geminilake || display->platform.broxton)
4465 pipe_config->lane_lat_optim_mask =
4466 bxt_dpio_phy_calc_lane_lat_optim_mask(lane_count: pipe_config->lane_count);
4467
4468 intel_ddi_compute_min_voltage_level(crtc_state: pipe_config);
4469
4470 return 0;
4471}
4472
4473static bool mode_equal(const struct drm_display_mode *mode1,
4474 const struct drm_display_mode *mode2)
4475{
4476 return drm_mode_match(mode1, mode2,
4477 DRM_MODE_MATCH_TIMINGS |
4478 DRM_MODE_MATCH_FLAGS |
4479 DRM_MODE_MATCH_3D_FLAGS) &&
4480 mode1->clock == mode2->clock; /* we want an exact match */
4481}
4482
4483static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4484 const struct intel_link_m_n *m_n_2)
4485{
4486 return m_n_1->tu == m_n_2->tu &&
4487 m_n_1->data_m == m_n_2->data_m &&
4488 m_n_1->data_n == m_n_2->data_n &&
4489 m_n_1->link_m == m_n_2->link_m &&
4490 m_n_1->link_n == m_n_2->link_n;
4491}
4492
4493static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4494 const struct intel_crtc_state *crtc_state2)
4495{
4496 /*
4497 * FIXME the modeset sequence is currently wrong and
4498 * can't deal with joiner + port sync at the same time.
4499 */
4500 return crtc_state1->hw.active && crtc_state2->hw.active &&
4501 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes &&
4502 crtc_state1->output_types == crtc_state2->output_types &&
4503 crtc_state1->output_format == crtc_state2->output_format &&
4504 crtc_state1->lane_count == crtc_state2->lane_count &&
4505 crtc_state1->port_clock == crtc_state2->port_clock &&
4506 mode_equal(mode1: &crtc_state1->hw.adjusted_mode,
4507 mode2: &crtc_state2->hw.adjusted_mode) &&
4508 m_n_equal(m_n_1: &crtc_state1->dp_m_n, m_n_2: &crtc_state2->dp_m_n);
4509}
4510
4511static u8
4512intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4513 int tile_group_id)
4514{
4515 struct intel_display *display = to_intel_display(ref_crtc_state);
4516 struct drm_connector *connector;
4517 const struct drm_connector_state *conn_state;
4518 struct intel_atomic_state *state =
4519 to_intel_atomic_state(ref_crtc_state->uapi.state);
4520 u8 transcoders = 0;
4521 int i;
4522
4523 /*
4524 * We don't enable port sync on BDW due to missing w/as and
4525 * due to not having adjusted the modeset sequence appropriately.
4526 */
4527 if (DISPLAY_VER(display) < 9)
4528 return 0;
4529
4530 if (!intel_crtc_has_type(crtc_state: ref_crtc_state, type: INTEL_OUTPUT_DP))
4531 return 0;
4532
4533 for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4534 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4535 const struct intel_crtc_state *crtc_state;
4536
4537 if (!crtc)
4538 continue;
4539
4540 if (!connector->has_tile ||
4541 connector->tile_group->id !=
4542 tile_group_id)
4543 continue;
4544 crtc_state = intel_atomic_get_new_crtc_state(state,
4545 crtc);
4546 if (!crtcs_port_sync_compatible(crtc_state1: ref_crtc_state,
4547 crtc_state2: crtc_state))
4548 continue;
4549 transcoders |= BIT(crtc_state->cpu_transcoder);
4550 }
4551
4552 return transcoders;
4553}
4554
4555static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4556 struct intel_crtc_state *crtc_state,
4557 struct drm_connector_state *conn_state)
4558{
4559 struct intel_display *display = to_intel_display(encoder);
4560 struct drm_connector *connector = conn_state->connector;
4561 u8 port_sync_transcoders = 0;
4562
4563 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
4564 encoder->base.base.id, encoder->base.name,
4565 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4566
4567 if (connector->has_tile)
4568 port_sync_transcoders = intel_ddi_port_sync_transcoders(ref_crtc_state: crtc_state,
4569 tile_group_id: connector->tile_group->id);
4570
4571 /*
4572 * EDP Transcoders cannot be ensalved
4573 * make them a master always when present
4574 */
4575 if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4576 crtc_state->master_transcoder = TRANSCODER_EDP;
4577 else
4578 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4579
4580 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4581 crtc_state->master_transcoder = INVALID_TRANSCODER;
4582 crtc_state->sync_mode_slaves_mask =
4583 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4584 }
4585
4586 return 0;
4587}
4588
4589static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4590{
4591 struct intel_display *display = to_intel_display(encoder->dev);
4592 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4593
4594 intel_dp_encoder_flush_work(encoder);
4595 if (intel_encoder_is_tc(encoder: &dig_port->base))
4596 intel_tc_port_cleanup(dig_port);
4597 intel_display_power_flush_work(display);
4598
4599 drm_encoder_cleanup(encoder);
4600 kfree(objp: dig_port->hdcp.port_data.streams);
4601 kfree(objp: dig_port);
4602}
4603
4604static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
4605{
4606 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
4607 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4608
4609 intel_dp->reset_link_params = true;
4610 intel_dp_invalidate_source_oui(intel_dp);
4611
4612 intel_pps_encoder_reset(intel_dp);
4613
4614 if (intel_encoder_is_tc(encoder: &dig_port->base))
4615 intel_tc_port_init_mode(dig_port);
4616}
4617
4618static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder)
4619{
4620 struct intel_encoder *encoder = to_intel_encoder(_encoder);
4621
4622 intel_tc_port_link_reset(dig_port: enc_to_dig_port(encoder));
4623
4624 return 0;
4625}
4626
4627static const struct drm_encoder_funcs intel_ddi_funcs = {
4628 .reset = intel_ddi_encoder_reset,
4629 .destroy = intel_ddi_encoder_destroy,
4630 .late_register = intel_ddi_encoder_late_register,
4631};
4632
4633static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4634{
4635 struct intel_display *display = to_intel_display(dig_port);
4636 struct intel_connector *connector;
4637 enum port port = dig_port->base.port;
4638
4639 connector = intel_connector_alloc();
4640 if (!connector)
4641 return -ENOMEM;
4642
4643 dig_port->dp.output_reg = DDI_BUF_CTL(port);
4644 if (DISPLAY_VER(display) >= 14)
4645 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain;
4646 else
4647 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4648 dig_port->dp.set_link_train = intel_ddi_set_link_train;
4649 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4650
4651 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4652 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4653
4654 if (!intel_dp_init_connector(dig_port, intel_connector: connector)) {
4655 kfree(objp: connector);
4656 return -EINVAL;
4657 }
4658
4659 if (dig_port->base.type == INTEL_OUTPUT_EDP) {
4660 struct drm_privacy_screen *privacy_screen;
4661
4662 privacy_screen = drm_privacy_screen_get(dev: display->drm->dev, NULL);
4663 if (!IS_ERR(ptr: privacy_screen)) {
4664 drm_connector_attach_privacy_screen_provider(connector: &connector->base,
4665 priv: privacy_screen);
4666 } else if (PTR_ERR(ptr: privacy_screen) != -ENODEV) {
4667 drm_warn(display->drm, "Error getting privacy-screen\n");
4668 }
4669 }
4670
4671 return 0;
4672}
4673
4674static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4675 struct drm_modeset_acquire_ctx *ctx)
4676{
4677 struct intel_display *display = to_intel_display(encoder);
4678 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4679 struct intel_connector *connector = hdmi->attached_connector;
4680 struct i2c_adapter *ddc = connector->base.ddc;
4681 struct drm_connector_state *conn_state;
4682 struct intel_crtc_state *crtc_state;
4683 struct intel_crtc *crtc;
4684 u8 config;
4685 int ret;
4686
4687 if (connector->base.status != connector_status_connected)
4688 return 0;
4689
4690 ret = drm_modeset_lock(lock: &display->drm->mode_config.connection_mutex,
4691 ctx);
4692 if (ret)
4693 return ret;
4694
4695 conn_state = connector->base.state;
4696
4697 crtc = to_intel_crtc(conn_state->crtc);
4698 if (!crtc)
4699 return 0;
4700
4701 ret = drm_modeset_lock(lock: &crtc->base.mutex, ctx);
4702 if (ret)
4703 return ret;
4704
4705 crtc_state = to_intel_crtc_state(crtc->base.state);
4706
4707 drm_WARN_ON(display->drm,
4708 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4709
4710 if (!crtc_state->hw.active)
4711 return 0;
4712
4713 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4714 !crtc_state->hdmi_scrambling)
4715 return 0;
4716
4717 if (conn_state->commit &&
4718 !try_wait_for_completion(x: &conn_state->commit->hw_done))
4719 return 0;
4720
4721 ret = drm_scdc_readb(adapter: ddc, SCDC_TMDS_CONFIG, value: &config);
4722 if (ret < 0) {
4723 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
4724 connector->base.base.id, connector->base.name, ret);
4725 return 0;
4726 }
4727
4728 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4729 crtc_state->hdmi_high_tmds_clock_ratio &&
4730 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4731 crtc_state->hdmi_scrambling)
4732 return 0;
4733
4734 /*
4735 * HDMI 2.0 says that one should not send scrambled data
4736 * prior to configuring the sink scrambling, and that
4737 * TMDS clock/data transmission should be suspended when
4738 * changing the TMDS clock rate in the sink. So let's
4739 * just do a full modeset here, even though some sinks
4740 * would be perfectly happy if were to just reconfigure
4741 * the SCDC settings on the fly.
4742 */
4743 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx);
4744}
4745
4746static void intel_ddi_link_check(struct intel_encoder *encoder)
4747{
4748 struct intel_display *display = to_intel_display(encoder);
4749 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4750
4751 /* TODO: Move checking the HDMI link state here as well. */
4752 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector);
4753
4754 intel_dp_link_check(encoder);
4755}
4756
4757static enum intel_hotplug_state
4758intel_ddi_hotplug(struct intel_encoder *encoder,
4759 struct intel_connector *connector)
4760{
4761 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4762 struct intel_dp *intel_dp = &dig_port->dp;
4763 bool is_tc = intel_encoder_is_tc(encoder);
4764 struct drm_modeset_acquire_ctx ctx;
4765 enum intel_hotplug_state state;
4766 int ret;
4767
4768 if (intel_dp_test_phy(intel_dp))
4769 return INTEL_HOTPLUG_UNCHANGED;
4770
4771 state = intel_encoder_hotplug(encoder, connector);
4772
4773 if (!intel_tc_port_link_reset(dig_port)) {
4774 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
4775 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
4776 ret = intel_hdmi_reset_link(encoder, ctx: &ctx);
4777 drm_WARN_ON(encoder->base.dev, ret);
4778 } else {
4779 intel_dp_check_link_state(intel_dp);
4780 }
4781 }
4782
4783 /*
4784 * Unpowered type-c dongles can take some time to boot and be
4785 * responsible, so here giving some time to those dongles to power up
4786 * and then retrying the probe.
4787 *
4788 * On many platforms the HDMI live state signal is known to be
4789 * unreliable, so we can't use it to detect if a sink is connected or
4790 * not. Instead we detect if it's connected based on whether we can
4791 * read the EDID or not. That in turn has a problem during disconnect,
4792 * since the HPD interrupt may be raised before the DDC lines get
4793 * disconnected (due to how the required length of DDC vs. HPD
4794 * connector pins are specified) and so we'll still be able to get a
4795 * valid EDID. To solve this schedule another detection cycle if this
4796 * time around we didn't detect any change in the sink's connection
4797 * status.
4798 *
4799 * Type-c connectors which get their HPD signal deasserted then
4800 * reasserted, without unplugging/replugging the sink from the
4801 * connector, introduce a delay until the AUX channel communication
4802 * becomes functional. Retry the detection for 5 seconds on type-c
4803 * connectors to account for this delay.
4804 */
4805 if (state == INTEL_HOTPLUG_UNCHANGED &&
4806 connector->hotplug_retries < (is_tc ? 5 : 1) &&
4807 !dig_port->dp.is_mst)
4808 state = INTEL_HOTPLUG_RETRY;
4809
4810 return state;
4811}
4812
4813static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4814{
4815 struct intel_display *display = to_intel_display(encoder);
4816 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
4817
4818 return intel_de_read(display, SDEISR) & bit;
4819}
4820
4821static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4822{
4823 struct intel_display *display = to_intel_display(encoder);
4824 u32 bit = display->hotplug.hpd[encoder->hpd_pin];
4825
4826 return intel_de_read(display, DEISR) & bit;
4827}
4828
4829static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4830{
4831 struct intel_display *display = to_intel_display(encoder);
4832 u32 bit = display->hotplug.hpd[encoder->hpd_pin];
4833
4834 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit;
4835}
4836
4837static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4838{
4839 struct intel_connector *connector;
4840 enum port port = dig_port->base.port;
4841
4842 connector = intel_connector_alloc();
4843 if (!connector)
4844 return -ENOMEM;
4845
4846 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4847
4848 if (!intel_hdmi_init_connector(dig_port, intel_connector: connector)) {
4849 /*
4850 * HDMI connector init failures may just mean conflicting DDC
4851 * pins or not having enough lanes. Handle them gracefully, but
4852 * don't fail the entire DDI init.
4853 */
4854 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG;
4855 kfree(objp: connector);
4856 }
4857
4858 return 0;
4859}
4860
4861static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4862{
4863 struct intel_display *display = to_intel_display(dig_port);
4864
4865 if (dig_port->base.port != PORT_A)
4866 return false;
4867
4868 if (dig_port->ddi_a_4_lanes)
4869 return false;
4870
4871 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4872 * supported configuration
4873 */
4874 if (display->platform.geminilake || display->platform.broxton)
4875 return true;
4876
4877 return false;
4878}
4879
4880static int
4881intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4882{
4883 struct intel_display *display = to_intel_display(dig_port);
4884 enum port port = dig_port->base.port;
4885 int max_lanes = 4;
4886
4887 if (DISPLAY_VER(display) >= 11)
4888 return max_lanes;
4889
4890 if (port == PORT_A || port == PORT_E) {
4891 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4892 max_lanes = port == PORT_A ? 4 : 0;
4893 else
4894 /* Both A and E share 2 lanes */
4895 max_lanes = 2;
4896 }
4897
4898 /*
4899 * Some BIOS might fail to set this bit on port A if eDP
4900 * wasn't lit up at boot. Force this bit set when needed
4901 * so we use the proper lane count for our calculations.
4902 */
4903 if (intel_ddi_a_force_4_lanes(dig_port)) {
4904 drm_dbg_kms(display->drm,
4905 "Forcing DDI_A_4_LANES for port A\n");
4906 dig_port->ddi_a_4_lanes = true;
4907 max_lanes = 4;
4908 }
4909
4910 return max_lanes;
4911}
4912
4913static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port)
4914{
4915 if (port >= PORT_D_XELPD)
4916 return HPD_PORT_D + port - PORT_D_XELPD;
4917 else if (port >= PORT_TC1)
4918 return HPD_PORT_TC1 + port - PORT_TC1;
4919 else
4920 return HPD_PORT_A + port - PORT_A;
4921}
4922
4923static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port)
4924{
4925 if (port >= PORT_TC1)
4926 return HPD_PORT_C + port - PORT_TC1;
4927 else
4928 return HPD_PORT_A + port - PORT_A;
4929}
4930
4931static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port)
4932{
4933 if (port >= PORT_TC1)
4934 return HPD_PORT_TC1 + port - PORT_TC1;
4935 else
4936 return HPD_PORT_A + port - PORT_A;
4937}
4938
4939static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port)
4940{
4941 if (HAS_PCH_TGP(display))
4942 return tgl_hpd_pin(display, port);
4943
4944 if (port >= PORT_TC1)
4945 return HPD_PORT_C + port - PORT_TC1;
4946 else
4947 return HPD_PORT_A + port - PORT_A;
4948}
4949
4950static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port)
4951{
4952 if (port >= PORT_C)
4953 return HPD_PORT_TC1 + port - PORT_C;
4954 else
4955 return HPD_PORT_A + port - PORT_A;
4956}
4957
4958static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port)
4959{
4960 if (port == PORT_D)
4961 return HPD_PORT_A;
4962
4963 if (HAS_PCH_TGP(display))
4964 return icl_hpd_pin(display, port);
4965
4966 return HPD_PORT_A + port - PORT_A;
4967}
4968
4969static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port)
4970{
4971 if (HAS_PCH_TGP(display))
4972 return icl_hpd_pin(display, port);
4973
4974 return HPD_PORT_A + port - PORT_A;
4975}
4976
4977static bool intel_ddi_is_tc(struct intel_display *display, enum port port)
4978{
4979 if (DISPLAY_VER(display) >= 12)
4980 return port >= PORT_TC1;
4981 else if (DISPLAY_VER(display) >= 11)
4982 return port >= PORT_C;
4983 else
4984 return false;
4985}
4986
4987static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4988{
4989 intel_dp_encoder_suspend(intel_encoder: encoder);
4990}
4991
4992static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder)
4993{
4994 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4995 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4996
4997 /*
4998 * TODO: Move this to intel_dp_encoder_suspend(),
4999 * once modeset locking around that is removed.
5000 */
5001 intel_encoder_link_check_flush_work(encoder);
5002 intel_tc_port_suspend(dig_port);
5003}
5004
5005static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
5006{
5007 if (intel_encoder_is_dp(encoder))
5008 intel_dp_encoder_shutdown(intel_encoder: encoder);
5009 if (intel_encoder_is_hdmi(encoder))
5010 intel_hdmi_encoder_shutdown(encoder);
5011}
5012
5013static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder)
5014{
5015 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5016 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5017
5018 intel_tc_port_cleanup(dig_port);
5019}
5020
5021#define port_tc_name(port) ((port) - PORT_TC1 + '1')
5022#define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
5023
5024static bool port_strap_detected(struct intel_display *display, enum port port)
5025{
5026 /* straps not used on skl+ */
5027 if (DISPLAY_VER(display) >= 9)
5028 return true;
5029
5030 switch (port) {
5031 case PORT_A:
5032 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
5033 case PORT_B:
5034 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;
5035 case PORT_C:
5036 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;
5037 case PORT_D:
5038 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;
5039 case PORT_E:
5040 return true; /* no strap for DDI-E */
5041 default:
5042 MISSING_CASE(port);
5043 return false;
5044 }
5045}
5046
5047static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp)
5048{
5049 return init_dp || intel_encoder_is_tc(encoder);
5050}
5051
5052static bool assert_has_icl_dsi(struct intel_display *display)
5053{
5054 return !drm_WARN(display->drm, !display->platform.alderlake_p &&
5055 !display->platform.tigerlake && DISPLAY_VER(display) != 11,
5056 "Platform does not support DSI\n");
5057}
5058
5059static bool port_in_use(struct intel_display *display, enum port port)
5060{
5061 struct intel_encoder *encoder;
5062
5063 for_each_intel_encoder(display->drm, encoder) {
5064 /* FIXME what about second port for dual link DSI? */
5065 if (encoder->port == port)
5066 return true;
5067 }
5068
5069 return false;
5070}
5071
5072static const char *intel_ddi_encoder_name(struct intel_display *display,
5073 enum port port, enum phy phy,
5074 struct seq_buf *s)
5075{
5076 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) {
5077 seq_buf_printf(s, fmt: "DDI %c/PHY %c",
5078 port_name(port - PORT_D_XELPD + PORT_D),
5079 phy_name(phy));
5080 } else if (DISPLAY_VER(display) >= 12) {
5081 enum tc_port tc_port = intel_port_to_tc(display, port);
5082
5083 seq_buf_printf(s, fmt: "DDI %s%c/PHY %s%c",
5084 port >= PORT_TC1 ? "TC" : "",
5085 port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
5086 tc_port != TC_PORT_NONE ? "TC" : "",
5087 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5088 } else if (DISPLAY_VER(display) >= 11) {
5089 enum tc_port tc_port = intel_port_to_tc(display, port);
5090
5091 seq_buf_printf(s, fmt: "DDI %c%s/PHY %s%c",
5092 port_name(port),
5093 port >= PORT_C ? " (TC)" : "",
5094 tc_port != TC_PORT_NONE ? "TC" : "",
5095 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5096 } else {
5097 seq_buf_printf(s, fmt: "DDI %c/PHY %c", port_name(port), phy_name(phy));
5098 }
5099
5100 drm_WARN_ON(display->drm, seq_buf_has_overflowed(s));
5101
5102 return seq_buf_str(s);
5103}
5104
5105void intel_ddi_init(struct intel_display *display,
5106 const struct intel_bios_encoder_data *devdata)
5107{
5108 struct intel_digital_port *dig_port;
5109 struct intel_encoder *encoder;
5110 DECLARE_SEQ_BUF(encoder_name, 20);
5111 bool init_hdmi, init_dp;
5112 enum port port;
5113 enum phy phy;
5114 u32 ddi_buf_ctl;
5115
5116 port = intel_bios_encoder_port(devdata);
5117 if (port == PORT_NONE)
5118 return;
5119
5120 if (!port_strap_detected(display, port)) {
5121 drm_dbg_kms(display->drm,
5122 "Port %c strap not detected\n", port_name(port));
5123 return;
5124 }
5125
5126 if (!assert_port_valid(display, port))
5127 return;
5128
5129 if (port_in_use(display, port)) {
5130 drm_dbg_kms(display->drm,
5131 "Port %c already claimed\n", port_name(port));
5132 return;
5133 }
5134
5135 if (intel_bios_encoder_supports_dsi(devdata)) {
5136 /* BXT/GLK handled elsewhere, for now at least */
5137 if (!assert_has_icl_dsi(display))
5138 return;
5139
5140 icl_dsi_init(display, devdata);
5141 return;
5142 }
5143
5144 phy = intel_port_to_phy(display, port);
5145
5146 /*
5147 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
5148 * have taken over some of the PHYs and made them unavailable to the
5149 * driver. In that case we should skip initializing the corresponding
5150 * outputs.
5151 */
5152 if (intel_hti_uses_phy(display, phy)) {
5153 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n",
5154 port_name(port), phy_name(phy));
5155 return;
5156 }
5157
5158 init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
5159 intel_bios_encoder_supports_hdmi(devdata);
5160 init_dp = intel_bios_encoder_supports_dp(devdata);
5161
5162 if (intel_bios_encoder_is_lspcon(devdata)) {
5163 /*
5164 * Lspcon device needs to be driven with DP connector
5165 * with special detection sequence. So make sure DP
5166 * is initialized before lspcon.
5167 */
5168 init_dp = true;
5169 init_hdmi = false;
5170 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n",
5171 port_name(port));
5172 }
5173
5174 if (!init_dp && !init_hdmi) {
5175 drm_dbg_kms(display->drm,
5176 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
5177 port_name(port));
5178 return;
5179 }
5180
5181 if (intel_phy_is_snps(display, phy) &&
5182 display->snps.phy_failed_calibration & BIT(phy)) {
5183 drm_dbg_kms(display->drm,
5184 "SNPS PHY %c failed to calibrate, proceeding anyway\n",
5185 phy_name(phy));
5186 }
5187
5188 dig_port = intel_dig_port_alloc();
5189 if (!dig_port)
5190 return;
5191
5192 encoder = &dig_port->base;
5193 encoder->devdata = devdata;
5194
5195 drm_encoder_init(dev: display->drm, encoder: &encoder->base, funcs: &intel_ddi_funcs,
5196 DRM_MODE_ENCODER_TMDS, name: "%s",
5197 intel_ddi_encoder_name(display, port, phy, s: &encoder_name));
5198
5199 intel_encoder_link_check_init(encoder, callback: intel_ddi_link_check);
5200
5201 encoder->hotplug = intel_ddi_hotplug;
5202 encoder->compute_output_type = intel_ddi_compute_output_type;
5203 encoder->compute_config = intel_ddi_compute_config;
5204 encoder->compute_config_late = intel_ddi_compute_config_late;
5205 encoder->enable = intel_ddi_enable;
5206 encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
5207 encoder->pre_enable = intel_ddi_pre_enable;
5208 encoder->disable = intel_ddi_disable;
5209 encoder->post_pll_disable = intel_ddi_post_pll_disable;
5210 encoder->post_disable = intel_ddi_post_disable;
5211 encoder->update_pipe = intel_ddi_update_pipe;
5212 encoder->audio_enable = intel_audio_codec_enable;
5213 encoder->audio_disable = intel_audio_codec_disable;
5214 encoder->get_hw_state = intel_ddi_get_hw_state;
5215 encoder->sync_state = intel_ddi_sync_state;
5216 encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
5217 encoder->suspend = intel_ddi_encoder_suspend;
5218 encoder->shutdown = intel_ddi_encoder_shutdown;
5219 encoder->get_power_domains = intel_ddi_get_power_domains;
5220
5221 encoder->type = INTEL_OUTPUT_DDI;
5222 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
5223 encoder->port = port;
5224 encoder->cloneable = 0;
5225 encoder->pipe_mask = ~0;
5226
5227 if (DISPLAY_VER(display) >= 14) {
5228 encoder->enable_clock = intel_mtl_pll_enable;
5229 encoder->disable_clock = intel_mtl_pll_disable;
5230 encoder->port_pll_type = intel_mtl_port_pll_type;
5231 encoder->get_config = mtl_ddi_get_config;
5232 } else if (display->platform.dg2) {
5233 encoder->enable_clock = intel_mpllb_enable;
5234 encoder->disable_clock = intel_mpllb_disable;
5235 encoder->get_config = dg2_ddi_get_config;
5236 } else if (display->platform.alderlake_s) {
5237 encoder->enable_clock = adls_ddi_enable_clock;
5238 encoder->disable_clock = adls_ddi_disable_clock;
5239 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
5240 encoder->get_config = adls_ddi_get_config;
5241 } else if (display->platform.rocketlake) {
5242 encoder->enable_clock = rkl_ddi_enable_clock;
5243 encoder->disable_clock = rkl_ddi_disable_clock;
5244 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
5245 encoder->get_config = rkl_ddi_get_config;
5246 } else if (display->platform.dg1) {
5247 encoder->enable_clock = dg1_ddi_enable_clock;
5248 encoder->disable_clock = dg1_ddi_disable_clock;
5249 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
5250 encoder->get_config = dg1_ddi_get_config;
5251 } else if (display->platform.jasperlake || display->platform.elkhartlake) {
5252 if (intel_ddi_is_tc(display, port)) {
5253 encoder->enable_clock = jsl_ddi_tc_enable_clock;
5254 encoder->disable_clock = jsl_ddi_tc_disable_clock;
5255 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
5256 encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5257 encoder->get_config = icl_ddi_combo_get_config;
5258 } else {
5259 encoder->enable_clock = icl_ddi_combo_enable_clock;
5260 encoder->disable_clock = icl_ddi_combo_disable_clock;
5261 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
5262 encoder->get_config = icl_ddi_combo_get_config;
5263 }
5264 } else if (DISPLAY_VER(display) >= 11) {
5265 if (intel_ddi_is_tc(display, port)) {
5266 encoder->enable_clock = icl_ddi_tc_enable_clock;
5267 encoder->disable_clock = icl_ddi_tc_disable_clock;
5268 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
5269 encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5270 encoder->get_config = icl_ddi_tc_get_config;
5271 } else {
5272 encoder->enable_clock = icl_ddi_combo_enable_clock;
5273 encoder->disable_clock = icl_ddi_combo_disable_clock;
5274 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
5275 encoder->get_config = icl_ddi_combo_get_config;
5276 }
5277 } else if (display->platform.geminilake || display->platform.broxton) {
5278 /* BXT/GLK have fixed PLL->port mapping */
5279 encoder->get_config = bxt_ddi_get_config;
5280 } else if (DISPLAY_VER(display) == 9) {
5281 encoder->enable_clock = skl_ddi_enable_clock;
5282 encoder->disable_clock = skl_ddi_disable_clock;
5283 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
5284 encoder->get_config = skl_ddi_get_config;
5285 } else if (display->platform.broadwell || display->platform.haswell) {
5286 encoder->enable_clock = hsw_ddi_enable_clock;
5287 encoder->disable_clock = hsw_ddi_disable_clock;
5288 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
5289 encoder->get_config = hsw_ddi_get_config;
5290 }
5291
5292 if (DISPLAY_VER(display) >= 14) {
5293 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
5294 } else if (display->platform.dg2) {
5295 encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
5296 } else if (DISPLAY_VER(display) >= 12) {
5297 if (intel_encoder_is_combo(encoder))
5298 encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
5299 else
5300 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
5301 } else if (DISPLAY_VER(display) >= 11) {
5302 if (intel_encoder_is_combo(encoder))
5303 encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
5304 else
5305 encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
5306 } else if (display->platform.geminilake || display->platform.broxton) {
5307 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels;
5308 } else {
5309 encoder->set_signal_levels = hsw_set_signal_levels;
5310 }
5311
5312 intel_ddi_buf_trans_init(encoder);
5313
5314 if (DISPLAY_VER(display) >= 13)
5315 encoder->hpd_pin = xelpd_hpd_pin(display, port);
5316 else if (display->platform.dg1)
5317 encoder->hpd_pin = dg1_hpd_pin(display, port);
5318 else if (display->platform.rocketlake)
5319 encoder->hpd_pin = rkl_hpd_pin(display, port);
5320 else if (DISPLAY_VER(display) >= 12)
5321 encoder->hpd_pin = tgl_hpd_pin(display, port);
5322 else if (display->platform.jasperlake || display->platform.elkhartlake)
5323 encoder->hpd_pin = ehl_hpd_pin(display, port);
5324 else if (DISPLAY_VER(display) == 11)
5325 encoder->hpd_pin = icl_hpd_pin(display, port);
5326 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton)
5327 encoder->hpd_pin = skl_hpd_pin(display, port);
5328 else
5329 encoder->hpd_pin = intel_hpd_pin_default(port);
5330
5331 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port));
5332
5333 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) ||
5334 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL;
5335
5336 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES;
5337
5338 dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
5339
5340 if (need_aux_ch(encoder, init_dp)) {
5341 dig_port->aux_ch = intel_dp_aux_ch(encoder);
5342 if (dig_port->aux_ch == AUX_CH_NONE)
5343 goto err;
5344 }
5345
5346 if (intel_encoder_is_tc(encoder)) {
5347 bool is_legacy =
5348 !intel_bios_encoder_supports_typec_usb(devdata) &&
5349 !intel_bios_encoder_supports_tbt(devdata);
5350
5351 if (!is_legacy && init_hdmi) {
5352 is_legacy = !init_dp;
5353
5354 drm_dbg_kms(display->drm,
5355 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n",
5356 port_name(port),
5357 str_yes_no(init_dp),
5358 is_legacy ? "legacy" : "non-legacy");
5359 }
5360
5361 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete;
5362 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete;
5363
5364 dig_port->lock = intel_tc_port_lock;
5365 dig_port->unlock = intel_tc_port_unlock;
5366
5367 if (intel_tc_port_init(dig_port, is_legacy) < 0)
5368 goto err;
5369 }
5370
5371 drm_WARN_ON(display->drm, port > PORT_I);
5372 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port);
5373
5374 if (DISPLAY_VER(display) >= 11) {
5375 if (intel_encoder_is_tc(encoder))
5376 dig_port->connected = intel_tc_port_connected;
5377 else
5378 dig_port->connected = lpt_digital_port_connected;
5379 } else if (display->platform.geminilake || display->platform.broxton) {
5380 dig_port->connected = bdw_digital_port_connected;
5381 } else if (DISPLAY_VER(display) == 9) {
5382 dig_port->connected = lpt_digital_port_connected;
5383 } else if (display->platform.broadwell) {
5384 if (port == PORT_A)
5385 dig_port->connected = bdw_digital_port_connected;
5386 else
5387 dig_port->connected = lpt_digital_port_connected;
5388 } else if (display->platform.haswell) {
5389 if (port == PORT_A)
5390 dig_port->connected = hsw_digital_port_connected;
5391 else
5392 dig_port->connected = lpt_digital_port_connected;
5393 }
5394
5395 intel_infoframe_init(dig_port);
5396
5397 if (init_dp) {
5398 if (intel_ddi_init_dp_connector(dig_port))
5399 goto err;
5400
5401 dig_port->hpd_pulse = intel_dp_hpd_pulse;
5402
5403 if (dig_port->dp.mso_link_count)
5404 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display);
5405 }
5406
5407 /*
5408 * In theory we don't need the encoder->type check,
5409 * but leave it just in case we have some really bad VBTs...
5410 */
5411 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5412 if (intel_ddi_init_hdmi_connector(dig_port))
5413 goto err;
5414 }
5415
5416 return;
5417
5418err:
5419 drm_encoder_cleanup(encoder: &encoder->base);
5420 kfree(objp: dig_port);
5421}
5422