1/*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/debugfs.h>
25#include <linux/iopoll.h>
26#include <linux/time.h>
27
28#include <drm/drm_fixed.h>
29
30#include "soc/intel_dram.h"
31
32#include "hsw_ips.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "i915_utils.h"
36#include "intel_atomic.h"
37#include "intel_audio.h"
38#include "intel_bw.h"
39#include "intel_cdclk.h"
40#include "intel_crtc.h"
41#include "intel_de.h"
42#include "intel_display_regs.h"
43#include "intel_display_types.h"
44#include "intel_mchbar_regs.h"
45#include "intel_pci_config.h"
46#include "intel_pcode.h"
47#include "intel_plane.h"
48#include "intel_psr.h"
49#include "intel_vdsc.h"
50#include "skl_watermark.h"
51#include "skl_watermark_regs.h"
52#include "vlv_dsi.h"
53#include "vlv_sideband.h"
54
55/**
56 * DOC: CDCLK / RAWCLK
57 *
58 * The display engine uses several different clocks to do its work. There
59 * are two main clocks involved that aren't directly related to the actual
60 * pixel clock or any symbol/bit clock of the actual output port. These
61 * are the core display clock (CDCLK) and RAWCLK.
62 *
63 * CDCLK clocks most of the display pipe logic, and thus its frequency
64 * must be high enough to support the rate at which pixels are flowing
65 * through the pipes. Downscaling must also be accounted as that increases
66 * the effective pixel rate.
67 *
68 * On several platforms the CDCLK frequency can be changed dynamically
69 * to minimize power consumption for a given display configuration.
70 * Typically changes to the CDCLK frequency require all the display pipes
71 * to be shut down while the frequency is being changed.
72 *
73 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
74 * DMC will not change the active CDCLK frequency however, so that part
75 * will still be performed by the driver directly.
76 *
77 * There are multiple components involved in the generation of the CDCLK
78 * frequency:
79 *
80 * - We have the CDCLK PLL, which generates an output clock based on a
81 * reference clock and a ratio parameter.
82 * - The CD2X Divider, which divides the output of the PLL based on a
83 * divisor selected from a set of pre-defined choices.
84 * - The CD2X Squasher, which further divides the output based on a
85 * waveform represented as a sequence of bits where each zero
86 * "squashes out" a clock cycle.
87 * - And, finally, a fixed divider that divides the output frequency by 2.
88 *
89 * As such, the resulting CDCLK frequency can be calculated with the
90 * following formula:
91 *
92 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
93 *
94 * , where vco is the frequency generated by the PLL; cd2x_div
95 * represents the CD2X Divider; sq_len and sq_div are the bit length
96 * and the number of high bits for the CD2X Squasher waveform, respectively;
97 * and 2 represents the fixed divider.
98 *
99 * Note that some older platforms do not contain the CD2X Divider
100 * and/or CD2X Squasher, in which case we can ignore their respective
101 * factors in the formula above.
102 *
103 * Several methods exist to change the CDCLK frequency, which ones are
104 * supported depends on the platform:
105 *
106 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
107 * - CD2X divider update. Single pipe can be active as the divider update
108 * can be synchronized with the pipe's start of vblank.
109 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
110 * - Squash waveform update. Pipes can be active.
111 * - Crawl and squash can also be done back to back. Pipes can be active.
112 *
113 * RAWCLK is a fixed frequency clock, often used by various auxiliary
114 * blocks such as AUX CH or backlight PWM. Hence the only thing we
115 * really need to know about RAWCLK is its frequency so that various
116 * dividers can be programmed correctly.
117 */
118
119struct intel_cdclk_state {
120 struct intel_global_state base;
121
122 /*
123 * Logical configuration of cdclk (used for all scaling,
124 * watermark, etc. calculations and checks). This is
125 * computed as if all enabled crtcs were active.
126 */
127 struct intel_cdclk_config logical;
128
129 /*
130 * Actual configuration of cdclk, can be different from the
131 * logical configuration only when all crtc's are DPMS off.
132 */
133 struct intel_cdclk_config actual;
134
135 /* minimum acceptable cdclk to satisfy bandwidth requirements */
136 int bw_min_cdclk;
137 /* minimum acceptable cdclk for each pipe */
138 int min_cdclk[I915_MAX_PIPES];
139 /* minimum acceptable voltage level for each pipe */
140 u8 min_voltage_level[I915_MAX_PIPES];
141
142 /* pipe to which cd2x update is synchronized */
143 enum pipe pipe;
144
145 /* forced minimum cdclk for glk+ audio w/a */
146 int force_min_cdclk;
147
148 /* bitmask of active pipes */
149 u8 active_pipes;
150
151 /* update cdclk with pipes disabled */
152 bool disable_pipes;
153};
154
155struct intel_cdclk_funcs {
156 void (*get_cdclk)(struct intel_display *display,
157 struct intel_cdclk_config *cdclk_config);
158 void (*set_cdclk)(struct intel_display *display,
159 const struct intel_cdclk_config *cdclk_config,
160 enum pipe pipe);
161 int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
162 u8 (*calc_voltage_level)(int cdclk);
163};
164
165void intel_cdclk_get_cdclk(struct intel_display *display,
166 struct intel_cdclk_config *cdclk_config)
167{
168 display->funcs.cdclk->get_cdclk(display, cdclk_config);
169}
170
171static void intel_cdclk_set_cdclk(struct intel_display *display,
172 const struct intel_cdclk_config *cdclk_config,
173 enum pipe pipe)
174{
175 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);
176}
177
178static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
179{
180 struct intel_display *display = to_intel_display(state);
181
182 return display->funcs.cdclk->modeset_calc_cdclk(state);
183}
184
185static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
186 int cdclk)
187{
188 return display->funcs.cdclk->calc_voltage_level(cdclk);
189}
190
191static void fixed_133mhz_get_cdclk(struct intel_display *display,
192 struct intel_cdclk_config *cdclk_config)
193{
194 cdclk_config->cdclk = 133333;
195}
196
197static void fixed_200mhz_get_cdclk(struct intel_display *display,
198 struct intel_cdclk_config *cdclk_config)
199{
200 cdclk_config->cdclk = 200000;
201}
202
203static void fixed_266mhz_get_cdclk(struct intel_display *display,
204 struct intel_cdclk_config *cdclk_config)
205{
206 cdclk_config->cdclk = 266667;
207}
208
209static void fixed_333mhz_get_cdclk(struct intel_display *display,
210 struct intel_cdclk_config *cdclk_config)
211{
212 cdclk_config->cdclk = 333333;
213}
214
215static void fixed_400mhz_get_cdclk(struct intel_display *display,
216 struct intel_cdclk_config *cdclk_config)
217{
218 cdclk_config->cdclk = 400000;
219}
220
221static void fixed_450mhz_get_cdclk(struct intel_display *display,
222 struct intel_cdclk_config *cdclk_config)
223{
224 cdclk_config->cdclk = 450000;
225}
226
227static void i85x_get_cdclk(struct intel_display *display,
228 struct intel_cdclk_config *cdclk_config)
229{
230 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
231 u16 hpllcc = 0;
232
233 /*
234 * 852GM/852GMV only supports 133 MHz and the HPLLCC
235 * encoding is different :(
236 * FIXME is this the right way to detect 852GM/852GMV?
237 */
238 if (pdev->revision == 0x1) {
239 cdclk_config->cdclk = 133333;
240 return;
241 }
242
243 pci_bus_read_config_word(bus: pdev->bus,
244 PCI_DEVFN(0, 3), HPLLCC, val: &hpllcc);
245
246 /* Assume that the hardware is in the high speed state. This
247 * should be the default.
248 */
249 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
250 case GC_CLOCK_133_200:
251 case GC_CLOCK_133_200_2:
252 case GC_CLOCK_100_200:
253 cdclk_config->cdclk = 200000;
254 break;
255 case GC_CLOCK_166_250:
256 cdclk_config->cdclk = 250000;
257 break;
258 case GC_CLOCK_100_133:
259 cdclk_config->cdclk = 133333;
260 break;
261 case GC_CLOCK_133_266:
262 case GC_CLOCK_133_266_2:
263 case GC_CLOCK_166_266:
264 cdclk_config->cdclk = 266667;
265 break;
266 }
267}
268
269static void i915gm_get_cdclk(struct intel_display *display,
270 struct intel_cdclk_config *cdclk_config)
271{
272 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
273 u16 gcfgc = 0;
274
275 pci_read_config_word(dev: pdev, GCFGC, val: &gcfgc);
276
277 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
278 cdclk_config->cdclk = 133333;
279 return;
280 }
281
282 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
283 case GC_DISPLAY_CLOCK_333_320_MHZ:
284 cdclk_config->cdclk = 333333;
285 break;
286 default:
287 case GC_DISPLAY_CLOCK_190_200_MHZ:
288 cdclk_config->cdclk = 190000;
289 break;
290 }
291}
292
293static void i945gm_get_cdclk(struct intel_display *display,
294 struct intel_cdclk_config *cdclk_config)
295{
296 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
297 u16 gcfgc = 0;
298
299 pci_read_config_word(dev: pdev, GCFGC, val: &gcfgc);
300
301 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
302 cdclk_config->cdclk = 133333;
303 return;
304 }
305
306 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
307 case GC_DISPLAY_CLOCK_333_320_MHZ:
308 cdclk_config->cdclk = 320000;
309 break;
310 default:
311 case GC_DISPLAY_CLOCK_190_200_MHZ:
312 cdclk_config->cdclk = 200000;
313 break;
314 }
315}
316
317static unsigned int intel_hpll_vco(struct intel_display *display)
318{
319 static const unsigned int blb_vco[8] = {
320 [0] = 3200000,
321 [1] = 4000000,
322 [2] = 5333333,
323 [3] = 4800000,
324 [4] = 6400000,
325 };
326 static const unsigned int pnv_vco[8] = {
327 [0] = 3200000,
328 [1] = 4000000,
329 [2] = 5333333,
330 [3] = 4800000,
331 [4] = 2666667,
332 };
333 static const unsigned int cl_vco[8] = {
334 [0] = 3200000,
335 [1] = 4000000,
336 [2] = 5333333,
337 [3] = 6400000,
338 [4] = 3333333,
339 [5] = 3566667,
340 [6] = 4266667,
341 };
342 static const unsigned int elk_vco[8] = {
343 [0] = 3200000,
344 [1] = 4000000,
345 [2] = 5333333,
346 [3] = 4800000,
347 };
348 static const unsigned int ctg_vco[8] = {
349 [0] = 3200000,
350 [1] = 4000000,
351 [2] = 5333333,
352 [3] = 6400000,
353 [4] = 2666667,
354 [5] = 4266667,
355 };
356 const unsigned int *vco_table;
357 unsigned int vco;
358 u8 tmp = 0;
359
360 /* FIXME other chipsets? */
361 if (display->platform.gm45)
362 vco_table = ctg_vco;
363 else if (display->platform.g45)
364 vco_table = elk_vco;
365 else if (display->platform.i965gm)
366 vco_table = cl_vco;
367 else if (display->platform.pineview)
368 vco_table = pnv_vco;
369 else if (display->platform.g33)
370 vco_table = blb_vco;
371 else
372 return 0;
373
374 tmp = intel_de_read(display, reg: display->platform.pineview ||
375 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO);
376
377 vco = vco_table[tmp & 0x7];
378 if (vco == 0)
379 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
380 tmp);
381 else
382 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
383
384 return vco;
385}
386
387static void g33_get_cdclk(struct intel_display *display,
388 struct intel_cdclk_config *cdclk_config)
389{
390 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
391 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
392 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
393 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
394 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
395 const u8 *div_table;
396 unsigned int cdclk_sel;
397 u16 tmp = 0;
398
399 cdclk_config->vco = intel_hpll_vco(display);
400
401 pci_read_config_word(dev: pdev, GCFGC, val: &tmp);
402
403 cdclk_sel = (tmp >> 4) & 0x7;
404
405 if (cdclk_sel >= ARRAY_SIZE(div_3200))
406 goto fail;
407
408 switch (cdclk_config->vco) {
409 case 3200000:
410 div_table = div_3200;
411 break;
412 case 4000000:
413 div_table = div_4000;
414 break;
415 case 4800000:
416 div_table = div_4800;
417 break;
418 case 5333333:
419 div_table = div_5333;
420 break;
421 default:
422 goto fail;
423 }
424
425 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
426 div_table[cdclk_sel]);
427 return;
428
429fail:
430 drm_err(display->drm,
431 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
432 cdclk_config->vco, tmp);
433 cdclk_config->cdclk = 190476;
434}
435
436static void pnv_get_cdclk(struct intel_display *display,
437 struct intel_cdclk_config *cdclk_config)
438{
439 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
440 u16 gcfgc = 0;
441
442 pci_read_config_word(dev: pdev, GCFGC, val: &gcfgc);
443
444 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
445 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
446 cdclk_config->cdclk = 266667;
447 break;
448 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
449 cdclk_config->cdclk = 333333;
450 break;
451 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
452 cdclk_config->cdclk = 444444;
453 break;
454 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
455 cdclk_config->cdclk = 200000;
456 break;
457 default:
458 drm_err(display->drm,
459 "Unknown pnv display core clock 0x%04x\n", gcfgc);
460 fallthrough;
461 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
462 cdclk_config->cdclk = 133333;
463 break;
464 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
465 cdclk_config->cdclk = 166667;
466 break;
467 }
468}
469
470static void i965gm_get_cdclk(struct intel_display *display,
471 struct intel_cdclk_config *cdclk_config)
472{
473 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
474 static const u8 div_3200[] = { 16, 10, 8 };
475 static const u8 div_4000[] = { 20, 12, 10 };
476 static const u8 div_5333[] = { 24, 16, 14 };
477 const u8 *div_table;
478 unsigned int cdclk_sel;
479 u16 tmp = 0;
480
481 cdclk_config->vco = intel_hpll_vco(display);
482
483 pci_read_config_word(dev: pdev, GCFGC, val: &tmp);
484
485 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
486
487 if (cdclk_sel >= ARRAY_SIZE(div_3200))
488 goto fail;
489
490 switch (cdclk_config->vco) {
491 case 3200000:
492 div_table = div_3200;
493 break;
494 case 4000000:
495 div_table = div_4000;
496 break;
497 case 5333333:
498 div_table = div_5333;
499 break;
500 default:
501 goto fail;
502 }
503
504 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
505 div_table[cdclk_sel]);
506 return;
507
508fail:
509 drm_err(display->drm,
510 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
511 cdclk_config->vco, tmp);
512 cdclk_config->cdclk = 200000;
513}
514
515static void gm45_get_cdclk(struct intel_display *display,
516 struct intel_cdclk_config *cdclk_config)
517{
518 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
519 unsigned int cdclk_sel;
520 u16 tmp = 0;
521
522 cdclk_config->vco = intel_hpll_vco(display);
523
524 pci_read_config_word(dev: pdev, GCFGC, val: &tmp);
525
526 cdclk_sel = (tmp >> 12) & 0x1;
527
528 switch (cdclk_config->vco) {
529 case 2666667:
530 case 4000000:
531 case 5333333:
532 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
533 break;
534 case 3200000:
535 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
536 break;
537 default:
538 drm_err(display->drm,
539 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
540 cdclk_config->vco, tmp);
541 cdclk_config->cdclk = 222222;
542 break;
543 }
544}
545
546static void hsw_get_cdclk(struct intel_display *display,
547 struct intel_cdclk_config *cdclk_config)
548{
549 u32 lcpll = intel_de_read(display, LCPLL_CTL);
550 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
551
552 if (lcpll & LCPLL_CD_SOURCE_FCLK)
553 cdclk_config->cdclk = 800000;
554 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
555 cdclk_config->cdclk = 450000;
556 else if (freq == LCPLL_CLK_FREQ_450)
557 cdclk_config->cdclk = 450000;
558 else if (display->platform.haswell_ult)
559 cdclk_config->cdclk = 337500;
560 else
561 cdclk_config->cdclk = 540000;
562}
563
564static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)
565{
566 struct drm_i915_private *dev_priv = to_i915(dev: display->drm);
567 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
568 333333 : 320000;
569
570 /*
571 * We seem to get an unstable or solid color picture at 200MHz.
572 * Not sure what's wrong. For now use 200MHz only when all pipes
573 * are off.
574 */
575 if (display->platform.valleyview && min_cdclk > freq_320)
576 return 400000;
577 else if (min_cdclk > 266667)
578 return freq_320;
579 else if (min_cdclk > 0)
580 return 266667;
581 else
582 return 200000;
583}
584
585static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)
586{
587 struct drm_i915_private *dev_priv = to_i915(dev: display->drm);
588
589 if (display->platform.valleyview) {
590 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
591 return 2;
592 else if (cdclk >= 266667)
593 return 1;
594 else
595 return 0;
596 } else {
597 /*
598 * Specs are full of misinformation, but testing on actual
599 * hardware has shown that we just need to write the desired
600 * CCK divider into the Punit register.
601 */
602 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
603 }
604}
605
606static void vlv_get_cdclk(struct intel_display *display,
607 struct intel_cdclk_config *cdclk_config)
608{
609 u32 val;
610
611 vlv_iosf_sb_get(drm: display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
612
613 cdclk_config->vco = vlv_get_hpll_vco(drm: display->drm);
614 cdclk_config->cdclk = vlv_get_cck_clock(drm: display->drm, name: "cdclk",
615 CCK_DISPLAY_CLOCK_CONTROL,
616 ref_freq: cdclk_config->vco);
617
618 val = vlv_punit_read(drm: display->drm, PUNIT_REG_DSPSSPM);
619
620 vlv_iosf_sb_put(drm: display->drm,
621 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
622
623 if (display->platform.valleyview)
624 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
625 DSPFREQGUAR_SHIFT;
626 else
627 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
628 DSPFREQGUAR_SHIFT_CHV;
629}
630
631static void vlv_program_pfi_credits(struct intel_display *display)
632{
633 struct drm_i915_private *dev_priv = to_i915(dev: display->drm);
634 unsigned int credits, default_credits;
635
636 if (display->platform.cherryview)
637 default_credits = PFI_CREDIT(12);
638 else
639 default_credits = PFI_CREDIT(8);
640
641 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
642 /* CHV suggested value is 31 or 63 */
643 if (display->platform.cherryview)
644 credits = PFI_CREDIT_63;
645 else
646 credits = PFI_CREDIT(15);
647 } else {
648 credits = default_credits;
649 }
650
651 /*
652 * WA - write default credits before re-programming
653 * FIXME: should we also set the resend bit here?
654 */
655 intel_de_write(display, GCI_CONTROL,
656 VGA_FAST_MODE_DISABLE | default_credits);
657
658 intel_de_write(display, GCI_CONTROL,
659 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
660
661 /*
662 * FIXME is this guaranteed to clear
663 * immediately or should we poll for it?
664 */
665 drm_WARN_ON(display->drm,
666 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);
667}
668
669static void vlv_set_cdclk(struct intel_display *display,
670 const struct intel_cdclk_config *cdclk_config,
671 enum pipe pipe)
672{
673 struct drm_i915_private *dev_priv = to_i915(dev: display->drm);
674 int cdclk = cdclk_config->cdclk;
675 u32 val, cmd = cdclk_config->voltage_level;
676 intel_wakeref_t wakeref;
677 int ret;
678
679 switch (cdclk) {
680 case 400000:
681 case 333333:
682 case 320000:
683 case 266667:
684 case 200000:
685 break;
686 default:
687 MISSING_CASE(cdclk);
688 return;
689 }
690
691 /* There are cases where we can end up here with power domains
692 * off and a CDCLK frequency other than the minimum, like when
693 * issuing a modeset without actually changing any display after
694 * a system suspend. So grab the display core domain, which covers
695 * the HW blocks needed for the following programming.
696 */
697 wakeref = intel_display_power_get(display, domain: POWER_DOMAIN_DISPLAY_CORE);
698
699 vlv_iosf_sb_get(drm: display->drm,
700 BIT(VLV_IOSF_SB_CCK) |
701 BIT(VLV_IOSF_SB_BUNIT) |
702 BIT(VLV_IOSF_SB_PUNIT));
703
704 val = vlv_punit_read(drm: display->drm, PUNIT_REG_DSPSSPM);
705 val &= ~DSPFREQGUAR_MASK;
706 val |= (cmd << DSPFREQGUAR_SHIFT);
707 vlv_punit_write(drm: display->drm, PUNIT_REG_DSPSSPM, val);
708
709 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
710 (val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
711 500, 50 * 1000, false);
712 if (ret)
713 drm_err(display->drm, "timed out waiting for CDCLK change\n");
714
715 if (cdclk == 400000) {
716 u32 divider;
717
718 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
719 cdclk) - 1;
720
721 /* adjust cdclk divider */
722 val = vlv_cck_read(drm: display->drm, CCK_DISPLAY_CLOCK_CONTROL);
723 val &= ~CCK_FREQUENCY_VALUES;
724 val |= divider;
725 vlv_cck_write(drm: display->drm, CCK_DISPLAY_CLOCK_CONTROL, val);
726
727 ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL),
728 (val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
729 500, 50 * 1000, false);
730 if (ret)
731 drm_err(display->drm, "timed out waiting for CDCLK change\n");
732 }
733
734 /* adjust self-refresh exit latency value */
735 val = vlv_bunit_read(drm: display->drm, BUNIT_REG_BISOC);
736 val &= ~0x7f;
737
738 /*
739 * For high bandwidth configs, we set a higher latency in the bunit
740 * so that the core display fetch happens in time to avoid underruns.
741 */
742 if (cdclk == 400000)
743 val |= 4500 / 250; /* 4.5 usec */
744 else
745 val |= 3000 / 250; /* 3.0 usec */
746 vlv_bunit_write(drm: display->drm, BUNIT_REG_BISOC, val);
747
748 vlv_iosf_sb_put(drm: display->drm,
749 BIT(VLV_IOSF_SB_CCK) |
750 BIT(VLV_IOSF_SB_BUNIT) |
751 BIT(VLV_IOSF_SB_PUNIT));
752
753 intel_update_cdclk(display);
754
755 vlv_program_pfi_credits(display);
756
757 intel_display_power_put(display, domain: POWER_DOMAIN_DISPLAY_CORE, wakeref);
758}
759
760static void chv_set_cdclk(struct intel_display *display,
761 const struct intel_cdclk_config *cdclk_config,
762 enum pipe pipe)
763{
764 int cdclk = cdclk_config->cdclk;
765 u32 val, cmd = cdclk_config->voltage_level;
766 intel_wakeref_t wakeref;
767 int ret;
768
769 switch (cdclk) {
770 case 333333:
771 case 320000:
772 case 266667:
773 case 200000:
774 break;
775 default:
776 MISSING_CASE(cdclk);
777 return;
778 }
779
780 /* There are cases where we can end up here with power domains
781 * off and a CDCLK frequency other than the minimum, like when
782 * issuing a modeset without actually changing any display after
783 * a system suspend. So grab the display core domain, which covers
784 * the HW blocks needed for the following programming.
785 */
786 wakeref = intel_display_power_get(display, domain: POWER_DOMAIN_DISPLAY_CORE);
787
788 vlv_punit_get(drm: display->drm);
789 val = vlv_punit_read(drm: display->drm, PUNIT_REG_DSPSSPM);
790 val &= ~DSPFREQGUAR_MASK_CHV;
791 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
792 vlv_punit_write(drm: display->drm, PUNIT_REG_DSPSSPM, val);
793
794 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
795 (val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
796 500, 50 * 1000, false);
797 if (ret)
798 drm_err(display->drm, "timed out waiting for CDCLK change\n");
799
800 vlv_punit_put(drm: display->drm);
801
802 intel_update_cdclk(display);
803
804 vlv_program_pfi_credits(display);
805
806 intel_display_power_put(display, domain: POWER_DOMAIN_DISPLAY_CORE, wakeref);
807}
808
809static int bdw_calc_cdclk(int min_cdclk)
810{
811 if (min_cdclk > 540000)
812 return 675000;
813 else if (min_cdclk > 450000)
814 return 540000;
815 else if (min_cdclk > 337500)
816 return 450000;
817 else
818 return 337500;
819}
820
821static u8 bdw_calc_voltage_level(int cdclk)
822{
823 switch (cdclk) {
824 default:
825 case 337500:
826 return 2;
827 case 450000:
828 return 0;
829 case 540000:
830 return 1;
831 case 675000:
832 return 3;
833 }
834}
835
836static void bdw_get_cdclk(struct intel_display *display,
837 struct intel_cdclk_config *cdclk_config)
838{
839 u32 lcpll = intel_de_read(display, LCPLL_CTL);
840 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
841
842 if (lcpll & LCPLL_CD_SOURCE_FCLK)
843 cdclk_config->cdclk = 800000;
844 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
845 cdclk_config->cdclk = 450000;
846 else if (freq == LCPLL_CLK_FREQ_450)
847 cdclk_config->cdclk = 450000;
848 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
849 cdclk_config->cdclk = 540000;
850 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
851 cdclk_config->cdclk = 337500;
852 else
853 cdclk_config->cdclk = 675000;
854
855 /*
856 * Can't read this out :( Let's assume it's
857 * at least what the CDCLK frequency requires.
858 */
859 cdclk_config->voltage_level =
860 bdw_calc_voltage_level(cdclk: cdclk_config->cdclk);
861}
862
863static u32 bdw_cdclk_freq_sel(int cdclk)
864{
865 switch (cdclk) {
866 default:
867 MISSING_CASE(cdclk);
868 fallthrough;
869 case 337500:
870 return LCPLL_CLK_FREQ_337_5_BDW;
871 case 450000:
872 return LCPLL_CLK_FREQ_450;
873 case 540000:
874 return LCPLL_CLK_FREQ_54O_BDW;
875 case 675000:
876 return LCPLL_CLK_FREQ_675_BDW;
877 }
878}
879
880static void bdw_set_cdclk(struct intel_display *display,
881 const struct intel_cdclk_config *cdclk_config,
882 enum pipe pipe)
883{
884 int cdclk = cdclk_config->cdclk;
885 int ret;
886
887 if (drm_WARN(display->drm,
888 (intel_de_read(display, LCPLL_CTL) &
889 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
890 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
891 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
892 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
893 "trying to change cdclk frequency with cdclk not enabled\n"))
894 return;
895
896 ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
897 if (ret) {
898 drm_err(display->drm,
899 "failed to inform pcode about cdclk change\n");
900 return;
901 }
902
903 intel_de_rmw(display, LCPLL_CTL,
904 clear: 0, LCPLL_CD_SOURCE_FCLK);
905
906 /*
907 * According to the spec, it should be enough to poll for this 1 us.
908 * However, extensive testing shows that this can take longer.
909 */
910 ret = intel_de_wait_custom(display, LCPLL_CTL,
911 LCPLL_CD_SOURCE_FCLK_DONE, LCPLL_CD_SOURCE_FCLK_DONE,
912 fast_timeout_us: 100, slow_timeout_ms: 0, NULL);
913 if (ret)
914 drm_err(display->drm, "Switching to FCLK failed\n");
915
916 intel_de_rmw(display, LCPLL_CTL,
917 LCPLL_CLK_FREQ_MASK, set: bdw_cdclk_freq_sel(cdclk));
918
919 intel_de_rmw(display, LCPLL_CTL,
920 LCPLL_CD_SOURCE_FCLK, set: 0);
921
922 ret = intel_de_wait_custom(display, LCPLL_CTL,
923 LCPLL_CD_SOURCE_FCLK_DONE, value: 0,
924 fast_timeout_us: 1, slow_timeout_ms: 0, NULL);
925 if (ret)
926 drm_err(display->drm, "Switching back to LCPLL failed\n");
927
928 intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ,
929 cdclk_config->voltage_level);
930
931 intel_de_write(display, CDCLK_FREQ,
932 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
933
934 intel_update_cdclk(display);
935}
936
937static int skl_calc_cdclk(int min_cdclk, int vco)
938{
939 if (vco == 8640000) {
940 if (min_cdclk > 540000)
941 return 617143;
942 else if (min_cdclk > 432000)
943 return 540000;
944 else if (min_cdclk > 308571)
945 return 432000;
946 else
947 return 308571;
948 } else {
949 if (min_cdclk > 540000)
950 return 675000;
951 else if (min_cdclk > 450000)
952 return 540000;
953 else if (min_cdclk > 337500)
954 return 450000;
955 else
956 return 337500;
957 }
958}
959
960static u8 skl_calc_voltage_level(int cdclk)
961{
962 if (cdclk > 540000)
963 return 3;
964 else if (cdclk > 450000)
965 return 2;
966 else if (cdclk > 337500)
967 return 1;
968 else
969 return 0;
970}
971
972static void skl_dpll0_update(struct intel_display *display,
973 struct intel_cdclk_config *cdclk_config)
974{
975 u32 val;
976
977 cdclk_config->ref = 24000;
978 cdclk_config->vco = 0;
979
980 val = intel_de_read(display, LCPLL1_CTL);
981 if ((val & LCPLL_PLL_ENABLE) == 0)
982 return;
983
984 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
985 return;
986
987 val = intel_de_read(display, DPLL_CTRL1);
988
989 if (drm_WARN_ON(display->drm,
990 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
991 DPLL_CTRL1_SSC(SKL_DPLL0) |
992 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
993 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
994 return;
995
996 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
997 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
998 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
999 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
1000 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
1001 cdclk_config->vco = 8100000;
1002 break;
1003 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
1004 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
1005 cdclk_config->vco = 8640000;
1006 break;
1007 default:
1008 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
1009 break;
1010 }
1011}
1012
1013static void skl_get_cdclk(struct intel_display *display,
1014 struct intel_cdclk_config *cdclk_config)
1015{
1016 u32 cdctl;
1017
1018 skl_dpll0_update(display, cdclk_config);
1019
1020 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
1021
1022 if (cdclk_config->vco == 0)
1023 goto out;
1024
1025 cdctl = intel_de_read(display, CDCLK_CTL);
1026
1027 if (cdclk_config->vco == 8640000) {
1028 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1029 case CDCLK_FREQ_450_432:
1030 cdclk_config->cdclk = 432000;
1031 break;
1032 case CDCLK_FREQ_337_308:
1033 cdclk_config->cdclk = 308571;
1034 break;
1035 case CDCLK_FREQ_540:
1036 cdclk_config->cdclk = 540000;
1037 break;
1038 case CDCLK_FREQ_675_617:
1039 cdclk_config->cdclk = 617143;
1040 break;
1041 default:
1042 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1043 break;
1044 }
1045 } else {
1046 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1047 case CDCLK_FREQ_450_432:
1048 cdclk_config->cdclk = 450000;
1049 break;
1050 case CDCLK_FREQ_337_308:
1051 cdclk_config->cdclk = 337500;
1052 break;
1053 case CDCLK_FREQ_540:
1054 cdclk_config->cdclk = 540000;
1055 break;
1056 case CDCLK_FREQ_675_617:
1057 cdclk_config->cdclk = 675000;
1058 break;
1059 default:
1060 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1061 break;
1062 }
1063 }
1064
1065 out:
1066 /*
1067 * Can't read this out :( Let's assume it's
1068 * at least what the CDCLK frequency requires.
1069 */
1070 cdclk_config->voltage_level =
1071 skl_calc_voltage_level(cdclk: cdclk_config->cdclk);
1072}
1073
1074/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
1075static int skl_cdclk_decimal(int cdclk)
1076{
1077 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
1078}
1079
1080static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
1081{
1082 bool changed = display->cdclk.skl_preferred_vco_freq != vco;
1083
1084 display->cdclk.skl_preferred_vco_freq = vco;
1085
1086 if (changed)
1087 intel_update_max_cdclk(display);
1088}
1089
1090static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
1091{
1092 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
1093
1094 /*
1095 * We always enable DPLL0 with the lowest link rate possible, but still
1096 * taking into account the VCO required to operate the eDP panel at the
1097 * desired frequency. The usual DP link rates operate with a VCO of
1098 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
1099 * The modeset code is responsible for the selection of the exact link
1100 * rate later on, with the constraint of choosing a frequency that
1101 * works with vco.
1102 */
1103 if (vco == 8640000)
1104 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
1105 else
1106 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
1107}
1108
1109static void skl_dpll0_enable(struct intel_display *display, int vco)
1110{
1111 intel_de_rmw(display, DPLL_CTRL1,
1112 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
1113 DPLL_CTRL1_SSC(SKL_DPLL0) |
1114 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
1115 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
1116 skl_dpll0_link_rate(display, vco));
1117 intel_de_posting_read(display, DPLL_CTRL1);
1118
1119 intel_de_rmw(display, LCPLL1_CTL,
1120 clear: 0, LCPLL_PLL_ENABLE);
1121
1122 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, timeout_ms: 5))
1123 drm_err(display->drm, "DPLL0 not locked\n");
1124
1125 display->cdclk.hw.vco = vco;
1126
1127 /* We'll want to keep using the current vco from now on. */
1128 skl_set_preferred_cdclk_vco(display, vco);
1129}
1130
1131static void skl_dpll0_disable(struct intel_display *display)
1132{
1133 intel_de_rmw(display, LCPLL1_CTL,
1134 LCPLL_PLL_ENABLE, set: 0);
1135
1136 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, timeout_ms: 1))
1137 drm_err(display->drm, "Couldn't disable DPLL0\n");
1138
1139 display->cdclk.hw.vco = 0;
1140}
1141
1142static u32 skl_cdclk_freq_sel(struct intel_display *display,
1143 int cdclk, int vco)
1144{
1145 switch (cdclk) {
1146 default:
1147 drm_WARN_ON(display->drm,
1148 cdclk != display->cdclk.hw.bypass);
1149 drm_WARN_ON(display->drm, vco != 0);
1150 fallthrough;
1151 case 308571:
1152 case 337500:
1153 return CDCLK_FREQ_337_308;
1154 case 450000:
1155 case 432000:
1156 return CDCLK_FREQ_450_432;
1157 case 540000:
1158 return CDCLK_FREQ_540;
1159 case 617143:
1160 case 675000:
1161 return CDCLK_FREQ_675_617;
1162 }
1163}
1164
1165static void skl_set_cdclk(struct intel_display *display,
1166 const struct intel_cdclk_config *cdclk_config,
1167 enum pipe pipe)
1168{
1169 int cdclk = cdclk_config->cdclk;
1170 int vco = cdclk_config->vco;
1171 u32 freq_select, cdclk_ctl;
1172 int ret;
1173
1174 /*
1175 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1176 * unsupported on SKL. In theory this should never happen since only
1177 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1178 * supported on SKL either, see the above WA. WARN whenever trying to
1179 * use the corresponding VCO freq as that always leads to using the
1180 * minimum 308MHz CDCLK.
1181 */
1182 drm_WARN_ON_ONCE(display->drm,
1183 display->platform.skylake && vco == 8640000);
1184
1185 ret = intel_pcode_request(drm: display->drm, SKL_PCODE_CDCLK_CONTROL,
1186 SKL_CDCLK_PREPARE_FOR_CHANGE,
1187 SKL_CDCLK_READY_FOR_CHANGE,
1188 SKL_CDCLK_READY_FOR_CHANGE, timeout_base_ms: 3);
1189 if (ret) {
1190 drm_err(display->drm,
1191 "Failed to inform PCU about cdclk change (%d)\n", ret);
1192 return;
1193 }
1194
1195 freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
1196
1197 if (display->cdclk.hw.vco != 0 &&
1198 display->cdclk.hw.vco != vco)
1199 skl_dpll0_disable(display);
1200
1201 cdclk_ctl = intel_de_read(display, CDCLK_CTL);
1202
1203 if (display->cdclk.hw.vco != vco) {
1204 /* Wa Display #1183: skl,kbl,cfl */
1205 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1206 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1207 intel_de_write(display, CDCLK_CTL, val: cdclk_ctl);
1208 }
1209
1210 /* Wa Display #1183: skl,kbl,cfl */
1211 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1212 intel_de_write(display, CDCLK_CTL, val: cdclk_ctl);
1213 intel_de_posting_read(display, CDCLK_CTL);
1214
1215 if (display->cdclk.hw.vco != vco)
1216 skl_dpll0_enable(display, vco);
1217
1218 /* Wa Display #1183: skl,kbl,cfl */
1219 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1220 intel_de_write(display, CDCLK_CTL, val: cdclk_ctl);
1221
1222 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1223 intel_de_write(display, CDCLK_CTL, val: cdclk_ctl);
1224
1225 /* Wa Display #1183: skl,kbl,cfl */
1226 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1227 intel_de_write(display, CDCLK_CTL, val: cdclk_ctl);
1228 intel_de_posting_read(display, CDCLK_CTL);
1229
1230 /* inform PCU of the change */
1231 intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
1232 cdclk_config->voltage_level);
1233
1234 intel_update_cdclk(display);
1235}
1236
1237static void skl_sanitize_cdclk(struct intel_display *display)
1238{
1239 u32 cdctl, expected;
1240
1241 /*
1242 * check if the pre-os initialized the display
1243 * There is SWF18 scratchpad register defined which is set by the
1244 * pre-os which can be used by the OS drivers to check the status
1245 */
1246 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1247 goto sanitize;
1248
1249 intel_update_cdclk(display);
1250 intel_cdclk_dump_config(display, cdclk_config: &display->cdclk.hw, context: "Current CDCLK");
1251
1252 /* Is PLL enabled and locked ? */
1253 if (display->cdclk.hw.vco == 0 ||
1254 display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
1255 goto sanitize;
1256
1257 /* DPLL okay; verify the cdclock
1258 *
1259 * Noticed in some instances that the freq selection is correct but
1260 * decimal part is programmed wrong from BIOS where pre-os does not
1261 * enable display. Verify the same as well.
1262 */
1263 cdctl = intel_de_read(display, CDCLK_CTL);
1264 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1265 skl_cdclk_decimal(cdclk: display->cdclk.hw.cdclk);
1266 if (cdctl == expected)
1267 /* All well; nothing to sanitize */
1268 return;
1269
1270sanitize:
1271 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
1272
1273 /* force cdclk programming */
1274 display->cdclk.hw.cdclk = 0;
1275 /* force full PLL disable + enable */
1276 display->cdclk.hw.vco = ~0;
1277}
1278
1279static void skl_cdclk_init_hw(struct intel_display *display)
1280{
1281 struct intel_cdclk_config cdclk_config;
1282
1283 skl_sanitize_cdclk(display);
1284
1285 if (display->cdclk.hw.cdclk != 0 &&
1286 display->cdclk.hw.vco != 0) {
1287 /*
1288 * Use the current vco as our initial
1289 * guess as to what the preferred vco is.
1290 */
1291 if (display->cdclk.skl_preferred_vco_freq == 0)
1292 skl_set_preferred_cdclk_vco(display,
1293 vco: display->cdclk.hw.vco);
1294 return;
1295 }
1296
1297 cdclk_config = display->cdclk.hw;
1298
1299 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
1300 if (cdclk_config.vco == 0)
1301 cdclk_config.vco = 8100000;
1302 cdclk_config.cdclk = skl_calc_cdclk(min_cdclk: 0, vco: cdclk_config.vco);
1303 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk: cdclk_config.cdclk);
1304
1305 skl_set_cdclk(display, cdclk_config: &cdclk_config, pipe: INVALID_PIPE);
1306}
1307
1308static void skl_cdclk_uninit_hw(struct intel_display *display)
1309{
1310 struct intel_cdclk_config cdclk_config = display->cdclk.hw;
1311
1312 cdclk_config.cdclk = cdclk_config.bypass;
1313 cdclk_config.vco = 0;
1314 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk: cdclk_config.cdclk);
1315
1316 skl_set_cdclk(display, cdclk_config: &cdclk_config, pipe: INVALID_PIPE);
1317}
1318
1319struct intel_cdclk_vals {
1320 u32 cdclk;
1321 u16 refclk;
1322 u16 waveform;
1323 u8 ratio;
1324};
1325
1326static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1327 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1328 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1329 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1330 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1331 { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1332 {}
1333};
1334
1335static const struct intel_cdclk_vals glk_cdclk_table[] = {
1336 { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1337 { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1338 { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1339 {}
1340};
1341
1342static const struct intel_cdclk_vals icl_cdclk_table[] = {
1343 { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1344 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1345 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1346 { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1347 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1348 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1349
1350 { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1351 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1352 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1353 { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1354 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1355 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1356
1357 { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
1358 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1359 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1360 { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1361 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1362 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1363 {}
1364};
1365
1366static const struct intel_cdclk_vals rkl_cdclk_table[] = {
1367 { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
1368 { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
1369 { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
1370 { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1371 { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1372 { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1373
1374 { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
1375 { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
1376 { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
1377 { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1378 { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
1379 { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1380
1381 { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1382 { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1383 { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1384 { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1385 { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1386 { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1387 {}
1388};
1389
1390static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
1391 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1392 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1393 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1394
1395 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1396 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1397 { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1398
1399 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1400 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1401 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1402 {}
1403};
1404
1405static const struct intel_cdclk_vals adlp_cdclk_table[] = {
1406 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1407 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1408 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1409 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1410 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1411
1412 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1413 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1414 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1415 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1416 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1417
1418 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1419 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1420 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1421 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1422 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1423 {}
1424};
1425
1426static const struct intel_cdclk_vals rplu_cdclk_table[] = {
1427 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1428 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1429 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1430 { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1431 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1432 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1433
1434 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1435 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1436 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1437 { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1438 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1439 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1440
1441 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1442 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1443 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1444 { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1445 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1446 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1447 {}
1448};
1449
1450static const struct intel_cdclk_vals dg2_cdclk_table[] = {
1451 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1452 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1453 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1454 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1455 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1456 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1457 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1458 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1459 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1460 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1461 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1462 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1463 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1464 {}
1465};
1466
1467static const struct intel_cdclk_vals mtl_cdclk_table[] = {
1468 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1469 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1470 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1471 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1472 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1473 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1474 {}
1475};
1476
1477static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = {
1478 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1479 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1480 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1481 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1482 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1483 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1484 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1485 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1486 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1487 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1488 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1489 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1490 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1491 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1492 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1493 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1494 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1495 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1496 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1497 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1498 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1499 {}
1500};
1501
1502/*
1503 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771
1504 */
1505static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = {
1506 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1507 {}
1508};
1509
1510static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
1511 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1512 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1513 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1514 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1515 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1516 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1517 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1518 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1519 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1520 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff },
1521 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },
1522 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },
1523 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },
1524 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1525 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1526 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1527 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1528 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1529 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1530 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1531 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1532 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1533 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1534 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1535 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1536 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1537 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1538 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1539 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1540 {}
1541};
1542
1543static const int cdclk_squash_len = 16;
1544
1545static int cdclk_squash_divider(u16 waveform)
1546{
1547 return hweight16(waveform ?: 0xffff);
1548}
1549
1550static int cdclk_divider(int cdclk, int vco, u16 waveform)
1551{
1552 /* 2 * cd2x divider */
1553 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1554 cdclk * cdclk_squash_len);
1555}
1556
1557static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)
1558{
1559 const struct intel_cdclk_vals *table = display->cdclk.table;
1560 int i;
1561
1562 for (i = 0; table[i].refclk; i++)
1563 if (table[i].refclk == display->cdclk.hw.ref &&
1564 table[i].cdclk >= min_cdclk)
1565 return table[i].cdclk;
1566
1567 drm_WARN(display->drm, 1,
1568 "Cannot satisfy minimum cdclk %d with refclk %u\n",
1569 min_cdclk, display->cdclk.hw.ref);
1570 return 0;
1571}
1572
1573static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)
1574{
1575 const struct intel_cdclk_vals *table = display->cdclk.table;
1576 int i;
1577
1578 if (cdclk == display->cdclk.hw.bypass)
1579 return 0;
1580
1581 for (i = 0; table[i].refclk; i++)
1582 if (table[i].refclk == display->cdclk.hw.ref &&
1583 table[i].cdclk == cdclk)
1584 return display->cdclk.hw.ref * table[i].ratio;
1585
1586 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1587 cdclk, display->cdclk.hw.ref);
1588 return 0;
1589}
1590
1591static u8 bxt_calc_voltage_level(int cdclk)
1592{
1593 return DIV_ROUND_UP(cdclk, 25000);
1594}
1595
1596static u8 calc_voltage_level(int cdclk, int num_voltage_levels,
1597 const int voltage_level_max_cdclk[])
1598{
1599 int voltage_level;
1600
1601 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {
1602 if (cdclk <= voltage_level_max_cdclk[voltage_level])
1603 return voltage_level;
1604 }
1605
1606 MISSING_CASE(cdclk);
1607 return num_voltage_levels - 1;
1608}
1609
1610static u8 icl_calc_voltage_level(int cdclk)
1611{
1612 static const int icl_voltage_level_max_cdclk[] = {
1613 [0] = 312000,
1614 [1] = 556800,
1615 [2] = 652800,
1616 };
1617
1618 return calc_voltage_level(cdclk,
1619 ARRAY_SIZE(icl_voltage_level_max_cdclk),
1620 voltage_level_max_cdclk: icl_voltage_level_max_cdclk);
1621}
1622
1623static u8 ehl_calc_voltage_level(int cdclk)
1624{
1625 static const int ehl_voltage_level_max_cdclk[] = {
1626 [0] = 180000,
1627 [1] = 312000,
1628 [2] = 326400,
1629 /*
1630 * Bspec lists the limit as 556.8 MHz, but some JSL
1631 * development boards (at least) boot with 652.8 MHz
1632 */
1633 [3] = 652800,
1634 };
1635
1636 return calc_voltage_level(cdclk,
1637 ARRAY_SIZE(ehl_voltage_level_max_cdclk),
1638 voltage_level_max_cdclk: ehl_voltage_level_max_cdclk);
1639}
1640
1641static u8 tgl_calc_voltage_level(int cdclk)
1642{
1643 static const int tgl_voltage_level_max_cdclk[] = {
1644 [0] = 312000,
1645 [1] = 326400,
1646 [2] = 556800,
1647 [3] = 652800,
1648 };
1649
1650 return calc_voltage_level(cdclk,
1651 ARRAY_SIZE(tgl_voltage_level_max_cdclk),
1652 voltage_level_max_cdclk: tgl_voltage_level_max_cdclk);
1653}
1654
1655static u8 rplu_calc_voltage_level(int cdclk)
1656{
1657 static const int rplu_voltage_level_max_cdclk[] = {
1658 [0] = 312000,
1659 [1] = 480000,
1660 [2] = 556800,
1661 [3] = 652800,
1662 };
1663
1664 return calc_voltage_level(cdclk,
1665 ARRAY_SIZE(rplu_voltage_level_max_cdclk),
1666 voltage_level_max_cdclk: rplu_voltage_level_max_cdclk);
1667}
1668
1669static u8 xe3lpd_calc_voltage_level(int cdclk)
1670{
1671 /*
1672 * Starting with xe3lpd power controller does not need the voltage
1673 * index when doing the modeset update. This function is best left
1674 * defined but returning 0 to the mask.
1675 */
1676 return 0;
1677}
1678
1679static void icl_readout_refclk(struct intel_display *display,
1680 struct intel_cdclk_config *cdclk_config)
1681{
1682 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1683
1684 switch (dssm) {
1685 default:
1686 MISSING_CASE(dssm);
1687 fallthrough;
1688 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1689 cdclk_config->ref = 24000;
1690 break;
1691 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1692 cdclk_config->ref = 19200;
1693 break;
1694 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1695 cdclk_config->ref = 38400;
1696 break;
1697 }
1698}
1699
1700static void bxt_de_pll_readout(struct intel_display *display,
1701 struct intel_cdclk_config *cdclk_config)
1702{
1703 u32 val, ratio;
1704
1705 if (display->platform.dg2)
1706 cdclk_config->ref = 38400;
1707 else if (DISPLAY_VER(display) >= 11)
1708 icl_readout_refclk(display, cdclk_config);
1709 else
1710 cdclk_config->ref = 19200;
1711
1712 val = intel_de_read(display, BXT_DE_PLL_ENABLE);
1713 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1714 (val & BXT_DE_PLL_LOCK) == 0) {
1715 /*
1716 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1717 * setting it to zero is a way to signal that.
1718 */
1719 cdclk_config->vco = 0;
1720 return;
1721 }
1722
1723 /*
1724 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
1725 * gen9lp had it in a separate PLL control register.
1726 */
1727 if (DISPLAY_VER(display) >= 11)
1728 ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
1729 else
1730 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1731
1732 cdclk_config->vco = ratio * cdclk_config->ref;
1733}
1734
1735static void bxt_get_cdclk(struct intel_display *display,
1736 struct intel_cdclk_config *cdclk_config)
1737{
1738 u32 squash_ctl = 0;
1739 u32 divider;
1740 int div;
1741
1742 bxt_de_pll_readout(display, cdclk_config);
1743
1744 if (DISPLAY_VER(display) >= 12)
1745 cdclk_config->bypass = cdclk_config->ref / 2;
1746 else if (DISPLAY_VER(display) >= 11)
1747 cdclk_config->bypass = 50000;
1748 else
1749 cdclk_config->bypass = cdclk_config->ref;
1750
1751 if (cdclk_config->vco == 0) {
1752 cdclk_config->cdclk = cdclk_config->bypass;
1753 goto out;
1754 }
1755
1756 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1757
1758 switch (divider) {
1759 case BXT_CDCLK_CD2X_DIV_SEL_1:
1760 div = 2;
1761 break;
1762 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1763 div = 3;
1764 break;
1765 case BXT_CDCLK_CD2X_DIV_SEL_2:
1766 div = 4;
1767 break;
1768 case BXT_CDCLK_CD2X_DIV_SEL_4:
1769 div = 8;
1770 break;
1771 default:
1772 MISSING_CASE(divider);
1773 return;
1774 }
1775
1776 if (HAS_CDCLK_SQUASH(display))
1777 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);
1778
1779 if (squash_ctl & CDCLK_SQUASH_ENABLE) {
1780 u16 waveform;
1781 int size;
1782
1783 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;
1784 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);
1785
1786 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1787 cdclk_config->vco, size * div);
1788 } else {
1789 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1790 }
1791
1792 out:
1793 if (DISPLAY_VER(display) >= 20)
1794 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
1795 /*
1796 * Can't read this out :( Let's assume it's
1797 * at least what the CDCLK frequency requires.
1798 */
1799 cdclk_config->voltage_level =
1800 intel_cdclk_calc_voltage_level(display, cdclk: cdclk_config->cdclk);
1801}
1802
1803static void bxt_de_pll_disable(struct intel_display *display)
1804{
1805 intel_de_write(display, BXT_DE_PLL_ENABLE, val: 0);
1806
1807 /* Timeout 200us */
1808 if (intel_de_wait_for_clear(display,
1809 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, timeout_ms: 1))
1810 drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
1811
1812 display->cdclk.hw.vco = 0;
1813}
1814
1815static void bxt_de_pll_enable(struct intel_display *display, int vco)
1816{
1817 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1818
1819 intel_de_rmw(display, BXT_DE_PLL_CTL,
1820 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1821
1822 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1823
1824 /* Timeout 200us */
1825 if (intel_de_wait_for_set(display,
1826 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, timeout_ms: 1))
1827 drm_err(display->drm, "timeout waiting for DE PLL lock\n");
1828
1829 display->cdclk.hw.vco = vco;
1830}
1831
1832static void icl_cdclk_pll_disable(struct intel_display *display)
1833{
1834 intel_de_rmw(display, BXT_DE_PLL_ENABLE,
1835 BXT_DE_PLL_PLL_ENABLE, set: 0);
1836
1837 /* Timeout 200us */
1838 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, timeout_ms: 1))
1839 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
1840
1841 display->cdclk.hw.vco = 0;
1842}
1843
1844static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
1845{
1846 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1847 u32 val;
1848
1849 val = ICL_CDCLK_PLL_RATIO(ratio);
1850 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1851
1852 val |= BXT_DE_PLL_PLL_ENABLE;
1853 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1854
1855 /* Timeout 200us */
1856 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, timeout_ms: 1))
1857 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
1858
1859 display->cdclk.hw.vco = vco;
1860}
1861
1862static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
1863{
1864 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1865 u32 val;
1866
1867 /* Write PLL ratio without disabling */
1868 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
1869 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1870
1871 /* Submit freq change request */
1872 val |= BXT_DE_PLL_FREQ_REQ;
1873 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1874
1875 /* Timeout 200us */
1876 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
1877 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, timeout_ms: 1))
1878 drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
1879
1880 val &= ~BXT_DE_PLL_FREQ_REQ;
1881 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1882
1883 display->cdclk.hw.vco = vco;
1884}
1885
1886static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)
1887{
1888 if (DISPLAY_VER(display) >= 12) {
1889 if (pipe == INVALID_PIPE)
1890 return TGL_CDCLK_CD2X_PIPE_NONE;
1891 else
1892 return TGL_CDCLK_CD2X_PIPE(pipe);
1893 } else if (DISPLAY_VER(display) >= 11) {
1894 if (pipe == INVALID_PIPE)
1895 return ICL_CDCLK_CD2X_PIPE_NONE;
1896 else
1897 return ICL_CDCLK_CD2X_PIPE(pipe);
1898 } else {
1899 if (pipe == INVALID_PIPE)
1900 return BXT_CDCLK_CD2X_PIPE_NONE;
1901 else
1902 return BXT_CDCLK_CD2X_PIPE(pipe);
1903 }
1904}
1905
1906static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,
1907 int cdclk, int vco, u16 waveform)
1908{
1909 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1910 switch (cdclk_divider(cdclk, vco, waveform)) {
1911 default:
1912 drm_WARN_ON(display->drm,
1913 cdclk != display->cdclk.hw.bypass);
1914 drm_WARN_ON(display->drm, vco != 0);
1915 fallthrough;
1916 case 2:
1917 return BXT_CDCLK_CD2X_DIV_SEL_1;
1918 case 3:
1919 return BXT_CDCLK_CD2X_DIV_SEL_1_5;
1920 case 4:
1921 return BXT_CDCLK_CD2X_DIV_SEL_2;
1922 case 8:
1923 return BXT_CDCLK_CD2X_DIV_SEL_4;
1924 }
1925}
1926
1927static u16 cdclk_squash_waveform(struct intel_display *display,
1928 int cdclk)
1929{
1930 const struct intel_cdclk_vals *table = display->cdclk.table;
1931 int i;
1932
1933 if (cdclk == display->cdclk.hw.bypass)
1934 return 0;
1935
1936 for (i = 0; table[i].refclk; i++)
1937 if (table[i].refclk == display->cdclk.hw.ref &&
1938 table[i].cdclk == cdclk)
1939 return table[i].waveform;
1940
1941 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1942 cdclk, display->cdclk.hw.ref);
1943
1944 return 0xffff;
1945}
1946
1947static void icl_cdclk_pll_update(struct intel_display *display, int vco)
1948{
1949 if (display->cdclk.hw.vco != 0 &&
1950 display->cdclk.hw.vco != vco)
1951 icl_cdclk_pll_disable(display);
1952
1953 if (display->cdclk.hw.vco != vco)
1954 icl_cdclk_pll_enable(display, vco);
1955}
1956
1957static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
1958{
1959 if (display->cdclk.hw.vco != 0 &&
1960 display->cdclk.hw.vco != vco)
1961 bxt_de_pll_disable(display);
1962
1963 if (display->cdclk.hw.vco != vco)
1964 bxt_de_pll_enable(display, vco);
1965}
1966
1967static void dg2_cdclk_squash_program(struct intel_display *display,
1968 u16 waveform)
1969{
1970 u32 squash_ctl = 0;
1971
1972 if (waveform)
1973 squash_ctl = CDCLK_SQUASH_ENABLE |
1974 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
1975
1976 intel_de_write(display, CDCLK_SQUASH_CTL, val: squash_ctl);
1977}
1978
1979static bool cdclk_pll_is_unknown(unsigned int vco)
1980{
1981 /*
1982 * Ensure driver does not take the crawl path for the
1983 * case when the vco is set to ~0 in the
1984 * sanitize path.
1985 */
1986 return vco == ~0;
1987}
1988
1989static bool mdclk_source_is_cdclk_pll(struct intel_display *display)
1990{
1991 return DISPLAY_VER(display) >= 20;
1992}
1993
1994static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)
1995{
1996 if (mdclk_source_is_cdclk_pll(display))
1997 return MDCLK_SOURCE_SEL_CDCLK_PLL;
1998
1999 return MDCLK_SOURCE_SEL_CD2XCLK;
2000}
2001
2002int intel_mdclk_cdclk_ratio(struct intel_display *display,
2003 const struct intel_cdclk_config *cdclk_config)
2004{
2005 if (mdclk_source_is_cdclk_pll(display))
2006 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
2007
2008 /* Otherwise, source for MDCLK is CD2XCLK. */
2009 return 2;
2010}
2011
2012static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,
2013 const struct intel_cdclk_config *cdclk_config)
2014{
2015 intel_dbuf_mdclk_cdclk_ratio_update(display,
2016 ratio: intel_mdclk_cdclk_ratio(display, cdclk_config),
2017 joined_mbus: cdclk_config->joined_mbus);
2018}
2019
2020static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,
2021 const struct intel_cdclk_config *old_cdclk_config,
2022 const struct intel_cdclk_config *new_cdclk_config,
2023 struct intel_cdclk_config *mid_cdclk_config)
2024{
2025 u16 old_waveform, new_waveform, mid_waveform;
2026 int old_div, new_div, mid_div;
2027
2028 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */
2029 if (cdclk_pll_is_unknown(vco: old_cdclk_config->vco))
2030 return false;
2031
2032 /* Return if both Squash and Crawl are not present */
2033 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
2034 return false;
2035
2036 old_waveform = cdclk_squash_waveform(display, cdclk: old_cdclk_config->cdclk);
2037 new_waveform = cdclk_squash_waveform(display, cdclk: new_cdclk_config->cdclk);
2038
2039 /* Return if Squash only or Crawl only is the desired action */
2040 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
2041 old_cdclk_config->vco == new_cdclk_config->vco ||
2042 old_waveform == new_waveform)
2043 return false;
2044
2045 old_div = cdclk_divider(cdclk: old_cdclk_config->cdclk,
2046 vco: old_cdclk_config->vco, waveform: old_waveform);
2047 new_div = cdclk_divider(cdclk: new_cdclk_config->cdclk,
2048 vco: new_cdclk_config->vco, waveform: new_waveform);
2049
2050 /*
2051 * Should not happen currently. We might need more midpoint
2052 * transitions if we need to also change the cd2x divider.
2053 */
2054 if (drm_WARN_ON(display->drm, old_div != new_div))
2055 return false;
2056
2057 *mid_cdclk_config = *new_cdclk_config;
2058
2059 /*
2060 * Populate the mid_cdclk_config accordingly.
2061 * - If moving to a higher cdclk, the desired action is squashing.
2062 * The mid cdclk config should have the new (squash) waveform.
2063 * - If moving to a lower cdclk, the desired action is crawling.
2064 * The mid cdclk config should have the new vco.
2065 */
2066
2067 if (cdclk_squash_divider(waveform: new_waveform) > cdclk_squash_divider(waveform: old_waveform)) {
2068 mid_cdclk_config->vco = old_cdclk_config->vco;
2069 mid_div = old_div;
2070 mid_waveform = new_waveform;
2071 } else {
2072 mid_cdclk_config->vco = new_cdclk_config->vco;
2073 mid_div = new_div;
2074 mid_waveform = old_waveform;
2075 }
2076
2077 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
2078 mid_cdclk_config->vco,
2079 cdclk_squash_len * mid_div);
2080
2081 /* make sure the mid clock came out sane */
2082
2083 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <
2084 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
2085 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >
2086 display->cdclk.max_cdclk_freq);
2087 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=
2088 mid_waveform);
2089
2090 return true;
2091}
2092
2093static bool pll_enable_wa_needed(struct intel_display *display)
2094{
2095 return (DISPLAY_VERx100(display) == 2000 ||
2096 DISPLAY_VERx100(display) == 1400 ||
2097 display->platform.dg2) &&
2098 display->cdclk.hw.vco > 0;
2099}
2100
2101static u32 bxt_cdclk_ctl(struct intel_display *display,
2102 const struct intel_cdclk_config *cdclk_config,
2103 enum pipe pipe)
2104{
2105 int cdclk = cdclk_config->cdclk;
2106 int vco = cdclk_config->vco;
2107 u16 waveform;
2108 u32 val;
2109
2110 waveform = cdclk_squash_waveform(display, cdclk);
2111
2112 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
2113 bxt_cdclk_cd2x_pipe(display, pipe);
2114
2115 /*
2116 * Disable SSA Precharge when CD clock frequency < 500 MHz,
2117 * enable otherwise.
2118 */
2119 if ((display->platform.geminilake || display->platform.broxton) &&
2120 cdclk >= 500000)
2121 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
2122
2123 if (DISPLAY_VER(display) >= 20)
2124 val |= xe2lpd_mdclk_source_sel(display);
2125 else
2126 val |= skl_cdclk_decimal(cdclk);
2127
2128 return val;
2129}
2130
2131static void _bxt_set_cdclk(struct intel_display *display,
2132 const struct intel_cdclk_config *cdclk_config,
2133 enum pipe pipe)
2134{
2135 int cdclk = cdclk_config->cdclk;
2136 int vco = cdclk_config->vco;
2137
2138 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
2139 !cdclk_pll_is_unknown(vco: display->cdclk.hw.vco)) {
2140 if (display->cdclk.hw.vco != vco)
2141 adlp_cdclk_pll_crawl(display, vco);
2142 } else if (DISPLAY_VER(display) >= 11) {
2143 /* wa_15010685871: dg2, mtl */
2144 if (pll_enable_wa_needed(display))
2145 dg2_cdclk_squash_program(display, waveform: 0);
2146
2147 icl_cdclk_pll_update(display, vco);
2148 } else {
2149 bxt_cdclk_pll_update(display, vco);
2150 }
2151
2152 if (HAS_CDCLK_SQUASH(display)) {
2153 u16 waveform = cdclk_squash_waveform(display, cdclk);
2154
2155 dg2_cdclk_squash_program(display, waveform);
2156 }
2157
2158 intel_de_write(display, CDCLK_CTL, val: bxt_cdclk_ctl(display, cdclk_config, pipe));
2159
2160 if (pipe != INVALID_PIPE)
2161 intel_crtc_wait_for_next_vblank(crtc: intel_crtc_for_pipe(display, pipe));
2162}
2163
2164static void bxt_set_cdclk(struct intel_display *display,
2165 const struct intel_cdclk_config *cdclk_config,
2166 enum pipe pipe)
2167{
2168 struct intel_cdclk_config mid_cdclk_config;
2169 int cdclk = cdclk_config->cdclk;
2170 int ret = 0;
2171
2172 /*
2173 * Inform power controller of upcoming frequency change.
2174 * Display versions 14 and beyond do not follow the PUnit
2175 * mailbox communication, skip
2176 * this step.
2177 */
2178 if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
2179 ; /* NOOP */
2180 else if (DISPLAY_VER(display) >= 11)
2181 ret = intel_pcode_request(drm: display->drm, SKL_PCODE_CDCLK_CONTROL,
2182 SKL_CDCLK_PREPARE_FOR_CHANGE,
2183 SKL_CDCLK_READY_FOR_CHANGE,
2184 SKL_CDCLK_READY_FOR_CHANGE, timeout_base_ms: 3);
2185 else
2186 /*
2187 * BSpec requires us to wait up to 150usec, but that leads to
2188 * timeouts; the 2ms used here is based on experiment.
2189 */
2190 ret = intel_pcode_write_timeout(drm: display->drm,
2191 HSW_PCODE_DE_WRITE_FREQ_REQ,
2192 val: 0x80000000, timeout_ms: 2);
2193
2194 if (ret) {
2195 drm_err(display->drm,
2196 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
2197 ret, cdclk);
2198 return;
2199 }
2200
2201 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
2202 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2203
2204 if (cdclk_compute_crawl_and_squash_midpoint(display, old_cdclk_config: &display->cdclk.hw,
2205 new_cdclk_config: cdclk_config, mid_cdclk_config: &mid_cdclk_config)) {
2206 _bxt_set_cdclk(display, cdclk_config: &mid_cdclk_config, pipe);
2207 _bxt_set_cdclk(display, cdclk_config, pipe);
2208 } else {
2209 _bxt_set_cdclk(display, cdclk_config, pipe);
2210 }
2211
2212 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
2213 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2214
2215 if (DISPLAY_VER(display) >= 14)
2216 /*
2217 * NOOP - No Pcode communication needed for
2218 * Display versions 14 and beyond
2219 */;
2220 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
2221 ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
2222 cdclk_config->voltage_level);
2223 if (DISPLAY_VER(display) < 11) {
2224 /*
2225 * The timeout isn't specified, the 2ms used here is based on
2226 * experiment.
2227 * FIXME: Waiting for the request completion could be delayed
2228 * until the next PCODE request based on BSpec.
2229 */
2230 ret = intel_pcode_write_timeout(drm: display->drm,
2231 HSW_PCODE_DE_WRITE_FREQ_REQ,
2232 val: cdclk_config->voltage_level, timeout_ms: 2);
2233 }
2234 if (ret) {
2235 drm_err(display->drm,
2236 "PCode CDCLK freq set failed, (err %d, freq %d)\n",
2237 ret, cdclk);
2238 return;
2239 }
2240
2241 intel_update_cdclk(display);
2242
2243 if (DISPLAY_VER(display) >= 11)
2244 /*
2245 * Can't read out the voltage level :(
2246 * Let's just assume everything is as expected.
2247 */
2248 display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
2249}
2250
2251static void bxt_sanitize_cdclk(struct intel_display *display)
2252{
2253 u32 cdctl, expected;
2254 int cdclk, vco;
2255
2256 intel_update_cdclk(display);
2257 intel_cdclk_dump_config(display, cdclk_config: &display->cdclk.hw, context: "Current CDCLK");
2258
2259 if (display->cdclk.hw.vco == 0 ||
2260 display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
2261 goto sanitize;
2262
2263 /* Make sure this is a legal cdclk value for the platform */
2264 cdclk = bxt_calc_cdclk(display, min_cdclk: display->cdclk.hw.cdclk);
2265 if (cdclk != display->cdclk.hw.cdclk)
2266 goto sanitize;
2267
2268 /* Make sure the VCO is correct for the cdclk */
2269 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
2270 if (vco != display->cdclk.hw.vco)
2271 goto sanitize;
2272
2273 /*
2274 * Some BIOS versions leave an incorrect decimal frequency value and
2275 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
2276 * so sanitize this register.
2277 */
2278 cdctl = intel_de_read(display, CDCLK_CTL);
2279 expected = bxt_cdclk_ctl(display, cdclk_config: &display->cdclk.hw, pipe: INVALID_PIPE);
2280
2281 /*
2282 * Let's ignore the pipe field, since BIOS could have configured the
2283 * dividers both syncing to an active pipe, or asynchronously
2284 * (PIPE_NONE).
2285 */
2286 cdctl &= ~bxt_cdclk_cd2x_pipe(display, pipe: INVALID_PIPE);
2287 expected &= ~bxt_cdclk_cd2x_pipe(display, pipe: INVALID_PIPE);
2288
2289 if (cdctl == expected)
2290 /* All well; nothing to sanitize */
2291 return;
2292
2293sanitize:
2294 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
2295
2296 /* force cdclk programming */
2297 display->cdclk.hw.cdclk = 0;
2298
2299 /* force full PLL disable + enable */
2300 display->cdclk.hw.vco = ~0;
2301}
2302
2303static void bxt_cdclk_init_hw(struct intel_display *display)
2304{
2305 struct intel_cdclk_config cdclk_config;
2306
2307 bxt_sanitize_cdclk(display);
2308
2309 if (display->cdclk.hw.cdclk != 0 &&
2310 display->cdclk.hw.vco != 0)
2311 return;
2312
2313 cdclk_config = display->cdclk.hw;
2314
2315 /*
2316 * FIXME:
2317 * - The initial CDCLK needs to be read from VBT.
2318 * Need to make this change after VBT has changes for BXT.
2319 */
2320 cdclk_config.cdclk = bxt_calc_cdclk(display, min_cdclk: 0);
2321 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk: cdclk_config.cdclk);
2322 cdclk_config.voltage_level =
2323 intel_cdclk_calc_voltage_level(display, cdclk: cdclk_config.cdclk);
2324
2325 bxt_set_cdclk(display, cdclk_config: &cdclk_config, pipe: INVALID_PIPE);
2326}
2327
2328static void bxt_cdclk_uninit_hw(struct intel_display *display)
2329{
2330 struct intel_cdclk_config cdclk_config = display->cdclk.hw;
2331
2332 cdclk_config.cdclk = cdclk_config.bypass;
2333 cdclk_config.vco = 0;
2334 cdclk_config.voltage_level =
2335 intel_cdclk_calc_voltage_level(display, cdclk: cdclk_config.cdclk);
2336
2337 bxt_set_cdclk(display, cdclk_config: &cdclk_config, pipe: INVALID_PIPE);
2338}
2339
2340/**
2341 * intel_cdclk_init_hw - Initialize CDCLK hardware
2342 * @display: display instance
2343 *
2344 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2345 * sanitizing the state of the hardware if needed. This is generally done only
2346 * during the display core initialization sequence, after which the DMC will
2347 * take care of turning CDCLK off/on as needed.
2348 */
2349void intel_cdclk_init_hw(struct intel_display *display)
2350{
2351 if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2352 bxt_cdclk_init_hw(display);
2353 else if (DISPLAY_VER(display) == 9)
2354 skl_cdclk_init_hw(display);
2355}
2356
2357/**
2358 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2359 * @display: display instance
2360 *
2361 * Uninitialize CDCLK. This is done only during the display core
2362 * uninitialization sequence.
2363 */
2364void intel_cdclk_uninit_hw(struct intel_display *display)
2365{
2366 if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2367 bxt_cdclk_uninit_hw(display);
2368 else if (DISPLAY_VER(display) == 9)
2369 skl_cdclk_uninit_hw(display);
2370}
2371
2372static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,
2373 const struct intel_cdclk_config *a,
2374 const struct intel_cdclk_config *b)
2375{
2376 u16 old_waveform;
2377 u16 new_waveform;
2378
2379 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
2380
2381 if (a->vco == 0 || b->vco == 0)
2382 return false;
2383
2384 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
2385 return false;
2386
2387 old_waveform = cdclk_squash_waveform(display, cdclk: a->cdclk);
2388 new_waveform = cdclk_squash_waveform(display, cdclk: b->cdclk);
2389
2390 return a->vco != b->vco &&
2391 old_waveform != new_waveform;
2392}
2393
2394static bool intel_cdclk_can_crawl(struct intel_display *display,
2395 const struct intel_cdclk_config *a,
2396 const struct intel_cdclk_config *b)
2397{
2398 int a_div, b_div;
2399
2400 if (!HAS_CDCLK_CRAWL(display))
2401 return false;
2402
2403 /*
2404 * The vco and cd2x divider will change independently
2405 * from each, so we disallow cd2x change when crawling.
2406 */
2407 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2408 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2409
2410 return a->vco != 0 && b->vco != 0 &&
2411 a->vco != b->vco &&
2412 a_div == b_div &&
2413 a->ref == b->ref;
2414}
2415
2416static bool intel_cdclk_can_squash(struct intel_display *display,
2417 const struct intel_cdclk_config *a,
2418 const struct intel_cdclk_config *b)
2419{
2420 /*
2421 * FIXME should store a bit more state in intel_cdclk_config
2422 * to differentiate squasher vs. cd2x divider properly. For
2423 * the moment all platforms with squasher use a fixed cd2x
2424 * divider.
2425 */
2426 if (!HAS_CDCLK_SQUASH(display))
2427 return false;
2428
2429 return a->cdclk != b->cdclk &&
2430 a->vco != 0 &&
2431 a->vco == b->vco &&
2432 a->ref == b->ref;
2433}
2434
2435/**
2436 * intel_cdclk_clock_changed - Check whether the clock changed
2437 * @a: first CDCLK configuration
2438 * @b: second CDCLK configuration
2439 *
2440 * Returns:
2441 * True if CDCLK changed in a way that requires re-programming and
2442 * False otherwise.
2443 */
2444bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
2445 const struct intel_cdclk_config *b)
2446{
2447 return a->cdclk != b->cdclk ||
2448 a->vco != b->vco ||
2449 a->ref != b->ref;
2450}
2451
2452/**
2453 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2454 * configurations requires only a cd2x divider update
2455 * @display: display instance
2456 * @a: first CDCLK configuration
2457 * @b: second CDCLK configuration
2458 *
2459 * Returns:
2460 * True if changing between the two CDCLK configurations
2461 * can be done with just a cd2x divider update, false if not.
2462 */
2463static bool intel_cdclk_can_cd2x_update(struct intel_display *display,
2464 const struct intel_cdclk_config *a,
2465 const struct intel_cdclk_config *b)
2466{
2467 /* Older hw doesn't have the capability */
2468 if (DISPLAY_VER(display) < 10 && !display->platform.broxton)
2469 return false;
2470
2471 /*
2472 * FIXME should store a bit more state in intel_cdclk_config
2473 * to differentiate squasher vs. cd2x divider properly. For
2474 * the moment all platforms with squasher use a fixed cd2x
2475 * divider.
2476 */
2477 if (HAS_CDCLK_SQUASH(display))
2478 return false;
2479
2480 return a->cdclk != b->cdclk &&
2481 a->vco != 0 &&
2482 a->vco == b->vco &&
2483 a->ref == b->ref;
2484}
2485
2486/**
2487 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2488 * @a: first CDCLK configuration
2489 * @b: second CDCLK configuration
2490 *
2491 * Returns:
2492 * True if the CDCLK configurations don't match, false if they do.
2493 */
2494static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
2495 const struct intel_cdclk_config *b)
2496{
2497 return intel_cdclk_clock_changed(a, b) ||
2498 a->voltage_level != b->voltage_level;
2499}
2500
2501void intel_cdclk_dump_config(struct intel_display *display,
2502 const struct intel_cdclk_config *cdclk_config,
2503 const char *context)
2504{
2505 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2506 context, cdclk_config->cdclk, cdclk_config->vco,
2507 cdclk_config->ref, cdclk_config->bypass,
2508 cdclk_config->voltage_level);
2509}
2510
2511static void intel_pcode_notify(struct intel_display *display,
2512 u8 voltage_level,
2513 u8 active_pipe_count,
2514 u16 cdclk,
2515 bool cdclk_update_valid,
2516 bool pipe_count_update_valid)
2517{
2518 int ret;
2519 u32 update_mask = 0;
2520
2521 if (!display->platform.dg2)
2522 return;
2523
2524 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
2525
2526 if (cdclk_update_valid)
2527 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID;
2528
2529 if (pipe_count_update_valid)
2530 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
2531
2532 ret = intel_pcode_request(drm: display->drm, SKL_PCODE_CDCLK_CONTROL,
2533 SKL_CDCLK_PREPARE_FOR_CHANGE |
2534 update_mask,
2535 SKL_CDCLK_READY_FOR_CHANGE,
2536 SKL_CDCLK_READY_FOR_CHANGE, timeout_base_ms: 3);
2537 if (ret)
2538 drm_err(display->drm,
2539 "Failed to inform PCU about display config (err %d)\n",
2540 ret);
2541}
2542
2543static void intel_set_cdclk(struct intel_display *display,
2544 const struct intel_cdclk_config *cdclk_config,
2545 enum pipe pipe, const char *context)
2546{
2547 struct intel_encoder *encoder;
2548
2549 if (!intel_cdclk_changed(a: &display->cdclk.hw, b: cdclk_config))
2550 return;
2551
2552 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))
2553 return;
2554
2555 intel_cdclk_dump_config(display, cdclk_config, context);
2556
2557 for_each_intel_encoder_with_psr(display->drm, encoder) {
2558 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2559
2560 intel_psr_pause(intel_dp);
2561 }
2562
2563 intel_audio_cdclk_change_pre(display);
2564
2565 /*
2566 * Lock aux/gmbus while we change cdclk in case those
2567 * functions use cdclk. Not all platforms/ports do,
2568 * but we'll lock them all for simplicity.
2569 */
2570 mutex_lock(lock: &display->gmbus.mutex);
2571 for_each_intel_dp(display->drm, encoder) {
2572 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2573
2574 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
2575 &display->gmbus.mutex);
2576 }
2577
2578 intel_cdclk_set_cdclk(display, cdclk_config, pipe);
2579
2580 for_each_intel_dp(display->drm, encoder) {
2581 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2582
2583 mutex_unlock(lock: &intel_dp->aux.hw_mutex);
2584 }
2585 mutex_unlock(lock: &display->gmbus.mutex);
2586
2587 for_each_intel_encoder_with_psr(display->drm, encoder) {
2588 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2589
2590 intel_psr_resume(intel_dp);
2591 }
2592
2593 intel_audio_cdclk_change_post(display);
2594
2595 if (drm_WARN(display->drm,
2596 intel_cdclk_changed(&display->cdclk.hw, cdclk_config),
2597 "cdclk state doesn't match!\n")) {
2598 intel_cdclk_dump_config(display, cdclk_config: &display->cdclk.hw, context: "[hw state]");
2599 intel_cdclk_dump_config(display, cdclk_config, context: "[sw state]");
2600 }
2601}
2602
2603static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
2604{
2605 struct intel_display *display = to_intel_display(state);
2606 const struct intel_cdclk_state *old_cdclk_state =
2607 intel_atomic_get_old_cdclk_state(state);
2608 const struct intel_cdclk_state *new_cdclk_state =
2609 intel_atomic_get_new_cdclk_state(state);
2610 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2611 bool change_cdclk, update_pipe_count;
2612
2613 if (!intel_cdclk_changed(a: &old_cdclk_state->actual,
2614 b: &new_cdclk_state->actual) &&
2615 new_cdclk_state->active_pipes ==
2616 old_cdclk_state->active_pipes)
2617 return;
2618
2619 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */
2620 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX;
2621
2622 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2623 update_pipe_count = hweight8(new_cdclk_state->active_pipes) >
2624 hweight8(old_cdclk_state->active_pipes);
2625
2626 /*
2627 * According to "Sequence Before Frequency Change",
2628 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK,
2629 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
2630 * which basically means we choose the maximum of old and new CDCLK, if we know both
2631 */
2632 if (change_cdclk)
2633 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2634
2635 /*
2636 * According to "Sequence For Pipe Count Change",
2637 * if pipe count is increasing, set bits 25:16 to upcoming pipe count
2638 * (power well is enabled)
2639 * no action if it is decreasing, before the change
2640 */
2641 if (update_pipe_count)
2642 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2643
2644 intel_pcode_notify(display, voltage_level, active_pipe_count: num_active_pipes, cdclk,
2645 cdclk_update_valid: change_cdclk, pipe_count_update_valid: update_pipe_count);
2646}
2647
2648static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
2649{
2650 struct intel_display *display = to_intel_display(state);
2651 const struct intel_cdclk_state *new_cdclk_state =
2652 intel_atomic_get_new_cdclk_state(state);
2653 const struct intel_cdclk_state *old_cdclk_state =
2654 intel_atomic_get_old_cdclk_state(state);
2655 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2656 bool update_cdclk, update_pipe_count;
2657
2658 /* According to "Sequence After Frequency Change", set voltage to used level */
2659 voltage_level = new_cdclk_state->actual.voltage_level;
2660
2661 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2662 update_pipe_count = hweight8(new_cdclk_state->active_pipes) <
2663 hweight8(old_cdclk_state->active_pipes);
2664
2665 /*
2666 * According to "Sequence After Frequency Change",
2667 * set bits 25:16 to current CDCLK
2668 */
2669 if (update_cdclk)
2670 cdclk = new_cdclk_state->actual.cdclk;
2671
2672 /*
2673 * According to "Sequence For Pipe Count Change",
2674 * if pipe count is decreasing, set bits 25:16 to current pipe count,
2675 * after the change(power well is disabled)
2676 * no action if it is increasing, after the change
2677 */
2678 if (update_pipe_count)
2679 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2680
2681 intel_pcode_notify(display, voltage_level, active_pipe_count: num_active_pipes, cdclk,
2682 cdclk_update_valid: update_cdclk, pipe_count_update_valid: update_pipe_count);
2683}
2684
2685bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
2686{
2687 const struct intel_cdclk_state *old_cdclk_state =
2688 intel_atomic_get_old_cdclk_state(state);
2689 const struct intel_cdclk_state *new_cdclk_state =
2690 intel_atomic_get_new_cdclk_state(state);
2691
2692 return new_cdclk_state && !new_cdclk_state->disable_pipes &&
2693 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
2694}
2695
2696/**
2697 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2698 * @state: intel atomic state
2699 *
2700 * Program the hardware before updating the HW plane state based on the
2701 * new CDCLK state, if necessary.
2702 */
2703void
2704intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
2705{
2706 struct intel_display *display = to_intel_display(state);
2707 const struct intel_cdclk_state *old_cdclk_state =
2708 intel_atomic_get_old_cdclk_state(state);
2709 const struct intel_cdclk_state *new_cdclk_state =
2710 intel_atomic_get_new_cdclk_state(state);
2711 struct intel_cdclk_config cdclk_config;
2712 enum pipe pipe;
2713
2714 if (!intel_cdclk_changed(a: &old_cdclk_state->actual,
2715 b: &new_cdclk_state->actual))
2716 return;
2717
2718 if (display->platform.dg2)
2719 intel_cdclk_pcode_pre_notify(state);
2720
2721 if (new_cdclk_state->disable_pipes) {
2722 cdclk_config = new_cdclk_state->actual;
2723 pipe = INVALID_PIPE;
2724 } else {
2725 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
2726 cdclk_config = new_cdclk_state->actual;
2727 pipe = new_cdclk_state->pipe;
2728 } else {
2729 cdclk_config = old_cdclk_state->actual;
2730 pipe = INVALID_PIPE;
2731 }
2732
2733 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
2734 old_cdclk_state->actual.voltage_level);
2735 }
2736
2737 /*
2738 * mbus joining will be changed later by
2739 * intel_dbuf_mbus_{pre,post}_ddb_update()
2740 */
2741 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
2742
2743 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2744
2745 intel_set_cdclk(display, cdclk_config: &cdclk_config, pipe,
2746 context: "Pre changing CDCLK to");
2747}
2748
2749/**
2750 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2751 * @state: intel atomic state
2752 *
2753 * Program the hardware after updating the HW plane state based on the
2754 * new CDCLK state, if necessary.
2755 */
2756void
2757intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2758{
2759 struct intel_display *display = to_intel_display(state);
2760 const struct intel_cdclk_state *old_cdclk_state =
2761 intel_atomic_get_old_cdclk_state(state);
2762 const struct intel_cdclk_state *new_cdclk_state =
2763 intel_atomic_get_new_cdclk_state(state);
2764 enum pipe pipe;
2765
2766 if (!intel_cdclk_changed(a: &old_cdclk_state->actual,
2767 b: &new_cdclk_state->actual))
2768 return;
2769
2770 if (display->platform.dg2)
2771 intel_cdclk_pcode_post_notify(state);
2772
2773 if (!new_cdclk_state->disable_pipes &&
2774 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
2775 pipe = new_cdclk_state->pipe;
2776 else
2777 pipe = INVALID_PIPE;
2778
2779 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2780
2781 intel_set_cdclk(display, cdclk_config: &new_cdclk_state->actual, pipe,
2782 context: "Post changing CDCLK to");
2783}
2784
2785/* pixels per CDCLK */
2786static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
2787{
2788 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;
2789}
2790
2791/* max pixel rate as % of CDCLK (not accounting for PPC) */
2792static int intel_cdclk_guardband(struct intel_display *display)
2793{
2794 if (DISPLAY_VER(display) >= 9 ||
2795 display->platform.broadwell || display->platform.haswell)
2796 return 100;
2797 else if (display->platform.cherryview)
2798 return 95;
2799 else
2800 return 90;
2801}
2802
2803static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2804{
2805 struct intel_display *display = to_intel_display(crtc_state);
2806 int ppc = intel_cdclk_ppc(display, double_wide: crtc_state->double_wide);
2807 int guardband = intel_cdclk_guardband(display);
2808 int pixel_rate = crtc_state->pixel_rate;
2809
2810 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc);
2811}
2812
2813static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
2814{
2815 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2816 struct intel_display *display = to_intel_display(crtc);
2817 struct intel_plane *plane;
2818 int min_cdclk = 0;
2819
2820 for_each_intel_plane_on_crtc(display->drm, crtc, plane)
2821 min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);
2822
2823 return min_cdclk;
2824}
2825
2826static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2827{
2828 int min_cdclk;
2829
2830 if (!crtc_state->hw.enable)
2831 return 0;
2832
2833 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2834 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
2835 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
2836 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));
2837 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state));
2838 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
2839
2840 return min_cdclk;
2841}
2842
2843static int intel_compute_min_cdclk(struct intel_atomic_state *state)
2844{
2845 struct intel_display *display = to_intel_display(state);
2846 struct intel_cdclk_state *cdclk_state =
2847 intel_atomic_get_new_cdclk_state(state);
2848 const struct intel_bw_state *bw_state;
2849 struct intel_crtc *crtc;
2850 struct intel_crtc_state *crtc_state;
2851 int min_cdclk, i;
2852 enum pipe pipe;
2853
2854 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2855 int ret;
2856
2857 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2858 if (min_cdclk < 0)
2859 return min_cdclk;
2860
2861 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
2862 continue;
2863
2864 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
2865
2866 ret = intel_atomic_lock_global_state(obj_state: &cdclk_state->base);
2867 if (ret)
2868 return ret;
2869 }
2870
2871 bw_state = intel_atomic_get_new_bw_state(state);
2872 if (bw_state) {
2873 min_cdclk = intel_bw_min_cdclk(display, bw_state);
2874
2875 if (cdclk_state->bw_min_cdclk != min_cdclk) {
2876 int ret;
2877
2878 cdclk_state->bw_min_cdclk = min_cdclk;
2879
2880 ret = intel_atomic_lock_global_state(obj_state: &cdclk_state->base);
2881 if (ret)
2882 return ret;
2883 }
2884 }
2885
2886 min_cdclk = max(cdclk_state->force_min_cdclk,
2887 cdclk_state->bw_min_cdclk);
2888 for_each_pipe(display, pipe)
2889 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]);
2890
2891 /*
2892 * Avoid glk_force_audio_cdclk() causing excessive screen
2893 * blinking when multiple pipes are active by making sure
2894 * CDCLK frequency is always high enough for audio. With a
2895 * single active pipe we can always change CDCLK frequency
2896 * by changing the cd2x divider (see glk_cdclk_table[]) and
2897 * thus a full modeset won't be needed then.
2898 */
2899 if (display->platform.geminilake && cdclk_state->active_pipes &&
2900 !is_power_of_2(n: cdclk_state->active_pipes))
2901 min_cdclk = max(min_cdclk, 2 * 96000);
2902
2903 if (min_cdclk > display->cdclk.max_cdclk_freq) {
2904 drm_dbg_kms(display->drm,
2905 "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2906 min_cdclk, display->cdclk.max_cdclk_freq);
2907 return -EINVAL;
2908 }
2909
2910 return min_cdclk;
2911}
2912
2913/*
2914 * Account for port clock min voltage level requirements.
2915 * This only really does something on DISPLA_VER >= 11 but can be
2916 * called on earlier platforms as well.
2917 *
2918 * Note that this functions assumes that 0 is
2919 * the lowest voltage value, and higher values
2920 * correspond to increasingly higher voltages.
2921 *
2922 * Should that relationship no longer hold on
2923 * future platforms this code will need to be
2924 * adjusted.
2925 */
2926static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
2927{
2928 struct intel_display *display = to_intel_display(state);
2929 struct intel_cdclk_state *cdclk_state =
2930 intel_atomic_get_new_cdclk_state(state);
2931 struct intel_crtc *crtc;
2932 struct intel_crtc_state *crtc_state;
2933 u8 min_voltage_level;
2934 int i;
2935 enum pipe pipe;
2936
2937 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2938 int ret;
2939
2940 if (crtc_state->hw.enable)
2941 min_voltage_level = crtc_state->min_voltage_level;
2942 else
2943 min_voltage_level = 0;
2944
2945 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
2946 continue;
2947
2948 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
2949
2950 ret = intel_atomic_lock_global_state(obj_state: &cdclk_state->base);
2951 if (ret)
2952 return ret;
2953 }
2954
2955 min_voltage_level = 0;
2956 for_each_pipe(display, pipe)
2957 min_voltage_level = max(min_voltage_level,
2958 cdclk_state->min_voltage_level[pipe]);
2959
2960 return min_voltage_level;
2961}
2962
2963static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
2964{
2965 struct intel_display *display = to_intel_display(state);
2966 struct intel_cdclk_state *cdclk_state =
2967 intel_atomic_get_new_cdclk_state(state);
2968 int min_cdclk, cdclk;
2969
2970 min_cdclk = intel_compute_min_cdclk(state);
2971 if (min_cdclk < 0)
2972 return min_cdclk;
2973
2974 cdclk = vlv_calc_cdclk(display, min_cdclk);
2975
2976 cdclk_state->logical.cdclk = cdclk;
2977 cdclk_state->logical.voltage_level =
2978 vlv_calc_voltage_level(display, cdclk);
2979
2980 if (!cdclk_state->active_pipes) {
2981 cdclk = vlv_calc_cdclk(display, min_cdclk: cdclk_state->force_min_cdclk);
2982
2983 cdclk_state->actual.cdclk = cdclk;
2984 cdclk_state->actual.voltage_level =
2985 vlv_calc_voltage_level(display, cdclk);
2986 } else {
2987 cdclk_state->actual = cdclk_state->logical;
2988 }
2989
2990 return 0;
2991}
2992
2993static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
2994{
2995 struct intel_cdclk_state *cdclk_state =
2996 intel_atomic_get_new_cdclk_state(state);
2997 int min_cdclk, cdclk;
2998
2999 min_cdclk = intel_compute_min_cdclk(state);
3000 if (min_cdclk < 0)
3001 return min_cdclk;
3002
3003 cdclk = bdw_calc_cdclk(min_cdclk);
3004
3005 cdclk_state->logical.cdclk = cdclk;
3006 cdclk_state->logical.voltage_level =
3007 bdw_calc_voltage_level(cdclk);
3008
3009 if (!cdclk_state->active_pipes) {
3010 cdclk = bdw_calc_cdclk(min_cdclk: cdclk_state->force_min_cdclk);
3011
3012 cdclk_state->actual.cdclk = cdclk;
3013 cdclk_state->actual.voltage_level =
3014 bdw_calc_voltage_level(cdclk);
3015 } else {
3016 cdclk_state->actual = cdclk_state->logical;
3017 }
3018
3019 return 0;
3020}
3021
3022static int skl_dpll0_vco(struct intel_atomic_state *state)
3023{
3024 struct intel_display *display = to_intel_display(state);
3025 struct intel_cdclk_state *cdclk_state =
3026 intel_atomic_get_new_cdclk_state(state);
3027 struct intel_crtc *crtc;
3028 struct intel_crtc_state *crtc_state;
3029 int vco, i;
3030
3031 vco = cdclk_state->logical.vco;
3032 if (!vco)
3033 vco = display->cdclk.skl_preferred_vco_freq;
3034
3035 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
3036 if (!crtc_state->hw.enable)
3037 continue;
3038
3039 if (!intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_EDP))
3040 continue;
3041
3042 /*
3043 * DPLL0 VCO may need to be adjusted to get the correct
3044 * clock for eDP. This will affect cdclk as well.
3045 */
3046 switch (crtc_state->port_clock / 2) {
3047 case 108000:
3048 case 216000:
3049 vco = 8640000;
3050 break;
3051 default:
3052 vco = 8100000;
3053 break;
3054 }
3055 }
3056
3057 return vco;
3058}
3059
3060static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
3061{
3062 struct intel_cdclk_state *cdclk_state =
3063 intel_atomic_get_new_cdclk_state(state);
3064 int min_cdclk, cdclk, vco;
3065
3066 min_cdclk = intel_compute_min_cdclk(state);
3067 if (min_cdclk < 0)
3068 return min_cdclk;
3069
3070 vco = skl_dpll0_vco(state);
3071
3072 cdclk = skl_calc_cdclk(min_cdclk, vco);
3073
3074 cdclk_state->logical.vco = vco;
3075 cdclk_state->logical.cdclk = cdclk;
3076 cdclk_state->logical.voltage_level =
3077 skl_calc_voltage_level(cdclk);
3078
3079 if (!cdclk_state->active_pipes) {
3080 cdclk = skl_calc_cdclk(min_cdclk: cdclk_state->force_min_cdclk, vco);
3081
3082 cdclk_state->actual.vco = vco;
3083 cdclk_state->actual.cdclk = cdclk;
3084 cdclk_state->actual.voltage_level =
3085 skl_calc_voltage_level(cdclk);
3086 } else {
3087 cdclk_state->actual = cdclk_state->logical;
3088 }
3089
3090 return 0;
3091}
3092
3093static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
3094{
3095 struct intel_display *display = to_intel_display(state);
3096 struct intel_cdclk_state *cdclk_state =
3097 intel_atomic_get_new_cdclk_state(state);
3098 int min_cdclk, min_voltage_level, cdclk, vco;
3099
3100 min_cdclk = intel_compute_min_cdclk(state);
3101 if (min_cdclk < 0)
3102 return min_cdclk;
3103
3104 min_voltage_level = bxt_compute_min_voltage_level(state);
3105 if (min_voltage_level < 0)
3106 return min_voltage_level;
3107
3108 cdclk = bxt_calc_cdclk(display, min_cdclk);
3109 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3110
3111 cdclk_state->logical.vco = vco;
3112 cdclk_state->logical.cdclk = cdclk;
3113 cdclk_state->logical.voltage_level =
3114 max_t(int, min_voltage_level,
3115 intel_cdclk_calc_voltage_level(display, cdclk));
3116
3117 if (!cdclk_state->active_pipes) {
3118 cdclk = bxt_calc_cdclk(display, min_cdclk: cdclk_state->force_min_cdclk);
3119 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3120
3121 cdclk_state->actual.vco = vco;
3122 cdclk_state->actual.cdclk = cdclk;
3123 cdclk_state->actual.voltage_level =
3124 intel_cdclk_calc_voltage_level(display, cdclk);
3125 } else {
3126 cdclk_state->actual = cdclk_state->logical;
3127 }
3128
3129 return 0;
3130}
3131
3132static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
3133{
3134 int min_cdclk;
3135
3136 /*
3137 * We can't change the cdclk frequency, but we still want to
3138 * check that the required minimum frequency doesn't exceed
3139 * the actual cdclk frequency.
3140 */
3141 min_cdclk = intel_compute_min_cdclk(state);
3142 if (min_cdclk < 0)
3143 return min_cdclk;
3144
3145 return 0;
3146}
3147
3148static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
3149{
3150 struct intel_cdclk_state *cdclk_state;
3151
3152 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
3153 if (!cdclk_state)
3154 return NULL;
3155
3156 cdclk_state->pipe = INVALID_PIPE;
3157 cdclk_state->disable_pipes = false;
3158
3159 return &cdclk_state->base;
3160}
3161
3162static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
3163 struct intel_global_state *state)
3164{
3165 kfree(objp: state);
3166}
3167
3168static const struct intel_global_state_funcs intel_cdclk_funcs = {
3169 .atomic_duplicate_state = intel_cdclk_duplicate_state,
3170 .atomic_destroy_state = intel_cdclk_destroy_state,
3171};
3172
3173struct intel_cdclk_state *
3174intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
3175{
3176 struct intel_display *display = to_intel_display(state);
3177 struct intel_global_state *cdclk_state;
3178
3179 cdclk_state = intel_atomic_get_global_obj_state(state, obj: &display->cdclk.obj);
3180 if (IS_ERR(ptr: cdclk_state))
3181 return ERR_CAST(ptr: cdclk_state);
3182
3183 return to_intel_cdclk_state(cdclk_state);
3184}
3185
3186int intel_cdclk_atomic_check(struct intel_atomic_state *state,
3187 bool *need_cdclk_calc)
3188{
3189 const struct intel_cdclk_state *old_cdclk_state;
3190 const struct intel_cdclk_state *new_cdclk_state;
3191 struct intel_plane_state __maybe_unused *plane_state;
3192 struct intel_plane *plane;
3193 int ret;
3194 int i;
3195
3196 /*
3197 * active_planes bitmask has been updated, and potentially affected
3198 * planes are part of the state. We can now compute the minimum cdclk
3199 * for each plane.
3200 */
3201 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3202 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
3203 if (ret)
3204 return ret;
3205 }
3206
3207 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc);
3208 if (ret)
3209 return ret;
3210
3211 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3212 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
3213
3214 if (new_cdclk_state &&
3215 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
3216 *need_cdclk_calc = true;
3217
3218 return 0;
3219}
3220
3221int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus)
3222{
3223 struct intel_cdclk_state *cdclk_state;
3224
3225 cdclk_state = intel_atomic_get_cdclk_state(state);
3226 if (IS_ERR(ptr: cdclk_state))
3227 return PTR_ERR(ptr: cdclk_state);
3228
3229 cdclk_state->actual.joined_mbus = joined_mbus;
3230 cdclk_state->logical.joined_mbus = joined_mbus;
3231
3232 return intel_atomic_lock_global_state(obj_state: &cdclk_state->base);
3233}
3234
3235int intel_cdclk_init(struct intel_display *display)
3236{
3237 struct intel_cdclk_state *cdclk_state;
3238
3239 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
3240 if (!cdclk_state)
3241 return -ENOMEM;
3242
3243 intel_atomic_global_obj_init(display, obj: &display->cdclk.obj,
3244 state: &cdclk_state->base, funcs: &intel_cdclk_funcs);
3245
3246 return 0;
3247}
3248
3249static bool intel_cdclk_need_serialize(struct intel_display *display,
3250 const struct intel_cdclk_state *old_cdclk_state,
3251 const struct intel_cdclk_state *new_cdclk_state)
3252{
3253 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
3254 hweight8(new_cdclk_state->active_pipes);
3255 bool cdclk_changed = intel_cdclk_changed(a: &old_cdclk_state->actual,
3256 b: &new_cdclk_state->actual);
3257 /*
3258 * We need to poke hw for gen >= 12, because we notify PCode if
3259 * pipe power well count changes.
3260 */
3261 return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed);
3262}
3263
3264int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
3265{
3266 struct intel_display *display = to_intel_display(state);
3267 const struct intel_cdclk_state *old_cdclk_state;
3268 struct intel_cdclk_state *new_cdclk_state;
3269 enum pipe pipe = INVALID_PIPE;
3270 int ret;
3271
3272 new_cdclk_state = intel_atomic_get_cdclk_state(state);
3273 if (IS_ERR(ptr: new_cdclk_state))
3274 return PTR_ERR(ptr: new_cdclk_state);
3275
3276 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3277
3278 new_cdclk_state->active_pipes =
3279 intel_calc_active_pipes(state, active_pipes: old_cdclk_state->active_pipes);
3280
3281 ret = intel_cdclk_modeset_calc_cdclk(state);
3282 if (ret)
3283 return ret;
3284
3285 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {
3286 /*
3287 * Also serialize commits across all crtcs
3288 * if the actual hw needs to be poked.
3289 */
3290 ret = intel_atomic_serialize_global_state(obj_state: &new_cdclk_state->base);
3291 if (ret)
3292 return ret;
3293 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
3294 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
3295 intel_cdclk_changed(a: &old_cdclk_state->logical,
3296 b: &new_cdclk_state->logical)) {
3297 ret = intel_atomic_lock_global_state(obj_state: &new_cdclk_state->base);
3298 if (ret)
3299 return ret;
3300 } else {
3301 return 0;
3302 }
3303
3304 if (is_power_of_2(n: new_cdclk_state->active_pipes) &&
3305 intel_cdclk_can_cd2x_update(display,
3306 a: &old_cdclk_state->actual,
3307 b: &new_cdclk_state->actual)) {
3308 struct intel_crtc *crtc;
3309 struct intel_crtc_state *crtc_state;
3310
3311 pipe = ilog2(new_cdclk_state->active_pipes);
3312 crtc = intel_crtc_for_pipe(display, pipe);
3313
3314 crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
3315 if (IS_ERR(ptr: crtc_state))
3316 return PTR_ERR(ptr: crtc_state);
3317
3318 if (intel_crtc_needs_modeset(crtc_state))
3319 pipe = INVALID_PIPE;
3320 }
3321
3322 if (intel_cdclk_can_crawl_and_squash(display,
3323 a: &old_cdclk_state->actual,
3324 b: &new_cdclk_state->actual)) {
3325 drm_dbg_kms(display->drm,
3326 "Can change cdclk via crawling and squashing\n");
3327 } else if (intel_cdclk_can_squash(display,
3328 a: &old_cdclk_state->actual,
3329 b: &new_cdclk_state->actual)) {
3330 drm_dbg_kms(display->drm,
3331 "Can change cdclk via squashing\n");
3332 } else if (intel_cdclk_can_crawl(display,
3333 a: &old_cdclk_state->actual,
3334 b: &new_cdclk_state->actual)) {
3335 drm_dbg_kms(display->drm,
3336 "Can change cdclk via crawling\n");
3337 } else if (pipe != INVALID_PIPE) {
3338 new_cdclk_state->pipe = pipe;
3339
3340 drm_dbg_kms(display->drm,
3341 "Can change cdclk cd2x divider with pipe %c active\n",
3342 pipe_name(pipe));
3343 } else if (intel_cdclk_clock_changed(a: &old_cdclk_state->actual,
3344 b: &new_cdclk_state->actual)) {
3345 /* All pipes must be switched off while we change the cdclk. */
3346 ret = intel_modeset_all_pipes_late(state, reason: "CDCLK change");
3347 if (ret)
3348 return ret;
3349
3350 new_cdclk_state->disable_pipes = true;
3351
3352 drm_dbg_kms(display->drm,
3353 "Modeset required for cdclk change\n");
3354 }
3355
3356 if (intel_mdclk_cdclk_ratio(display, cdclk_config: &old_cdclk_state->actual) !=
3357 intel_mdclk_cdclk_ratio(display, cdclk_config: &new_cdclk_state->actual)) {
3358 int ratio = intel_mdclk_cdclk_ratio(display, cdclk_config: &new_cdclk_state->actual);
3359
3360 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
3361 if (ret)
3362 return ret;
3363 }
3364
3365 drm_dbg_kms(display->drm,
3366 "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3367 new_cdclk_state->logical.cdclk,
3368 new_cdclk_state->actual.cdclk);
3369 drm_dbg_kms(display->drm,
3370 "New voltage level calculated to be logical %u, actual %u\n",
3371 new_cdclk_state->logical.voltage_level,
3372 new_cdclk_state->actual.voltage_level);
3373
3374 return 0;
3375}
3376
3377void intel_cdclk_update_hw_state(struct intel_display *display)
3378{
3379 const struct intel_bw_state *bw_state =
3380 to_intel_bw_state(obj_state: display->bw.obj.state);
3381 struct intel_cdclk_state *cdclk_state =
3382 to_intel_cdclk_state(display->cdclk.obj.state);
3383 struct intel_crtc *crtc;
3384
3385 cdclk_state->active_pipes = 0;
3386
3387 for_each_intel_crtc(display->drm, crtc) {
3388 const struct intel_crtc_state *crtc_state =
3389 to_intel_crtc_state(crtc->base.state);
3390 enum pipe pipe = crtc->pipe;
3391
3392 if (crtc_state->hw.active)
3393 cdclk_state->active_pipes |= BIT(pipe);
3394
3395 cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state);
3396 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
3397 }
3398
3399 cdclk_state->bw_min_cdclk = intel_bw_min_cdclk(display, bw_state);
3400}
3401
3402void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc)
3403{
3404 struct intel_display *display = to_intel_display(crtc);
3405
3406 intel_cdclk_update_hw_state(display);
3407}
3408
3409static int intel_compute_max_dotclk(struct intel_display *display)
3410{
3411 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));
3412 int guardband = intel_cdclk_guardband(display);
3413 int max_cdclk_freq = display->cdclk.max_cdclk_freq;
3414
3415 return ppc * max_cdclk_freq * guardband / 100;
3416}
3417
3418/**
3419 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3420 * @display: display instance
3421 *
3422 * Determine the maximum CDCLK frequency the platform supports, and also
3423 * derive the maximum dot clock frequency the maximum CDCLK frequency
3424 * allows.
3425 */
3426void intel_update_max_cdclk(struct intel_display *display)
3427{
3428 if (DISPLAY_VERx100(display) >= 3002) {
3429 display->cdclk.max_cdclk_freq = 480000;
3430 } else if (DISPLAY_VER(display) >= 30) {
3431 display->cdclk.max_cdclk_freq = 691200;
3432 } else if (display->platform.jasperlake || display->platform.elkhartlake) {
3433 if (display->cdclk.hw.ref == 24000)
3434 display->cdclk.max_cdclk_freq = 552000;
3435 else
3436 display->cdclk.max_cdclk_freq = 556800;
3437 } else if (DISPLAY_VER(display) >= 11) {
3438 if (display->cdclk.hw.ref == 24000)
3439 display->cdclk.max_cdclk_freq = 648000;
3440 else
3441 display->cdclk.max_cdclk_freq = 652800;
3442 } else if (display->platform.geminilake) {
3443 display->cdclk.max_cdclk_freq = 316800;
3444 } else if (display->platform.broxton) {
3445 display->cdclk.max_cdclk_freq = 624000;
3446 } else if (DISPLAY_VER(display) == 9) {
3447 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
3448 int max_cdclk, vco;
3449
3450 vco = display->cdclk.skl_preferred_vco_freq;
3451 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
3452
3453 /*
3454 * Use the lower (vco 8640) cdclk values as a
3455 * first guess. skl_calc_cdclk() will correct it
3456 * if the preferred vco is 8100 instead.
3457 */
3458 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
3459 max_cdclk = 617143;
3460 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
3461 max_cdclk = 540000;
3462 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
3463 max_cdclk = 432000;
3464 else
3465 max_cdclk = 308571;
3466
3467 display->cdclk.max_cdclk_freq = skl_calc_cdclk(min_cdclk: max_cdclk, vco);
3468 } else if (display->platform.broadwell) {
3469 /*
3470 * FIXME with extra cooling we can allow
3471 * 540 MHz for ULX and 675 Mhz for ULT.
3472 * How can we know if extra cooling is
3473 * available? PCI ID, VTB, something else?
3474 */
3475 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
3476 display->cdclk.max_cdclk_freq = 450000;
3477 else if (display->platform.broadwell_ulx)
3478 display->cdclk.max_cdclk_freq = 450000;
3479 else if (display->platform.broadwell_ult)
3480 display->cdclk.max_cdclk_freq = 540000;
3481 else
3482 display->cdclk.max_cdclk_freq = 675000;
3483 } else if (display->platform.cherryview) {
3484 display->cdclk.max_cdclk_freq = 320000;
3485 } else if (display->platform.valleyview) {
3486 display->cdclk.max_cdclk_freq = 400000;
3487 } else {
3488 /* otherwise assume cdclk is fixed */
3489 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;
3490 }
3491
3492 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);
3493
3494 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",
3495 display->cdclk.max_cdclk_freq);
3496
3497 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",
3498 display->cdclk.max_dotclk_freq);
3499}
3500
3501/**
3502 * intel_update_cdclk - Determine the current CDCLK frequency
3503 * @display: display instance
3504 *
3505 * Determine the current CDCLK frequency.
3506 */
3507void intel_update_cdclk(struct intel_display *display)
3508{
3509 intel_cdclk_get_cdclk(display, cdclk_config: &display->cdclk.hw);
3510
3511 /*
3512 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
3513 * Programmng [sic] note: bit[9:2] should be programmed to the number
3514 * of cdclk that generates 4MHz reference clock freq which is used to
3515 * generate GMBus clock. This will vary with the cdclk freq.
3516 */
3517 if (display->platform.valleyview || display->platform.cherryview)
3518 intel_de_write(display, GMBUSFREQ_VLV,
3519 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));
3520}
3521
3522static int dg1_rawclk(struct intel_display *display)
3523{
3524 /*
3525 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
3526 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
3527 */
3528 intel_de_write(display, PCH_RAWCLK_FREQ,
3529 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
3530
3531 return 38400;
3532}
3533
3534static int cnp_rawclk(struct intel_display *display)
3535{
3536 int divider, fraction;
3537 u32 rawclk;
3538
3539 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
3540 /* 24 MHz */
3541 divider = 24000;
3542 fraction = 0;
3543 } else {
3544 /* 19.2 MHz */
3545 divider = 19000;
3546 fraction = 200;
3547 }
3548
3549 rawclk = CNP_RAWCLK_DIV(divider / 1000);
3550 if (fraction) {
3551 int numerator = 1;
3552
3553 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
3554 fraction) - 1);
3555 if (INTEL_PCH_TYPE(display) >= PCH_ICP)
3556 rawclk |= ICP_RAWCLK_NUM(numerator);
3557 }
3558
3559 intel_de_write(display, PCH_RAWCLK_FREQ, val: rawclk);
3560 return divider + fraction;
3561}
3562
3563static int pch_rawclk(struct intel_display *display)
3564{
3565 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
3566}
3567
3568static int vlv_hrawclk(struct intel_display *display)
3569{
3570 /* RAWCLK_FREQ_VLV register updated from power well code */
3571 return vlv_get_cck_clock_hpll(drm: display->drm, name: "hrawclk",
3572 CCK_DISPLAY_REF_CLOCK_CONTROL);
3573}
3574
3575static int i9xx_hrawclk(struct intel_display *display)
3576{
3577 struct drm_i915_private *i915 = to_i915(dev: display->drm);
3578
3579 /* hrawclock is 1/4 the FSB frequency */
3580 return DIV_ROUND_CLOSEST(intel_fsb_freq(i915), 4);
3581}
3582
3583/**
3584 * intel_read_rawclk - Determine the current RAWCLK frequency
3585 * @display: display instance
3586 *
3587 * Determine the current RAWCLK frequency. RAWCLK is a fixed
3588 * frequency clock so this needs to done only once.
3589 */
3590u32 intel_read_rawclk(struct intel_display *display)
3591{
3592 u32 freq;
3593
3594 if (INTEL_PCH_TYPE(display) >= PCH_MTL)
3595 /*
3596 * MTL always uses a 38.4 MHz rawclk. The bspec tells us
3597 * "RAWCLK_FREQ defaults to the values for 38.4 and does
3598 * not need to be programmed."
3599 */
3600 freq = 38400;
3601 else if (INTEL_PCH_TYPE(display) >= PCH_DG1)
3602 freq = dg1_rawclk(display);
3603 else if (INTEL_PCH_TYPE(display) >= PCH_CNP)
3604 freq = cnp_rawclk(display);
3605 else if (HAS_PCH_SPLIT(display))
3606 freq = pch_rawclk(display);
3607 else if (display->platform.valleyview || display->platform.cherryview)
3608 freq = vlv_hrawclk(display);
3609 else if (DISPLAY_VER(display) >= 3)
3610 freq = i9xx_hrawclk(display);
3611 else
3612 /* no rawclk on other platforms, or no need to know it */
3613 return 0;
3614
3615 return freq;
3616}
3617
3618static int i915_cdclk_info_show(struct seq_file *m, void *unused)
3619{
3620 struct intel_display *display = m->private;
3621
3622 seq_printf(m, fmt: "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);
3623 seq_printf(m, fmt: "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);
3624 seq_printf(m, fmt: "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);
3625
3626 return 0;
3627}
3628
3629DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
3630
3631void intel_cdclk_debugfs_register(struct intel_display *display)
3632{
3633 debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root,
3634 display, &i915_cdclk_info_fops);
3635}
3636
3637static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = {
3638 .get_cdclk = bxt_get_cdclk,
3639 .set_cdclk = bxt_set_cdclk,
3640 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3641 .calc_voltage_level = xe3lpd_calc_voltage_level,
3642};
3643
3644static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
3645 .get_cdclk = bxt_get_cdclk,
3646 .set_cdclk = bxt_set_cdclk,
3647 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3648 .calc_voltage_level = rplu_calc_voltage_level,
3649};
3650
3651static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
3652 .get_cdclk = bxt_get_cdclk,
3653 .set_cdclk = bxt_set_cdclk,
3654 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3655 .calc_voltage_level = tgl_calc_voltage_level,
3656};
3657
3658static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
3659 .get_cdclk = bxt_get_cdclk,
3660 .set_cdclk = bxt_set_cdclk,
3661 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3662 .calc_voltage_level = ehl_calc_voltage_level,
3663};
3664
3665static const struct intel_cdclk_funcs icl_cdclk_funcs = {
3666 .get_cdclk = bxt_get_cdclk,
3667 .set_cdclk = bxt_set_cdclk,
3668 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3669 .calc_voltage_level = icl_calc_voltage_level,
3670};
3671
3672static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
3673 .get_cdclk = bxt_get_cdclk,
3674 .set_cdclk = bxt_set_cdclk,
3675 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3676 .calc_voltage_level = bxt_calc_voltage_level,
3677};
3678
3679static const struct intel_cdclk_funcs skl_cdclk_funcs = {
3680 .get_cdclk = skl_get_cdclk,
3681 .set_cdclk = skl_set_cdclk,
3682 .modeset_calc_cdclk = skl_modeset_calc_cdclk,
3683};
3684
3685static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
3686 .get_cdclk = bdw_get_cdclk,
3687 .set_cdclk = bdw_set_cdclk,
3688 .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
3689};
3690
3691static const struct intel_cdclk_funcs chv_cdclk_funcs = {
3692 .get_cdclk = vlv_get_cdclk,
3693 .set_cdclk = chv_set_cdclk,
3694 .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3695};
3696
3697static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
3698 .get_cdclk = vlv_get_cdclk,
3699 .set_cdclk = vlv_set_cdclk,
3700 .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3701};
3702
3703static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
3704 .get_cdclk = hsw_get_cdclk,
3705 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3706};
3707
3708/* SNB, IVB, 965G, 945G */
3709static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
3710 .get_cdclk = fixed_400mhz_get_cdclk,
3711 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3712};
3713
3714static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
3715 .get_cdclk = fixed_450mhz_get_cdclk,
3716 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3717};
3718
3719static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
3720 .get_cdclk = gm45_get_cdclk,
3721 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3722};
3723
3724/* G45 uses G33 */
3725
3726static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
3727 .get_cdclk = i965gm_get_cdclk,
3728 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3729};
3730
3731/* i965G uses fixed 400 */
3732
3733static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
3734 .get_cdclk = pnv_get_cdclk,
3735 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3736};
3737
3738static const struct intel_cdclk_funcs g33_cdclk_funcs = {
3739 .get_cdclk = g33_get_cdclk,
3740 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3741};
3742
3743static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
3744 .get_cdclk = i945gm_get_cdclk,
3745 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3746};
3747
3748/* i945G uses fixed 400 */
3749
3750static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
3751 .get_cdclk = i915gm_get_cdclk,
3752 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3753};
3754
3755static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
3756 .get_cdclk = fixed_333mhz_get_cdclk,
3757 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3758};
3759
3760static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
3761 .get_cdclk = fixed_266mhz_get_cdclk,
3762 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3763};
3764
3765static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
3766 .get_cdclk = i85x_get_cdclk,
3767 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3768};
3769
3770static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
3771 .get_cdclk = fixed_200mhz_get_cdclk,
3772 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3773};
3774
3775static const struct intel_cdclk_funcs i830_cdclk_funcs = {
3776 .get_cdclk = fixed_133mhz_get_cdclk,
3777 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3778};
3779
3780/**
3781 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3782 * @display: display instance
3783 */
3784void intel_init_cdclk_hooks(struct intel_display *display)
3785{
3786 if (DISPLAY_VER(display) >= 30) {
3787 display->funcs.cdclk = &xe3lpd_cdclk_funcs;
3788 display->cdclk.table = xe3lpd_cdclk_table;
3789 } else if (DISPLAY_VER(display) >= 20) {
3790 display->funcs.cdclk = &rplu_cdclk_funcs;
3791 display->cdclk.table = xe2lpd_cdclk_table;
3792 } else if (DISPLAY_VERx100(display) >= 1401) {
3793 display->funcs.cdclk = &rplu_cdclk_funcs;
3794 display->cdclk.table = xe2hpd_cdclk_table;
3795 } else if (DISPLAY_VER(display) >= 14) {
3796 display->funcs.cdclk = &rplu_cdclk_funcs;
3797 display->cdclk.table = mtl_cdclk_table;
3798 } else if (display->platform.dg2) {
3799 display->funcs.cdclk = &tgl_cdclk_funcs;
3800 display->cdclk.table = dg2_cdclk_table;
3801 } else if (display->platform.alderlake_p) {
3802 /* Wa_22011320316:adl-p[a0] */
3803 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
3804 display->cdclk.table = adlp_a_step_cdclk_table;
3805 display->funcs.cdclk = &tgl_cdclk_funcs;
3806 } else if (display->platform.alderlake_p_raptorlake_u) {
3807 display->cdclk.table = rplu_cdclk_table;
3808 display->funcs.cdclk = &rplu_cdclk_funcs;
3809 } else {
3810 display->cdclk.table = adlp_cdclk_table;
3811 display->funcs.cdclk = &tgl_cdclk_funcs;
3812 }
3813 } else if (display->platform.rocketlake) {
3814 display->funcs.cdclk = &tgl_cdclk_funcs;
3815 display->cdclk.table = rkl_cdclk_table;
3816 } else if (DISPLAY_VER(display) >= 12) {
3817 display->funcs.cdclk = &tgl_cdclk_funcs;
3818 display->cdclk.table = icl_cdclk_table;
3819 } else if (display->platform.jasperlake || display->platform.elkhartlake) {
3820 display->funcs.cdclk = &ehl_cdclk_funcs;
3821 display->cdclk.table = icl_cdclk_table;
3822 } else if (DISPLAY_VER(display) >= 11) {
3823 display->funcs.cdclk = &icl_cdclk_funcs;
3824 display->cdclk.table = icl_cdclk_table;
3825 } else if (display->platform.geminilake || display->platform.broxton) {
3826 display->funcs.cdclk = &bxt_cdclk_funcs;
3827 if (display->platform.geminilake)
3828 display->cdclk.table = glk_cdclk_table;
3829 else
3830 display->cdclk.table = bxt_cdclk_table;
3831 } else if (DISPLAY_VER(display) == 9) {
3832 display->funcs.cdclk = &skl_cdclk_funcs;
3833 } else if (display->platform.broadwell) {
3834 display->funcs.cdclk = &bdw_cdclk_funcs;
3835 } else if (display->platform.haswell) {
3836 display->funcs.cdclk = &hsw_cdclk_funcs;
3837 } else if (display->platform.cherryview) {
3838 display->funcs.cdclk = &chv_cdclk_funcs;
3839 } else if (display->platform.valleyview) {
3840 display->funcs.cdclk = &vlv_cdclk_funcs;
3841 } else if (display->platform.sandybridge || display->platform.ivybridge) {
3842 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3843 } else if (display->platform.ironlake) {
3844 display->funcs.cdclk = &ilk_cdclk_funcs;
3845 } else if (display->platform.gm45) {
3846 display->funcs.cdclk = &gm45_cdclk_funcs;
3847 } else if (display->platform.g45) {
3848 display->funcs.cdclk = &g33_cdclk_funcs;
3849 } else if (display->platform.i965gm) {
3850 display->funcs.cdclk = &i965gm_cdclk_funcs;
3851 } else if (display->platform.i965g) {
3852 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3853 } else if (display->platform.pineview) {
3854 display->funcs.cdclk = &pnv_cdclk_funcs;
3855 } else if (display->platform.g33) {
3856 display->funcs.cdclk = &g33_cdclk_funcs;
3857 } else if (display->platform.i945gm) {
3858 display->funcs.cdclk = &i945gm_cdclk_funcs;
3859 } else if (display->platform.i945g) {
3860 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3861 } else if (display->platform.i915gm) {
3862 display->funcs.cdclk = &i915gm_cdclk_funcs;
3863 } else if (display->platform.i915g) {
3864 display->funcs.cdclk = &i915g_cdclk_funcs;
3865 } else if (display->platform.i865g) {
3866 display->funcs.cdclk = &i865g_cdclk_funcs;
3867 } else if (display->platform.i85x) {
3868 display->funcs.cdclk = &i85x_cdclk_funcs;
3869 } else if (display->platform.i845g) {
3870 display->funcs.cdclk = &i845g_cdclk_funcs;
3871 } else if (display->platform.i830) {
3872 display->funcs.cdclk = &i830_cdclk_funcs;
3873 }
3874
3875 if (drm_WARN(display->drm, !display->funcs.cdclk,
3876 "Unknown platform. Assuming i830\n"))
3877 display->funcs.cdclk = &i830_cdclk_funcs;
3878}
3879
3880int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
3881{
3882 return cdclk_state->logical.cdclk;
3883}
3884
3885int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state)
3886{
3887 return cdclk_state->actual.cdclk;
3888}
3889
3890int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state)
3891{
3892 return cdclk_state->actual.voltage_level;
3893}
3894
3895int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe)
3896{
3897 return cdclk_state->min_cdclk[pipe];
3898}
3899
3900int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state)
3901{
3902 return cdclk_state->bw_min_cdclk;
3903}
3904
3905bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state)
3906{
3907 const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
3908
3909 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
3910 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3911
3912 if (new_cdclk_state &&
3913 (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk ||
3914 new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level))
3915 return true;
3916
3917 return false;
3918}
3919
3920void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk)
3921{
3922 cdclk_state->force_min_cdclk = force_min_cdclk;
3923}
3924
3925void intel_cdclk_read_hw(struct intel_display *display)
3926{
3927 struct intel_cdclk_state *cdclk_state;
3928
3929 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);
3930
3931 intel_update_cdclk(display);
3932 intel_cdclk_dump_config(display, cdclk_config: &display->cdclk.hw, context: "Current CDCLK");
3933 cdclk_state->actual = display->cdclk.hw;
3934 cdclk_state->logical = display->cdclk.hw;
3935}
3936